CN103545185B - A kind of method that use dummy grid manufactures semiconductor devices - Google Patents
A kind of method that use dummy grid manufactures semiconductor devices Download PDFInfo
- Publication number
- CN103545185B CN103545185B CN201210243837.XA CN201210243837A CN103545185B CN 103545185 B CN103545185 B CN 103545185B CN 201210243837 A CN201210243837 A CN 201210243837A CN 103545185 B CN103545185 B CN 103545185B
- Authority
- CN
- China
- Prior art keywords
- layer
- dummy grid
- polysilicon layer
- substrate
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 118
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000010790 dilution Methods 0.000 claims description 2
- 239000012895 dilution Substances 0.000 claims description 2
- 239000006117 anti-reflective coating Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- -1 8slm Chemical compound 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of method that use dummy grid manufactures semiconductor devices, including step：Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；The first dummy grid is formed on the substrate of the first area, the second dummy grid is formed on the substrate of the second area, first dummy grid and the second dummy grid include the gate dielectric of storehouse, coating and polysilicon layer successively；Source-drain electrode is formed in the substrate；Barrier layer is formed at the top of second dummy grid；Wet etching is used to remove the polysilicon layer of first dummy grid to form groove；Fill the groove and form metal gates.The present invention can be to the dummy grid of polysilicon in the manufacturing process of semiconductor appropriate section carry out the removal of high selectivity, such that it is able to avoid that device is caused to damage, so as to improve the performance of manufactured semiconductor devices.
Description
Technical field
The present invention is to be related to a kind of technical field of manufacturing semiconductors, more precisely, the present invention relates to one kind using pseudo- grid
The method that pole manufactures semiconductor devices.
Background technology
During semiconductor devices is manufactured using dummy grid, it is typically included on substrate and forms dummy grid, source electrode leakage
Pole, then removes the appropriate section on dummy grid and fills the groove produced because removing the dummy grid part to form grid etc.
A series of step.In a series of this step, the removal of dummy grid appropriate section is an extremely crucial step.Generally
In the case of using dry etching in the dummy grid that is formed by polysilicon of removal, but the Etch selectivity of dry etching is undesirable, it is past
Toward unnecessary damage can be caused to device, so as to the performance to manufactured device is impacted.
But overcome above mentioned problem using there is no method in the technique of dummy grid manufacture semiconductor devices at present.
The content of the invention
In view of problem above, the method that a kind of use dummy grid of present invention offer manufactures semiconductor devices, including step：
A) Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；
B) the first dummy grid is formed on the substrate of the first area, second is formed on the substrate of the second area
Dummy grid, first dummy grid and the second dummy grid include the gate dielectric of storehouse, coating and polysilicon layer successively；
C) source-drain electrode is formed in the substrate；
D) barrier layer is formed at the top of second dummy grid；
E) wet etching is used to remove the polysilicon layer of first dummy grid to form groove；
F) fill the groove and form metal gates.
Further, the step d）Including：
Mask layer is formed on the polysilicon layer of first dummy grid；
The barrier layer is formed on the polysilicon layer of second dummy grid；
Remove the mask layer on the polysilicon layer of first dummy grid；
Further, wherein the mask layer is photoresist layer.
Further, BARC is formed wherein being additionally included between the photoresist layer and the polysilicon layer.
Further, wherein the barrier layer is oxide layer or nitration case.
Further, wherein the barrier layer has the thickness more than 30 angstroms.
Further, wherein the method on the formation barrier layer is the method for the method or ion implanting of plasma.
Further, the gas of H2 and N2 is included wherein being used in the removal mask layer step.
Further, wherein the solution used in the polysilicon layer step of the dummy grid of the wet etching first includes TMAH.
Further, wherein the solution used in the polysilicon layer step of the dummy grid of the wet etching first includes KTMAH.
Further, it is additionally included in after the removal mask layer step the step of be removed natural oxidizing layer.
Further, wherein performing the removal of the natural oxidizing layer using DHF.
Further, wherein it is described removal natural oxidizing layer the step of it is identical the step of with the wet etching polysilicon layer
Reaction chamber in perform.
Further, it is additionally included in step f）The polysilicon layer for being removed the second dummy grid afterwards forms groove；Filling institute
State groove and form metal gates.
Further, wherein the method for the polysilicon layer of the second dummy grid of the removal is the method for wet etching removal.
Further, it is additionally included between the substrate and the dummy grid and forms boundary layer.
Further, wherein forming the gate dielectric using hafnium.
Further, wherein forming the coating using TiN or TaN.
Further, it is additionally included in step b）Afterwards, on the side wall and substrate of the dummy grid formed offset side wall and
The step of gap wall.
Further, it is additionally included in step c）Afterwards formed ILD on the substrate and first and second dummy grid with
And the step of planarize the ILD to expose first dummy grid and the second dummy grid.
Method in the present invention using dummy grid can be in the manufacture of semiconductor in the manufacturing process of semiconductor devices
Appropriate section in journey to the dummy grid of polysilicon carries out the removal of high selectivity, such that it is able to avoid that device is caused to damage
Wound, so as to improve the performance of manufactured semiconductor devices.
Brief description of the drawings
Fig. 1-8 is the device profile map of each processing step of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Use dummy grid manufacture semiconductor devices method.Obviously, it is of the invention to implement the technology for being not limited to semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
It should be appreciated that when use in this manual term "comprising" and/or " including " when, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more other features, entirety,
Step, operation, element, component and/or combinations thereof will be next, the present invention will be more fully described by with reference to accompanying drawing.
Reference picture 1.First, there is provided Semiconductor substrate 200.Including first area and second area, the first area can
Think PMOS area, the second area can be NMOS area.The substrate can in the following material being previously mentioned extremely
Few one kind：Silicon, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）With
And germanium on insulator SiClx（SiGeOI）Deng.Could be formed with doped region and/or isolation structure in the substrate, it is described every
From structure for shallow trench is isolated（STI）Structure or selective oxidation silicon（LOCOS）Isolation structure.In an embodiment of the present invention,
The substrate can be Si substrates, and it is additionally may included in the boundary layer on Si, not shown in figure.In an embodiment by
Rapid thermal oxidation process（RTO）Or atom layer deposition process（ALD）To form the SiO2 boundary layers with 5-10A.Then at this
Gate dielectric 201 is formed on substrate, the gate dielectric can be formed from hafnium, be used for example in drawing in Hf02
Enter the elements such as Si, Al, N, La, Ta and optimize the ratio of each element hafnium for obtaining etc..The formation gate dielectric
Method can be physical gas-phase deposition or atom layer deposition process (ALD).In an embodiment of the present invention, in the SiO2
HfAION gate dielectrics are formed on boundary layer, its thickness is 15 to 60 angstroms.Afterwards, grid is formed on gate dielectric 201
The coating 202 of stack architecture, can be the coating of TiN that ALD is formed or TaN.Deposited on coating 202 afterwards many
Crystal silicon layer 300.In one embodiment of the invention, polysilicon is formed using low-pressure chemical vapor phase deposition (LPCVD) technique
Layer, its process conditions include：Reacting gas is silane (SiH4), and the range of flow of the silane is 100~200 cubes lis
M/min (sccm), such as 150sccm；Temperature range is 700~750 degrees Celsius in reaction chamber；Reaction cavity pressure be 250~
350 milli millimetress of mercury (mTorr), such as 300mTorr；Also include buffer gas in the reacting gas, the buffer gas can be
The range of flow of helium (He) or nitrogen, the helium and nitrogen be 5~20 liters/min (slm), such as 8slm, 10slm or
15slm。
It is then possible to the boundary layer, gate dielectric 201, the coating 202 that are formed to above step using photoetching process
Carry out patterned process to form the dummy gate structure of storehouse with polysilicon layer 300.
As shown in Figure 2.Can also carry out forming offset side wall（offset spacer）211 the step of.The material of offset side wall
Material can be silicon nitride, the insulating materials such as silica or silicon oxynitride.Offset side wall can improve the ditch of the transistor of formation
Road length, reduces short-channel effect and the hot carrier's effect caused due to short-channel effect.The technique for forming offset side wall can
Being chemical vapor deposition.The thickness of the offset side wall for being formed in one embodiment may diminish to 80 angstroms.
And formation is lightly doped step of the source/drain (LDD) in the substrate of grid structure either side.The formation
The method of LDD can be ion implantation technology or diffusion technique.The ionic type of LDD injections is according to the semiconductor device that will be formed
The electrical decision of part, that is, the device for being formed be nmos device, then in LDD injection technologies mix foreign ion for phosphorus, arsenic, antimony,
One kind or combination in bismuth；If the device for being formed is PMOS device, the foreign ion for injecting is boron.According to required impurity from
The concentration of son, ion implantation technology can be completed with one or multi-step.
And form clearance wall on the offset side wall that substrate 200 and above-mentioned steps are formed（Spacer）212 the step of.
Silicon nitride, carborundum, silicon oxynitride or its material for combining can be used.The first silicon oxide layer, can be deposited on substrate
One silicon nitride layer and the second silicon oxide layer, then form clearance wall using engraving method, and the clearance wall can have 10-
The thickness of 30NM.
And with ion implantation technology or diffusion technique heavy doping source electrode and drain electrode（S/D）It is formed at grid gap wall any
Step in the substrate of side, high-temperature annealing step forms metal silicide（SAB）The step (not shown) such as barrier layer.
Reference picture 3.Then can also be in the surface depositing etch stop layer of device, not shown in figure.Etching stopping layer can
Formed with SiCN, SiN, SiC, SiOF, SiON etc..Then interlevel dielectric deposition is carried out（ILD）220 on grid structure and
Between it.Can be using chemical vapour deposition technique, high density plasma CVD method, method of spin coating, sputter etc.
Method is formed, and the interlayer dielectric layer can be formed using materials such as silica, silicon oxynitride, silicon nitrides.
Reference picture 4.Then planarization process is carried out to interlayer dielectric layer 220 and/or etching stop layer.At the planarization
The non-limiting examples of reason include mechanical planarization method and chemically mechanical polishing flattening method.To expose dummy gate structure
Upper surface.In one embodiment with the method for CMP with exposed polysilicon layer 300.
Reference picture 5.The interlayer dielectric layer of the first dummy gate region for then being treated in planarisation step and institute are exposed
Mask layer 301 is formed in first dummy gate structure.In one embodiment, in the exposed polysilicon layer of PFET regions institute and ILD
Upper formation mask layer.Any one of several mask materials can be included, including but not limited to：Hard mask material and photoresist are covered
Mold materials.Preferably, mask layer includes photoresist mask material.Photoresist mask material can include being selected from including positive-tone photo
Glue material, negative photo glue material and mixing Other substrate materials etc..The mask layer can include have thickness from about 2000 to
About 5000 angstroms of positive-tone photo glue material or negative photo glue material.The bottom of photoresist can also be included in one embodiment
Portion's ARC（BARC）, the BARC can be formed with TiN or SiN.
Reference picture 6.Barrier layer 302 is formed after the planarisation step on the polysilicon layer of exposed second dummy grid.One
In individual embodiment, the barrier layer is formed on the polysilicon layer of NFET regions dummy grid.The barrier layer can be formed at polycrystalline
Oxide layer or nitration case on silicon layer, it is possible to use the method for the method and ion implanting of plasma oxidation or nitridation.
The method of the plasma oxidation in one embodiment is carried out in the system of PECVD, and its radio frequency primary frequency is 13.56Hz, gas
Source is the mixed gas of argon gas and oxygen, and its ratio is 9:1, gas flow is 50sccm, and reative cell air pressure is 5.26*104Pa,
Underlayer temperature is 250 degrees Celsius, and RF source power is 2W/cm2, and the thickness of the oxide layer for being formed can be more than 30 angstroms.
Reference picture 7.Then the step of being removed mask layer 301.Its condition includes being passed through O2 in the reactor chamber.At one
In embodiment, also including the mixed gas being passed through, it includes appropriate N2 and H2, and removal is accelerated to increase ion concentration
Speed.
After above step is completed, the thickness of the oxide layer being formed on the polysilicon layer of dummy gate structure will have
Different thickness, it also includes natural oxidizing layer.Observed oxide layer includes oneself of about 10 angstroms in one embodiment
The oxide layer of right oxide layer and the diauxic growth at about 30 angstroms of PFET regions.
Then the step of being removed natural oxidizing layer and the polycrystalline that the first dummy gate structure is removed with the method for wet etching
The step of silicon layer.In an embodiment of the present invention, using the hydrofluoric acid of dilution（DHF）Technique erodes natural oxidizing layer, HF：
The volume ratio of H2O can be 1：（10-200）, treatment temperature is 20-25 degrees Celsius, and the technique can make the corruption of natural oxidizing layer
Erosion terminates at the very low polysilicon layer surface of oxygen content.
TMAH can be utilized（TMAH）To remove the polysilicon layer of the first dummy grid.Make in one embodiment
The polysilicon layer of NFET regions dummy grid is removed with the tetramethyl hydrogen ammonia spirit that concentration is 22%wt.In further embodiment
In, also use anisotropic etchant（KTMAH）To remove polysilicon layer, potassium hydroxide is added in the TMAH aqueous solution（KOH）,
Wherein the mass fraction of TMAH is that the mol ratio of 10%-25%, TMAH and KOH is 2-4, and the temperature of reaction is 60-90 degrees Celsius.From
And the polysilicon layer of the first dummy grid can be removed to form groove, as shown in Figure 8.
The step of polysilicon layer of the first dummy gate structure of removal natural oxide more than wherein and removal, can be same
The probability to reduce the movement of device so as to reduce damage is carried out in individual reaction chamber.
By it is above-mentioned the second dummy grid the barrier layer that is formed on exposed polysilicon layer there is certain thickness, and this
The effect that the wet etching of invention is etched to it is limited, so it can protect polysilicon layer below so that with high selection
The lithographic method of property can be applied in the removal step of the first dummy grid polysilicon layer.
Then grid material is filled in the groove that is formed to form grid removing the first dummy grid polysilicon layer, can be with
It is to fill metal material to form metal gate.Metal gate in one embodiment can also include：TiN, TaN, TiN and TaN
With combinations of the above workfunction layers；The barrier layer of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above；
With conductive layer etc..The method for forming grid can include the steps such as deposition, annealing and planarization.
Then the step of being removed the second dummy grid polysilicon layer to form groove and the filling groove form grid
The step of pole.
Then subsequent technique is carried out to complete the manufacture of semiconductor element.
For the purpose of illustration and description, the above description of various aspects of the present invention is given.It is not intended as limit row
Disclosed precise forms are lifted or limited the invention to, and it is apparent that numerous modifications and variations can be carried out.It is contemplated that
Will become readily apparent to those skilled in the art these modifications and variations and be included in the present invention being defined by the following claims
In the range of.
Claims (18)
1. a kind of method that use dummy grid manufactures semiconductor devices, including step：
A) Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；
B) the first dummy grid is formed on the substrate of the first area, the second pseudo- grid is formed on the substrate of the second area
Pole, first dummy grid and the second dummy grid include the gate dielectric of storehouse, coating and polysilicon layer successively；
C) source-drain electrode is formed in the substrate；
D) barrier layer is formed at the top of second dummy grid, wherein, the barrier layer is oxide layer or nitration case, forms institute
The method for stating barrier layer is to use plasma oxidation or the method for nitridation or the method for ion implanting to process the described second pseudo- grid
Polysilicon layer at the top of pole；
E) wet etching is used to remove the polysilicon layer of first dummy grid to form groove；
F) fill the groove and form metal gates.
2. method according to claim 1, the step d) includes：
Mask layer is formed on the polysilicon layer of first dummy grid；
The barrier layer is formed on the polysilicon layer of second dummy grid；
Remove the mask layer on the polysilicon layer of first dummy grid.
3. method according to claim 2, wherein the mask layer is photoresist layer.
4. method according to claim 3, wherein be additionally included between the photoresist layer and the polysilicon layer being formed
Bottom antireflective coating.
5. method according to claim 1, wherein the barrier layer has the thickness more than 30 angstroms.
6. the method according to claim 2,3 or 4, wherein using including H in the removal mask layer step2And N2Gas
Body.
7. method according to claim 1, wherein being used in the polysilicon layer step of the dummy grid of the wet etching first
Solution include TMAH.
8. method according to claim 1, wherein being used in the polysilicon layer step of the dummy grid of the wet etching first
Solution include anisotropic etchant.
9. the method according to claim 2,3 or 4, is additionally included in after the removal mask layer step and is removed nature
The step of oxide layer.
10. method according to claim 9, wherein performing going for the natural oxidizing layer using the hydrofluoric acid of dilution
Remove.
11. methods according to claim 9, wherein the step of removal natural oxidizing layer is more with the wet etching
Performed in the step of crystal silicon layer identical reaction chamber.
12. methods according to claim 1, are additionally included in the polysilicon layer that step f) is removed the second dummy grid afterwards
Form groove；Fill the groove and form metal gates.
13. methods according to claim 12, wherein the method for the polysilicon layer of the second dummy grid of the removal is wet method
The method for etching removal.
14. methods according to claim 1, are additionally included between the substrate and the dummy grid and form boundary layer.
15. methods according to claim 1, wherein forming the gate dielectric using hafnium.
16. methods according to claim 1, wherein forming the coating using TiN or TaN.
17. methods according to claim 1, are additionally included in after step b), form inclined on the side wall of the dummy grid
The step of moving side wall and clearance wall.
18. methods according to claim 1, formation interlayer dielectric layer is in the substrate and institute after being additionally included in step c)
The interlayer dielectric layer is stated on the first and second dummy grids and planarized to expose first dummy grid and the second dummy grid
The step of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210243837.XA CN103545185B (en) | 2012-07-13 | 2012-07-13 | A kind of method that use dummy grid manufactures semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210243837.XA CN103545185B (en) | 2012-07-13 | 2012-07-13 | A kind of method that use dummy grid manufactures semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103545185A CN103545185A (en) | 2014-01-29 |
| CN103545185B true CN103545185B (en) | 2017-06-13 |
Family
ID=49968542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210243837.XA Active CN103545185B (en) | 2012-07-13 | 2012-07-13 | A kind of method that use dummy grid manufactures semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103545185B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632908B (en) * | 2014-11-06 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105719945B (en) * | 2014-12-02 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| TWI612674B (en) * | 2016-03-24 | 2018-01-21 | 台灣積體電路製造股份有限公司 | Finfet and the methods of fabricating the same |
| US10276677B2 (en) * | 2016-11-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
| US11600713B2 (en) * | 2018-05-30 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114206A (en) * | 1998-11-06 | 2000-09-05 | Advanced Micro Devices, Inc. | Multiple threshold voltage transistor implemented by a damascene process |
| CN102157381A (en) * | 2010-02-11 | 2011-08-17 | 三星电子株式会社 | Method of manufacturing semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100899565B1 (en) * | 2002-10-21 | 2009-05-27 | 주식회사 하이닉스반도체 | Method of forming dual metal gate for semiconductor device |
| US8450834B2 (en) * | 2010-02-16 | 2013-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers |
-
2012
- 2012-07-13 CN CN201210243837.XA patent/CN103545185B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114206A (en) * | 1998-11-06 | 2000-09-05 | Advanced Micro Devices, Inc. | Multiple threshold voltage transistor implemented by a damascene process |
| CN102157381A (en) * | 2010-02-11 | 2011-08-17 | 三星电子株式会社 | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103545185A (en) | 2014-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9490348B2 (en) | Method of forming a FinFET having an oxide region in the source/drain region | |
| KR101027107B1 (en) | Metal gate mosfet by full semiconductor metal alloy conversion | |
| US9276089B2 (en) | FinFETs and methods for forming the same | |
| US7078282B2 (en) | Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films | |
| TWI696220B (en) | Method of fabricating semiconductor device | |
| US8324038B2 (en) | Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device | |
| US8835267B2 (en) | Semiconductor device and fabrication method thereof | |
| CN102738221B (en) | Method of fabricating a gate dielectric layer | |
| WO2011066747A1 (en) | Semiconductor device and forming method thereof | |
| CN101872742A (en) | Semiconductor device and manufacturing method | |
| US8741759B2 (en) | Method for fabricating a semiconductor device | |
| US8329552B1 (en) | Semiconductor device and method of manufacture | |
| CN107123618B (en) | Method for manufacturing fin field effect transistor and shallow trench isolation | |
| WO2011066746A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103545185B (en) | A kind of method that use dummy grid manufactures semiconductor devices | |
| US9530861B2 (en) | Method for manufacturing semiconductor device | |
| US7892929B2 (en) | Shallow trench isolation corner rounding | |
| CN103545186A (en) | Method for manufacturing metal gate semiconductor device | |
| WO2011075991A1 (en) | High performance semiconductor device and manufacturing method thereof | |
| US9306033B2 (en) | Semiconductor device and fabrication method thereof | |
| CN105097534B (en) | A method of making semiconductor devices | |
| CN104851802B (en) | A kind of semiconductor devices and preparation method thereof | |
| US9941372B2 (en) | Semiconductor device having electrode and manufacturing method thereof | |
| CN104051245B (en) | A kind of preparation method of semiconductor devices | |
| CN103456614A (en) | Manufacturing method for semiconductor device with high-K metal gate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |