CN107785267B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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CN107785267B
CN107785267B CN201610755894.4A CN201610755894A CN107785267B CN 107785267 B CN107785267 B CN 107785267B CN 201610755894 A CN201610755894 A CN 201610755894A CN 107785267 B CN107785267 B CN 107785267B
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forming
layer
substrate
annealing
opening
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CN107785267A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A method of forming a semiconductor structure, comprising: forming a substrate; forming a pseudo gate structure; forming a stress layer; forming a source drain doped region; forming an interlayer dielectric layer; forming an opening, wherein the bottom of the opening exposes the oxide layer; carrying out first annealing treatment to activate the doped ions of the source drain doped region; and in the first annealing treatment process, repairing the oxide layer at the bottom of the opening. In the technical scheme of the invention, the interlayer dielectric layer covers the stress layer, so that the interlayer dielectric layer can inhibit the stress layer, the possibility of melting of the stress layer in the first annealing treatment process can be reduced, the stress release of the stress layer in the first annealing treatment process can be inhibited, and the shrinkage of the stress layer in the first annealing treatment process can be inhibited. And the first annealing treatment can activate the doped ions in the source-drain doped region and repair the exposed oxide layer, so that the heating process in the forming process of the semiconductor structure is reduced, and the performance of the formed semiconductor structure is improved.

Description

Method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. In the fin field effect transistor, the grid can control the fin part at least from two sides, the control capability on a channel is stronger than that of a planar device, and the short channel effect can be well inhibited; and compared with other devices, the fin field effect transistor has better compatibility with the existing integrated circuit manufacturing technology.
In addition, the mobility of carriers is one of the main factors affecting the performance of the transistor. Effectively improving carrier mobility becomes one of the key points in the transistor device manufacturing process. Since the energy gap and carrier mobility of silicon materials can be changed by stress, it is becoming a more and more common means to improve the performance of transistors by forming stress layers. Specifically, a stress layer capable of providing tensile stress is formed in the N-type transistor to improve electron mobility, and a stress layer capable of providing compressive stress is formed in the N-type transistor to improve hole mobility.
However, after the stress layer is introduced in the prior art, the performance of the semiconductor needs to be improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
forming a substrate; forming a pseudo gate structure on the substrate, wherein the pseudo gate structure comprises an oxide layer positioned on the substrate and a pseudo gate positioned on the oxide layer; forming stress layers in the substrate on two sides of the pseudo gate structure; carrying out ion doping on the stress layer to form a source drain doped region; forming an interlayer dielectric layer covering the stress layer, wherein the top surface of the interlayer dielectric layer is exposed out of the pseudo gate; removing the pseudo grid electrode, forming an opening in the interlayer dielectric layer, and exposing the oxide layer at the bottom of the opening; and carrying out first annealing treatment to activate the doped ions of the source-drain doped region and repair the oxide layer at the bottom of the opening.
Optionally, the step of performing the first annealing treatment includes: and carrying out the first annealing treatment in a spike annealing mode.
Optionally, the step of performing the first annealing treatment includes: and carrying out the first annealing treatment by adopting a spike annealing mode and a laser annealing mode.
Optionally, in the step of performing the first annealing treatment by using a spike annealing method, the annealing temperature is in a range of 1000 ℃ to 1050 ℃, and the pressure is a standard atmospheric pressure.
Optionally, in the first annealing process, the proportion of oxygen in the process gas is less than 10% by volume. .
Optionally, in the step of performing the first annealing treatment, the process gas includes oxygen and nitrogen.
Optionally, in the step of performing the first annealing treatment, a volume ratio of oxygen to nitrogen in the process gas is in a range of 1:10 to 1: 500.
Optionally, in the step of performing the first annealing treatment by using a laser annealing method, the annealing temperature is in a range of 1200 ℃ to 1250 ℃.
Optionally, in the step of forming the interlayer dielectric layer, the interlayer dielectric layer is made of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, in the step of forming the interlayer dielectric layer, the thickness of the interlayer dielectric layer is within
Figure BDA0001097873060000021
To
Figure BDA0001097873060000022
Within the range.
Optionally, the step of forming the interlayer dielectric layer includes: forming a precursor isolation film covering the stress layer on the substrate, wherein the precursor isolation film also covers the pseudo gate structure; carrying out second annealing treatment on the precursor isolating film, and converting the precursor isolating film into an interlayer dielectric film; and removing the interlayer dielectric film higher than the top of the dummy gate structure by adopting a planarization process to expose the dummy gate and form the interlayer dielectric layer.
Optionally, the step of forming the precursor isolation film includes: and forming the precursor isolation film by adopting a fluid chemical vapor deposition mode.
Optionally, the step of performing a second annealing process on the precursor isolation film includes: and carrying out second annealing treatment on the precursor isolation film by adopting a rapid annealing mode.
Optionally, in the step of performing a second annealing treatment on the precursor isolation film by using a rapid annealing manner, the annealing temperature is 950 ℃ to 1100 ℃, the annealing time is 0 second to 20 seconds, and the pressure is one standard atmospheric pressure.
Optionally, the substrate is used for forming an N-type transistor; in the step of forming the stress layer, the stress layer is made of SiC, SiP or SiCP; or, the substrate is used for forming a P-type transistor, and the stress layer is made of SiGe, SiB or SiGeB.
Optionally, the substrate is used for forming a fin field effect transistor; in the step of forming the base, the base comprises a substrate and a discrete fin part positioned on the substrate; in the step of forming the dummy gate structure, forming the dummy gate structure which crosses the fin part and covers part of the top of the fin part and part of the surface of the side wall; and in the step of forming the stress layer, forming the stress layer in the fin parts at two sides of the pseudo gate structure.
Optionally, the step of forming the stress layer in the fin portions on two sides of the dummy gate structure includes: forming grooves in the fin parts on two sides of the pseudo gate structure; and forming the stress layer in the groove by adopting a selective epitaxy process.
Optionally, the step of forming the source-drain doped region includes: and carrying out in-situ self-doping in the process of forming the stress layer in the fin parts at two sides of the pseudo gate structure to form the source-drain doped region.
Optionally, the substrate is used for forming an N-type transistor, the in-situ self-doping ions are phosphorus ions, and the doping concentration is 1E19atom/cm3To 5E22atom/cm3(ii) a Or the substrate is used for forming a P-type transistor and is self-doped with boron ions in situ, and the doping concentration is 2E19atom/cm3To 5E22atom/cm3。
Optionally, in the step of forming the substrate, the substrate includes a peripheral region for forming the input/output device and a core region for forming the core device; in the step of forming the opening, removing the pseudo gate of the pseudo gate structure on the substrate of the peripheral region, forming a first opening in the interlayer dielectric layer on the substrate of the peripheral region, and exposing the oxide layer on the substrate of the peripheral region at the bottom of the first opening; repairing the oxide layer at the bottom of the first opening in the process of carrying out first annealing treatment; after the first annealing treatment is performed, the forming method further includes: filling a protective layer in the first opening; removing the pseudo gate structure on the core region substrate, and forming a second opening in the interlayer dielectric layer on the core region substrate, wherein the bottom of the second opening is exposed out of the core region substrate; removing the protective layer to form a third opening, wherein the bottom of the third opening exposes the oxide layer on the substrate of the peripheral area; and respectively forming a gate structure in the second opening and the third opening.
Optionally, in the step of filling the first opening with the protective layer, the protective layer is a bottom anti-reflection layer, a photoresist layer, or an organic dielectric layer.
Optionally, the step of removing the protective layer includes: and removing the protective layer by ashing.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, after the stress layer is subjected to ion doping to form a source-drain doped region, an interlayer dielectric layer covering the stress layer is formed; removing the pseudo grid to expose the oxide layer; and then carrying out first annealing treatment to activate the doped ions of the source-drain doped region. The interlayer dielectric layer covers the stress layer, so that the interlayer dielectric layer can play a pressing role on the stress layer, can inhibit the stress layer from releasing stress in the first annealing treatment process, and can inhibit the stress layer from shrinking in the first annealing treatment process. And the first annealing treatment can activate the doped ions in the source-drain doped region and repair the exposed oxide layer, so that the heating process in the forming process of the semiconductor structure is reduced, and the performance of the formed semiconductor structure is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure during various steps of a method for forming the semiconductor structure;
fig. 2 to 11 are schematic cross-sectional views corresponding to respective steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the semiconductor structure in the prior art has a problem of poor performance. The cause of the performance problems is now analyzed in conjunction with a method for semiconductor structures:
fig. 1 is a schematic cross-sectional view illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, forming a base, where the base includes a substrate 10 and a discrete fin portion 11 located on the substrate 10; forming a gate structure 13 on the substrate, wherein the gate structure 13 crosses over the fin 11 and covers part of the top and part of the sidewall of the fin 11; and forming a stress layer 14 in the fin part 11 on two sides of the gate structure 13, and performing ion doping on the stress layer 14 by adopting an in-situ self-doping process to form a source-drain doped region.
Continuing to refer to fig. 1, an annealing process 15 is performed to activate the dopant ions in the source and drain doped regions and repair lattice damage in the source and drain doped regions.
In order to activate the doping ions in the source-drain doping region, the annealing temperature of the annealing treatment 15 is higher and is close to the melting point of the material of the stress layer 14. Therefore, during the annealing process, the stress layer 14 is formed to have a stress relaxation phenomenon and a shrinkage phenomenon, thereby causing degradation of the quality and performance of the stress layer 14. Degradation of the quality and performance of the stress layer 14 can affect the effect of the stress layer 14 in enhancing carrier mobility, and thus the performance of the resulting semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
forming a substrate; forming a pseudo gate structure on the substrate, wherein the pseudo gate structure comprises an oxide layer positioned on the substrate and a pseudo gate positioned on the oxide layer; forming stress layers in the substrate on two sides of the pseudo gate structure; carrying out ion doping on the stress layer to form a source drain doped region; forming an interlayer dielectric layer covering the stress layer, wherein the top surface of the interlayer dielectric layer is exposed out of the pseudo gate; removing the pseudo grid electrode, forming an opening in the interlayer dielectric layer, and exposing the oxide layer at the bottom of the opening; carrying out first annealing treatment to activate the doped ions of the source drain doped region; and in the first annealing treatment process, repairing the oxide layer at the bottom of the opening.
According to the technical scheme, after the stress layer is subjected to ion doping to form a source-drain doped region, an interlayer dielectric layer covering the stress layer is formed; removing the pseudo grid to expose the oxide layer; and then carrying out first annealing treatment to activate the doped ions of the source-drain doped region. The interlayer dielectric layer covers the stress layer, so that the interlayer dielectric layer can suppress the stress layer, the possibility of melting of the stress layer in the first annealing treatment process can be reduced, stress release of the stress layer in the first annealing treatment process is suppressed, and shrinkage of the stress layer in the first annealing treatment process is suppressed. And the first annealing treatment can activate the doped ions in the source-drain doped region and repair the exposed oxide layer, so that the heating process in the forming process of the semiconductor structure is reduced, and the performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate is formed.
The substrate is used for providing a process foundation for a subsequent semiconductor process. The substrate includes a peripheral region 100i for forming input-output devices and a core region 100c for forming core devices.
In this embodiment, the base is used for forming a finfet, and includes a substrate 100 and a discrete fin 110 on the substrate 100.
The substrate 100 is used to provide an operating platform for a semiconductor process, and the fin 110 is used to form a finfet.
In this embodiment, the step of forming the substrate includes: providing an initial substrate; the initial substrate is etched to form a substrate 100 and discrete fins 110 on the substrate 100.
The initial substrate is used to form the substrate 100 and etch to form the fins 110. In this embodiment, the material of the initial substrate is monocrystalline silicon. The material of the substrate 100 and the fin 110 is also single crystal silicon.
In other embodiments of the present invention, the material of the initial substrate may also be selected from germanium, gallium arsenide, or silicon germanium compounds; the initial substrate may also be other semiconductor materials. In addition, the initial substrate can also be selected from an epitaxial layer or a silicon structure on the epitaxial layer. The substrate can be selected to be suitable for process requirements or easy to integrate; the material of the semiconductor layer may be selected to be suitable for forming the fin portion.
The step of etching the initial substrate comprises: forming a patterned fin mask layer (marked in the figure) on the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask to form the substrate 100 and the discrete fin parts 110 positioned on the substrate 100.
The fin mask layer may be a patterned photoresist layer formed by a coating process and a photolithography process. Alternatively, the fin mask layer may be a hard mask layer or a mask layer formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
In addition, the base further includes an isolation layer (not shown) on the substrate 100 between adjacent fins 110, and a top surface of the isolation layer is lower than a top surface of the fins 110 to expose a portion of the top surface and sidewalls of the fins 110. After forming the substrate 100 and the fin 110, the forming method further includes: the isolation layer is formed on the substrate 100 between adjacent fins 110.
The isolation layer is used to achieve electrical isolation between adjacent fins 110 and between the semiconductor structure and other semiconductor structures on the substrate 100.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride. Specifically, the step of forming the isolation layer includes: forming an isolation material layer on the substrate 100 between adjacent fins 110, wherein the top surface of the isolation material layer is higher than the top surface of the fin mask layer; and removing part of the thickness of the isolation material layer to form an isolation layer, so that the top surface of the formed isolation layer is lower than the top surface of the fin portion 110, and part of the surface of the side wall of the fin portion 110 is exposed.
It should be noted that, in this embodiment, after the isolation layer is formed, the fin mask layer is removed by a wet etching process to expose the top surface of the fin 110.
With continued reference to fig. 2, a dummy gate structure 120 is formed on the substrate, wherein the dummy gate structure 120 includes an oxide layer 121 on the substrate and a dummy gate 122 on the oxide layer 121.
In this embodiment, the substrate is used to form a finfet, so the step of forming the dummy gate structure 120 includes: forming a dummy gate structure 120 on the fin 110, wherein the dummy gate structure 120 crosses the fin 110 and covers part of the surface of the top and the sidewall of the fin 110.
The dummy gate structure 120 is used to occupy a spatial position for a subsequently formed gate structure.
The dummy gate structure 120 includes an oxide layer 121 on the substrate and a dummy gate 122 on the oxide layer 121. In this embodiment, the oxide layer 121 is made of silicon oxide; the material of the dummy gate 122 is polysilicon.
The step of forming the dummy gate structure 120 includes: forming an oxide layer 121 on the surface of the substrate; forming a gate electrode material layer on the oxide layer 121; forming a gate mask on the gate electrode material layer; and etching the gate electrode material layer by using the gate mask as a mask until the surface of the fin 110 is exposed, thereby forming the dummy gate 122 and the oxide layer 121 covered by the dummy gate 122.
In this embodiment, after the dummy gate structure 120 is formed, the forming method further includes forming a gate sidewall spacer located on the sidewalls of the dummy gate 122 and the oxide layer 121. The grid side wall is of a laminated structure of silicon oxide-silicon nitride-silicon oxide. In other embodiments of the present invention, the gate sidewall spacer may also be a single-layer structure of silicon nitride and other materials.
The step of forming the gate side wall includes: and forming side wall material layers on the surface of the substrate, the pseudo gate 122 and the top and side walls of the gate mask layer, and removing the side wall material layers on the surface of the substrate and the top surface of the gate mask layer in an anisotropic dry etching manner to form the gate side wall.
Referring to fig. 3, a stress layer 130 is formed in the substrate on both sides of the dummy gate structure 120; and performing ion doping on the stress layer 130 to form a source-drain doped region (not shown in the figure).
The stress layer 130 is used to apply stress to the channel region of the formed transistor to improve the mobility of carriers in the channel.
In this embodiment, the substrate is used to form a finfet. The step of forming the stress layer 130 includes: and forming the stress layer 130 in the fin parts 110 on two sides of the pseudo gate structure.
Specifically, the step of forming the stress layer 130 includes:
etching the fin parts 110 on the two sides of the dummy gate structure 120 by using the gate side wall as a mask, and forming a groove in the fin parts 110 on the two sides of the dummy gate structure 120; and filling a stress material layer into the groove by adopting a selective epitaxial process, and forming a stress layer 130 in the groove.
In this embodiment, the substrate is used to form a P-type transistor, so in the step of forming the trench, the trench is a sigma-shaped trench; and filling the stress material filled in the groove into SiGe. The stress layer 130 formed is a SiGe stress layer in the shape of a "sigma". The sigma-shaped SiGe stress layer can provide compressive stress for a channel region of the formed transistor, so that the mobility of holes in a channel of the P-type transistor is improved, and the performance of the formed semiconductor structure is improved. In other embodiments of the present invention, the stress material may also be SiB or SiGeB.
It should be noted that the method of forming the P-type transistor by using the substrate is only an example. In other embodiments of the present invention, the substrate may also be used to form an N-type transistor. The step of forming the trench is such that the trench is a "U" shaped trench when the substrate is used to form an N-type transistor; the stress material filled into the groove can be SiC, so that a square SiC stress layer is formed. The square SiC stress layer can provide tensile stress for a channel region of the formed transistor, so that the mobility of electrons in a channel of the N-type transistor is improved, and the performance of the formed semiconductor structure is improved. In the N-type transistor, the stress layer can also be made of SiP or SiCP.
In this embodiment, the stress layer 130 is a SiGe stress layer, and thus in the step of forming the SiGe stress layer, the reaction temperature is 650 ℃ to 850 ℃; the reactant gases include a Si source gas including SiH and a Ge source gas4、SiH2Cl2Or Si2Cl6The gas flow of the Si source gas is 0.5slm to 30 slm; the Ge source gas comprises GeH4And the gas flow of the Ge source gas is 0.5slm to 20 slm.
In addition, in this embodiment, the step of performing ion doping on the stress layer 130 to form a source-drain doped region includes: and performing in-situ self-doping in the process of forming the stress layer 130 in the fin parts 110 at two sides of the pseudo gate structure to form the source-drain doped region.
In particular, the method comprises the following steps of,the substrate is used for forming a P-type transistor, so in the step of forming the stress layer 130, boron ions are in-situ self-doped with the doping concentration of 2E19atom/cm3To 5E22atom/cm3。
In other embodiments of the present invention, the substrate is used to form an N-type transistor, so during the step of forming the stress layer 130, the in-situ self-doping ions are phosphorous ions with a doping concentration of 1E19atom/cm3To 5E22atom/cm3。
It should be noted that, after the source-drain doped region is formed, the forming method further includes performing heavy doping implantation on the source-drain doped region to reduce the on-resistance of the formed transistor. The specific technical scheme of the heavy doping injection is the same as that of the prior art, and the detailed description of the invention is omitted here.
Referring to fig. 4, an interlayer dielectric layer 140 covering the stress layer 130 is formed, and the top surface of the interlayer dielectric layer 140 exposes the dummy gate 122.
It should be noted that, after the source-drain doped region is formed and before the interlayer dielectric layer 140 is formed, the forming method further includes forming an etch stop layer (not labeled in the figure) covering the substrate, the dummy gate structure 120, the gate sidewall spacer and the stress layer 130. The etching stop layer plays a role in stopping etching in the subsequent contact hole etching process. In this embodiment, the etch stop layer is made of silicon nitride.
The interlayer dielectric layer 140 is used to realize electrical isolation between different semiconductor structures. In addition, the interlayer dielectric layer 140 covers the stress layer 130, and the interlayer dielectric layer 140 is further configured to compress the stress layer 130 in a subsequent process, so as to inhibit stress release of the stress layer 130 in the subsequent process and inhibit shrinkage of the stress layer 130 in the subsequent process, thereby improving quality and properties of the formed stress layer 130 and improving performance of the formed semiconductor structure.
In this embodiment, the interlayer dielectric layer 140 covering the stress layer 130 is filled on the substrate located between the adjacent dummy gate structures 120, and the top surface of the interlayer dielectric layer is exposed out of the dummy gate 122. Specifically, the interlayer dielectric layer 140 covers the fin 110, the stress layer 130, and the isolation layer between adjacent dummy gate structures 120.
The interlayer dielectric layer 140 is made of an insulating material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 140 is made of silicon oxide.
It should be noted that if the thickness of the interlayer dielectric layer 140 is too small, it is difficult to perform the function of compressing the stress layer 130 in the subsequent process, and it is difficult to reduce the possibility of the stress release phenomenon of the stress layer 130; if the thickness of the interlayer dielectric layer 140 is too large, the integration level of the device is not improved, and the problems of material waste and process difficulty increase are easily caused. In this embodiment, the thickness of the interlayer dielectric layer 140 is within
Figure BDA0001097873060000101
To
Figure BDA0001097873060000102
Within the range.
The step of forming the interlayer dielectric layer 140 includes: forming a precursor isolation film on the substrate to cover the stress layer 130, wherein the precursor isolation film also covers the pseudo gate structure 120; carrying out second annealing treatment on the precursor isolating film, and converting the precursor isolating film into an interlayer dielectric film; and removing the interlayer dielectric film higher than the top of the dummy gate structure 120 by adopting a planarization process to expose the dummy gate 122, thereby forming the interlayer dielectric layer 140.
In this embodiment, the step of forming the precursor isolation film includes: and forming the precursor isolation film by adopting a mode of Fluid Chemical Vapor Deposition (FCVD), thereby improving the filling effect of the precursor isolation film. In other embodiments of the present invention, the precursor isolation film may also be formed by a high aspect ratio chemical vapor deposition process (HAEP CVD).
In this embodiment, the interlayer dielectric layer 140 is made of silicon oxide, so the step of forming the precursor isolation film by using a fluid chemical vapor deposition method includes: depositing a thin film precursor containing Si, H, N and O on the substrate between the adjacent dummy gate structures 120; carrying out ultraviolet irradiation on the film precursor to break Si-H bonds; and after the ultraviolet light irradiation, carrying out water vapor annealing treatment on the film precursor to enable Si and O to react to form a precursor isolation film.
Specifically, the process temperature for forming the precursor isolation film is in the range of 40 ℃ to 90 ℃; and in the step of carrying out water vapor annealing treatment on the film precursor, the annealing temperature of the water vapor annealing treatment is in the range of 350 ℃ to 850 ℃, and the annealing time is in the range of 10 minutes to 120 minutes.
The annealing temperature of the water vapor annealing is lower and far lower than the melting point of the stress layer 130, so that the stress release and shrinkage phenomena of the stress layer 130 are less likely to occur, and the influence on the quality and the performance of the stress layer 130 is limited.
And the second annealing treatment is used for converting the precursor isolating film into an interlayer dielectric film. In particular, the method comprises the following steps of,
the step of performing a second annealing process on the precursor isolation film includes: and carrying out second annealing treatment on the precursor isolation film by adopting a rapid annealing mode.
And in the second annealing treatment step of carrying out rapid annealing on the precursor isolation film, the annealing temperature is 950-1100 ℃, the annealing time is 0-20 seconds, and the pressure is one standard atmospheric pressure.
In the step of performing the second annealing treatment on the precursor isolation film by adopting the rapid annealing mode, the annealing time is short, the possibility of causing the stress release and shrinkage phenomena of the stress layer 130 is low,
and therefore has a limited impact on the quality and performance of the stress layer 130.
It should be noted that before the interlayer dielectric layer 140 is formed, a gate mask covers the top of the dummy gate structure 120, and the interlayer dielectric film also covers the gate mask. In the step of removing the interlayer dielectric film higher than the top of the dummy gate structure 120 to expose the dummy gate 122, the interlayer dielectric film higher than the gate mask is removed first, so that the remaining interlayer dielectric film is flush with the surface of the gate mask; and removing the interlayer dielectric layer 140 higher than the dummy gate 122 and the gate mask on the dummy gate 122 to expose the dummy gate 122, and forming the interlayer dielectric layer 140 so that the surface of the interlayer dielectric layer 140 is flush with the dummy gate 122.
Referring to fig. 5, the dummy gate 122 is removed, and an opening (not shown) is formed in the interlayer dielectric layer 140, wherein the oxide layer 121 is exposed at the bottom of the opening.
The opening is used for providing a process space for the subsequent formation of a gate structure and can be formed in a dry etching or wet etching mode.
In this embodiment, the substrate includes the peripheral region 100i and the core region 100 c.
Therefore, in the step of forming the opening, the dummy gate 122 of the dummy gate structure 120 on the substrate of the peripheral region 100i is removed, a first opening 151 is formed in the interlayer dielectric layer 140 on the substrate of the peripheral region 100i, and the oxide layer 121 on the substrate of the peripheral region 100i is exposed at the bottom of the first opening 151. In this embodiment, the oxide layer 121 on the fin 110 in the peripheral region 100i is exposed at the bottom of the first opening 151.
It should be noted that, because the core device and the input/output device have different operating voltages, the gate dielectric layers of the core device and the input/output device have different thicknesses. Specifically, the thickness of the gate dielectric layer of the input/output device is greater than that of the gate dielectric layer of the core device, so the oxide layer 121 on the fin 110 in the peripheral region 100i is reserved in the subsequent process and is used as a part of the gate dielectric layer of the formed input/output device, so that the formed input/output device has a thicker gate dielectric layer.
Referring to fig. 6, a first annealing process 160 is performed to activate the dopant ions in the source/drain doped region and repair the oxide layer 121 at the bottom of the opening.
Specifically, the first annealing treatment 160 is used to activate the dopant ions in the source/drain doped region and repair the lattice damage in the source/drain doped region. In addition, since the opening is formed in the interlayer dielectric layer 140 before the first annealing treatment 160, and the oxide layer 121 is exposed at the bottom of the opening, the first annealing treatment 160 can also repair the oxide layer 121 at the bottom of the opening, thereby improving the performance of the formed semiconductor structure.
In this embodiment, before the first annealing 160, the oxide layer 121 on the substrate in the peripheral region 100i is exposed at the bottom of the first opening 151 formed in the interlayer dielectric layer 140 on the substrate in the peripheral region 100 i. Therefore, in the first annealing process 160, the oxide layer 121 at the bottom of the first opening 151 is repaired, so that the quality of the oxide layer 121 on the fin portion 110 in the peripheral region 100i is improved, defects in a gate dielectric layer of a subsequently formed input/output device are reduced, and the performance of a formed semiconductor structure is improved.
The step of performing the first annealing 160 includes: in the first annealing treatment process, the proportion of oxygen in the process gas is less than 10 percent by volume. Performing the first annealing treatment in an oxygen atmosphere with a volume percentage of less than 10% can improve the repair capability of the first annealing treatment 160 on the oxide layer 121. Specifically, in the step of performing the first annealing treatment, the process gas includes oxygen and nitrogen.
In the process of performing the first annealing treatment 160, if the oxygen content is too low, the repair capability of the first annealing treatment 160 on the oxide layer 121 cannot be effectively improved; if the oxygen content is too high, it may pose a risk to other semiconductor structures on the substrate 100. In this embodiment, in the step of performing the first annealing treatment, the volume ratio of oxygen to nitrogen in the process gas is in the range of 1:10 to 1: 500.
In addition, the first annealing treatment 160 is adopted for repairing, and an additional heating process is not needed to repair the oxide layer 121 on the fin portion 110 in the peripheral region 100i, so that the quality of the formed gate dielectric layer of the input/output device can be improved, the times of adopting the heating process can be reduced, the process complexity is reduced, and the process stability is improved.
Specifically, the step of performing the first annealing 160 includes: the first annealing process 160 is performed by spike annealing and laser annealing.
In this embodiment, in the step of performing the first annealing treatment 160, doped ions in the source and drain doped regions are activated in a spike annealing manner, and lattice damage of the source and drain doped regions is repaired to suppress channel leakage current; and then activating the doping ions of the source and drain doping regions in a laser annealing mode.
In the process of spike annealing, if the annealing temperature is too high, the melting point of the stress material is easily approached, so that the stress release phenomenon occurs in the stress layer 130, and the contraction field occurs in the stress layer 130, so that the quality of the stress layer 130 is reduced, the performance is degraded, the performance of the formed semiconductor structure is affected, and the adverse effect is easily caused on other semiconductor structures on the substrate 100,
increasing the risk of the process; if the annealing temperature is too low, it is difficult to activate the dopant ions in the source/drain doped region, or the activation efficiency is reduced, thereby affecting the production efficiency. Specifically, in this embodiment, in the step of performing the first annealing 160 by using a spike annealing method, the annealing temperature is in a range of 1000 ℃ to 1050 ℃, and the pressure is a standard atmospheric pressure.
In the process of laser annealing, if the annealing temperature is too high, the melting point of the stress material is easily approached, so that the stress release phenomenon occurs in the stress layer 130, and the contraction field occurs in the stress layer 130, so that the quality of the stress layer 130 is reduced, the performance is degraded, the performance of the formed semiconductor structure is affected, other semiconductor structures on the substrate 100 are easily affected, and the process risk is increased; if the annealing temperature is too low, it is difficult to activate the dopant ions in the source/drain doped region, or the activation efficiency is reduced, thereby affecting the production efficiency. In this embodiment, in the step of performing the first annealing 160 by laser annealing, the annealing temperature is in a range of 1200 ℃ to 1250 ℃.
It should be noted that laser annealing has the advantages of higher annealing temperature and higher annealing speed due to the higher annealing temperature of laser annealingBetter activation efficiency. Specifically, in this embodiment, in the step of performing the first annealing 160 by using the laser annealing method, CO is used2Laser light with a wavelength of 10.6 μm generated by a laser is used for the laser annealing.
It should be noted that, in this embodiment, the first annealing treatment 160 is performed in a sequence of performing spike annealing first and then performing laser annealing. This is merely an example. Other embodiments of the present invention may also employ a sequence of first performing laser annealing and then performing spike annealing to perform the first annealing 160. In addition, in other embodiments of the present invention, only the spike annealing may be used to activate the dopant ions in the source/drain doped region.
In this embodiment, after the first annealing 160 is performed, the forming method further includes: gate structures are formed on the core region 100c fin 110 and the peripheral region 100i fin 110, respectively.
Specifically, the forming process of the gate structure is described in detail below with reference to the accompanying drawings.
Referring to fig. 7 and 8, a protective layer 170 is filled in the first opening 151.
The protection layer 170 is used to protect the oxide layer 121 at the bottom of the first opening 151 and prevent the oxide layer 121 from being affected by the subsequent processes.
Specifically, the step of forming the protective layer 170 includes:
referring to fig. 7, a protective material layer 171 is filled in the first opening 151 (shown in fig. 6), and a top surface of the protective material layer 171 is higher than a surface of the interlayer dielectric layer 140.
In this embodiment, the protective material layer 171 is a Bottom Anti-reflective coating (BARC), and may be formed by a coating process. In other embodiments of the present invention, the protective material Layer 171 may also be a photoresist Layer or an Organic Dielectric Layer (ODL). When the protective material layer 171 is a photoresist layer, it may be formed by a coating process; when the protective material layer 171 is an organic dielectric layer, it may be formed by a film deposition process.
Referring to fig. 8, the protective material layer 171 (shown in fig. 7) above the interlayer dielectric layer 140 is removed, and a protective layer 170 located in the first opening 151 is formed, such that the surface of the protective layer 170 is flush with the surface of the interlayer dielectric layer 140.
The step of removing the protective material layer 171 above the interlayer dielectric layer 140 is used to form a protective layer 170.
In addition, the top surface of the protective material layer 171 is higher than the surface of the interlayer dielectric layer 140, so the protective material layer 171 is also located on the surface of the dummy gate structure 120 on the substrate of the core region 100 c. The step of removing the protective material layer 171 higher than the interlayer dielectric layer 140 is further used to remove the protective material layer 171 on the surface of the dummy gate structure 120 on the substrate of the core region 100c, so as to provide a process operation basis for the subsequent removal of the dummy gate structure 120.
Specifically, the protective material layer 171 higher than the interlayer dielectric layer 140 may be removed by etching back to expose the dummy gate 122 of the dummy gate structure 120 on the substrate of the core region 100 c.
It should be noted that, in the present embodiment, since the protection material layer 171 is a bottom anti-reflection layer, the protection layer 170 is also a bottom anti-reflection layer. In other embodiments of the present invention, the protective material layer may also be a photoresist layer or an organic dielectric layer, so the protective layer may also be a photoresist layer or an organic dielectric layer.
Referring to fig. 9, the dummy gate structure 120 on the substrate of the core region 100c is removed (as shown in fig. 8), a second opening 152 is formed in the interlayer dielectric layer 140 on the substrate of the core region 100c, and the bottom of the second opening 152 exposes the substrate of the core region 100 c.
In this embodiment, the dummy gate structure 120 on the substrate of the core region 100c is removed, a second opening 152 is formed in the interlayer dielectric layer 140 on the substrate of the core region 100c, and the bottom of the second opening 152 exposes the surface of the top and the sidewall of the fin 110 of the core region 100 c.
Specifically, the dummy gate 122 of the dummy gate structure 120 on the fin portion 110 of the core region 100c is removed, and the oxide layer 121 of the dummy gate structure 120 on the fin portion 110 of the core region 100c is exposed; the oxide layer 121 is removed to expose the surface of the top and sidewalls of the fin 110 in the core region 100 c.
Referring to fig. 10, the protection layer 170 is removed (as shown in fig. 9), and a third opening 153 is formed, wherein the oxide layer 121 on the substrate of the peripheral region 100i is exposed at the bottom of the third opening 153.
In this embodiment, the protection layer 170 is removed, a third opening 153 is formed in the interlayer dielectric layer 140 on the substrate of the peripheral region 100i, and the bottom of the third opening 153 exposes the oxide layer 121 on the top and the sidewall of the fin 110 of the peripheral region 100 i.
Since the protection layer 170 is a bottom anti-reflection layer, in this embodiment, the step of removing the protection layer 170 includes: the protective layer 170 is removed by ashing to reduce the possibility of damaging the oxide layer 121 and improve the performance of the formed semiconductor structure.
Specifically, in the step of removing the protective layer 170 by ashing, the process parameters include: the gas pressure is in the range of 200mTorr to 2000mTorr, and the power is in the range of 500W to 4000W; the process temperature is 100 ℃ to 400 ℃; the process gas comprises nitrogen gas and hydrogen gas, wherein the volume of nitrogen gas is in the range of 1000sccm to 10000sccm and the volume of hydrogen gas is in the range of 500sccm to 5000 sccm.
Referring to fig. 11, gate structures are formed in the second opening 152 (shown in fig. 10) and the third opening 153 (shown in fig. 10), respectively.
In the step of forming the gate structure, dielectric layers 182 are respectively formed at the bottoms of the second opening 152 and the third opening 153; a gate electrode 181 is formed on the dielectric layer 182. Specifically, a dielectric layer 182 is formed on the top of part of the fin 110 and on the surface of part of the sidewall of the core region 100c exposed at the bottom of the second opening 152, and a gate electrode 181 is formed on the dielectric layer 182; a dielectric layer 182 is formed on the oxide layer 121 exposed at the bottom of the third opening 153, and a gate electrode 181 is formed on the dielectric layer 182.
In this embodiment, the semiconductor structure has a "high-K metal gate structure". The dielectric layer 182 comprises a high K dielectric layer. The high-K dielectric layer is made of a high-K dielectric material, namely a material with a relative dielectric constant larger than that of silicon oxide, and can be one or more of hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, lanthanum aluminum oxide, yttrium oxide, hafnium oxynitride, zirconium oxynitride, lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, strontium titanium oxynitride, lanthanum aluminum oxynitride and yttrium oxynitride.
The gate electrode 181 is made of metal, and specifically includes copper, tungsten, aluminum, or silver.
Before forming the dielectric layer 182, the forming method further includes forming an Interfacial Layer (IL) at the bottom of the second opening 152 to improve lattice mismatch between the dielectric layer 182 and the surface of the fin 110 in the core region 100 c.
The gate dielectric layer of the gate structure of the core device includes an interfacial layer on a portion of the top and a portion of the sidewall of the fin 110 of the core region 100c and a dielectric layer on the interfacial layer; the gate structure of the core device includes the gate dielectric layer and a gate electrode 181 on the gate dielectric layer.
The gate dielectric layer of the gate structure of the input-output device comprises an oxide layer 121 on the partial top and partial side wall of the fin part 110 of the peripheral region 100i and a dielectric layer on the oxide layer 121; the gate structure of the core device includes the gate dielectric layer and a gate electrode 181 on the gate dielectric layer.
Since the oxide layer 121 on the top and the sidewall of the fin portion 110 of the peripheral region 100i is repaired by the first annealing treatment 160 (as shown in fig. 6), the defects in the oxide layer 121 are fewer, so that the quality of the gate dielectric layer of the gate structure of the input/output device is better, which is beneficial to improving the performance of the formed input/output device and the performance of the formed semiconductor structure.
In summary, according to the technical scheme of the invention, after the source-drain doped region is formed by ion doping the stress layer, the interlayer dielectric layer covering the stress layer is formed; removing the pseudo grid to expose the oxide layer; and then carrying out first annealing treatment to activate the doped ions of the source-drain doped region. The interlayer dielectric layer covers the stress layer, so that the interlayer dielectric layer can play a pressing role on the stress layer, can inhibit the stress layer from releasing stress in the first annealing treatment process, and can inhibit the stress layer from shrinking in the first annealing treatment process. And the first annealing treatment can activate the doped ions in the source-drain doped region and repair the exposed oxide layer, so that the heating process in the forming process of the semiconductor structure is reduced, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
forming a substrate;
forming a pseudo gate structure on the substrate, wherein the pseudo gate structure comprises an oxide layer positioned on the substrate and a pseudo gate positioned on the oxide layer;
forming stress layers in the substrate on two sides of the pseudo gate structure;
carrying out ion doping on the stress layer to form a source drain doped region;
forming an interlayer dielectric layer covering the stress layer, wherein the top surface of the interlayer dielectric layer is exposed out of the pseudo gate;
removing the pseudo grid electrode, forming an opening in the interlayer dielectric layer, and exposing the oxide layer at the bottom of the opening;
and after the opening is formed, carrying out first annealing treatment to activate the doped ions of the source-drain doped region and repair the oxide layer at the bottom of the opening.
2. The method of forming as claimed in claim 1, wherein the step of performing a first annealing process comprises: and carrying out the first annealing treatment in a spike annealing mode.
3. The method of forming as claimed in claim 1, wherein the step of performing a first annealing process comprises: and carrying out the first annealing treatment by adopting a spike annealing mode and a laser annealing mode.
4. The method of claim 2 or 3, wherein the step of performing the first annealing process by spike annealing is performed at an annealing temperature in a range of 1000 ℃ to 1050 ℃ and at a pressure of one standard atmosphere.
5. The method of forming as claimed in claim 4, wherein the step of performing the first annealing process includes: in the first annealing treatment process, the proportion of oxygen in the process gas is less than 10 percent by volume.
6. The forming method of claim 5, wherein in the step of performing the first annealing process, process gases include oxygen and nitrogen.
7. The forming method according to claim 6, wherein in the step of performing the first annealing treatment, a volume ratio of oxygen to nitrogen in a process gas is in a range of 1:10 to 1: 500.
8. The method of claim 3, wherein the step of performing the first annealing process by laser annealing is performed at an annealing temperature in a range of 1200 ℃ to 1250 ℃.
9. The method according to claim 1, wherein in the step of forming the interlayer dielectric layer, the interlayer dielectric layer is made of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
10. As in claimThe method of claim 1, wherein in the step of forming the interlayer dielectric layer, the interlayer dielectric layer has a thickness of
Figure FDA0002443787010000021
To
Figure FDA0002443787010000022
Within the range.
11. The method of forming of claim 1, wherein forming the interlevel dielectric layer comprises:
forming a precursor isolation film covering the stress layer on the substrate, wherein the precursor isolation film also covers the pseudo gate structure;
carrying out second annealing treatment on the precursor isolating film, and converting the precursor isolating film into an interlayer dielectric film;
and removing the interlayer dielectric film higher than the top of the dummy gate structure by adopting a planarization process to expose the dummy gate and form the interlayer dielectric layer.
12. The method of claim 11, wherein the step of performing a second annealing process on the precursor isolation film comprises: and carrying out second annealing treatment on the precursor isolation film by adopting a rapid annealing mode.
13. The method of claim 12, wherein the precursor isolation film is subjected to a second annealing step by a rapid anneal at a temperature of 950 ℃ to 1100 ℃ for a time of 0 seconds to 20 seconds at a pressure of one atm.
14. The method of forming of claim 1, wherein the substrate is used to form an N-type transistor; in the step of forming the stress layer, the stress layer is made of SiC, SiP or SiCP;
or, the substrate is used for forming a P-type transistor, and the stress layer is made of SiGe, SiB or SiGeB.
15. The method of claim 1, wherein the substrate is used to form a fin field effect transistor;
in the step of forming the base, the base comprises a substrate and a discrete fin part positioned on the substrate;
in the step of forming the dummy gate structure, forming the dummy gate structure which crosses the fin part and covers part of the top of the fin part and part of the surface of the side wall;
and in the step of forming the stress layer, forming the stress layer in the fin parts at two sides of the pseudo gate structure.
16. The method of claim 15, wherein the step of forming the stress layer in the fin portions on both sides of the dummy gate structure comprises:
forming grooves in the fin parts on two sides of the pseudo gate structure;
and forming the stress layer in the groove by adopting a selective epitaxy process.
17. The method of claim 16, wherein the step of forming source and drain doped regions comprises: and carrying out in-situ self-doping in the process of forming the stress layer in the fin parts at two sides of the pseudo gate structure to form the source-drain doped region.
18. The method of forming of claim 1, wherein in the step of forming a substrate, the substrate includes a peripheral region for forming input-output devices and a core region for forming core devices;
in the step of forming the opening, removing the pseudo gate of the pseudo gate structure on the substrate of the peripheral region, forming a first opening in the interlayer dielectric layer on the substrate of the peripheral region, and exposing the oxide layer on the substrate of the peripheral region at the bottom of the first opening;
repairing the oxide layer at the bottom of the first opening in the process of carrying out first annealing treatment;
after the first annealing treatment is performed, the forming method further includes:
filling a protective layer in the first opening;
removing the pseudo gate structure on the core region substrate, and forming a second opening in the interlayer dielectric layer on the core region substrate, wherein the bottom of the second opening is exposed out of the core region substrate;
removing the protective layer to form a third opening, wherein the bottom of the third opening exposes the oxide layer on the substrate of the peripheral area;
and respectively forming a gate structure in the second opening and the third opening.
19. The method as claimed in claim 18, wherein in the step of filling the first opening with a protective layer, the protective layer is a bottom anti-reflection layer, a photoresist layer or an organic dielectric layer.
20. The method of forming of claim 18, wherein the step of removing the protective layer comprises:
and removing the protective layer by ashing.
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CN103594365A (en) * 2012-08-14 2014-02-19 中芯国际集成电路制造(上海)有限公司 A method for forming a PMOS transistor
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