CN110098151B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN110098151B CN110098151B CN201810097227.0A CN201810097227A CN110098151B CN 110098151 B CN110098151 B CN 110098151B CN 201810097227 A CN201810097227 A CN 201810097227A CN 110098151 B CN110098151 B CN 110098151B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device and a method of forming the same, the method comprising: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part and a first grid structure crossing the first fin part; forming a first doping layer on the side wall and the top surface of the first fin part at two sides of the first grid structure, wherein the first doping layer is internally provided with first doping ions; and performing first annealing treatment to enable first doping ions in the first doping layer to enter the fin portion, and forming a first lightly doped region in the first fin portion. The method improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, the performance of the semiconductor device formed by the existing method for forming the semiconductor device is poor.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can optimize the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part and a first grid structure crossing the first fin part; forming a first doping layer on the side wall and the top surface of the first fin part at two sides of the first grid structure, wherein the first doping layer is internally provided with first doping ions; performing first annealing treatment to enable first doping ions in the first doping layer to enter the fin portion, and forming a first lightly doped region in the first fin portion;
optionally, the method further includes: before the first doping layer is formed, forming a protective side wall on the side wall of the first gate structure; the forming method of the protective side wall comprises the following steps: forming an initial protection layer on the semiconductor substrate, wherein the initial protection layer covers the side wall and the top surface of the first grid structure and the side wall and the top surface of the first fin part; and removing the first fin part side walls on two sides of the first grid structure and the initial protection layer on the top, and forming protection side walls on the side walls of the first grid structure.
Optionally, the method further includes: and after the first annealing treatment, forming a first source drain doping layer in the first gate structure and the first fin parts at two sides of the protective side wall.
Optionally, the method for forming the first source-drain doping layer includes: after the first annealing treatment, forming first grooves in the first gate structure and the first fin parts on two sides of the protective side wall; and forming a first source drain doped layer in the first groove.
Optionally, the method for forming the source-drain doping layer further includes: after the first annealing treatment and before the first groove is formed, etching back the first doping layer, and forming a first sacrificial layer on the side wall of the first fin part; after the first sacrificial layer is formed, removing the first grid structure and the first fin parts on two sides of the protective side wall to form a first groove, wherein the side wall of the first groove exposes out of the first sacrificial layer; forming a first source drain doping layer in the first groove; and removing the first sacrificial layer after the first source-drain doped layer is formed.
Optionally, the process of forming the first doping layer includes a deposition process; the process of doping the first doping ions in the first doping layer is an in-situ doping process.
Optionally, when the first gate structure is used to form an N-type device, the material of the first doping layer includes silicon oxide and silicon nitride; the first doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
Optionally, the thickness of the first doped layer is 10to 50 angstroms,
optionally, the first doping ion is a phosphorus ion, and the concentration of the phosphorus ion in the first doping layer is 1.0E18atm/cm3～1.0E21atm/cm3。
Optionally, when the first gate structure is used for forming a P-type device, the material of the first doping layer includes silicon oxide and silicon nitride; the first doping ions are P-type ions and comprise boron ions and BF2-Ions or indium ions.
Optionally, the thickness of the first doped layer is 20 to 80 angstroms.
Optionally, the first doping ion is a boron ion, and the concentration of the boron ion in the first doping layer is 1.0E19atm/cm3～2.5E22atm/cm3。
Optionally, the parameters of the first annealing treatment include: the temperature range of the annealing treatment is 900-1100 ℃, the time of the annealing treatment is 0-20 seconds, the gas used in the annealing treatment is nitrogen, and the flow range of the nitrogen is 10-1000 sccm.
Optionally, the semiconductor substrate includes a first region and a second region, and the types of semiconductor devices formed in the first region and the second region are opposite; the first fin portion and the first grid electrode structure are located in a first region of the semiconductor substrate, the second region of the semiconductor substrate is further provided with a second fin portion, and a second grid electrode structure crossing the second fin portion is arranged on the second fin portion.
Optionally, the initial protection layer is further located on the sidewall and the top surface of the second fin portion and the sidewall and the top surface of the second gate structure, and after the protective sidewall is formed, a portion of the initial protection layer located on the second region becomes a protection layer.
Optionally, the method for removing the initial protection layer on the sidewalls and the top of the first fin portions on the two sides of the first gate structure includes: forming a first patterning layer on the initial protection layer, wherein the first patterning layer exposes the position of a first region of the semiconductor substrate; etching the initial protection layer back by taking the first patterning layer as a mask until the first fin part and the top surface of the first grid electrode structure are exposed, and forming an initial protection side wall on the side wall of the first grid electrode structure and the side wall of the first fin part; after the initial protective side wall is formed, forming a second patterned layer on the first fin portion, the first grid structure, the second fin portion and the second grid structure; and the second patterning layer exposes the position of the initial protective side wall of the first fin part side wall, and the second patterning layer is used as a mask to etch and remove the initial protective side wall of the first fin part side wall and expose the first grid structure, the first fin part side wall on two sides of the protective side wall and the top surface.
Optionally, after forming the first source-drain doping layer on the first region, forming a second source-drain doping layer on the second region, where the forming of the second source-drain doping layer includes: after the first sacrificial layer is removed, forming a second protective layer on the first fin portion, the first grid structure, the first source drain doping layer, the second fin portion and the second grid structure; removing the side walls of the second fin parts at two sides of the second grid electrode structure on the second area and the second protective layer at the top; after removing the second fin part side walls on two sides of the second gate structure and the second protection layer on the top on the second region, forming second doping layers on the second fin part side walls on two sides of the second gate structure and the surface of the top, wherein the second doping layers have second doping ions; performing second annealing treatment on the second doping layer and the second fin portion, so that second doping ions in the second doping layer enter the second fin portion to form a second lightly doped region; and after the second annealing treatment, forming a second groove in the second fin parts at two sides of the second gate structure, and forming a second source drain doping layer in the second groove.
The invention also provides a semiconductor device formed by any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the technical scheme, the first doping layer is formed on the first fin portion on two sides of the first grid electrode structure, the first doping layer is internally provided with first doping ions, and the first doping ions are driven to diffuse into the first fin portion through first annealing treatment to form the first light doping area. Since the first doping ions are diffused in disorder and move in all directions, the first lightly doped region close to the first gate structure can be formed. The first annealing treatment is disordered diffusion carried out by thermally driving the first doping ions, the energy carried by the first doping ions is small, the damage to the first fin portion is small, meanwhile, the thermal annealing can repair the damage defect in the first fin portion, the lattice state in the first fin portion is improved, and therefore the performance of the device is improved.
Drawings
Fig. 1 to 16 are schematic structural views illustrating a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, as the density of semiconductor devices increases and the size decreases, the performance of semiconductor devices still remains to be improved.
A method of forming a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of fin parts; forming an isolation structure on the semiconductor substrate, wherein the isolation structure covers the side wall of the fin part; forming a grid electrode structure crossing the fin part on the fin part, wherein the grid electrode structure covers part of the side wall and the top surface of the fin part; forming first side walls on two sides of the grid structure, wherein the first side walls cover the side walls of the grid structure; after the first side wall is formed, ion implantation is carried out on a lightly doped region formed on the fin portion, a lightly doped region is formed, after the lightly doped region is formed, a second side wall is formed on the grid structure and the side wall of the first side wall, and grooves are formed on two sides of the grid structure and the second side wall; and epitaxially forming a source-drain doped layer in the groove.
However, the performance of the semiconductor device formed by the method is poor, in the above embodiment, with the development of semiconductor technology, the dimension of the fin portion in the width direction is smaller and smaller, the ion implantation is directly performed on the exposed lightly doped region of the fin portion, the energy bombardment of the ion implantation easily causes that part of crystal lattices of the fin portion are changed from a single crystal state to an amorphous state, the atomic arrangement is changed from a regular arrangement to a disordered state, and the fin portion is damaged; meanwhile, the thermal effect of annealing treatment can be that under the condition that the single crystalline state of the complete crystal lattice is dominant, the fin part which is not subjected to ion implantation is in the single crystalline state, and the fin part in the amorphous state is recrystallized on the basis of the fin part in the single crystalline state.
In order to solve the technical problem, according to the technical scheme of the invention, the doping layer is formed on the fin part, and the ion doping of the lightly doped region of the fin part is realized in a solid source doping mode, so that the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 16 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 1 and 2, region I in fig. 2 is a cross-sectional view taken along the direction M-M1 in fig. 1, and region II in fig. 2 is a cross-sectional view taken along the direction M2-M3 in fig. 3, providing a semiconductor substrate 200.
The semiconductor substrate 200 includes a first region I and a second region II, the first region I has a first fin portion 211 on the semiconductor substrate 200, and the second region II has a second fin portion 212 on the semiconductor substrate 200. The semiconductor substrate 200 further has an isolation structure 201 thereon, and the isolation structure 201 covers a portion of sidewalls of the first fin portion 211 and the second fin portion 212.
The first region I is used for forming a P type device, the second region II is used for forming an N type device, and the first region I is used for forming an N type device, and the second region II is used for forming a P type device.
In this embodiment, the first region I is used to form an N-type finfet, and the second region II is used to form a P-type finfet.
The material of the semiconductor substrate 200 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and the like, wherein the silicon material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 200 can also be a semiconductor-on-insulator structure including an insulator and a semiconductor material layer on the insulator, wherein the semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and the like.
In this embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.
In this embodiment, the first fin portion 211 and the second fin portion 212 are formed by patterning the semiconductor substrate 200. In other embodiments, it may be: a fin material layer is formed on the semiconductor substrate, and then patterned, thereby forming the first fin 211 and the second fin 212.
In this embodiment, the material of the first fin portion 211 and the second fin portion 212 is monocrystalline silicon. In other embodiments, the material of the first fin 211 and the second fin 212 is single crystal silicon germanium or other semiconductor materials.
The step of forming the isolation structure 201 includes: forming an initial isolation film (not shown) on the substrate 200, the initial isolation film covering top surfaces of the first and second fins 211 and 212; planarizing the initial isolation film until the surfaces of the tops of the first fin portion 211 and the second fin portion 212 are exposed; and etching back the initial isolation film to expose partial side walls of the first fin portion 211 and the second fin portion 212, thereby forming the isolation structure 201. The isolation structure 201 is used to electrically isolate the first fin portion 211 and the second fin portion 212.
The material of the initial isolation film comprises silicon oxide or silicon nitride.
In this embodiment, the material of the initial isolation film is silicon oxide; the thickness of the initial isolation film after the back etching is 1/4-1/2 of the height of the first fin portion 211 and the height of the second fin portion 212. The formation process of the initial isolation film is a Fluid Chemical Vapor Deposition (FCVD).
In other embodiments, the initial isolation film can also employ a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
The planarization process is a chemical mechanical polishing process (CMP); in the present embodiment, the chemical mechanical polishing process is performed until the top surfaces of the first and second fins 211 and 212 are exposed.
In this embodiment, the isolation structure 201 is made of silicon oxide.
Referring to fig. 3, the cross-sectional directions of fig. 3 and fig. 2 are the same, a first gate structure 221 crossing over the first fin 211 is formed on the first region I of the semiconductor substrate 200, and the first gate structure 221 crosses over the first fin 211 and covers a portion of the top surface and a portion of the sidewall surface of the first fin 211; a second gate structure 222 crossing the second fin 212 is formed on the second region II of the semiconductor substrate 200, and the second gate structure 222 crosses the second fin 212 and covers a portion of the top surface and a portion of the sidewall surface of the second fin 212.
In this embodiment, the first gate structure 221 includes a first gate dielectric layer crossing the first fin portion 211, a first gate electrode layer on the first gate dielectric layer, and a first gate protection layer on top of the first gate electrode layer. The second gate structure 222 includes a second gate dielectric layer crossing the second fin portion 212, a second gate electrode layer on the gate dielectric layer, and a second gate protection layer on top of the second gate electrode layer. In other embodiments, the first gate protective layer and the second gate protective layer are not formed.
In this embodiment, the first gate dielectric layer and the second gate dielectric layer are made of silicon oxide, and the first gate electrode layer and the second gate electrode layer are made of polysilicon. The first gate protection layer and the second gate protection layer are made of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the first gate structure 221 and the second gate structure 222 are used as dummy gate structures, and a high-K metal gate is formed subsequently to replace the dummy gate structures. In other embodiments, the first gate structure 221 and the second gate structure 222 are used as gate structures of the device.
Referring to fig. 4, after the first gate structure 221 and the second gate structure 222 are formed, a first sidewall 231 is formed on a sidewall of the first gate structure 221, and a second sidewall 232 is formed on a sidewall of the second gate structure 222.
The first sidewall spacers 231 protect sidewalls of the first gate layer, and the second sidewall spacers 232 protect sidewalls of the second gate layer.
The forming steps of the first side wall 231 and the second side wall 232 include: forming a first sidewall material layer on the first fin portion 211, the first gate structure 221, the second fin portion 212 and the second gate structure 222 of the isolation structure 201, wherein the first sidewall material layer covers a part of the sidewall surface and a part of the top surface of the first fin portion 211, the sidewall surface and the top surface of the first gate structure 221, a part of the sidewall surface and a part of the top surface of the second fin portion 212, and the sidewall surface and the top surface of the second gate structure 222; and etching the first sidewall material layer back until the top surfaces of the first fin portion 211, the second fin portion 212, the first gate protection layer and the second gate protection layer are exposed, forming a first sidewall 231 covering the sidewall of the first gate structure 221 on the first fin portion 211, and forming a second sidewall 232 covering the sidewall of the second gate structure 222 on the second fin portion 212.
The forming process of the first side wall material layer is one or more of a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The first side wall material layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the forming process of the first sidewall material layer is a chemical vapor deposition process. The material of the first sidewall 231 and the second sidewall 232 is silicon nitride.
Referring to fig. 5 and 6, fig. 5 is a cross-sectional view taken along a direction of N-N1 in fig. 5, and fig. 6 is a cross-sectional view taken along a direction of N-N1 in fig. 5, after forming the first and second sidewalls 231 and 232, an initial protection layer 240 is formed on the first fin portion 211, the first gate structure 221, the second fin portion 212, and the second gate structure 222 of the isolation structure 201.
In this embodiment, the first region I and the second region II are different in formed devices, and in the process of forming the N-type finfet on the first region I, the initial protection layer 240 is used to form a protection layer to protect the second gate structure 222 and the second fin portion 212 on the second region II, and simultaneously form a protective sidewall on a sidewall of the first gate structure 221 to protect the first gate structure 221.
The material of the initial protective layer 240 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The process of forming the initial protection layer 240 is a deposition process, such as an atomic layer deposition process or a plasma chemical vapor deposition process.
In this embodiment, the initial protection layer 240 is made of silicon nitride.
The thickness of the initial protective layer 240 is 20 to 200 angstroms.
The thickness of the initial protection layer 240 is greater than 200 angstroms, the thickness of the formed protection side wall 241 is thicker, the subsequent first lightly doped region is farther from the trench region, the distance of the first doped ions needing to be laterally diffused is farther, and the formation of the first lightly doped region is not facilitated; the thickness of the initial protection layer 240 is less than 20 angstroms, the distance between the source-drain doping layer and the channel region formed subsequently is too short, and the short channel effect is obvious.
The process of the initial protection layer 240 is an atomic layer deposition process, and the parameters of the atomic layer deposition process include: the gas used is SiH2Cl2And NH3The flow rate of the mixed gas is 1500 sccm-4000 sccm, the pressure is 1 mtorr-10 mtorr, the temperature is 200 ℃ to 600 ℃, and the deposition times are 30 to 300 times.
Referring to fig. 7 and 8, fig. 7 is a cross-sectional view taken along a direction of N-N1 in fig. 5, and fig. 8 is a cross-sectional view taken along a direction of N-N1 in fig. 7. after the formation of the initial protection layer 240, the sidewalls of the first fin portions 211 and the initial protection layer 240 on the top surface at two sides of the first gate structure 221 in the first region I are removed, and protective sidewalls 241 are formed on the sidewalls of the first gate structure 221.
The step of removing the protection layer on the sidewalls and the top of the first fin 211 at the two sides of the first gate structure 221 includes: etching back the initial protection layer 240 on the first region I, and forming an initial protection sidewall on the sidewalls of the first gate structure 221 and the first fin portion 211; after the initial protective sidewall is formed, the initial protective sidewall on the sidewall of the first fin portion 211 is removed to expose the sidewall and the top surface of the first fin portion 211 on both sides of the first gate structure 221, and a protective sidewall 241 is formed on the sidewall of the first gate structure 221.
The protective sidewall 241 defines the position of the subsequently formed first source-drain doped layer, and can protect the first gate structure 221.
The step of etching back the initial protection layer 240 on the first region I includes: forming a first patterning layer (not shown) on the initial protection layer 240, wherein the first patterning layer exposes the first region I of the semiconductor substrate, etching the initial protection layer 240 by using the first patterning layer (not shown) as a mask to expose the top surface of the first gate structure 221 and the top surface of the first fin portion 211, and forming an initial protection sidewall on the sidewall of the first fin portion 211 and the sidewall of the first gate structure 221.
The process for etching back the initial protection layer 240 on the first region I is a dry etching process, and the dry etching process parameters include: the gas used comprises CF4Gas, CH3F gas and O2，CF4The flow rate of the gas is 5 sccm-100 sccm, CH3The flow rate of the F gas is 8sccm to 50sccm, and O2The flow rate of the gas source is 10-100 sccm, the pressure of the chamber is 10-2000 mtorr, the radio frequency power is 50-300W, the voltage is 30-100V, and the time is 4-50 seconds.
The step of removing the initial protective sidewall on the sidewall of the first fin 211 includes: forming a second patterned layer (shown in the figure) on the first fin portion 211, the first gate structure 221, the second fin portion 212 and the second gate structure 222, wherein the second patterned layer exposes the position of the initial protective sidewall on the sidewall of the first fin portion 211; and etching and removing the initial protective sidewall on the sidewall of the first fin portion 211 by using the second patterning layer as a mask to expose the top surface of the isolation structure 201.
The process of removing the initial protective sidewall on the sidewall of the first fin portion 211 is a dry etching process, and the dry etching process parameters include: the gas used comprises CH3F gas, N2And O2，CH3The flow rate of the F gas is 8sccm to 50sccm, N2The flow rate of the gas was 200sccm, O2The flow rate of the gas is 10sccm, the pressure of the chamber is 10-200 mtorr, the radio frequency power is 100W, the voltage is 30-100V, and the time is 4-50 seconds.
In the process of removing the sidewalls and the top of the first fin 211 at the two sides of the first gate structure 221, the initial passivation layer 240 on the second region II is not removed to become the passivation layer 242 on the second region II.
In this embodiment, the types of the semiconductor devices formed in the first region I and the second region II are different, and in the process of forming the semiconductor device in the first region I, the initial protection layer is a protection layer formed on the second region II to protect the second fin portion and the second gate structure. In other embodiments, when the types of the semiconductor devices formed in the first region I and the second region II are the same, the semiconductor device on the second region II is also formed in the process of forming the semiconductor device on the first region I without forming a protective layer on the second region II.
Referring to fig. 9 and 10, fig. 9 is a cross-sectional view taken along the direction of N-N1 in fig. 9, and fig. 10 is a cross-sectional view taken along the direction of N-N1 in fig. 9, after removing the initial passivation layer 240 on the sidewall and top surface of the first fin 211 on both sides of the first gate structure 221 and the protective sidewall 241 in the first region I, the first doping layer 204 is formed on the surface of the passivation layer 242 on the second region II, the isolation structure 201 on the first region I, the first fin 211, and the first gate structure 221. The first doping layer 204 covers a portion of the sidewalls and the top surface of the first fin 221.
The first doped layer 204 has first doping ions.
When the first gate structure 221 is used for forming a P-type device, the material of the first doping layer 204 includes silicon oxide and silicon nitride; the first doping ions are P-type ions and comprise boron ions and BF2-Ions or indium ions.
When the first gate structure 221 is used to form an N-type device, the material of the first doped layer 204 includes silicon oxide and silicon nitride; the first doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
In this embodiment, the first region I is used for forming an N-type finfet. The first fin portion 221 is made of silicon, the first doping layer 204 is made of silicon oxide, and the first doping ions are phosphorus ions.
The thickness of the first doped layer 204 is 10to 50 angstroms. The concentration of phosphorus-containing ions in the first doped layer 204 is 1.0E18atm/cm3～1.0E21atm/cm3。
The formation process of the first doping layer 204 includes: a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the first doping layer 204 is formed by a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are as follows: introducing an organic precursor gas containing Si and O into the reactor under the conditions of 200-700 ℃ and 5-50 torr of pressure intensity3Gas, pH3The flow rate of the catalyst is 20sccm to 5000sccm, and the process times are 5 times to 100 times.
In other embodiments, the first region I is used for forming a P-type finfet. The first fin portion 221 is made of silicon, the first doping layer 206 is made of silicon oxide, and the first doping ions are boron ions.
The thickness of the first doped layer 204 is 20 to 80 angstroms. The dosage of boron-containing ions in the first doped layer 204 is 1.0E19atm/cm3～2.5E22atm/cm3。
Forming the first doped layer 204 using a chemical vapor deposition process, the chemistry beingThe parameters of the vapor deposition process were: introducing BH into organic precursor gas containing Si and O at 200-700 deg.c and 5-50 torr3Gas, BH3The flow rate of the catalyst is 10sccm to 2000sccm, and the process times are 5 times to 100 times.
The concentration of the first doping ions in the first doping layer 204 is too low to meet the ion concentration requirement for forming the first lightly doped region; the first doping layer 204 has too high concentration of the first doping ions, the lateral diffusion distance of the first doping ions is too large, and the number of the first doping ions entering the fin channel region is too large, so that the first doping ions are easy to conduct and not beneficial to the performance of the device.
Since the first doping layer 204 is doped with the first doping ions through the in-situ doping process, the first doping layer 204 and the first fin portion 211 are subsequently annealed, the first doping ions are driven by thermal power in the annealing process to enter the first fin portion 211, and since the diffusion of the ions is disordered, the first doping ions also diffuse into the first fin portion 211 located below the first side wall 231 and the protective side wall 241 of the first gate structure 221 side wall to form a first lightly doped region. Since the first doped ions enter the first fin portion 211 through diffusion movement, the crystal lattice of the first fin portion 211 is not affected, damage to the first fin portion 211 is small, and meanwhile, the crystal lattice damage of the first fin portion 211 can be repaired, so that the performance of the device is improved.
Referring to fig. 11, after the first doping layer 204 is formed, the first fin 221 is annealed to make the first doping ions in the first doping layer 204 enter the first fin 211 to form a first lightly doped region, with the cross-sectional directions of fig. 11 and 9 being the same.
The first annealing process is used to drive the first dopant ions in the first dopant layer 204 into the first fin 211, and since the first dopant ions are randomly diffused and move in all directions, a first lightly doped region close to the first gate structure 221 may be formed. The first annealing treatment is disordered diffusion performed by thermally driving the first doping ions, the energy carried by the first doping ions is small, damage to the first fin portion 211 is small, and meanwhile, damage defects in the first fin portion 211 can be repaired through thermal annealing, so that the lattice state in the first fin portion 211 is improved, and the performance of the device is improved.
The first annealing treatment may be rapid thermal annealing, laser annealing, spike annealing, or furnace tube annealing. In this embodiment, the first annealing process is rapid thermal annealing. The temperature range of the annealing treatment is 900-1100 ℃, the time of the annealing treatment is 0-20 seconds, the gas used in the annealing treatment is nitrogen, and the flow range of the nitrogen is 10-1000 sccm.
In one embodiment, laser annealing is used, the annealing temperature ranges from 1000 ℃ to 1350 ℃, and the annealing time ranges from 40 milliseconds to 100 milliseconds.
The first annealing treatment is short in time, small in damage to the first fin portion 211, high in temperature and enough for the first doping ions to diffuse into the first fin portion 211 at the bottom of the first gate structure to form a first lightly doped region, and meanwhile, the crystal lattice damage of the first fin portion 211 can be repaired, the crystal lattice state in the first fin portion 211 is improved, and therefore the performance of the device is improved.
Referring to fig. 12, the cross-sectional direction of fig. 12 is the same as that of fig. 10, and after the first annealing treatment, the first doping layer 204 is etched back to form a first sacrificial layer 251 on the sidewall of the first fin portion 221.
The first doping layer 204 is etched back, and a second sacrificial layer 252 is further formed on the sidewall of the protection layer 241 on the sidewall of the second fin 222.
The first sacrificial layer 251 is also located on the sidewall of the first gate structure 221, and the second sacrificial layer 252 is also located on the sidewall of the second gate structure 222.
The first sacrificial layer 251 limits the growth direction of the bottom of the first source-drain doping layer 261 formed subsequently, so that the size of the bottom of the first source-drain doping layer 261 in the width direction of the first fin portion 211 is small, the growth rate of the first source-drain doping layer 261 formed subsequently in the width direction of the first fin portion 211 is slow, and under the condition that the width of the first fin portion 211 is small, the adjacent source-drain doping layers are prevented from being connected, so that electric leakage is avoided, and the performance of a device is influenced.
The process of etching back the first doped layer 204 is anisotropic dry etching, and the dry etching parameters include: the gas used comprises CH4Gas, CHF3Gas, CH4The flow rate of the gas is 8sccm to 500sccm, CHF3The flow rate of the gas is 30 sccm-200 sccm, the pressure of the chamber is 10 mtorr-2000 mtorr, the radio frequency power is 100W-1300W, the voltage is 80V-500V, and the time is 4 seconds-50 seconds.
Referring to fig. 13, after forming the first sacrificial layer 251, a first groove 205 is formed in the first fin 211 at two sides of the first gate structure 221 and the protective sidewall 241.
The first groove 205 provides a space for the subsequent formation of the first source-drain doping layer 261.
Specifically, the first gate structure 221 and the first fin portion 211 on two sides of the protective sidewall 241 are etched, a first groove 205 is formed in the first fin portion 211, and the first sacrificial layer 251 is located on a sidewall of the first groove 205.
The first gate structure 221 and the first fin portions 211 on the two sides of the protective sidewall 241 are etched, a process of forming the first groove 205 in the first fin portions 211 is a dry etching process, and the process parameters include: the first stage using CF4And H2Mixed gas of gases, CF4The flow rate is 10sccm to 30sccm, H2The flow rate is 10 sccm-30 sccm, the time is 7s, and the temperature is 70 ℃; second stage using a channel comprising CH3F gas, O2Mixed gas of He and CH3F flow rate is 60 sccm-200 sccm, O2The flow rate is 50 sccm-115 sccm, the He flow rate is 50 sccm-200 sccm, the time is 5 seconds-100 seconds, and the temperature is 35 ℃ to 75 ℃.
Referring to fig. 14, after the first recess 205 is formed, a first source-drain doping layer 261 is formed in the first recess 205.
The process of forming the first source-drain doping layer 261 is an epitaxial growth process. In the process of forming the first source-drain doping layer 261 through epitaxial growth, in-situ doping is further performed on the first source-drain doping layer 261, and the doping ions are first source-drain ions.
When the first gate structure is used for forming a P-type device, the material of the first source-drain doping layer 261 includes silicon germanium doped with first source-drain doping ions, and the conductivity type of the first source-drain doping ions is P-type; when the first gate structure is used to form an N-type device, the material of the first source-drain doping layer 261 includes silicon doped with first source-drain doping ions, and the conductivity type of the first source-drain doping ions is N-type.
In this embodiment, the first region I is used to form an N-type device, the first source-drain doping layer 261 is made of silicon doped with phosphorus ions, and the first source-drain ions are phosphorus ions.
In an embodiment, the first region I is used to form a P-type device, the material of the first source-drain doping layer 261 is silicon germanium doped with boron ions, and the first source-drain ions are boron ions.
Referring to fig. 15, after the first source-drain doping layer 261 is formed, the first sacrificial layer 251 on the sidewall of the first fin 211 is removed.
In this embodiment, the first sacrificial layer 251 on the sidewall of the first fin portion 211 is removed, and the second sacrificial layer 252 on the sidewall of the protection layer 242 on the sidewall of the second fin portion 212 is also removed. In other embodiments, the second sacrificial layer 252 on the sidewalls of the protection layer 242 on the sidewalls of the second fins 212 may not be removed.
The process of removing the first sacrificial layer 251 on the sidewall of the first fin portion 211 is a wet etching process, and parameters of the wet etching process include: the gas used comprises NH3Gas, NF3Gas and He, NH3The flow rate of the gas is 200 sccm-500 sccm, NF3The flow rate of the gas is 20sccm to 200sccm, the flow rate of the He is 600sccm to 2000sccm, the pressure is 2torr to 10torr, and the time is 20 seconds to 100 seconds.
Referring to fig. 16, after forming the first source-drain doping layer 261 on the first region I, the second source-drain doping layer 262 is formed on the second region II.
The forming step of the second source-drain doping layer 262 includes: after removing the first sacrificial layer 251, forming a second protection layer on the first fin portion 211, the first gate structure 221, the first source-drain doping layer 261, the second fin portion 212, and the second gate structure 222; removing the sidewalls and the second protective layer at the top of the second fin portions 212 at the two sides of the second gate structure 222 in the second region II; after removing the sidewalls of the second fin portions 212 on the two sides of the second gate structure 222 and the second protection layer on the top of the second region II, forming second doping layers on the sidewalls of the second fin portions 212 on the two sides of the second gate structure 222 and the surface of the top of the second fin portions, where the second doping layers have second doping ions; performing second annealing treatment on the second doping layer and the second fin portion 212, so that second doping ions in the second doping layer enter the second fin portion to form a second lightly doped region; and after the second annealing treatment, forming a second groove in the second fin parts at two sides of the second gate structure, and forming a second source drain doping layer in the second groove.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part and a first grid structure crossing the first fin part;
forming a first doping layer on the side wall and the top surface of the first fin part at two sides of the first grid structure, wherein the first doping layer is internally provided with first doping ions;
performing first annealing treatment to enable first doping ions in the first doping layer to enter the fin portion, and forming a first lightly doped region in the first fin portion;
after the first annealing treatment, etching back the first doping layer to form a first sacrificial layer on the side wall of the first fin part;
after the first sacrificial layer is formed, removing the first fin parts on two sides of the first grid structure to form a first groove, wherein the side wall of the first groove is exposed out of the first sacrificial layer;
and forming a first source drain doping layer in the first groove.
2. The method for forming a semiconductor device according to claim 1, further comprising: before the first doping layer is formed, forming a protective side wall on the side wall of the first gate structure; the forming method of the protective side wall comprises the following steps: forming an initial protection layer on the semiconductor substrate, wherein the initial protection layer covers the side wall and the top surface of the first grid structure and the side wall and the top surface of the first fin part; and removing the first fin part side walls on two sides of the first grid structure and the initial protection layer on the top, and forming protection side walls on the side walls of the first grid structure.
3. The method for forming a semiconductor device according to claim 2, further comprising: and after the first annealing treatment, forming a first source drain doping layer in the first gate structure and the first fin parts at two sides of the protective side wall.
4. The method for forming the semiconductor device according to claim 3, wherein the method for forming the first source-drain doping layer comprises: after the first annealing treatment, forming first grooves in the first gate structure and the first fin parts on two sides of the protective side wall; and forming a first source drain doped layer in the first groove.
5. The method for forming the semiconductor device according to claim 4, wherein the method for forming the source-drain doping layer further comprises: and removing the first sacrificial layer after the first source-drain doped layer is formed.
6. The method for forming a semiconductor device according to claim 1, wherein a process of forming the first doping layer includes a deposition process; the process of doping the first doping ions in the first doping layer is an in-situ doping process.
7. The method of claim 1, wherein when the first gate structure is used to form an N-type device, the material of the first doped layer comprises silicon oxide, silicon nitride; the first doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
8. The method for forming a semiconductor device according to claim 7, wherein a thickness of the first doped layer is 10to 50 angstroms.
9. The method for forming a semiconductor device according to claim 8, wherein the first doping ion is a phosphorus ion, and wherein a concentration of the phosphorus ion in the first doping layer is 1.0E18atm/cm3～1.0E21atm/cm3。
10. The method of forming a semiconductor device of claim 1, wherein when the first gate structure is used to form a P-type device, the material of the first doped layer comprises silicon oxide, silicon nitride; the first doping ions are P-type ions and comprise boron ions and BF2-Ions or indium ions.
11. The method for forming a semiconductor device according to claim 10, wherein a thickness of the first doped layer is 20 to 80 angstroms.
12. The method for forming a semiconductor device according to claim 11, wherein the first dopant ions are boron ions, and wherein a concentration of boron ions in the first doped layer is 1.0E19atm/cm3～2.5E22atm/cm3。
13. The method of forming a semiconductor device according to claim 1, wherein the parameters of the first annealing process include: the temperature range of the annealing treatment is 900-1100 ℃, the time of the annealing treatment is 0-20 seconds, the gas used in the annealing treatment is nitrogen, and the flow range of the nitrogen is 10-1000 sccm.
14. The method for forming a semiconductor device according to claim 5, wherein the semiconductor substrate includes a first region and a second region, and types of semiconductor devices formed by the first region and the second region are opposite; the first fin portion and the first grid electrode structure are located in a first region of the semiconductor substrate, the second region of the semiconductor substrate is further provided with a second fin portion, and a second grid electrode structure crossing the second fin portion is arranged on the second fin portion.
15. The method of forming a semiconductor device of claim 14, wherein the initial protective layer is further on sidewalls and a top surface of the second fin and sidewalls and a top surface of the second gate structure, and wherein a portion of the initial protective layer on the second region becomes the protective layer after forming the protective sidewall.
16. The method of forming a semiconductor device of claim 15, wherein removing the initial protection layer on the sidewalls and top of the first fin on both sides of the first gate structure comprises: forming a first patterning layer on the initial protection layer, wherein the first patterning layer exposes the position of a first region of the semiconductor substrate; etching the initial protection layer back by taking the first patterning layer as a mask until the first fin part and the top surface of the first grid electrode structure are exposed, and forming an initial protection side wall on the side wall of the first grid electrode structure and the side wall of the first fin part; after the initial protective side wall is formed, forming a second patterned layer on the first fin portion, the first grid structure, the second fin portion and the second grid structure; and the second patterning layer exposes the position of the initial protective side wall of the first fin part side wall, and the second patterning layer is used as a mask to etch and remove the initial protective side wall of the first fin part side wall and expose the first grid structure, the first fin part side wall on two sides of the protective side wall and the top surface.
17. The method for forming a semiconductor device according to claim 14, wherein after forming the first source-drain doping layer on the first region, the method further comprises forming a second source-drain doping layer on the second region, and the step of forming the second source-drain doping layer comprises: after the first sacrificial layer is removed, forming a second protective layer on the first fin portion, the first grid structure, the first source drain doping layer, the second fin portion and the second grid structure; removing the side walls of the second fin parts at two sides of the second grid electrode structure on the second area and the second protective layer at the top; after removing the second fin part side walls on two sides of the second gate structure and the second protection layer on the top on the second region, forming second doping layers on the second fin part side walls on two sides of the second gate structure and the surface of the top, wherein the second doping layers have second doping ions; performing second annealing treatment on the second doping layer and the second fin portion, so that second doping ions in the second doping layer enter the second fin portion to form a second lightly doped region; and after the second annealing treatment, forming a second groove in the second fin parts at two sides of the second gate structure, and forming a second source drain doping layer in the second groove.
18. A semiconductor device formed by the method of any one of claims 1 through 17.
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