CN112038291A - Manufacturing method of semiconductor device, semiconductor device and electronic equipment - Google Patents

Manufacturing method of semiconductor device, semiconductor device and electronic equipment Download PDF

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Publication number
CN112038291A
CN112038291A CN202010725278.0A CN202010725278A CN112038291A CN 112038291 A CN112038291 A CN 112038291A CN 202010725278 A CN202010725278 A CN 202010725278A CN 112038291 A CN112038291 A CN 112038291A
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China
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material layer
layer
silicon
germanium
trench isolation
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CN202010725278.0A
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Chinese (zh)
Inventor
李永亮
程晓红
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202010725278.0A priority Critical patent/CN112038291A/en
Publication of CN112038291A publication Critical patent/CN112038291A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation

Abstract

The invention discloses a manufacturing method of a semiconductor device, the semiconductor device and electronic equipment, and relates to the technical field of semiconductors, so that process difficulty and compatibility risk cannot be increased while a germanium-silicon channel or a germanium channel is protected. The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor structure; the semiconductor structure is provided with a plurality of fin parts, a groove is formed between every two adjacent fin parts, and each fin part comprises a germanium-silicon material layer or a germanium material layer; forming a shallow trench isolation material layer in the trench; forming a silicon protection layer around the fin portion; and annealing the shallow trench isolation material layer to obtain the shallow trench isolation layer. The semiconductor manufacturing method of the present invention is used for manufacturing the semiconductor device.

Description

Manufacturing method of semiconductor device, semiconductor device and electronic equipment
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device, and an electronic apparatus.
Background
In order to pursue the mobility of the conductive channel of the semiconductor device, the material for forming the conductive channel is often a high mobility germanium-silicon material or a high mobility germanium material. However, when a semiconductor device having a sige or ge high mobility channel is fabricated, if a conventional STI (shallow trench isolation) oxide material is used, the ge element in the sige or ge channel is easily oxidized during the STI annealing process even under the condition of reducing the STI annealing thermal budget. In addition, too low thermal budget for STI annealing may result in poor STI quality, increasing etch rate and reducing reliability. Therefore, how to avoid oxidation of high mobility channel materials such as silicon germanium channels or germanium channels under proper STI anneal thermal pre-patterning conditions has become one of the major challenges limiting their practical applications.
Currently, in order to solve the above problems, a silicon nitride liner layer may be used to isolate the germanium-silicon channel or the germanium channel from the STI oxide layer, so as to protect the germanium-silicon channel or the germanium channel. However, this not only increases the processes of silicon nitride deposition, removal, etc., but also poses a certain risk of process compatibility.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, the semiconductor device and electronic equipment, so that the process difficulty and compatibility risk are not increased while a germanium-silicon channel or a germanium channel is protected.
In a first aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of:
providing a semiconductor structure; the semiconductor structure is provided with a plurality of fin parts, a groove is formed between every two adjacent fin parts, each fin part comprises a channel region, and each channel region comprises a germanium-silicon layer or a germanium layer; (ii) a
Forming a shallow trench isolation material layer in the trench;
forming a silicon protection layer around the fin portion;
and annealing the shallow trench isolation material layer to obtain the shallow trench isolation layer.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention forms the silicon protection layer around the fin part after the shallow trench isolation material layer is formed. And annealing the shallow trench isolation material layer after the silicon protection layer surrounding the fin portion is formed. Compared with the prior art that the germanium element in the channel region is oxidized due to the annealing treatment of the shallow trench isolation material layer, so that the performance of the semiconductor device is influenced, the silicon protection layer formed in the manufacturing method of the semiconductor device can protect the channel region of the fin part in the annealing treatment, and the oxidation effect of the annealing treatment on the channel region of germanium silicon or germanium materials is reduced. Moreover, the protective layer is a silicon protective layer, and a part of the silicon protective layer can form a silicon oxide layer in the annealing treatment of the shallow trench isolation material layer, and the silicon oxide layer is easier to remove compared with a silicon nitride liner layer in the prior art, so that the difficulty in manufacturing a semiconductor device can be reduced.
In a second aspect, the present invention provides a semiconductor device fabricated by the above-described method of fabricating a semiconductor device.
In a third aspect, the present invention provides an electronic apparatus including the above semiconductor device.
The advantageous effects of the second and third aspects and their various implementations in the present invention are the same as those of the first aspect or any possible implementation of the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 2, fig. 6, fig. 10, fig. 15 and fig. 20 are schematic structural diagrams of various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3, fig. 7, fig. 11 and fig. 16 are schematic structural diagrams of various stages of another semiconductor device manufacturing method according to an embodiment of the present invention;
fig. 4, fig. 8, fig. 12, fig. 17, and fig. 19 and fig. 20 are schematic structural diagrams of various stages of another semiconductor device manufacturing method according to an embodiment of the present invention;
fig. 5, 9, 13 and 18 are schematic structural diagrams of stages of a manufacturing method of a semiconductor device according to another embodiment of the present invention;
FIG. 14 is a schematic view of a semiconductor structure with a silicon protection layer formed around a fin according to an embodiment of the present invention;
fig. 21 is a schematic structural view illustrating a third sti material layer formed on the first sti material layer according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
At present, germanium-silicon or germanium high-mobility channel materials are strong candidates for high-mobility conductive channels of semiconductor devices due to higher carrier mobility, reliability and process compatibility. However, in the STI annealing process, the germanium element in the sige or ge high mobility channel may diffuse or undergo an oxidation reaction in the semiconductor device of the sige or ge high mobility channel. Therefore, although the STI annealing temperature is reduced, the thermal stability of the silicon germanium or germanium channel material can be improved, and the diffusion of germanium elements or the oxidation reaction can be relieved. However, too low a temperature may result in poor quality of the STI, and may increase the etching rate and deteriorate reliability. At present, in order to prevent the oxidation reaction of the silicon germanium material or the germanium material, a liner layer formed by a silicon nitride material may be used to isolate the silicon germanium material or the germanium material from the STI, so as to increase the temperature of the STI annealing and obtain better quality of the STI oxide layer.
In order to solve the above technical problem, embodiments of the present invention provide a method for manufacturing a semiconductor device and a semiconductor device. The manufacturing method of the semiconductor device comprises the following steps:
referring to fig. 1, a semiconductor structure is provided. The semiconductor structure 10 has a substrate 101 and a plurality of fins 102 formed on the substrate. There is a trench 20 between two adjacent fins. Each fin includes a layer of silicon germanium material or a layer of germanium material for subsequently forming a channel of a semiconductor device. The semiconductor structure may subsequently be formed into fin-shaped semiconductor devices or gate-all-around semiconductor devices.
Illustratively, referring to fig. 2, the semiconductor structure 10 includes a base 101, and the base 101 may be a first substrate. The fin may include a second substrate 1021 and a channel material layer 1022 which are stacked from bottom to top. At this time, the semiconductor device formed by the semiconductor structure may be a fin-shaped semiconductor device.
Referring to fig. 2, the semiconductor structure may be formed by providing a substrate material layer and forming a front channel material layer on the substrate material layer. The front channel material layer and the substrate material layer are etched to form the fin portion 102. Wherein the unetched part of the substrate material layer forms a base (first substrate) 101. The etched portions of the substrate material layer form a second substrate 1021.
Referring to fig. 2, the first substrate 101 and the second substrate 1021 may be a Silicon substrate, other semiconductor substrates, or an SOI (Silicon-On-Insulator) substrate, which is not limited in this embodiment of the present invention.
Referring to fig. 2, the channel material layer 1022 may be a sige material layer or a ge material layer, wherein the mass percentage of ge element in the sige material layer is greater than 0% and less than 100%.
For example, referring to fig. 3, when the substrate material layer is a silicon material layer, in order to improve lattice matching between the substrate material layer and the front channel material layer and satisfy the stress of the formed channel material layer, a first strain buffer material layer may be formed between the substrate material layer and the front channel material layer.
Referring to fig. 3, the forming process of the semiconductor structure may be: providing a substrate material layer, forming a first strain buffer material layer on the substrate material layer, and forming a front channel material layer on the first strain buffer material layer. The front channel material layer and a portion of the first strain buffer material layer are etched to form the fin 102. The fin 102 includes a channel material layer 1022 formed by etching a pre-channel material layer and a first strain buffer layer 1021 formed by etching a first strain buffer layer. The base 101 includes a substrate 1011 and an unetched portion of a first strain buffer material layer 1012.
Referring to fig. 3, the substrate 1011 may be a Silicon substrate, other semiconductor substrate, or an SOI (Silicon-On-Insulator) substrate, which is not limited in the embodiments of the present invention.
Referring to fig. 3, the channel material layer 1022 may be a sige material layer or a ge material layer, wherein the ge element in the sige material layer is greater than 0% and less than 100% by mass.
Referring to fig. 3, the first strain buffer layer is a germanium-silicon strain buffer layer, and the mass percentage of germanium element in the germanium-silicon strain buffer layer is greater than 0% and less than or equal to 80%. The thickness of the germanium-silicon strain buffer layer can be 0.5um-3 um.
For example: the germanium element mass percentage in the germanium-silicon strain buffer layer is 30%, and the germanium element mass percentage in the germanium-silicon channel material layer is 60%.
For example: the germanium element mass percentage in the germanium-silicon strain buffer layer is 40%, and the germanium element mass percentage in the germanium-silicon channel material layer is 65%.
Referring to fig. 4 and 5, the fin may include a stack of a plurality of channel material layers and a plurality of sacrificial material layers stacked from bottom to top. At this time, the semiconductor device is a gate-all-around semiconductor device.
In order to improve carrier mobility, reliability and process compatibility of the channel layer, the channel material layer may be a germanium-silicon channel material layer or a germanium channel material layer. Meanwhile, in order to obtain nanowires or chips later, a certain etching selection ratio is required between the sacrificial material layer and the channel material layer. For example: the sacrificial material layer may be a silicon sacrificial material layer, or a germanium-silicon sacrificial material layer having a certain etching selection ratio with the germanium-silicon channel material layer or the germanium channel material layer.
It is understood that, in the stack formed by the channel material layer and the sacrificial material layer, the channel material layer may be located on the sacrificial material layer, or the sacrificial material layer may be located on the channel material layer.
Referring to fig. 4, for example: when the channel material layer is located on the sacrificial material layer, the fin includes a stack of a plurality of sacrificial material layers 1022 and channel material layers 1023 stacked from bottom to top.
Referring to fig. 4, the semiconductor structure 10 may be formed by: providing a substrate material layer, then extending a front sacrificial material layer on the substrate material layer, and then extending a front channel material layer on the front sacrificial material layer to form a laminated material layer. And then repeating the steps of forming the front sacrificial layer and the front channel material layer according to specific requirements to form a plurality of laminated material layers. And etching the multilayer laminated material layer and part of the substrate to obtain a substrate and a fin part. Wherein, part of the un-etched substrate material layer forms a first substrate 101, and the first substrate 101 is a base. The etched partial substrate material layer forms a second substrate 1021, and the etched multi-layer laminated material layer forms a multi-layer laminated layer. Each stack layer includes a sacrificial material layer 1022 and a channel material layer 1023 stacked from bottom to top. It is understood that the lamination layer shown in fig. 4 is three layers, but the number of the lamination layer is not limited in the embodiment of the present invention, and may be set according to specific requirements.
Referring to fig. 4, by way of further example: when the sacrificial material layer is located on the channel material layer, the fin includes a stack of multiple layers of channel material 1022 and sacrificial material 1023 stacked from bottom to top.
Referring to fig. 4, the semiconductor structure 10 may be formed by: providing a substrate material layer, then extending a front channel material layer on the substrate material layer, and then extending a front sacrificial material layer on the front channel material layer to form a laminated material layer. The steps of forming the front channel layer and the front sacrificial material layer are then repeated according to specific requirements to form a plurality of stacked material layers. And etching the multilayer laminated material layer and part of the substrate to obtain a substrate and a fin part. Wherein, part of the un-etched substrate material layer forms a first substrate 101, and the first substrate 101 is a base. The etched partial substrate material layer forms a second substrate 1021, and the etched multi-layer laminated material layer forms a multi-layer laminated layer. Each stack layer includes a channel material layer 1022 and a sacrificial material layer 1023 stacked from bottom to top. It is understood that the lamination layer shown in fig. 4 is three layers, but the number of the lamination layer is not limited in the embodiment of the present invention, and may be set according to specific requirements.
It can be understood that, in order to make the sacrificial material layer and the channel material layer have a sufficient etching selection ratio, when the channel material layer is a sige channel material layer and the sacrificial material layer is a sige sacrificial material layer, the mass percentage of the germanium element in the sige channel material layer may be set to be greater than 0% and less than or equal to 100%, and the mass percentage of the germanium element in the sige sacrificial material layer is greater than 0% and less than 80%; and the difference between the mass percent of the germanium element in the germanium-silicon channel material layer and the mass percent of the germanium element in the germanium-silicon sacrificial material layer is more than 20%.
For example: the germanium element in the germanium-silicon sacrificial layer accounts for 25% by mass, and the germanium element in the germanium-silicon channel material layer accounts for 65% by mass.
For example: the germanium element in the germanium-silicon sacrificial layer accounts for 40% by mass, and the germanium element in the germanium-silicon channel material layer accounts for 85% by mass.
For example, referring to fig. 5, when the substrate material layer is a silicon material layer, in order to improve lattice matching between the substrate material layer and the front channel material layer and satisfy the stress of the formed channel material layer, a second strain buffer material layer may be formed between the substrate material layer and the front channel material layer.
Referring to fig. 5, the semiconductor structure may be formed by: providing a substrate material layer, forming a second strain buffer material layer on the substrate material layer, and forming the multi-layer laminated material layer on the second strain buffer material layer. And etching the multilayer laminated material layer and part of the second strain buffer material layer to form the fin portion 102. The fin 102 includes a multi-layer stack formed by etching a plurality of stacked material layers, and a second strain buffer layer 1021 formed by etching a second strain buffer material layer. The base 101 comprises a layer of substrate material 1011 and an unetched part of the second strain buffer material 1012.
Referring to fig. 5, the substrate 1011 may be a Silicon substrate, other semiconductor substrate, or an SOI (Silicon-On-Insulator) substrate, which is not limited in the embodiments of the present invention.
Referring to fig. 5, the second strain buffer layer is a germanium-silicon strain buffer layer, and the mass percentage of germanium element in the germanium-silicon strain buffer layer is greater than 0% and less than or equal to 80%. The thickness of the germanium-silicon strain buffer layer can be 0.5um-3 um.
Referring to fig. 1 to 5, in the semiconductor structure 10, a trench 20 is formed between two adjacent fins 102. The trench 20 may be used to isolate subsequently formed components of two adjacent fins 102. At this time, referring to fig. 6 to 9, a shallow trench isolation material layer 301 may be formed within the trench. Fig. 6 is a schematic diagram illustrating the structure of the semiconductor structure of fig. 2 after forming a shallow trench isolation material layer 301 in the trench. Fig. 7 is a schematic diagram illustrating the structure of the semiconductor structure of fig. 3 after forming a shallow trench isolation material layer 301 in the trench. Fig. 8 is a schematic diagram illustrating the structure of the semiconductor structure of fig. 4 after forming a shallow trench isolation material layer 301 in the trench. Fig. 9 is a schematic diagram illustrating the structure of the semiconductor structure of fig. 5 after forming a shallow trench isolation material layer 301 in the trench.
The shallow trench isolation material layer 301 may be a silicon oxide material layer, or may be another material layer, which is not limited in the embodiment of the present invention.
As a specific example, referring to fig. 6 to 9, the shallow trench isolation material layer may be formed by: a first shallow trench isolation material layer 301 is formed within the trench 20. Depending on the structure of the semiconductor structure 10, the top of the first shallow trench isolation material layer 301 is not higher than the second substrate 1021 in the fin 102, or the top of the first shallow trench isolation material layer 301 is not higher than the first strain buffer layer 1021, or the top of the first shallow trench isolation material layer 301 is not higher than the top of the second strain buffer layer 1021.
Specifically, the step of forming the first shallow trench isolation material layer in the trench may be: and forming a front shallow trench isolation material layer in the trench, wherein the top of the front shallow trench isolation material layer is higher than the top of the fin part. After the front sti material layer is planarized, referring to fig. 2 to 9, since the fin 102 is formed with the hard mask 501, the planarized top of the front sti material layer may be flush with the top of the hard mask 501. After the front trench isolation material layer is planarized, the front shallow trench isolation material layer is etched back. Specifically, the front shallow trench isolation material is etched back until the germanium-silicon channel or the germanium channel in the fin portion is completely exposed, so as to obtain the first shallow trench isolation layer 301.
Referring to fig. 10 to 13, a silicon protection layer 401 is formed around the fin 102. Fig. 10 is a schematic structural diagram of the fin portion in fig. 6 after a silicon protection layer 401 is formed around the fin portion. Fig. 11 is a schematic structural diagram illustrating the fin portion of fig. 7 after a silicon protection layer 401 is formed around the fin portion. Fig. 12 is a schematic structural diagram of the fin portion in fig. 8 after a silicon protection layer 401 is formed around the fin portion. Fig. 13 is a schematic structural diagram of the fin portion of fig. 9 after a silicon protection layer 401 is formed around the fin portion.
The silicon protection layer 401 serves to protect the germanium-silicon channel layer or the germanium channel layer in the fin portion during the annealing process, so as to reduce the oxidation of the germanium-silicon channel or the germanium channel in the channel region by the annealing process. The silicon protection layer 401 may be implemented by a process such as selective epitaxy.
It is understood that the silicon protection layer 401 has a thickness of 3nm to 15nm in order to meet the requirements of the germanium-silicon channel layer or the germanium-channel layer in the protection fin, and other subsequent processes. The specific thickness can be set according to the requirements of the semiconductor device, which is not limited in the embodiments of the present invention. For example, when the thickness of the silicon protection layer 401 is 5nm to 8nm, it has a better protection effect on the germanium-silicon channel layer or the germanium channel layer in the fin portion.
As an example, referring to fig. 2-13, the semiconductor structure includes a hard mask 501 formed on the fin, where the formation of the silicon protection layer around the fin is: a silicon protection layer 401 is formed around the sidewalls of the fins using a selective epitaxy process. The semiconductor structure comprises a fin-shaped semiconductor structure or a gate-all-around semiconductor structure. The hard mask 501 may be made of a silicon nitride material, or may be made of other materials, which is not limited in the present invention.
As another example, referring to fig. 14, taking a semiconductor structure of a gate-all-around semiconductor device as an example, the fin 102 of the semiconductor structure 10 may include at least one channel material layer and a silicon capping layer 601; the silicon cap layer 601 is formed on the uppermost channel material layer in the at least one channel material layer; the uppermost channel material layer is a germanium-silicon channel material layer or a germanium channel material layer. A hard mask 501 is also formed on the silicon cap 601. At this time, forming the silicon protection layer 401 around the fin 102 includes: a silicon protection layer 401 is formed around the fin 102 using a selective epitaxy process. Wherein, in order to meet the performance requirement of the semiconductor device, the thickness of the silicon cap layer 601 is 1nm-5 nm. It is understood that the thickness of the silicon cap 601 can be set according to the actual performance requirement of the semiconductor device, which is not particularly limited by the embodiment of the invention.
It is understood that if the channel material layer in the fin-shaped semiconductor device is a silicon germanium channel material layer or a germanium channel material layer, the fin of the fin-shaped semiconductor device may also include a silicon capping layer formed on the channel material layer.
Referring to fig. 15 to 18, after forming the silicon protection layer, the first shallow trench isolation material layer 301 is annealed to obtain a shallow trench isolation layer 302. Fig. 15 is a schematic structural diagram of the shallow trench isolation layer 302 obtained after annealing the first shallow trench isolation material layer 301 in fig. 10. Fig. 16 is a schematic structural diagram of the first shallow trench isolation material layer 301 in fig. 11 after being annealed to obtain a shallow trench isolation layer 302. Fig. 17 is a schematic structural diagram of the first shallow trench isolation material layer 301 in fig. 12 after being annealed to obtain a shallow trench isolation layer 302. Fig. 18 is a schematic structural diagram of the first shallow trench isolation material layer 301 in fig. 13 after being annealed to obtain a shallow trench isolation layer 302.
Referring to fig. 15 to 18, after the silicon protection layer 401 is formed, the first shallow trench isolation material layer 301 is annealed to obtain the shallow trench isolation layer 302. Since the silicon protection layer is formed around the fin 102, the first shallow trench isolation material layer 301 may be annealed at a desired annealing temperature. After annealing treatment is carried out at the required annealing temperature, the shallow trench isolation layer meeting the requirements can be obtained. Furthermore, in the annealing process for the first shallow trench isolation material layer 301, a portion of the silicon protection layer 401 is oxidized into the silicon oxide layer 402, and the portion that is not oxidized forms the silicon protection layer 403.
As one implementation, after the annealing treatment, the silicon oxide layer needs to be removed according to the specific process of the semiconductor device. Referring to fig. 19, fig. 19 shows a schematic structural view of the silicon oxide layer 402 in fig. 15 after removal. After the silicon oxide layer 402 is removed, a portion of the silicon passivation layer surrounding the fin portion remains, i.e., the silicon passivation layer 403. The silicon protection layer 403 may be used to satisfy a thickness required in the source-drain annealing process and the lightly doped drain process.
As another implementation, referring to fig. 19 and 20, the hard mask 501 is further used to protect the fin when removing the silicon oxide layer. After the silicon oxide layer is removed, the hard mask 501 on the fin portion may be removed according to a specific process of the semiconductor device, and the specific removal process may correspond to a manufacturing method of other semiconductor devices, which is not limited in the embodiment of the present invention.
Exemplarily, referring to fig. 6, 10, 15 and 21, the shallow trench isolation material layer may be formed by the following steps: referring to fig. 6, a first shallow trench isolation material layer 301 is formed within the trench, wherein a top of the first shallow trench isolation material layer 301 is not higher than a top of the second substrate 1021 in the fin 102.
Thereafter, referring to fig. 10, a silicon protection layer 401 is formed around the fin 1022. Here, the process of forming the silicon passivation layer is the same as the above-mentioned scheme, and therefore, the description thereof is omitted.
Then, referring to fig. 21, after the silicon protection 401 is formed, a second shallow trench isolation material layer is deposited on the first shallow trench isolation material layer, and the second shallow trench isolation material layer is subjected to planarization processing, so as to obtain a third shallow trench isolation material layer 303, wherein the top of the third shallow trench isolation material layer 303 is not lower than the top of the fin portion.
Based on the process, annealing treatment is carried out on the third shallow trench isolation material layer and the first shallow trench isolation material layer, so that a second shallow trench isolation layer and a first shallow trench isolation layer which are stacked from bottom to top are obtained. In the above scheme, since the silicon protection layer is located in the third shallow trench isolation material layer, when the third shallow trench isolation material layer and the first shallow trench isolation material layer are annealed, the influence of the annealing temperature on the germanium-silicon channel or the germanium channel in the fin portion can be further reduced.
After the second shallow trench isolation layer and the first shallow trench isolation layer are stacked from bottom to top, referring to fig. 15, the second shallow trench isolation layer may be etched until the first shallow trench isolation layer is exposed according to the process requirements of the semiconductor device, so as to obtain the shallow trench isolation layer 302. In the annealing process, the silicon protection layer can form a silicon oxide layer, and the etching liquid used in the process step from the etching of the second shallow trench isolation layer to the exposure of the first shallow trench isolation layer has an etching effect on the silicon oxide generated in the shallow trench isolation material layer in the annealing process, and can synchronously remove the silicon oxide layer formed on the silicon protection layer. Based on the scheme, the germanium-silicon channel or the germanium channel can be further protected to a certain extent, and the process steps of removing the silicon oxide layer formed by the silicon protection layer can be reduced.
In the embodiment of the invention, the thickness of the silicon protection layer can be set, so that the silicon protection layer can meet the requirements of the annealing process of the shallow trench isolation layer, the annealing process of the source and drain and the thickness of silicon materials required to be consumed in the light doping drain process. At this time, the thickness of the silicon protective layer may be set to 3nm to 15 nm.
Based on this, after removing the silicon oxide layer, referring to fig. 14, when the fin 102 of the semiconductor structure 10 includes the silicon capping layer 601 and at least one channel material layer, the silicon capping layer 601 is formed on the uppermost channel material layer of the at least one channel material layer; the uppermost channel material layer is a germanium-silicon channel material layer or a germanium channel material layer. At this time, the semiconductor device structure has a structure similar to that of a silicon-based device, and the difficulty of subsequent processes can be reduced, for example: the dummy gate etching, the side wall etching and the like can be prepared according to the process of the silicon-based device.
The following processes of the manufacturing method of the semiconductor device of the invention are noteworthy: after removing the dummy gate and the silicon oxide layer, the remaining silicon protection layer needs to be removed for the fin-shaped semiconductor device. For the gate-all-around semiconductor device, when the sacrificial material layer included in the fin portion is a silicon material layer, the remaining silicon protection layer and the silicon sacrificial layer may be removed simultaneously. When the sacrificial material layer included in the fin is silicon material layers, the remaining silicon protection layer may be removed first, and then the silicon sacrificial layer may be removed. Illustratively, the removal of the silicon protective layer may employ a TMAH alkaline solution with a high selectivity ratio.
The embodiment of the invention also provides a semiconductor device, and the semiconductor device is manufactured by the manufacturing method of the semiconductor device.
The beneficial effects of the semiconductor device provided by the embodiment of the present invention are the same as the beneficial effects of the manufacturing method of the semiconductor device provided by the above embodiment, and are not described herein again.
The embodiment of the invention also provides electronic equipment which comprises the semiconductor device provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, the terminal device comprises a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligence device, a mobile power supply and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the invention are the same as those of the method for manufacturing the semiconductor device provided by the embodiment, and are not described herein again.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (20)

1. A manufacturing method of a semiconductor device is characterized by comprising the following steps:
providing a semiconductor structure; the semiconductor structure is provided with a plurality of fin parts, a groove is formed between every two adjacent fin parts, and each fin part comprises a germanium-silicon material layer or a germanium material layer;
forming a shallow trench isolation material layer in the trench;
forming a silicon protection layer around the fin portion;
and annealing the shallow trench isolation material layer to obtain the shallow trench isolation layer.
2. The method of claim 1, wherein forming a shallow trench isolation material layer within the trench comprises:
forming a first shallow trench isolation material layer in the trench, wherein the top of the first shallow trench isolation material layer is not higher than the top of the substrate in the fin part;
the annealing treatment of the shallow trench isolation material layer to obtain the shallow trench isolation layer comprises the following steps:
annealing the first shallow trench isolation material layer to obtain a shallow trench isolation layer;
after the shallow trench isolation material layer is annealed to obtain a shallow trench isolation layer, the manufacturing method of the semiconductor device further comprises the following steps:
and removing the silicon oxide layer formed in the annealing treatment of the silicon protective layer.
3. The method of claim 1, wherein the forming a shallow trench isolation material layer in the trench comprises:
forming a first shallow trench isolation material layer in the trench; the top of the first shallow trench isolation material layer is not higher than the top of the substrate in the fin part;
after forming the silicon protection layer around the fin portion, the method for manufacturing the semiconductor device further includes:
depositing a second shallow trench isolation material layer on the first shallow trench isolation material layer;
performing planarization treatment on the second shallow trench isolation material layer to obtain a third shallow trench isolation material layer, wherein the top of the third shallow trench isolation material layer is not lower than the top of the fin portion;
the annealing treatment of the shallow trench isolation layer to obtain the shallow trench isolation layer comprises the following steps:
annealing the third shallow trench isolation material layer and the first shallow trench isolation material layer to obtain a second shallow trench isolation layer and a first shallow trench isolation layer which are stacked from bottom to top;
and etching the second shallow trench isolation layer until the first shallow trench isolation layer is exposed to obtain the shallow trench isolation layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the etching the second shallow trench isolation layer until the first shallow trench isolation layer is exposed to obtain the shallow trench isolation layer, the method further comprises:
and removing the silicon oxide layer formed in the annealing treatment of the silicon protective layer.
5. The method of claim 1, wherein the fin comprises a layer of channel material; the channel material layer is the germanium-silicon material layer or the germanium material layer;
wherein, the mass percentage of the germanium element in the germanium-silicon material layer is more than 0 percent and less than 100 percent.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor structure comprises a substrate and a first strain buffer layer to be formed on the substrate;
the fin portion comprises a part of the first strain buffer layer;
the channel material layer is formed on the first strain buffer layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein when the substrate is a silicon substrate, the first strain buffer layer is a silicon germanium strain buffer layer;
the mass percentage of germanium element in the germanium-silicon strain buffer layer is more than 0 percent and less than or equal to 80 percent;
the thickness of the germanium-silicon strain buffer layer is 0.5um-3 um.
8. The method of manufacturing a semiconductor device according to claim 1, wherein the fin portion comprises a plurality of stacked layers arranged in a stacked manner; each lamination comprises a silicon sacrificial material layer and a channel material layer which are stacked from bottom to top;
wherein the channel material layer is the germanium-silicon material layer or the germanium material layer.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the fin portion comprises a plurality of stacked layers arranged in a stacked manner; each lamination comprises a channel material layer and a silicon sacrificial material layer which are stacked from bottom to top;
wherein the channel material layer is the germanium-silicon material layer or the germanium material layer.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the fin portion comprises a plurality of stacked layers arranged in a stacked manner; each lamination comprises a channel material layer and a germanium-silicon sacrificial material layer which are stacked from bottom to top;
the channel material layer is the germanium-silicon material layer or the germanium material layer; the mass percentage of germanium element in the channel material layer is more than 0% and less than or equal to 100%; the mass percentage of germanium element in the germanium-silicon sacrificial material layer is more than 0% and less than 80%; the difference between the mass percent of the germanium element in the channel material layer and the mass percent of the germanium element in the germanium-silicon sacrificial material layer is more than 20%;
or the fin part comprises a plurality of stacked layers which are stacked; each lamination comprises a germanium-silicon sacrificial material layer and a channel material layer which are stacked from bottom to top;
wherein the channel material layer is the germanium-silicon material layer or the germanium material layer; the mass percentage of germanium element in the channel material layer is more than 0% and less than or equal to 100%; the mass percentage of germanium element in the germanium-silicon sacrificial material layer is more than 0% and less than 80%; the difference between the mass percent of the germanium element in the channel material layer and the mass percent of the germanium element in the germanium-silicon sacrificial material layer is larger than 20%.
11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10,
the semiconductor structure comprises a substrate and a second buffer layer formed on the substrate;
the fin comprises a portion of the second strain buffer layer;
the plurality of stacked layers are formed on the second strain buffer layer.
12. The method of manufacturing a semiconductor device according to claim 11, wherein when the substrate is a silicon substrate, the second strain buffer layer is a silicon-germanium strain buffer layer;
the mass percentage of germanium element in the germanium-silicon strain buffer layer is more than 0 percent and less than or equal to 80 percent;
the thickness of the germanium-silicon strain buffer layer is 0.5um-3 um.
13. The method of any of claims 1-10, wherein the semiconductor structure further comprises a hard mask formed on the fin; the forming a silicon protection layer around the fin includes:
and forming a silicon protection layer around the side wall of the fin part by using a selective epitaxy process.
14. The method for manufacturing a semiconductor device according to claim 13,
the fin part comprises at least one channel material layer and a silicon cap layer;
the silicon cap layer is formed on the uppermost channel material layer in the at least one channel material layer;
the uppermost channel material layer is a germanium-silicon channel material layer or a germanium channel material layer.
15. The method for manufacturing a semiconductor device according to claim 14,
the thickness of the silicon cap layer is 1nm-5 nm.
16. The method of claim 13, wherein after the annealing the shallow trench isolation material layer to obtain the shallow trench isolation layer, the method further comprises:
removing the hard mask formed on the fin.
17. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the thickness of the silicon protective layer is 3nm to 15 nm.
18. A method for fabricating a semiconductor device according to any one of claims 1 to 10, wherein the trench isolation material layer is a silicon oxide material layer.
19. A semiconductor device characterized by being manufactured by the manufacturing method of a semiconductor device according to any one of claims 1 to 18.
20. An electronic device characterized by comprising the semiconductor device as claimed in claim 19.
CN202010725278.0A 2020-07-24 2020-07-24 Manufacturing method of semiconductor device, semiconductor device and electronic equipment Pending CN112038291A (en)

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