TW201715582A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein a conductive type of the first well and a conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein a conductive type of the first heavy-doping region and the conductive type of the first well are same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.

Description

Semiconductor structure and method of forming same

The present invention relates to semiconductor structures, and more particularly to structures having a low voltage and high voltage MOS device and methods of forming the same.

In order to make the product have extended functions and low prices, the manufacture of electronic products has been under pressure. In the case of mobile phones, the competition between manufacturers and resellers keeps them low, even if the phone functions are significantly larger than previous products. In fact, in addition to sending and receiving words, today's mobile phones also include e-mail, web browsing, text communication, music storage, photography, and video playback.

In order to expand the functionality of the device at a low price, manufacturers must develop new processors and algorithms, as well as develop new semiconductor technologies that are low cost and more closely integrated. However, high device integration typically requires incompatible techniques to be incorporated into a common device substrate.

Many electronic devices, such as cell phones, use low voltage CMOS devices in a variety of circuits, such as data encryption and decryption. However, other circuits of the same electronic device (such as modulators/demodulators and power amplifiers) use relatively high voltage devices. Unfortunately, low voltages do not effectively operate high voltage devices, while high voltages can damage low voltage devices. The above contradictions often lead to the use of different independent circuits in the prior art, some being low voltage devices and others being high voltage devices. However, the above Different types of devices cannot meet the requirements of high integration density and low cost.

To overcome the above problems, many technical solutions have been developed. However, in the existing process description, if the driving voltage of the high voltage device is changed, the doping concentration of the different doping regions needs to be changed. However, the difficulty and cost of adjusting the dopant concentration is higher than the design of the new mask and doped region shape. In other words, the compatible structure of the existing high voltage device-low voltage device is often only applicable to a specific high voltage-low voltage, and cannot be simply adjusted according to the driving voltage of the product.

In summary, there is a need for a new process method and corresponding structure. The structure can be adjusted to correspond to different driving voltages without increasing the number of masks or changing the doping concentration of the doping regions.

A semiconductor structure according to an embodiment of the present invention includes: a first high voltage MOS half device region, including: a first well region; a first lightly doped region, located in a portion of the first well region, and the first well region Contrary to the conductivity type of the first lightly doped region; the first gate stack is located on a portion of the first well region and a portion of the first lightly doped region; and the plurality of first heavily doped regions are located at the first a first well region and a first lightly doped region on both sides of the gate stack, and the first heavily doped region and the first well region have the same conductivity type; wherein the first well region and the first heavily doped region The first lightly doped region is the channel region of the first high voltage MOS half device region.

A method for forming a semiconductor structure according to an embodiment of the present invention includes: forming a first well region in a substrate; forming a first lightly doped region in a portion of the first well region, and the first lightly doped region and the first The conductivity pattern of the well region is different; forming a first gate stacked on a portion of the first lightly doped region and a portion of the first well region; implanting the dopant into the first well region not covered by the first gate stack And the first lightly doped region Forming a plurality of first heavily doped regions on both sides of the first gate stack, and the first heavily doped region is of the same conductivity type as the first well region; wherein the first well region and the first heavily doped region are between The first lightly doped region is the channel region of the high voltage MOS half device region.

100‧‧‧Substrate

101‧‧‧Isolation structure

103, 105‧‧‧High voltage gold oxide half device area

107, 109‧‧‧Low voltage gold oxide half device area

111‧‧‧Shenjing District

113A, 113B, 115A, 115B‧‧‧ Well Area

117A, 117B‧‧‧lightly doped area

119A, 119B, 119C, 119D‧‧ ‧ gate stacking

120‧‧‧ spacers

121A, 121B, 123A, 123B‧‧‧ heavily doped areas

125‧‧‧Contacts

1 to 5 are cross-sectional views showing a process of a semiconductor structure in an embodiment.

1 to 5 are cross-sectional views showing a process of a semiconductor structure in an embodiment. First, as shown in Fig. 1, a p-type substrate 100 is provided. The substrate 100 may be a germanium substrate, a germanium-on-insulator (SOI) substrate, or the like. In an embodiment of the invention, the substrate 100 can be implanted with a p-type dopant after the substrate 100 is first provided. In another embodiment of the present invention, the p-type dopant may be doped in the field when the substrate 100 is epitaxially formed. In an embodiment of the invention, the doping concentration of the substrate 100 is between 7e13 atoms/cm ³ and 7e15 atoms/cm ³ .

Next, an isolation structure 101 is formed in the substrate 100 to separate and define a plurality of device regions such as a p-type high voltage MOS half device region 103, an n-type high voltage MOS half device region 105, and a p-type low voltage gold oxide. The half device region 107 and the n-type low voltage MOS half device region 109. An n-type deep well region 111 is then formed in the high voltage MOS half device region 103. In an embodiment of the present invention, the method for forming the deep well region 111 includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover the high voltage MOS device region 105 and the low voltage MOS half. The device region 107, and the low voltage MOS half device region 109, implant n-type dopants into the high voltage MOS half device region 103 to define the deep well region 111, and then remove the mask pattern. In an embodiment of the invention, the doping concentration of the deep well region 111 is between 5e14 atoms/cm ³ and 1e17 atoms/cm ³ .

The isolation structure 101 shown in FIG. 1 is a shallow trench isolation (STI), and the method for forming the same includes, but is not limited to, forming a mask layer on the substrate 100, and patterning the mask layer by a lithography and etching process to expose the portion. The substrate 100 etches the exposed portion of the substrate 100 to form a trench, fill an insulating material such as yttrium oxide into the trench, and remove the patterned mask layer. In other embodiments, the isolation structure 101 may be a local oxide ruthenium (LOCOS), and the formation method thereof includes, but is not limited to, depositing a mask layer such as a tantalum nitride layer on the substrate 100, and patterning the mask by a lithography and etching process. The layer exposes a portion of the substrate 100, thermally oxidizes the exposed portion of the substrate 100 to form a hafnium oxide layer, and removes the patterned mask layer. The yttrium oxide layer formed above is LOCOS.

Next, as shown in FIG. 2, p-type well regions 113A and 113B are respectively formed in the high voltage MOS half device region 103 and the low voltage MOS half device region 109, and n-type well regions 115A and 115B are respectively formed. The high voltage MOS half device region 105 is in the low voltage MOS half device region 107. In an embodiment of the invention, the method for forming the well regions 113A and 113B includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover the high voltage MOS device region 105 and the low voltage gold. The oxygen half device region 107 then implants the p-type dopant into the high voltage MOS half device region 103 and the low voltage MOS half device region 109 to define the well regions 113A and 113B, and then removes the mask pattern. In an embodiment of the invention, the doping concentrations of the well regions 113A and 113B are the same, ranging from 1e15 atoms/cm ³ to 1e17 atoms/cm ³ . As shown in FIG. 2, well regions 113A and 113B have the same depth, and well region 113A has a depth less than deep well region 111 to avoid leakage current problems caused by well region 113A and substrate 100 due to the same conductivity type. In an embodiment of the invention, the method for forming the well regions 115A and 115B includes, but is not limited to, forming a mask pattern (not shown) by a lithography process and an etching process to cover the high voltage MOS device region 103 and the low voltage gold. The oxygen half device region 109 then implants the n-type dopant into the high voltage MOS half device region 105 and the low voltage MOS half device region 107 to define the well regions 115A and 115B, and then removes the mask pattern. In an embodiment of the invention, the doping concentrations of the well regions 115A and 115B are the same, ranging from 1e15 atoms/cm ³ to 1e17 atoms/cm ³ . As shown in Figure 2, well regions 115A and 115B have the same depth. Although in FIG. 2, well region 113A/113B has the same depth as well region 115A/115B, well region 113A/113B and well region 115A/115B may also have different depths, depending on the needs. In an embodiment of the invention, the well regions 113A and 113B may be formed first and then the well regions 115A and 115B may be formed. In another embodiment of the invention, the well regions 115A and 115B may be formed first and then the well regions 113A and 113B may be formed.

Next, as shown in FIG. 3, an n-type lightly doped region 117A is formed in a portion of the well region 113A, and a p-type lightly doped region 117B is formed in a portion of the well region 113B. In an embodiment of the invention, the method for forming the lightly doped region 117A includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover a portion of the high voltage MOS device region 103, which is high. a voltage MOS half device region 105, a low voltage MOS half device region 107, and a low voltage MOS half device region 109, and then n-type dopants are implanted into a portion of the well region 113A to define a lightly doped region 117A. Then remove the mask pattern. In an embodiment of the invention, the doping concentration of the lightly doped region 117A is between 1e15 atoms/cm ³ and 5e17 atoms/cm ³ . As shown in FIG. 3, the depth of the lightly doped region 117A is less than the depth of the well region 113A. In an embodiment of the invention, the method for forming the lightly doped region 117B includes, but is not limited to, forming a mask pattern (not shown) by a lithography process and an etching process to cover the high voltage MOS device region 103, and partially high. a voltage MOS half device region 105, a low voltage MOS half device region 107, and a low voltage MOS half device region 109, and then p-type dopants are implanted into a portion of the well region 115A to define a lightly doped region 117B. Then remove the mask pattern. In an embodiment of the invention, the doping concentration of the lightly doped region 117B is between 1e15 atoms/cm ³ and 5e17 atoms/cm ³ . As shown in FIG. 3, the depth of the lightly doped region 117B is less than the depth of the well region 115A. Although in FIG. 3, the lightly doped regions 117A and 117B have the same depth, the lightly doped regions 117A and 117B may have different depths, depending on the needs. In an embodiment of the invention, the lightly doped region 117A may be formed after the lightly doped region 117A is formed. In another embodiment of the present invention, the lightly doped region 117B may be formed before the lightly doped region 117B is formed.

Next, as shown in FIG. 4, gate stacks 119A, 119B, 119C, and 119D are respectively formed in the high voltage MOS half device region 103, the high voltage MOS half device region 105, the low voltage MOS half device region 107, and Low voltage MOS half device area 109. The gate stack 119A covers a portion of the well region 113A and a portion of the lightly doped region 117A, and the gate stack 119B covers a portion of the well region 115A and a portion of the lightly doped region 117B. In an embodiment of the invention, the method for forming the gate stacks 119A, 119B, 119C, and 119D includes, but is not limited to, forming a gate dielectric layer on the structure of FIG. 3, forming a gate layer on the gate dielectric. On the layer, a mask pattern (not shown) is formed on the layer to form a mask pattern (not shown) to cover part of the gate layer, and then the gate layer not covered by the mask pattern and the gate dielectric layer below it are removed to define the gate. Stacks 119A, 119B, 119C, and 119D. In an embodiment of the invention, the gate dielectric layer may be yttrium oxide (SiO ₂ ), tantalum nitride, hafnium oxynitride, a high dielectric constant dielectric material, any other suitable dielectric material, or a combination thereof. And the gate material may be amorphous germanium, polycrystalline germanium, one or more metals, metal nitrides, conductive metal oxides, or a combination thereof. Spacers 120 are then formed on the sidewalls of the gate stacks 119A, 119B, 119C, and 119D as needed. In an embodiment of the invention, the method for forming the spacers 120 includes, but is not limited to, forming a spacer layer on the gate stack and the exposed doped region, and then removing the spacer layer by anisotropic etching to The spacers 120 are retained on the sidewalls of the gate stack. The spacer layer may be, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, or a multilayer structure as described above. In another embodiment of the invention, the spacers 120 may be omitted.

It should be noted that the order of FIG. 3 and FIG. 4 may be reversed, that is, the gate stack may be formed first to form lightly doped regions 117A and 117B. However, if the process of forming the gate stack is used first, the spacers 120 are formed on the sidewalls of the gate stack after the lightly doped regions 117A and 117B are formed, so that the subsequently formed heavily doped region 121A and the well region 113A are formed ( Or between the heavily doped region 123A and the well region 115A) is separated by a lightly doped region 117A (or 117B).

Next, as shown in FIG. 5, a p-type heavily doped region 121A is formed in the well region 113A and the lightly doped region 117A on both sides of the gate stack 119A, and an n-type heavily doped region 123A is formed on the gate stack 119B. In the well region 115A and the lightly doped region 117B on both sides, a p-type heavily doped region 121B is formed in the well region 115B on both sides of the gate stack 119C, and an n-type heavily doped region 123B is formed on the gate stack. In the well area 113B on both sides of the 119D. In an embodiment of the invention, the method for forming the heavily doped regions 121A and 121B includes, but is not limited to, forming a mask pattern (not shown) by a lithography process and an etching process to cover the high voltage MOS device region 105 and the low portion. After the voltage MOS half device region 109, the gate stacks 119A and 119C are used as the implant mask, and the p-type dopant is used to implant the high voltage MOS half device region 103 and the low voltage MOS half device region 107 to define the heavy doping. The miscellaneous regions 121A and 121B are then removed from the mask pattern. In an embodiment of the invention, the doping concentrations of the heavily doped regions 121A and 121B are the same, ranging from 5e17 atoms/cm ³ to 2e20 atoms/cm ³ . As shown in FIG. 5, the depths of the heavily doped regions 121A and 121B are the same, and the depth of the heavily doped region 121A is smaller than the depth of the lightly doped region 117A. An n-type lightly doped region 117A sandwiched between the p-type well region 113A and the right heavily doped region 121A, that is, the channel region of the high voltage MOS half device region 103. In the above structure, as long as the thickness of the spacer 120 in FIG. 4 is changed, the width of the gate stack 119A and the spacer 120 covering the lightly doped region 117A is changed. In this way, the same reticle and implantation process can be used to form the structure of FIGS. 1-5, and the length of the channel region of the high voltage MOS device region 103 can be changed by changing the thickness of the spacer 120. Drive voltage.

In an embodiment of the present invention, the method for forming the heavily doped regions 123A and 123B includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover the high voltage MOS device region 103 and the low portion. After the voltage MOS half device region 107, the gate stacks 119B and 119D are used as the implant mask, and the n-type dopant is implanted with the high voltage MOS half device region 105 and the low voltage MOS device region 109 to define the heavy doping. Miscellaneous areas 123A and 123B, and then the mask pattern is removed. In an embodiment of the invention, the doping concentrations of the heavily doped regions 123A and 123B are the same, ranging from 1e17 atoms/cm ³ to 5e19 atoms/cm ³ . As shown in FIG. 5, the depths of the heavily doped regions 123A and 123B are the same, and the depth of the heavily doped region 123A is smaller than the depth of the lightly doped region 117B. A p-type lightly doped region 117B sandwiched between the n-type well region 115A and the right heavily doped region 123A, that is, the channel region of the high voltage MOS half device region 105. In the above structure, as long as the thickness of the spacer 120 in FIG. 4 is changed, the width of the gate stack 119B and the spacer 120 covering the lightly doped region 117B is changed. In this way, the same reticle and implantation process can be used to form the structure of FIGS. 1-5, and the length of the channel region of the high voltage MOS device region 105 can be changed by changing the thickness of the spacer 120. Drive voltage. In other words, in the above embodiment, the driving voltage of the high voltage MOS half device region can be simply adjusted without adjusting the doping concentration of the doping region or changing the reticle design.

The n-type well region 115B between the p-type heavily doped regions 121B, that is, the channel region of the low voltage MOS half device region 107. A p-type well region 113B between the n-type heavily doped regions 123B, that is, a channel region of the low voltage MOS half device region 109. It can be understood that the heavily doped region 121A on both sides of the gate stack 119A is the source/drain region of the high voltage MOS device region 103, and the heavily doped region 123A on both sides of the gate stack 119B is a high voltage gold. The source/drain region of the oxygen half device region 105, the heavily doped region 121B on both sides of the gate stack 119C is the source/drain region of the low voltage MOS device region 107, and the gate stack 119D is on both sides. The heavily doped region 123B is the source/drain region of the low voltage MOS half device region 109. An interlayer dielectric layer (not shown) can then be formed over the structure, and contacts 125 are formed through the interlayer dielectric layer to contact the heavily doped regions 121A, 121B, 123A, and 123B, respectively.

In the above embodiment, the substrate 100, the high voltage MOS half device region 103, the low voltage MOS half device region 107, the well regions 113A and 113B, the lightly doped region 117B, and the heavily doped regions 121A and 121B are p-type. The high voltage MOS half device region 105, the low voltage MOS half device region 109, the deep well region 111, the well regions 115A and 115B, the lightly doped region 117A, and the heavily doped regions 123A and 123B are n-type. In another embodiment, the substrate 100, the high voltage MOS half device region 103, the low voltage MOS half device region 107, the well regions 113A and 113B, the lightly doped region 117B, and the heavily doped regions 121A and 121B are n. The high voltage MOS half device region 105, the low voltage MOS half device region 109, the deep well region 111, the well regions 115A and 115B, the lightly doped region 117A, and the heavily doped regions 123A and 123B are p-type. It will be appreciated that the n-type dopant may be phosphorus, arsenic, or antimony, and the p-type dopant may be boron or BF ₂ .

The present invention has been disclosed in the above several embodiments, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Substrate

101‧‧‧Isolation structure

103, 105‧‧‧High voltage gold oxide half device area

107, 109‧‧‧Low voltage gold oxide half device area

111‧‧‧Shenjing District

113A, 113B, 115A, 115B‧‧‧ Well Area

117A, 117B‧‧‧lightly doped area

119A, 119B, 119C, 119D‧‧ ‧ gate stacking

120‧‧‧ spacers

121A, 121B, 123A, 123B‧‧‧ heavily doped areas

125‧‧‧Contacts

Claims (11)

A semiconductor device comprising: a first high voltage MOS half device region, comprising: a first well region; a first lightly doped region located in a portion of the first well region, and the first well region and The first lightly doped region has a opposite conductivity type; a first gate stack is disposed on a portion of the first well region and a portion of the first lightly doped region; and a plurality of first heavily doped regions, The first well region and the first lightly doped region are located on both sides of the first gate stack, and the first heavily doped regions are the same as the first well region; wherein the first The first lightly doped region between the well region and the first heavily doped region is a channel region of the first high voltage MOS region. The semiconductor device of claim 1, wherein the first well region is located in a substrate, and the first well region is opposite to a conductivity type of the substrate. The semiconductor device of claim 1, further comprising: a first low voltage MOS half device region, comprising: a second well region, and the first well region and the second well region are of a conductivity type a second gate stack, located on a portion of the second well region; and a plurality of second heavily doped regions located in the second well region on both sides of the second gate stack, and The second heavily doped region is opposite to the conductivity type of the second well region; wherein the second well region between the second heavily doped regions is a channel region of the first low voltage MOS half device region; Depth and doping of the first heavily doped regions and the second heavily doped regions The concentration is the same. The semiconductor device of claim 1, wherein the first well region is located in a substrate, the first well region is the same as the conductive type of the substrate, and the first high voltage metal oxide half device region is further A deep well region is sandwiched between the first well region and the substrate, and the deep well region is different from the first well region. The semiconductor device of claim 4, further comprising: a second high voltage MOS half device region, comprising: a second well region, wherein the second well region and the first well region are of a conductivity type The second lightly doped region is located in a portion of the second well region, and the second well region is opposite to the conductive pattern of the second lightly doped region; a second gate stack is located at the portion a portion of the second well region and a portion of the second lightly doped region; a plurality of second heavily doped regions, the second well region and the second lightly doped region on both sides of the second gate stack And the second heavily doped regions are the same as the second well region; wherein the second lightly doped region between the second well region and the second heavily doped region is The channel area of the two high voltage gold oxide half device area. The semiconductor device of claim 1, further comprising a spacer on a sidewall of the first gate stack. A method for forming a semiconductor structure, comprising: forming a first well region in a substrate; forming a first lightly doped region in a portion of the first well region, and the first lightly doped The impurity region is opposite to the conductivity pattern of the first well region; forming a first gate stacked on a portion of the first lightly doped region and a portion of the first well region; implanting dopants to the first The first well region not covered by the gate stack and the first lightly doped region to form a plurality of first heavily doped regions on both sides of the first gate stack, and the first heavily doped regions The conductivity pattern of the first well region is the same; wherein the first lightly doped region between the first well region and the first heavily doped regions is a channel region of a high voltage MOS device region. The method for forming a semiconductor structure according to claim 7, wherein the step of forming the first well region also forms a second well region of the low voltage MOS half device region, forming the first gate stack The step also forms a second gate stack of the low voltage MOS half device region, and the step of forming the first heavily doped regions also forms a plurality of second heavily doped regions of the low voltage MOS half device region. And the second well region between the second heavily doped regions is a channel region of the low voltage MOS half device region. The method of forming a semiconductor structure according to claim 7, wherein the substrate is opposite to the conductivity type of the first well region. The method for forming a semiconductor structure according to claim 7, wherein the substrate is of the same conductivity type as the first well region, and further comprising forming a deep well region between the first well region and the substrate, And the deep well zone is opposite to the conductivity type of the first well zone. The method for forming a semiconductor structure according to claim 7, further comprising forming a spacer on a sidewall of the first gate stack.