TWI682542B - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device including a substrate of a first conductivity type, at least one gate structure combination, an inner doped region of a second conductivity type, two outer doped regions of the second conductivity type, and two lightly doped regions of the second conductivity type. Each of the gate structure combination including a first gate structure and a second gate structure. The gate structure combination is located on the substrate. The inner doped region is located in the substrate, and is sandwiched between the first gate structure and the second gate structure. The two outer doped regions are located in the substrate. The two outer doped regions are located in the substrate which outside the inner doped region, the first gate structure, and the second gate structure. The two lightly doped regions are located in the substrate. The lightly doped region covers a sidewall and a bottom surface of the outer doped region, and a sidewall and a bottom surface of the inner doped region are not covered by the lightly doped region.

Description

Semiconductor components

The present invention relates to an integrated circuit, and particularly to a semiconductor device.

With the trend of technology, it is expected to manufacture semiconductor devices with lower device-specific on-resistance (Ron-sp), and how to shorten the gate length to obtain lower device-specific on-resistance will become an important topic.

The invention provides a semiconductor element which can effectively shorten the gate length of the semiconductor element while maintaining certain electrical characteristics.

The invention provides a semiconductor device including a substrate having a first conductivity type, at least one gate structure combination, an inner doped region having a second conductivity type, two outer doped regions having a second conductivity type, and having a second conductivity Two lightly doped regions of the type. Each gate structure combination includes a first gate structure and a second gate structure. The gate structure combination is arranged on the substrate. The internally doped region is located in the substrate and is sandwiched between the first gate structure and the second gate structure. Two out-doped regions are located in the substrate. The two outer doped regions are located in the substrate outside the inner doped region, the first gate structure and the second gate structure. Two lightly doped regions are located in the substrate. The lightly doped region covers the side walls and bottom surface of the outer doped region, and the side walls and bottom surface of the inner doped region are not covered by the lightly doped region.

The invention provides a semiconductor device including a substrate having a first conductivity type, at least one gate structure combination, an inner doped region having a second conductivity type, two outer doped regions having a second conductivity type, and having a second conductivity Type lightly doped region. The two gate structures are arranged on the substrate. The inner doped region is located in the substrate. The internally doped region is sandwiched between the first gate structure and the second gate structure. Two out-doped regions are located in the substrate. The two outer doped regions are located in the substrate outside the inner doped region, the first gate structure and the second gate structure. The lightly doped region is located in the substrate. The lightly doped region covers the sidewalls and bottom surface of the inner doped region, and the side walls and bottom surface of the outer doped region are not covered by the lightly doped region.

Based on the above, the present invention has an internally doped region sandwiched between two gate structures in a single semiconductor device. The two externally doped regions are located in the substrate outside the internally doped region and the two gate structures. The doped region covers the sidewall and bottom surface of the outer doped region, but does not cover the sidewall and bottom surface of the inner doped region, or the lightly doped region covers the sidewall and bottom surface of the inner doped region; The side wall and bottom surface of the impurity region prevent two lightly doped regions from laterally diffusing and contacting each other near the two adjacent inner doped regions and outer doped regions to cause breakdown leakage current, which can effectively shorten the semiconductor The gate length of the device while maintaining certain electrical characteristics.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

Referring to FIG. 1A, this embodiment provides a method for manufacturing a semiconductor device 100, and the steps are as follows. First, a substrate 102 having a first conductivity type is provided. The substrate 102 is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The substrate 102 may also be, for example, an epitaxial layer (EPI), a non-epi layer (non-EPI), a silicon-on-insulator (SOI) substrate, or a combination thereof. In this embodiment, the first conductivity type is, for example, P type, and the substrate 102 is, for example, P type substrate. P-type doping is, for example, boron.

In some embodiments, as shown in FIG. 1F, the substrate 102 may have four unevenly doped regions PW1, PW2, PW3, and PW4 in sequence from the bottom surface 102b to the top surface 102a. In other embodiments, it may also be It is a plurality of well areas diffused by high temperature thermal annealing or rapid thermal annealing. The doped region PW1 is located at a position of 1 micrometer (μm) to 3 μm from the top surface 102a of the substrate 102; the doped region PW2 is located at a position of 0.5 μm to 2 μm from the top surface 102a of the substrate 102; PW3 is located at a position of 0.2 μm to 1 μm from the top surface 102 a of the substrate 102, for example; and doped region PW4 is located at a position of 0 μm to 0.6 μm from the top surface 102 a of the substrate 102, for example. In some embodiments, the doping concentration range in the doped region PW1 is, for example, between 10 ¹⁶ /cm ³ and 10 ¹⁸ /cm ³ ; the doping concentration range in the doped region PW2 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; the doping concentration range in the doped region PW3 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; and the doping concentration in the doped region PW4 The range is, for example, between 10 ¹⁶ /cm ³ and 10 ¹⁸ /cm ³ , where the doped region PW4 has the greatest influence on the threshold voltage. In this embodiment, by doping different regions in the substrate 102 with different concentration ranges, the threshold voltage of the semiconductor device 100 (FIG. 1E) can be directly adjusted, so there is no need to use an additional process to control the threshold voltage. For example, the present invention does not require additional pocket implant regions to effectively control the threshold voltage. The pocket doped regions cover the first lightly doped regions 122 and the second as shown in FIG. 1E The dotted area at the corner of the lightly doped region 124 and the inner doped region 140.

Please continue to refer to FIG. 1A. Next, an isolation structure 104 is formed in the substrate 102 to define the active area AA. The material of the isolation structure 104 is, for example, doped or undoped silicon oxide, low-stress silicon nitride, silicon oxynitride, or a combination thereof, and the formation method thereof may be, for example, local area thermal oxidation (LOCOS), shallow trench isolation or Deep trench isolation method. In an embodiment, the isolation structure 104 may be, for example, a field oxide structure (FOX), a shallow trench isolation structure (STI), a deep trench isolation structure (DTI), or a combination thereof.

1B, after forming the isolation structure 104, a gate structure assembly 110 is formed on the substrate 102. The gate structure combination 110 includes a first gate structure 112 and a second gate structure 114. The gate structure combination 110 is not limited to one set of first gate structures 112 and second gate structures 114, but also includes multiple sets of first gate structures 112 and second gate structures 114. In this embodiment, the first gate structure 112 and the second gate structure 114 may be the same type of gate structure. The first gate structure 112 includes, for example, the gate dielectric layer 12a and the conductor layer 12b sequentially stacked on the substrate 102; and the second gate structure 114 includes, for example, the gate dielectric layer sequentially stacked on the substrate 102 Layer 14a and conductor layer 14b. The materials of the gate dielectric layers 12a, 14a may include silicon oxide, silicon oxynitride, silicon nitride, and combinations thereof. In addition, multiple layers of materials may be used as the gate dielectric layers 12a, 14a. In this embodiment, the material of the conductor layers 12b, 14b is, for example, doped polysilicon. The doped polysilicon dopant may be a P-type conductivity type, such as boron. The concentration range of the dopant doped polysilicon is, for example, 10 ¹⁷ /cm ³ to 10 ¹⁹ /cm ³ .

The forming methods of the gate dielectric layers 12a, 14a and the conductor layers 12b, 14b are, for example, chemical vapor deposition (CVD) or furnace tube oxidation. In some embodiments, the manufacturing steps of the first gate structure 112 and the second gate structure 114 may be as follows. First, a gate dielectric material layer and a conductor material layer are formed on the substrate 102, and then the above material layer is patterned by a lithography and etching process.

In some embodiments, the gate length L1 of the first gate structure 112 ranges from 0.1 μm to 1 μm, for example, and the gate length L2 of the second gate structure 114 ranges from 0.1 μm to 1 μm, for example. The gate length L1 of the first gate structure 112 and the gate length L2 of the second gate structure 114 may be the same. In other embodiments, the gate length L1 of the first gate structure 112 and the gate length L2 of the second gate structure 114 may be different.

1B and 2A, after forming the first gate structure 112 and the second gate structure 114, a patterned photoresist layer 16 is formed on the substrate 102. The patterned photoresist layer 16 has two openings O1. The photoresist layer 16 covers the isolation structure 104, the first gate structure 112, the second gate structure 114, and a portion of the substrate 102 between the first gate structure 112 and the second gate structure 114. In other words, the opening O1 exposes a portion of the substrate 102 of the active area AA. In some embodiments, the opening O1 exposes the isolation structure 104, the first gate structure 112, and the second gate structure 114 in addition to the exposed portion of the substrate 102 in the active area AA, as shown in FIGS. 1B and 2A Show.

Next, an ion implantation process is performed to form a lightly doped region 120 in a portion of the substrate 102 exposed by the opening O1. The lightly doped region 120 includes a first lightly doped region 122 and a second lightly doped region 124. In other embodiments, based on process requirements, other photoresist pattern designs or other doping steps may be used to perform multiple ion implantation processes to form the first lightly doped region 122 and the second lightly doped region 124 . Next, the patterned photoresist layer 16 is removed.

The first lightly doped region 122 is adjacent to the first gate structure 112, and the second lightly doped region 124 is adjacent to the second gate structure 114. The first lightly doped region 122 and the second lightly doped region 124 may be lightly doped regions having a second conductivity type. In other words, the first lightly doped region 122 and the second lightly doped region 124 have the same conductivity type doping. The second conductivity type is different from the first conductivity type. In this embodiment, the second conductivity type is, for example, N type, and the first lightly doped region 122 and the second lightly doped region 124 are, for example, N type lightly doped regions. The N-type doping is, for example, phosphorus or arsenic. The concentration range of the first lightly doped region 122 and the second lightly doped region 124 is, for example, 10 ¹⁸ /cm ³ to 10 ²⁰ /cm ³ .

The first gate structure 112 has an outer sidewall 112a and an inner sidewall 112b; and the second gate structure 114 has an outer sidewall 114a and an inner sidewall 114b. The outer sidewall 112a of the first gate structure 112 and the outer sidewall 114a of the second gate structure 114 are closer to the isolation structure 104 than the inner sidewalls 112b and 114b; and the inner sidewall 112b of the first gate structure 112 and the second gate structure 114 The inner side wall 114b is adjacent. In some embodiments, the first lightly doped region 122 is located in the substrate 102 beside the outer sidewall 112a of the first gate structure 112; the second lightly doped region 124 is located beside the outer sidewall 114a of the second gate structure 114 In the substrate 102; the inner sidewall 112b of the first gate structure 112 and the inner sidewall 114b of the second gate structure 114 do not have a concentration similar to that of the first lightly doped region 122 and the second lightly doped region 124 Lightly doped area.

1C, after forming the first lightly doped region 122 and the second lightly doped region 124, a spacer 130 is formed on the sidewall of the gate structure assembly 110. In some embodiments, the spacer 130 is located on the outer sidewall 112 a and the inner sidewall 112 b of the first gate structure 112; and the outer sidewall 114 a and the inner sidewall 114 b of the second gate structure 114. In some embodiments, the top surfaces of the first gate structure 112 and the second gate structure 114 are exposed. In other embodiments, the spacer 130 may further cover the top surfaces of the first gate structure 112 and the second gate structure 114. The material of the spacer 130 may be a dielectric material. The material of the spacer 130 is, for example, silicon nitride or silicon oxide, and the formation method thereof is, for example, chemical vapor deposition. The spacer 130 may be a single layer or multiple layers. The forming step of the spacer 130 is, for example, to deposit a dielectric material layer on the substrate 102 first, and then perform anisotropic etching on the dielectric material layer.

Please refer to FIGS. 1D, 1E and 2B at the same time. After the spacer 130 is formed, a patterned photoresist layer 18 is formed on the substrate 102. The patterned photoresist layer 18 has an opening 02. The photoresist layer 18 covers the isolation structure 104. In some embodiments, the opening 02 exposes the substrate 102, the spacer 130, the first gate structure 112 and the second gate structure 114 of the active area AA. In other embodiments, the opening O2 not only exposes the substrate 102, the spacer 130, the first gate structure 112 and the second gate structure 114 of the active area AA, but also exposes the isolation structure 104 around the active area AA , As shown in Figure 1D and Figure 2B.

Next, an ion implantation process is performed to form an inner doped region 140 and an outer doped region 150 having a second conductivity type in a part of the substrate 102 of the active region AA exposed by the opening O2. The outer doped region 150 having the second conductivity type includes a first outer doped region 152 and a second outer doped region 154. In other embodiments, based on process requirements, other photoresist pattern designs or other doping steps may be used to perform multiple ion implantation processes to form the inner doped region 140 and the first outer doped region 152 and the first Two outer doped regions 154. Next, the patterned photoresist layer 18 is removed.

The first out-doped region 152 is adjacent to the first gate structure 112, and the second out-doped region 154 is adjacent to the second gate structure 112. The first and second externally doped regions 152 and 154 may be the same type of externally doped regions. The inner doped region 140 is, for example, sandwiched in the substrate 102 between the first gate structure 112 and the second gate structure 114; and the first outer doped region 152 and the second outer doped region 154 are located in the inner doped region 140. In the substrate 102 outside the first gate structure 112 and the second gate structure 114.

Specifically, the inner doped region 140 is, for example, sandwiched in the substrate 102 between the inner sidewall 112b of the first gate structure 112 and the inner sidewall 114b of the second gate structure 114. In other words, the first gate structure 112 and the second gate structure 114 share the inner doped region 140. The first outer doped region 152 is, for example, adjacent to the outer sidewall 112a of the first gate structure 112 in the substrate 102; and the second outer doped region 154 is, for example, adjacent to the outer sidewall of the second gate structure 114 In the substrate 102 next to 114a.

In some embodiments, the side wall 152a and the bottom surface 152b of the first outer doped region 152 are covered by the first lightly doped region 122; the side wall 154a and the bottom surface 154b of the second outer doped region 154 are covered by the second lightly doped region 124 coating. The sidewall 140a and the bottom surface 140b of the inner doped region 140 are not covered by the lightly doped region. In other words, each lightly doped region 120 separates the corresponding outer doped region 150 and the substrate 102 so that the corresponding outer doped region 150 does not directly contact the substrate 102; and the inner doped region 140 directly contacts the substrate 102 . In some embodiments, the first externally doped region 152 and the second externally doped region 154 may be electrically connected to each other through subsequent interconnection, as shown in FIG. 1E.

In some embodiments, the inner doped region 140 has a width W1; and the first outer doped region 152 and the second outer doped region 154 have a width W2. The width W1 of the inner doped region 140 is, for example, greater than or equal to the width W2 of the outer doped region 150, but the invention is not limited thereto.

In this embodiment, the second conductivity type is, for example, N type, and the inner doped region 140 and the first outer doped region 152 and the second outer doped region 154 are, for example, N type doped regions. The N-type doping is, for example, phosphorus or arsenic. The doping concentration range of the inner doped region 140, the first outer doped region 152, and the second outer doped region 154 is, for example, 10 ²⁰ /cm ³ to 10 ²² /cm ³ .

In some embodiments, the doping concentration of the inner doping region 140 and the doping concentration of the first outer doping region 152 and the second outer doping region 154 may be the same; the inner doping region 140, the first outer doping The doping concentration of the region 152 and the second outer doping region 154 and the doping concentration of the first lightly doped region 122 and the second lightly doped region 124 may be different. In some embodiments, the doping concentration of the inner doped region 140 is equal to the doping concentration of the first outer doped region 152 and the second outer doped region 154; the inner doped region 140, the first outer doped region 152 and The doping concentration of the second outer doped region 154 is greater than that of the lightly doped region 120. In some embodiments, the doping concentration of the first lightly doped region 122 and the second lightly doped region 124 is the doping of the inner doped region 140, the first outer doped region 152 and the second outer doped region 154 1/1000 to 1/10 of the concentration.

In some embodiments, the inner doped region 140 is used as a source region, for example, and the first outer doped region 152 and the second outer doped region 154 are used as drain regions, for example. The impurity region 122 covers the side wall 152a and the bottom surface 152b of the first outer doped region 152; the second lightly doped region 124 covers the side wall 154a and the bottom surface 154b of the second outer doped region 154, which can reduce the internal doping region ( Source region) 140 electron flow on the two outer doped regions (drain region) 150 caused by a hot carrier effect (hot carrier effect) to protect the two first doped regions 152 and the second doped Miscellaneous area (drainage area) 154. Thus, the semiconductor device 100 is completed.

In this embodiment, the first conductivity type is, for example, P type; the second conductivity type is, for example, N type. The semiconductor device 100 formed by the first gate structure 112, the second gate structure 114, the inner doped region 140, the first outer doped region 152, and the second outer doped region 154 is called an NMOS semiconductor device.

In this embodiment, by having the inner doped region 140 in the single semiconductor device 100 sandwiched between the first gate structure 112 and the second gate structure 114, the first outer doped region 152 and the second outer doped The region 154 is located in the substrate outside the inner doped region 140 and the two gate structures 112 and 114. The first lightly doped region 122 covers the sidewall 152a and the bottom surface 152b of the first outer doped region 152; the second lightly doped region The impurity region 124 covers the side wall 154a and the bottom surface 154b of the second outer doped region 154; and the side wall 140a and the bottom surface 140b of the inner doped region 140 are not covered by the lightly doped region, so that two adjacent inner doped regions 140 and the first outer doped region 152 or the second outer doped region 154 will not cause punch-through leakage current due to the lateral diffusion of two lightly doped regions 120 contacting each other. Furthermore, the gate length of the semiconductor element 100 can be effectively shortened.

It must be noted here that the following embodiments follow the element labels and partial contents of the above embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted, and the description of the omitted portions Reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

3A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 3B is a graph of the relationship between the thickness direction of the substrate and the doping concentration in FIG. 3A.

Please refer to FIGS. 3A and 3B at the same time. The semiconductor element 200 in FIG. 3A is similar to the semiconductor element 100 in FIG. 1E, the difference is that the first conductivity type of the semiconductor element 200 is, for example, N type; the second conductivity type is, for example, P type. The substrate 202 is, for example, an N-type substrate. The lightly doped region 220 is, for example, a P-type lightly doped region, wherein the lightly doped region 220 includes a first lightly doped region 222 and a second lightly doped region 224; the inner doped region 240 is, for example, a P type doped region; The externally doped region 250 is, for example, a P-type doped region, wherein the externally doped region 250 includes a first externally doped region 252 and a second externally doped region 254. In this embodiment, the semiconductor device 200 formed by the first gate structure 112, the second gate structure 114, the inner doped region 240, the first outer doped region 252, and the second outer doped region 254 is referred to as PMOS semiconductor element.

In some embodiments, as shown in FIG. 3B, the substrate 202 may have four non-uniform doped regions NW1, NW2, NW3, and NW4 in sequence from the bottom surface 202b to the top surface 202a. In other embodiments, it may be a plurality of well regions diffused through high-temperature thermal annealing or rapid thermal annealing. The doped region NW1 is located at a position of 1 μm to 3 μm from the top surface 202a of the substrate 202; the doped region NW2 is located at a position of 0.5 μm to 2 μm from the top surface 202a of the substrate 202; the doped region NW3 is located at a distance of the substrate, for example The position of 0.2 μm to 1 μm of the top surface 202 a of 202; and the doped region NW4 is, for example, located at a position of 0 μm to 0.6 μm from the top surface 202 a of the substrate 202. In some embodiments, the doping concentration range in the doped region NW1 is, for example, between 10 ¹⁴ /cm ³ and 10 ¹⁷ /cm ³ ; the doping concentration range in the doped region NW2 is, for example, between 10 ¹⁶ /cm ³ to 10 ¹⁸ /cm ³ ; the doping concentration range in the doped region NW3 is, for example, between 10 ¹⁷ /cm ³ to 10 ¹⁸ /cm ³ ; and the doping concentration in the doped region NW4 The range is, for example, between 10 ¹⁶ /cm ³ and 10 ¹⁸ /cm ³ . In this embodiment, by doping different regions in the substrate 202 with different concentration ranges, the deeper doped regions NW1, NW2 can reduce the resistance of the well region, and improve the latch-up effect (latch up) to slow down the parasitic Double carrier junction transistor (BJT) turn on phenomenon; the doped regions NW2 and NW3 in the middle of the depth, in addition to complementing the resistance distribution of the well region of the deeper doped region, can also reduce the source /The breakdown phenomenon generated by the bias voltage reduces the depletion phenomenon and improves the leakage current; and the shallowest depth of the doped region NW4 can adjust the threshold voltage of the semiconductor device, so no additional process is needed to control the threshold voltage.

Please refer to FIG. 4, the semiconductor device 300 in FIG. 4 is similar to the semiconductor device 100 in FIG. 1D, the difference is that the semiconductor device 300 has only one lightly doped region 320 having the second conductivity type, and the lightly doped region 320 Only the sidewall 140a and the bottom surface 140b of the inner doped region 140 are encapsulated. In other words, the lightly doped region 320 separates the inner doped region 140 from the substrate 102 so that the inner doped region 140 does not directly contact the substrate 102; and the lightly doped region 320 does not separate the first outer doped region 152 from The second out-doped region 154 makes the first out-doped region 152 and the second out-doped region 154 directly contact the substrate 102.

The efficacy of the semiconductor device according to the embodiment of the present invention will be described by experiments below.

<Example 1>

Conduct electrical tests on the semiconductor element 100 with a gate length (L) of 0.4 μm. The electrical test items include critical voltage (V _T ), characteristic on-resistance (R _on ), drain-source current (I _DS ), The breakdown voltage (BVD) and leakage current (I _OF ) are shown in Table 1 and Figure 5.

<Comparative Example 1>

A semiconductor element A is provided, wherein the semiconductor element A is an NMOS semiconductor element. The difference between the semiconductor element A and the semiconductor element 100 is that the semiconductor element A has only one gate structure, one source region and one drain region, and its gate length (L) is 0.6 μm. The semiconductor element A was electrically tested, and the results are shown in Table 1 and FIG. 5.

<Comparative example 2>

A semiconductor element B is provided, wherein the semiconductor element B is an NMOS semiconductor element. The difference between the semiconductor element B and the semiconductor element 100 is that the semiconductor element B has only one gate structure, one source region and one drain region, and its gate length (L) is 0.55 μm. The semiconductor element B was electrically tested, and the results are shown in Table 1 and FIG. 5.

<Comparative Example 3>

A semiconductor element C is provided, wherein the semiconductor element C is an NMOS semiconductor element. The difference between the semiconductor element C and the semiconductor element 100 is that the semiconductor element C has only one gate structure, one source region and one drain region, and its gate length (L) is 0.5 μm. The semiconductor element C was electrically tested, and the results are shown in Table 1 and FIG. 5.

Table 1 L (μm) V _T (V) R _on (mohm-mm ² ) I _DS (μA/μm) BVD (V) I _OF (pA/μm) Example 1 0.4 1 1.86 401 12.3 0.6 Comparative example 1 0.5 0.7 1.43 680 10.5 37.5 Comparative example 2 0.55 0.7 1.98 622 12.2 1.1 Comparative Example 3 0.6 0.8 2.31 572 12.3 0.07

The results from Table 1 and FIG. 5 show that the electrical performance of the device of Example 1 with a gate length of 0.4 μm can maintain the level of the devices of Comparative Examples 1 to 3 with a gate length of 0.6 μm, 0.55 μm, and 0.5 μm. , The semiconductor device 100 representing the present invention can still maintain certain electrical characteristics when shortening the gate length and reducing the specific on-resistance.

<Example 2>

The semiconductor element 200 having a gate length (L) of 0.4 μm was electrically tested, and the results are shown in Table 2 and FIG. 6.

<Comparative Example 4>

A semiconductor element D is provided, wherein the semiconductor element D is a PMOS semiconductor element. The difference between the semiconductor element D and the semiconductor element 200 is that the semiconductor element D has only one gate structure, one source region and one drain region, and its gate length (L) is 0.5 μm. The semiconductor element D was electrically tested, and the results are shown in Table 2 and FIG. 6.

Table 2 L (μm) V _T (V) R _on (mohm-mm ² ) I _DS (μA/μm) BVD (V) I _OF (pA/μm) Example 2 0.4 0.84 4.46 321 9 0.15 Comparative Example 4 0.5 0.82 8 290 9 0.25

The results from Table 2 and FIG. 6 show that the electrical performance of the device of Example 2 with a gate length of 0.4 μm can maintain the level of the device of Comparative Example 4 with a gate length of 0.5 μm, which represents the semiconductor device 200 of the present invention When shortening the gate length and reducing the specific on-resistance, certain electrical characteristics can still be maintained.

In summary, in the present invention, a single semiconductor device has an inner doped region sandwiched between two gate structures, and two outer doped regions are located in the substrate outside the inner doped region and the two gate structures , The lightly doped region covers the side wall and bottom surface of the outer doped region, but does not cover the side wall and bottom surface of the inner doped region, or the lightly doped region covers the side wall and bottom surface of the inner doped region; The side walls and bottom surface of the outer doped region prevent two adjacent lightly doped regions from laterally diffusing and contacting each other to cause breakdown leakage current near the two adjacent inner doped regions and the outer doped region, which can be effectively Shorten the gate length of the semiconductor device while maintaining certain electrical characteristics.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

16, 18‧‧‧ Patterned photoresist layer

100, 200, 300, A, B, C, D

102, 202‧‧‧ base

102a, 202a‧‧‧Top surface of the base

102b, 202b ‧‧‧ bottom of the base

104‧‧‧Isolated structure

110‧‧‧Gate structure combination

112、114‧‧‧Gate structure

12a, 14a ‧‧‧ gate dielectric layer

12b, 14b‧‧‧Conductor layer

120, 122, 124, 220, 222, 224, 320 ‧‧‧ lightly doped regions

112a, 114a‧‧‧Outside wall

112b, 114b‧‧‧Inner side wall

130‧‧‧Gap

140, 240‧‧‧Inner doped area

150, 152, 154, 250, 252, 254

140a‧‧‧Inner doped sidewall

140b‧‧‧Bottom surface of inner doped region

152a, 154a

152b, 154b ‧‧‧ bottom surface of the outer doped region

AA‧‧‧Active area

L1, L2‧‧‧ Gate length

O1, O2‧‧‧ opening

PW1, PW2, PW3, PW4, NW1, NW2, NW3, NW4

W1, W2‧‧‧Width

1A to 1E are schematic cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the invention. FIG. 1F is a graph of the relationship between the thickness direction of the substrate and the doping concentration in FIG. 1A. FIG. 2A is a schematic top view of the semiconductor device according to FIG. 1B. 2B is a schematic top view of the semiconductor device according to FIG. 1D. 3A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 3B is a graph of the relationship between the thickness direction of the substrate and the doping concentration in FIG. 3A. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 5 is an electrical graph of the semiconductor device according to FIG. 1E and the semiconductor device of the comparative example. 6 is an electrical graph of the semiconductor device according to FIG. 3A and the semiconductor device of the comparative example.

100‧‧‧Semiconductor components

102‧‧‧ base

104‧‧‧Isolated structure

110, 112, 114 ‧‧‧ gate structure

12a, 14a ‧‧‧ gate dielectric layer

12b, 14b‧‧‧Conductor layer

120, 122, 124 ‧‧‧ lightly doped regions

112a, 114a‧‧‧Outside wall

112b, 114b‧‧‧Inner side wall

130‧‧‧Gap

140‧‧‧Inner doped area

150, 152, 154

140a‧‧‧Inner doped sidewall

140b‧‧‧Bottom surface of inner doped region

152a, 154a

152b, 154b ‧‧‧ bottom surface of the outer doped region

AA‧‧‧Active area

W1, W2‧‧‧Width

Claims (8)

A semiconductor device includes: a substrate having a first conductivity type; at least one gate structure combination, each of the gate structure combinations includes a first gate structure and a second gate structure, and the gate structure combination is configured in On the substrate; wherein the semiconductor element including each of the gate structure combinations includes: an inner doped region having a second conductivity type, wherein the inner doped region is located in the substrate, the inner The doped region is in direct contact with the substrate, and the inner doped region is sandwiched between the first gate structure and the second gate structure; two outer doped regions have the second conductivity Type, wherein the two outer doped regions are located in the substrate, and the two outer doped regions are located between the inner doped region, the first gate structure, and the second gate structure Outside the substrate; and two lightly doped regions, having the second conductivity type, wherein the two lightly doped regions are located in the substrate, the lightly doped regions cover the outer doping The side wall and the bottom surface of the impurity region, and the side wall and the bottom surface of the inner doped region are not covered by the lightly doped region. The semiconductor device according to item 1 of the patent application range, wherein the inner doped region is a source region, and the outer doped region is a drain region. The semiconductor device according to item 2 of the patent application scope, wherein the two drain regions are electrically connected to each other. The semiconductor device according to item 1 of the patent application range, wherein the doping concentration of the outer doped region is greater than that of the lightly doped region. The semiconductor device according to item 1 of the patent application scope, wherein each of the lightly doped regions separates the corresponding outer doped region from the substrate. A semiconductor device includes: a substrate having a first conductivity type; at least one gate structure combination, each of the gate structure combinations includes a first gate structure and a second gate structure, and the gate structure combination is configured in On the substrate; wherein the semiconductor element including each of the gate structure combinations includes: an internally doped region having a second conductivity type, wherein the internally doped region is located in the substrate, and the The inner doped region is sandwiched between the first gate structure and the second gate structure; two outer doped regions have the second conductivity type, wherein the two outer doped regions are located at In the substrate, the two outer doped regions are in direct contact with the substrate, and the two outer doped regions are located in the inner doped region, the first gate structure, and the second gate In the substrate outside the structure; and a lightly doped region having the second conductivity type, wherein the lightly doped region is located in the substrate, the lightly doped region encapsulates the inner doped region And the bottom surface of the outer doped region, and the side walls and the bottom surface of the outer doped region are not covered by the lightly doped region. The semiconductor device according to item 6 of the patent application range, wherein the doping concentration of the inner doped region is greater than that of the lightly doped region. The semiconductor device as described in item 6 of the patent application range, wherein the inner doped region is a source region, and the outer doped region is a drain region.

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