KR100529447B1 - Method for manufacturing mos transistor - Google Patents

Abstract

The present invention relates to a method of manufacturing a MOS transistor of a semiconductor device, comprising the steps of: thermally oxidizing a surface of a semiconductor substrate to form an oxide film for forming a gate insulating film, depositing a gate layer polysilicon layer on the oxide film, and polysilicon Forming a first diffusion barrier layer formed of a nitride film by implanting first N + ions into a region adjacent to the gate dielectric of the lower surface of the layer; and implanting a second N + ion implanted into an upper surface of the polysilicon layer. And forming a diffusion barrier film. According to the present invention, it is possible to prevent the external diffusion of impurities generated during the high temperature annealing process and the doping process and the penetration of boron (B) through the gate dielectric to prevent an increase in resistance in the gate and source / drain regions. There is an effect that can improve the device performance.

Description

Method of manufacturing MOS transistor of semiconductor device {METHOD FOR MANUFACTURING MOS TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a moss of a semiconductor device suitable for preventing external diffusion of impurities generated during annealing and doping processes and penetration of boron (B) through a gate dielectric. A method of manufacturing a transistor.

As semiconductor devices become highly integrated, each cell becomes finer, and the internal electric field strength increases. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film generates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (VTH) or lowering the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like should be used.

1A-1C are cross-sectional views of a MOS transistor fabrication process for a typical semiconductor device including such an LDD structure.

Referring to FIG. 1A, a device active region and an isolation region are defined in a predetermined portion of a surface of a p-type semiconductor substrate 100 made of silicon by LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). A field oxide film (not shown), which is a device isolation film, is formed to define an active region and a field region of the device.

Then, a predetermined portion of the active region of the substrate is removed by photolithography to form a trench in which a gate is to be formed. After trench formation, ion implantation for adjusting the threshold voltage is performed on the exposed entire surface of the substrate.

Thereafter, the surface of the semiconductor substrate 100 including the trench inner surface is thermally oxidized to form an oxide film 102 for forming a gate insulating film.

Then, the gate forming polysilicon layer 104 is deposited on the field oxide film and the gate insulating film forming oxide film 102 by chemical vapor deposition (hereinafter, referred to as CVD). In this case, the polysilicon layer 104 is formed using a doped or undoped silicon layer and then doped by a method such as ion implantation to have conductivity.

Referring to FIG. 1B, after the photoresist is coated on the polysilicon layer 104, a photoresist pattern (not shown) covering the gate formation region is formed by performing exposure and development using an exposure mask defining a gate.

Then, the gate pattern 104 is formed by removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern by anisotropic etching such as dry etching. In this case, since the gate pattern 104 is formed in the trench, the effective channel length of the formed transistor is increased and the top pattern is partially protruded on the surface of the substrate, so that the step with the peripheral portion is improved.

Next, n-type impurity ion implantation using the gate pattern 104 as an ion implantation mask is performed in the exposed active region of the substrate 100 at low concentration to form a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern. do. At this time, the low concentration impurity ion buried layer is formed to form the low concentration impurity diffusion region 106 of the LDD structure.

Referring to FIG. 1C, an insulating layer such as silicon oxide or a nitride film is deposited on the substrate to cover the gate pattern 104, and then etched back to expose the surface of the semiconductor substrate 100 so as to expose sidewall spacers. Form 108. At this time, the sidewall spacer 108 is used as an ion implantation mask to insulate the gate 104 from the periphery and to form the high concentration impurity diffusion region 110 of the source / drain.

In addition, by using the gate pattern 104 and the sidewall spacers 108 as ion implantation masks, high concentrations of n-type impurity ions are implanted into the exposed active regions of the semiconductor substrate 100 to serve as source and drain regions. An impurity ion buried layer is formed. At this time, the high concentration impurity ion buried layer mostly overlaps with the low concentration impurity ion buried layer, but only the low concentration impurity ion buried layer exists under the sidewall spacer 108.

Then, an annealing or the like is performed on the substrate 100 on which the low concentration impurity ion buried layer and the high concentration impurity ion buried layer are formed to diffuse impurity ions for forming a source / drain junction, so that the low concentration impurity diffusion region 106 and A high concentration impurity diffusion region 110 is formed.

At this time, since the annealing process is performed at a high temperature, impurities in the gate 104 and the source / drain region 110 may diffuse to the outside. In particular, in the P type gate, boron (B) penetration phenomenon through the gate dielectric may occur. This may occur.

This increases the resistance in the gate 104 and source / drain regions 110, resulting in degradation of the device performance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and forms a nitride film by N + ion implantation in the adjacent portions of the gate dielectric and the source / drain regions of the upper and lower surfaces of the polysilicon layer for gate formation. It is an object of the present invention to provide a MOS transistor manufacturing method of a semiconductor device capable of preventing external diffusion.

According to an embodiment of the present invention for achieving the above object, in the semiconductor device manufacturing method, the step of thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film, and a polysilicon layer for forming a gate on the oxide film Depositing N, implanting N + ions into the lower surface of the polysilicon layer to form a first diffusion barrier layer, and performing N + ion implantation to the upper surface of the polysilicon layer to form a second diffusion barrier layer And applying a photoresist on the polysilicon layer, followed by exposure and development using an exposure mask defining a gate to form a photoresist pattern covering the gate formation region, and forming a gate not protected by the photoresist pattern. The gate pattern is formed by dry etching and removing the polysilicon layer and the oxide film for forming the gate insulating film by dry etching. Forming a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern, and depositing an insulating layer on the substrate to cover the gate pattern, and then etching back to expose the surface of the semiconductor substrate. Forming a sidewall spacer, forming a high concentration impurity ion buried layer in an exposed active region of the semiconductor substrate using the gate pattern and the sidewall spacer as an ion implantation mask, and performing an annealing process. A method of manufacturing a MOS transistor of a semiconductor device, the method including forming a low concentration impurity diffusion region and a high concentration impurity diffusion region by diffusing impurity ions for forming a source / drain junction.

According to another embodiment for achieving the object of the present invention, in the semiconductor device manufacturing method, the step of thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film, and a polysilicon layer for forming a gate on the oxide film Depositing, performing a first N + ion implantation on the lower surface of the polysilicon layer to form a first diffusion barrier layer, and applying a photoresist on the polysilicon layer and then using an exposure mask defining a gate And forming a photoresist pattern covering the gate formation region by developing, and forming a gate pattern by dry etching and removing a gate forming polysilicon layer and a gate insulating film forming oxide film which are not protected by the photoresist pattern. And implanting second N + ions into the upper surface of the gate pattern to form a second diffusion barrier layer. Forming a third diffusion barrier layer at a portion where the source / drain region is to be formed by the second N + ion implantation, and forming a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern; Depositing an insulating layer on the substrate to cover the gate pattern, and then etching back to expose the surface of the semiconductor substrate to form sidewall spacers, and using the gate pattern and the sidewall spacers as ion implantation masks to expose the active substrate. Forming a low concentration impurity diffusion region and a high concentration impurity diffusion region by forming a high concentration impurity ion buried layer in the region and diffusing impurity ions for forming a source / drain junction by performing an annealing process A method of manufacturing a MOS transistor is provided.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2E are process drawings for explaining a MOS transistor manufacturing method of a semiconductor device according to a first embodiment of the present invention.

First, referring to FIG. 2A, a device active region and an isolation region are formed on a predetermined portion of a surface of a p-type semiconductor substrate 200 made of silicon or the like by a method such as local oxide of silicon (LOCOS) or shallow trench isolation (STI). A field oxide film (not shown), which is a device isolation film, is defined to define an active region and a field region of the device.

Then, a predetermined portion of the active region of the substrate is removed by photolithography to form a trench in which a gate is to be formed. After trench formation, ion implantation for adjusting the threshold voltage is performed on the exposed entire surface of the substrate.

Then, the surface of the semiconductor substrate 200 including the trench inner surface is thermally oxidized to form an oxide film 202 for forming a gate insulating film.

Then, a gate forming polysilicon layer 204 is deposited on the field oxide film and the gate insulating film forming oxide film 202 by chemical vapor deposition (hereinafter, referred to as CVD). At this time, the polysilicon layer 204 is formed using a doped or undoped silicon layer and then doped by a method such as ion implantation to have conductivity.

Then, in FIG. 2B, N + ion implantation is performed on the lower surface of the polysilicon layer 204 according to the present embodiment to form the first diffusion barrier film 206, for example, a nitride film. In this case, the N + ion implantation is performed at a region adjacent to the gate dielectric of the lower surface of the polysilicon layer 204.

In FIG. 2C, an N + ion implantation is performed on the upper surface of the polysilicon layer 204 to form a second diffusion barrier 208, for example, a nitride film.

The first and second diffusion barrier layers 206 and 208 will then serve as barrier layers to prevent external diffusion of impurities.

Referring to FIG. 2D, a photoresist is applied on the polysilicon layer 204, followed by exposure and development using an exposure mask defining a gate to form a photoresist pattern (not shown) covering the gate formation region.

The gate pattern 204 is formed by removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern by anisotropic etching such as dry etching. At this time, since the gate pattern 204 is formed in the trench, the effective channel length of the formed transistor is increased and the top pattern is partially protruded on the surface of the substrate, thereby improving the level difference with the peripheral portion.

Next, n-type impurity ion implantation using the gate pattern 204 as an ion implantation mask is performed in the exposed active region of the substrate 200 at low concentration to form a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern. do. In this case, the low concentration impurity ion buried layer is formed to form the low concentration impurity diffusion region 210 of the LDD structure.

Subsequently, in FIG. 2E, an insulating layer such as silicon oxide or a nitride film is deposited on the substrate to cover the gate pattern 204, and then etched back to expose the surface of the semiconductor substrate 200. 212). At this time, the sidewall spacer 210 is used as an ion implantation mask to insulate the gate 204 from the periphery and to form the high concentration impurity diffusion region 214 of the source / drain.

In addition, by using the gate pattern 204 and the sidewall spacers 212 as ion implantation masks, high concentrations of n-type impurity ions are implanted into the exposed active regions of the semiconductor substrate 200 to serve as source and drain regions. An impurity ion buried layer is formed. At this time, the high concentration impurity ion buried layer mostly overlaps with the low concentration impurity ion buried layer, but only the low concentration impurity ion buried layer is present under the sidewall spacer 212.

Next, a thermal process such as annealing is performed on the substrate 200 on which the low concentration impurity ion buried layer and the high concentration impurity ion buried layer are formed to diffuse impurity ions for forming a source / drain cushion, so as to diffuse the low concentration impurity diffusion region 210. A high concentration impurity diffusion region 214 is formed.

That is, in the MOS transistor manufacturing method according to the first embodiment of the present invention, after forming polysilicon, a nitride film as a barrier layer is formed on the upper and lower surfaces of the gate to prevent external diffusion of impurities and to prevent boron through the gate dielectric. B) to prevent penetration.

3A to 3F are process drawings for explaining a MOS transistor manufacturing method of a semiconductor device according to a second embodiment of the present invention.

First, referring to FIG. 3A, a field oxide film, which is a device isolation film, defining an element active region and an isolation region is formed on a predetermined portion of a surface of a p-type semiconductor substrate 300 made of silicon or the like to define an active region and a field region of a device. do.

Then, a predetermined portion of the active region of the substrate is removed by photolithography to form a trench in which a gate is to be formed. After trench formation, ion implantation for adjusting the threshold voltage is performed on the exposed entire surface of the substrate.

Next, the surface of the semiconductor substrate 300 including the trench inner surface is thermally oxidized to form an oxide film 302 for forming a gate insulating film.

Then, a gate forming polysilicon layer 304 is deposited on the field oxide film and the gate insulating film forming oxide film 302 by chemical vapor deposition (hereinafter, referred to as CVD). In this case, the polysilicon layer 304 is formed using a doped or undoped silicon layer and then doped by a method such as ion implantation to have conductivity.

Then, in FIG. 3B, N + ion implantation is performed on the lower surface of the polysilicon layer 304 according to the present embodiment to form the first diffusion barrier 306, for example, a nitride film. In this case, N + ion implantation is characterized in that performed in the region adjacent to the gate dielectric of the lower surface of the polysilicon layer (304).

Referring to FIG. 3C, a photoresist is applied on the polysilicon layer 304 and then exposed and developed using an exposure mask defining a gate to form a photoresist pattern (not shown) covering the gate formation region.

The gate pattern 304 is formed by removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern by anisotropic etching such as dry etching. At this time, since the gate pattern 204 is formed in the trench, the effective channel length of the formed transistor is increased and the top pattern is partially protruded on the surface of the substrate, thereby improving the level difference with the peripheral portion.

Next, in FIG. 3D, the second diffusion barrier layer 308 and the third diffusion barrier layer 310 are formed by implanting N + ions into the upper surface of the gate pattern 304 and the portion where the source / drain region is to be formed, according to the present exemplary embodiment. Form.

In this case, the second diffusion barrier layer 308 is a nitride film, and the third diffusion barrier layer 310 is formed of a nitride oxide (Nitrided-Oxide).

Since the subsequent steps go through the same procedure as in the above-described first embodiment, a detailed description thereof will be omitted.

As described above, in the MOS transistor manufacturing method according to the second embodiment of the present invention, after the gate is etched, a nitride film as a barrier layer is formed on the gate surface and a nitride oxide film as a barrier layer is formed on the source / drain regions, thereby preventing external diffusion of impurities. This is to prevent boron (B) penetration through the gate dielectric.

According to the present invention, it is possible to prevent the external diffusion of impurities generated during the high temperature annealing process and the doping process and the penetration of boron (B) through the gate dielectric to prevent an increase in resistance in the gate and source / drain regions. There is an effect that can improve the device performance.

As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.

1A to 1C are views for explaining a MOS transistor manufacturing method of a conventional semiconductor device;

2A to 2E are views for explaining a MOS transistor manufacturing method of a semiconductor device according to an embodiment of the present invention;

3A to 3F are views for explaining a MOS transistor manufacturing method of a semiconductor device according to another embodiment of the present invention.

Claims (7)

In the semiconductor device manufacturing method, Thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film; Depositing a polysilicon layer for gate formation on the oxide layer; Forming a first diffusion barrier layer by implanting first N + ions into the lower surface of the polysilicon layer; Forming a second diffusion barrier layer by implanting second N + ions into an upper surface of the polysilicon layer; Applying a photoresist on the polysilicon layer and then performing exposure and development using an exposure mask defining a gate to form a photoresist pattern covering the gate formation region; Forming a gate pattern by dry etching and removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern; Forming a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern; Depositing an insulating layer on the substrate to cover the gate pattern, and then etching back to expose the surface of the semiconductor substrate to form sidewall spacers; Forming a high concentration impurity ion buried layer in an exposed active region of the semiconductor substrate using the gate pattern and the sidewall spacer as an ion implantation mask; Performing an annealing process to diffuse the impurity ions for forming the source / drain junction to form a low concentration impurity diffusion region and a high concentration impurity diffusion region; The MOS transistor manufacturing method of the semiconductor device containing the. The method of claim 1, And the first N + ion implantation is performed at a region adjacent to the gate dielectric of the lower surface of the polysilicon layer. The method of claim 1, And said first and second diffusion barrier layers are nitride films. In the semiconductor device manufacturing method, Thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film; Depositing a polysilicon layer for gate formation on the oxide layer; Forming a first diffusion barrier layer by implanting first N + ions into the lower surface of the polysilicon layer; Applying a photoresist on the polysilicon layer and then performing exposure and development using an exposure mask defining a gate to form a photoresist pattern covering the gate formation region; Forming a gate pattern by dry etching and removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern; Forming a second diffusion barrier layer by implanting second N + ions into an upper surface of the gate pattern; Forming a third diffusion barrier layer at a portion where the source / drain region is to be formed by the second N + ion implantation; Forming a low concentration impurity ion buried layer in a form corresponding to each other on both sides of the gate pattern; Depositing an insulating layer on the substrate to cover the gate pattern and then etching back to expose the surface of the semiconductor substrate to form sidewall spacers; Forming a high concentration impurity ion buried layer in an exposed active region of the semiconductor substrate using the gate pattern and the sidewall spacer as an ion implantation mask; Performing an annealing process to diffuse the impurity ions for forming the source / drain junction to form a low concentration impurity diffusion region and a high concentration impurity diffusion region; The MOS transistor manufacturing method of the semiconductor device containing the. The method of claim 4, wherein And the first N + ion implantation is performed at a region adjacent to the gate dielectric of the lower surface of the polysilicon. The method of claim 4, wherein And said first and second diffusion barrier layers are nitride films. The method of claim 4, wherein The third diffusion barrier layer is a nitride oxide film (Nitrided-Oxide) method of manufacturing a MOS transistor of a semiconductor device.