KR100632043B1 - Method for manufacturing mos transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor of a semiconductor device, wherein the surface of a semiconductor substrate is thermally oxidized to form an oxide film for forming a gate insulating film, and a gate forming polysilicon is deposited over the semiconductor substrate and the oxide film. The oxide film and the polysilicon are removed to form a gate pattern, and a low concentration of impurity ions are implanted onto the semiconductor substrate using the gate pattern as a mask to form a first LDD region, and a TEOS film is deposited and etched over the entire gate pattern. The first LDD is formed on the sidewall of the gate electrode, and the impurity ion implantation at a concentration higher than or equal to the ion implantation concentration at the time of forming the first LDD region is formed on the semiconductor substrate by using the gate electrode and the first spacer as a mask. Forming a region, and depositing and etching an insulating layer on the semiconductor substrate, Forming a source / drain region by forming a second spacer on a sidewall of the gate pattern outside the phaser, and implanting a high concentration of impurity ions onto the semiconductor substrate using the gate electrode, the first spacer, and the second spacer as a mask; do. According to the present invention, a buffer LDD structure is formed by using a TEOS film as a buffer LDD spacer without applying a separate new structure formation, thereby preventing deterioration of device characteristics due to a hot-carrier effect even if the channel is small on a nano scale. have.

LDD, hot-carrier effect

Description

Method of manufacturing MOS transistor of semiconductor device {METHOD FOR MANUFACTURING MOS TRANSISTOR}

1A to 1E are views for explaining a MOS transistor manufacturing method of a conventional semiconductor device;

2A to 2G are views for explaining a MOS transistor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device fabrication technology, and more particularly, to a method of manufacturing a MOS transistor of a semiconductor device suitable for improving transistor degradation characteristics caused by a hot-carrier effect.

As semiconductor devices become highly integrated, each cell becomes finer, and the internal electric field strength increases. This increase in electric field strength causes a hot-carrier effect in which carriers in the channel region are accelerated and injected into the gate oxide film in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film generates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (VTH) or lowering the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as LDD should be used.

1A-1E are cross-sectional views of a MOS transistor fabrication process for a typical semiconductor device including such an LDD structure.

Referring to FIG. 1A, a device active region and an isolation region are defined in a predetermined portion of a surface of a p-type semiconductor substrate 100 made of silicon by LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). A field oxide film (not shown), which is a device isolation film, is formed to define an active region and a field region of the device.

Then, a predetermined portion of the active region of the substrate is removed by photolithography to form a trench in which a gate is to be formed. After trench formation, ion implantation for adjusting the threshold voltage is performed on the exposed entire surface of the substrate.

Thereafter, the surface of the semiconductor substrate 100 including the trench inner surface is thermally oxidized to form an oxide film 102 for forming a gate insulating film.

Then, the gate forming polysilicon layer 104 is deposited on the field oxide film and the gate insulating film forming oxide film 102 by chemical vapor deposition (hereinafter, referred to as CVD). In this case, the polysilicon layer 104 is formed using a doped or undoped silicon layer and then doped by a method such as ion implantation to have conductivity.

Thereafter, after the photoresist is applied on the polysilicon layer 104, exposure and development using an exposure mask defining a gate are performed to form a photoresist pattern (not shown) covering the gate formation region.

Then, the gate pattern 104 is formed by removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern by anisotropic etching such as dry etching. In this case, since the gate pattern 104 is formed in the trench, the effective channel length of the formed transistor is increased and the top pattern is partially protruded on the surface of the substrate, so that the step with the peripheral portion is improved.

Next, as shown in FIG. 1B, the n-type impurity ion implantation using the gate pattern 104 as an ion implantation mask is applied to the exposed active region of the substrate 100 at low concentration to form a low concentration impurity ion buried layer in the gate pattern. It is formed in a form corresponding to each other on both sides. At this time, the low concentration impurity ion buried layer is formed to form the low concentration impurity diffusion region 106 of the LDD structure.

1C and 1D, the insulating layer 108, such as silicon oxide or nitride, is deposited on the substrate to cover the gate pattern 104 and then etched back to expose the surface of the semiconductor substrate 100. Sidewall spacers 108 'are formed. At this time, the sidewall spacer 108 'is used as an ion implantation mask to insulate the gate 104 from the periphery and to form a highly doped impurity diffusion region 110 of a source / drain described later.

In addition, in FIG. 1E, n-type impurity ions are implanted at a high concentration into the exposed active region of the semiconductor substrate 100 using the gate pattern 104 and the sidewall spacers 108 ′ as ion implantation masks, thereby forming source and drain regions. A high concentration impurity ion buried layer is used. At this time, the high concentration impurity ion buried layer mostly overlaps with the low concentration impurity ion buried layer, but only the low concentration impurity ion buried layer exists under the sidewall spacer 108.

The low concentration impurity diffusion region 106 and the high concentration impurity are diffused by performing impurity ions for forming a source / drain junction by performing a thermal process such as annealing on the substrate 100 on which the low concentration impurity ion buried layer and the high concentration impurity ion buried layer are formed. The diffusion region 110 is formed.

Thereafter, the logic process is completed through the PMD and the wiring process.

In this case, since the ion implantation process for forming the LDD region uses a relatively lower concentration of impurities than the ion implantation process for forming the source / drain regions, the channel currently being developed has a nano scale of 10 ^-9 m. As a short-circuit effect, the short-circuit effect exhibits a limitation in preventing transistor degradation due to the hot-carrier effect.

The deterioration of transistors is a factor that hinders normal chip use by modifying the characteristics of the transistors set at the time of design.

Degradation of the transistor due to such hot-carrier increases as the degree of integration of the device increases, and it is a problem to be solved because it not only makes the operation of the device difficult but also causes an initial process failure.

SUMMARY OF THE INVENTION The present invention has been implemented to solve the above-described problems of the prior art, and the MOS of a semiconductor device to prevent the hot-carrier effect by forming a buffer concentration layer after forming an LDD region and then forming a source / drain region. It is an object of the present invention to provide a transistor manufacturing method.

According to a preferred embodiment of the present invention for achieving this object, the step of thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film, and depositing a gate forming polysilicon over the semiconductor substrate and the oxide film And forming a gate pattern by removing the oxide layer and polysilicon through an exposure and etching process, and performing a low concentration impurity ion implantation on the semiconductor substrate using the gate pattern as a mask to form a first LDD region. And depositing and etching a TEOS film over the entire gate pattern to form first spacers on sidewalls of the gate electrodes, and ion implantation concentrations when forming the first LDD regions using the gate electrodes and the first spacers as masks. Higher or equal concentrations of impurity ions implanted into the semiconductor substrate Forming a second LDD region, depositing and etching an insulating layer on the semiconductor substrate to form a second spacer on a sidewall of a gate pattern outside the first spacer, and forming the gate electrode and the first spacer. And forming a source / drain region by implanting a high concentration of impurity ions onto the semiconductor substrate using the second spacer as a mask.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2G are process diagrams illustrating a MOS transistor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.

Referring to FIG. 2A, a field oxide film (not shown), which is a device isolation film defining an element active region and an isolation region, is formed on a predetermined portion of a surface of a p-type semiconductor substrate 200 made of silicon or the like by a method such as LOCOS or STI. To define the active and field regions of the device.

Then, a predetermined portion of the active region of the substrate is removed by photolithography to form a trench in which a gate is to be formed. After trench formation, ion implantation for adjusting the threshold voltage is performed on the exposed entire surface of the substrate.

Then, the surface of the semiconductor substrate 200 including the trench inner surface is thermally oxidized to form an oxide film 202 for forming a gate insulating film.

Then, a gate forming polysilicon layer 204 is deposited on the field oxide film and the gate insulating film forming oxide film 202 by, for example, a CVD technique. At this time, the polysilicon layer 204 is formed using a doped or undoped silicon layer and then doped by a method such as ion implantation to have conductivity.

Thereafter, after the photoresist is applied on the polysilicon layer 204, exposure and development using an exposure mask defining a gate are performed to form a photoresist pattern (not shown) covering the gate formation region.

The gate pattern 204 is formed by removing the gate forming polysilicon layer and the gate insulating film forming oxide film which are not protected by the photoresist pattern by anisotropic etching such as dry etching. At this time, since the gate pattern 204 is formed in the trench, the effective channel length of the formed transistor is increased and the top pattern is partially protruded on the surface of the substrate, thereby improving the level difference with the peripheral portion.

Next, as shown in FIG. 2B, the n-type impurity ion implantation using the gate pattern 204 as an ion implantation mask is applied to the exposed active region of the substrate 200 at low concentration to form the low concentration impurity ion buried layer as the gate pattern. It is formed in a form corresponding to each other on both sides. At this time, the low concentration impurity ion buried layer is formed to form the low concentration impurity diffusion region 206 of the LDD structure.

2C and 2D, a TEOS (TetraEthylOrthoSilicate) film 208 is deposited as an insulating film over the entire gate pattern 204 and etched to form a first sidewall spacer 208 ′ according to the present embodiment. Then, using the first sidewall spacer 208 'as an ion implantation mask, an impurity ion buried layer used as the buffer LDD region 210 by ion implanting n-type impurity ions into the exposed active region of the semiconductor substrate 200. To form. At this time, the ion implantation is preferably performed with low concentration impurities of the same or higher concentration as in the low concentration impurity diffusion region 206.

That is, FIG. 2D illustrates a result of forming the buffer LDD region 210 by performing an ion implantation process after etching the TEOS film 208 to form the first sidewall spacer 208 ′.

The TEOS film 208 is used to form the first sidewall spacer 208 'for the buffer LDD region 210, and the buffer LDD region 210 is larger than the low concentration impurity diffusion region 206 of the LDD structure described above. And a buffer layer having an impurity concentration (middle concentration) of less than the high concentration impurity diffusion region 214 of the source / drain structure described later.

2E and 2F, after the insulating layer 212, such as silicon oxide or nitride, is deposited on the substrate to cover the gate pattern 204, the second sidewall spacer is etched back to expose the surface of the semiconductor substrate 200. Form 212 '. In this case, the second sidewall spacer 212 ′ is used as an ion implantation mask to insulate the gate 204 from the periphery and to form a high concentration impurity diffusion region 214 of a source / drain described later.

In FIG. 2G, the gate pattern 204 and the second sidewall spacer 212 ′ are used as ion implantation masks to implant n-type impurity ions into the exposed active region of the semiconductor substrate 200 at a high concentration. A high concentration impurity ion buried layer used as the drain region is formed. At this time, the high concentration impurity ion buried layer mostly overlaps with the low concentration impurity ion buried layer, but only the low concentration impurity ion buried layer is present under the second sidewall spacer 212 ′.

Finally, thermal processing such as annealing is performed on the substrate 200 on which the low concentration impurity ion buried layer, the medium concentration impurity ion buried layer, and the high concentration impurity ion buried layer are formed to diffuse impurity ions for forming source / drain cushions. In this way, the low concentration impurity diffusion region 206, the medium concentration impurity diffusion region 210, and the high concentration impurity diffusion region 214 are formed, respectively.

Thereafter, the logic process is completed through the PMD and the wiring process.

As described above, the present invention maximizes the buffering effect by forming one more buffer concentration layer having an impurity concentration in the middle of the LDD region and the source / drain region.

According to the present invention, a buffer LDD structure is formed by using a TEOS film as a buffer LDD spacer without applying a separate new structure formation, thereby preventing deterioration of device characteristics due to a hot-carrier effect even if the channel is small on a nano scale. have.

The embodiments of the present invention have been described in detail above, but the present invention is not limited to these embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention described in the claims below.

Claims (1)

Thermally oxidizing the surface of the semiconductor substrate to form an oxide film for forming a gate insulating film; Depositing polysilicon for gate formation over the semiconductor substrate and the oxide film; Forming a gate pattern by removing the oxide layer and polysilicon through an exposure and etching process; Forming a first LDD region by implanting low concentration impurity ions onto the semiconductor substrate using the gate pattern as a mask; Depositing and etching a TEOS film over the entire gate pattern to form first spacers on sidewalls of the gate electrode; Forming a second LDD region by performing impurity ion implantation on the semiconductor substrate at a concentration higher than or equal to an ion implantation concentration when forming the first LDD region using the gate electrode and the first spacer as a mask; Depositing and etching an insulating layer on the semiconductor substrate to form a second spacer on a sidewall of the gate pattern outside the first spacer; Forming a source / drain region by implanting a high concentration of impurity ions onto the semiconductor substrate using the gate electrode, the first spacer, and the second spacer as a mask; The MOS transistor manufacturing method of the semiconductor device containing the.

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