JPH10189952A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and a manufacturing method thereof, in which increase of the threshold voltage can be suppressed through a reduction of reverse short channel effect, while enhancing hot carrier resistance. SOLUTION: This semiconductor device comprises a gate electrode 6, formed through a gate oxide 3, on a channel-forming region C between diffusion layer regions 4 formed on a semiconductor substrate 1, while being spaced apart from each other. An oxidation suppressing region 8 is formed at the opposite end parts of the gate electrode 6 and at a part of an adjacent diffusion layer region in order to retard thickening of the gate electrode 6 at the opposite end parts thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate field effect transistor constituting the semiconductor device, in which a reverse short channel effect is reduced and hot carrier resistance is reduced. Technology to improve.

[0002]

2. Description of the Related Art In recent years, MOS LSI (Metal Oxide Se
With the development of high integration and high density in the Large Scale Integrated Circuit (MOS), MOSFE
The element size of T (Field Effect Transistor) is becoming finer. With the miniaturization of semiconductor devices, the miniaturization of transistor dimensions has been followed, and the gate length is 0.35μ.
The development of 0.25 μm and 0.18 μm from the m generation has been actively conducted. When the transistor is miniaturized in this way, as the channel length of the nMOS gate becomes shorter,
A phenomenon in which the threshold voltage Vth rises occurs, and the threshold voltage Vth
th control becomes difficult.

[0003]

Generally, the above phenomenon is referred to as an inverse short channel effect, and there are various causes of the inverse short channel effect. For example, in the transistor shown in FIG. 5, a gate electrode 53 is formed on a silicon substrate 51 via a gate oxide film 52 made of, for example, polysilicon.
A DD (Light Doped Drain) region is formed by ion-implanting impurities. Here, the gate electrode 5 of the silicon substrate 51
The high concentration impurity region 56 is formed by ion-implanting impurities into the side portions of the oxide film 57. As a pre-process, an oxide film 57 is formed on the high concentration impurity region 56 by dry oxidation. 55 are formed. At this time, as shown in FIG. 5, at both ends of the gate oxide film 52, a so-called gate bird's beak 52a (Gate Bird's Beak) in which the gate oxide film 52 is partially thickened is generated.

The gate bird's beak 52a can be considered as one of the causes of the above-mentioned reverse short channel effect.
In other words, the gate edge is thickened by the gate bird's beak 52a, and as the transistor is miniaturized, the ratio of the thickened portion of the gate edge to the gate oxide film increases, so that the threshold voltage Vth increases. Become noticeable.

[0005] On the other hand, the need for a high-speed microprocessor demands the development of a higher-speed transistor. One method for increasing the speed of a transistor is to increase the concentration of impurities to be implanted into the diffusion layer to reduce series resistance. However, an increase in the impurity concentration of the diffusion layer causes an increase in the electric field, and deteriorates the hot carrier resistance of the transistor, particularly, the nMOS.

The present invention has been made in view of such circumstances, and a semiconductor device capable of suppressing an increase in the threshold voltage by reducing the reverse short channel effect and improving the hot carrier resistance, and a semiconductor device having the same. It is intended to provide a manufacturing method.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device in which a gate electrode is formed on a channel formation region interposed between diffusion layer regions formed in a semiconductor layer via an insulating oxide film, wherein both ends of the gate electrode of the semiconductor layer and In a part of the diffusion layer region adjacent to the gate electrode, an oxidation suppression region for suppressing an increase in the thickness of the insulating oxide film at both ends of the gate electrode is formed.

Thus, the oxidation suppression regions formed at both ends of the gate electrode and a part of the diffusion layer region adjacent thereto suppress generation of gate bird's beak due to oxidation of the gate edge before the formation of the diffusion layer region. Thus, a semiconductor device free from the reverse short channel effect is obtained.

In the semiconductor device according to the present invention, preferably, the diffusion layer region includes a high-concentration impurity region and a low-concentration impurity region, and the oxidation suppressing region is formed above the low-concentration impurity region. I have. Further, in the semiconductor device according to the present invention, the oxidation suppression region may be formed of a nitride layer. Thus, the LDD structure having the low-concentration impurity region and the high-concentration impurity region can suppress the short-channel effect, and, for example, suppress the reverse short-channel effect by the oxidation suppression region formed of the nitride layer. Can be performed simultaneously. Further, since the nitride layer is formed above the low-concentration impurity region, injection of hot carriers is also suppressed.

In a method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on a semiconductor substrate via an insulating oxide film, and a diffusion layer region made of a low-concentration impurity is formed on both sides of the gate electrode of the semiconductor substrate. Forming a contact with both ends of the gate electrode via the insulating oxide film,
An inert gas is ion-implanted in an oblique direction with respect to the side surface of the gate electrode into an upper layer of the diffusion layer region made of the low-concentration impurity, thereby suppressing the thickening of the insulating oxide film at both ends of the gate electrode. Forming an oxidation suppressing region, forming sidewall spacers on both sides of the gate electrode of the semiconductor substrate, and forming a diffusion layer region made of high-concentration impurities on both sides of the sidewall spacer of the semiconductor substrate. The method of manufacturing a semiconductor device according to the present invention may further comprise using nitrogen as the inert gas.

In the present invention, the nitride film is formed only on the upper layer of the LDD region by, for example, ion implantation of nitrogen obliquely with respect to the side surface of the gate electrode. Thus, a semiconductor device with reduced reverse short-channel effect and improved hot carrier resistance without charge leakage due to damage due to injection is manufactured.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention. In FIG. 1, a semiconductor substrate 1 made of, for example, an N-type silicon substrate is partitioned by a field oxide film 2 made of, for example, SiO ₂ for element isolation.
For example, WSi via a gate oxide film 3 made of SiO ₂
A gate electrode 6 having an x / PolySi structure is formed. Further, on both sides of the position where the gate electrode 6 is formed on the semiconductor substrate 1, for example, an LDD structure including a low-concentration impurity region 4 doped with As at a low concentration and a high-concentration impurity region 5 doped with As at a high concentration is provided. Source / drain diffusion layer regions are formed facing each other. Further, a sidewall spacer 7 is formed on the low-concentration impurity region 4, and a wiring metal layer 11 is formed on the semiconductor substrate 1 via an interlayer insulating film 10. Further, in the present embodiment, an oxidation suppression region 8 for suppressing the increase in the thickness of the gate oxide film 3 at both ends of the gate electrode 6 is provided above the low concentration impurity region 4 above the low concentration impurity region 4. It is formed so as to cover all. With the above configuration, an nMOS transistor is formed.

Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment configured as described above will be described. First,
As shown in FIG. 2, a semiconductor substrate 1 made of, for example, an N-type silicon substrate is prepared and, for example, a LOCOS (Local Ox
An isolation field oxide film 2 is selectively formed by an idation of silicon method or the like. Field oxide film 2
Is formed by stacking an oxidation prevention film such as an oxide film for a pad and a silicon nitride film in this order, and processing these into a predetermined pattern by dry etching.
Perform S oxidation. Thereby, isolation between elements is achieved.

Next, if necessary, ion implantation for a channel stopper is performed. After the annealing, the oxidation preventing film is removed, and a gate oxide film 3 is formed thereon by using a thermal oxidation method or the like. . Thus, the gate oxide film 3 covers the active region surrounded by the field oxide film 3. The thickness of the gate oxide film 3 is not particularly limited, but is set, for example, to about 7 to 15 nm.

Next, for example, CVD (Chemical Vapor D)
After depositing a polysilicon film on the entire surface by using an eposition method, the polysilicon layer is doped with, for example, P (phosphorus) to lower the resistance, and then, W (tungsten) is deposited to form a polycide layer. . The polycide film is patterned into a predetermined shape using a photolithography technique and an etching technique, and a gate electrode 6 made of a conductive polycide film is formed on the gate oxide film 3. The gate electrode 6 can be formed of a polysilicon layer or the like in addition to the polycide film.

When the formation of the gate electrode 6 is completed, the low concentration impurity region 4 is formed by ion implantation using the gate electrode 6 as a mask. The low concentration impurity region 4 is, for example,
s is formed by ion implantation in the order of 13 excess.

Next, in this embodiment, as shown in FIG. 3, an oxidation suppression region 8 is formed at both ends of the gate electrode 6 for suppressing the thickness of the gate oxide film 3 from increasing. In order to form the oxidation suppression region 8, an inert gas, for example, nitrogen N ₂ is ion-implanted with respect to the side surface of the gate electrode 6 from an oblique direction. The ion implantation is performed obliquely with respect to the side surface of the gate electrode 6 because the oxidation suppression region 8 is required at both ends of the gate electrode 6 of the semiconductor substrate 1. In addition, when ion implantation is performed in the channel formation region C, the damage may cause a charge leak, which lowers the reliability of the semiconductor device.

The conditions at this time are, for example, 13 to
Nitrogen is ion-implanted from a 45 degree direction in the order of 15 residues. Also, the energy at the time of ion implantation is
The size is such that nitrogen is implanted into a shallow portion of the surface of the substrate. As a result, as shown in FIG.
An oxidation suppression region 8 made of a nitride layer is formed in the upper layer.

Next, as shown in FIG.
Side wall spacers 7 are formed on the side walls. In order to form the side wall spacer 7, first, a side wall constituent material made of a silicon oxide film or the like is formed, and anisotropic etching such as RIE (Reactive Ion Etching) is performed from the surface. By this anisotropic etching, a silicon oxide film or the like is left only on the side wall of the gate electrode 6, thereby forming the sidewall spacer 7.

After the formation of the sidewall spacers 7, annealing is performed to form a through oxide film 9 for ion implantation. Conventionally, both ends of the gate electrode 6 are oxidized by the oxidation due to the annealing process, and a gate bird's beak in which the gate oxide film 3 is thickened has occurred. However, in the present embodiment, since the oxidation suppression region 8 made of a nitride layer is formed immediately below both ends of the gate oxide film 3, nitrogen piles up at the interface between the gate oxide film 3 and the semiconductor substrate 1. In addition, silicon oxidation at both ends of the gate electrode 6 is prevented, and the generation of gate bird's beak is suppressed as much as possible.

After the formation of the through oxide film 9, the high-concentration impurity region 5 is self-aligned by ion implantation using the field oxide film 2 and the sidewall spacers 7 as a mask.
Is formed facing the substrate surface. As a source for ion implantation, for example, As ions can be used, and doping is performed at a higher concentration than the low-concentration impurity region 4 described above.
Thereby, the high concentration impurity region 5 and the low concentration impurity region 4
And the source / drain regions respectively formed from the above.

Next, after an interlayer insulating film 10 is formed by a CVD method or the like, a contact hole is opened in the interlayer insulating film 10, a wiring metal layer 11 is formed, and source / drain electrodes are wired. The transistor manufacturing process ends.

As described above, in the semiconductor device according to the present embodiment, the generation of gate bird's beak at both ends of the gate electrode 6 is suppressed as much as possible, and the gate edge is thickened by the gate bird's beak, whereby the transistor is miniaturized. As the ratio of the thickened portion of the gate edge to the gate oxide film increases, the reverse short channel effect in which the threshold voltage Vth rises remarkably is suppressed, resulting in a highly reliable semiconductor device. . Further, the semiconductor device according to the present embodiment has the LDD structure, so that the inverse short channel effect can be suppressed and the short channel effect is also suppressed. Furthermore, in the semiconductor device according to the present embodiment, since the oxidation suppression region 8 made of a nitride layer is formed above the low-concentration impurity region 4 of the semiconductor substrate 1, injection of hot carriers is suppressed and hot carrier resistance is reduced. And a semiconductor device having improved characteristics.

In the method of manufacturing a semiconductor device according to the present embodiment, the oxidation suppression region 8 made of a nitride layer is formed immediately below both ends of the gate oxide film 3 so that the gate electrode is formed by thermal oxidation or the like in the semiconductor manufacturing process. 6 can be prevented from being oxidized at both ends to increase the thickness of the gate oxide film 3. In addition, when forming the oxidation suppressing region 8, ions are implanted obliquely to the side surface of the gate electrode 6 without damaging the channel forming region C and reducing the reliability of the semiconductor device. There is no.

[0025]

As described above, according to the semiconductor device of the present invention, the thickening of the oxide film at the end of the gate electrode can be suppressed by the oxidation suppressing region, so that the reverse short channel effect is suppressed. And a semiconductor device having improved hot carrier resistance can be obtained.

According to the method of manufacturing a semiconductor device of the present invention, an oxidation suppressing region is formed only in the upper layer of the LDD region by oblique ion implantation of an inert gas into the side of the gate electrode of the semiconductor substrate. Therefore, the generation of damage due to the injection of an inert gas into the channel formation region can be suppressed, and the reverse short channel effect can be suppressed, whereby a highly reliable semiconductor device with improved hot carrier resistance can be manufactured. be able to.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing an example of a gate bird's beak generated at an end of a gate electrode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Gate oxide film, 4 ... Low concentration impurity region, 5 ... High concentration impurity region,
6 gate electrode, 7 sidewall spacer, 8 oxidation suppression region, 9 through oxide film, 10 interlayer insulating layer, 1
1: Metal wiring layer

Claims (6)

[Claims] 1. A semiconductor device having a gate electrode formed on a channel formation region interposed between diffusion layer regions formed in a semiconductor layer via an insulating oxide film, wherein the gate electrode of the semiconductor layer is provided. A semiconductor device in which an oxidation suppressing region for suppressing an increase in the thickness of the insulating oxide film at both ends of the gate electrode is formed at both ends of the gate electrode and at a part of a diffusion layer region adjacent to the both ends. 2. The semiconductor device according to claim 1, wherein said diffusion layer region comprises a high-concentration impurity region and a low-concentration impurity region, respectively, and said oxidation suppressing region is formed above said low-concentration impurity region. . 3. The semiconductor device according to claim 1, wherein said oxidation suppression region comprises a nitride layer. 4. A step of forming a gate electrode on a semiconductor substrate with an insulating oxide film interposed therebetween, and a diffusion layer region made of a low-concentration impurity on both sides of the gate electrode of the semiconductor substrate at both ends of the gate electrode. Forming the insulating oxide film so as to be in contact with the insulating oxide film; and injecting an inert gas into the upper layer of the diffusion layer region made of the low-concentration impurity from an oblique direction with respect to a side surface of the gate electrode, Forming an oxidation-suppressing region that suppresses the increase in thickness of the insulating oxide film at both ends of the electrode; forming sidewall spacers on both sides of the gate electrode of the semiconductor substrate; and annealing the semiconductor substrate. Forming an oxide film on both sides of the sidewall spacer of the semiconductor substrate by using high-concentration impurities on both sides of the sidewall spacer of the semiconductor substrate. The method of manufacturing a semiconductor device having a step of forming a diffusion layer region. 5. The method of manufacturing a semiconductor device according to claim 4, wherein, when the inert gas is ion-implanted obliquely with respect to the side surface of the gate electrode, the inert gas is ion-implanted from a direction of 45 degrees. 6. The method according to claim 4, wherein said inert gas is nitrogen.