JP2005191594A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a nonvolatile semiconductor memory device, in which short channelization due to bird's beak is controlled, without complicating a manufacturing process, microfabrication and densification are attained, operation voltage can be reduced, and charge retention characteristics can be improved. <P>SOLUTION: A silicon layer 4 is formed immediately after forming an ONO film 3 which consists of a first insulating film 3a, a second insulating film 3b, and a third insulating film 3c on a silicon substrate 1. A bit line is formed, by performing arsenic ion implantation on the silicon layer 4 or the ONO film 3. A word line, which consists of conductive layers with two layer structures, is formed by depositing a second conductive layer 7, while leaving the silicon layer 4, as it is. Thereby, since a diffusion layer 2 is not oxidized, bird's beak is controlled, microfabrication limit due to short channel effect is relieved; and the deterioration of charge retention characteristics due to the curvature of the ONO film is prevented. Furthermore, by leaving at least the silicon layer 4 of a channel region, the ONO film/the silicon layer 4 interface is stabilized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and in particular, a MNOS (Metal Nitride Oxide Semiconductor) type or MONOS (Metal Oxide Nitride Oxide Semiconductor) that stores information using charges trapped in an insulating film having a laminated structure. The present invention relates to a method for manufacturing a non-volatile semiconductor memory device.

  In a nonvolatile semiconductor memory device called a flash memory, an FG (Floating Gate) transistor is generally used as a memory element. This FG transistor stores information charges in a floating gate electrode, which is a first gate electrode, in a two-layer gate electrode structure. In this structure, the first gate electrode is formed in a floating state on the silicon oxide film on the main surface of the semiconductor substrate, and an interlayer insulating film in which the silicon oxide film and the silicon nitride film are combined is provided on the first gate electrode. Further, a second gate electrode which is a control gate electrode is formed on the interlayer insulating film.

  However, in the FG type transistor, the information charge retention characteristic is not very good in principle, and a relatively thick silicon oxide film of 9 nm or more is required as a tunnel oxide film between the main surface of the semiconductor substrate and the floating gate electrode. . For this reason, there is a limit in reducing the voltage for writing and erasing information charges.

  Therefore, in recent years, an MNOS type or MONOS type transistor having a laminated film of a silicon oxide film and a silicon nitride film has been used. An MNOS transistor is a semiconductor that accumulates information charges in an interface level formed in a boundary region of a two-layer insulating film or a charge trap level in the insulating film in a two-layer gate insulating film. It is easy to reduce the thickness of the tunnel oxide film between the substrate main surface and the silicon nitride film, and a thin silicon oxide film of 3 nm or less can be used. For this reason, it is possible in principle to reduce the operating voltage, in particular, the voltage for writing and erasing information charges.

  In the MNOS transistor, information charges are written by injecting electrons from the semiconductor substrate into the interface region through a direct tunnel of a silicon oxide film having a thickness of about 2 nm formed on the main surface of the semiconductor substrate. The information charges are erased by emitting electrons from the semiconductor substrate to the semiconductor substrate. This information charge write state corresponds to logic 1 of stored information, and the information charge erased state corresponds to logic 0 of stored information. In view of this, various studies have been vigorously conducted in order to use an M (O) NOS type transistor capable of reducing the voltage for writing and erasing in principle as a memory element of a nonvolatile semiconductor memory device such as a flash memory. ing.

  For example, US Pat. No. 5,768,192 discloses a memory element whose basic structure is disclosed as a non-volatile semiconductor memory element for a flash memory using a MONOS transistor. Further, recently, a technology capable of greatly simplifying the manufacturing process of the nonvolatile memory is disclosed as NROM (Nitride Read Only Memory) in US Pat. No. 5,966,603. The basic structure of the nonvolatile memory element in this case is the same as that disclosed in the aforementioned US Pat. No. 5,768,192.

  A conventional NROM manufacturing method will be described below with reference to FIG. FIG. 9 is a process cross-sectional view showing a section taken along the word line of the NROM.

  First, as shown in FIG. 9A, a silicon oxide film is formed on the surface of the silicon substrate 1 by thermal oxidation, and a silicon nitride film is formed thereon by chemical vapor deposition (CVD). The surface of the nitride film is changed to a silicon oxide film by normal thermal oxidation or radical oxidation. In this way, the ONO film 3 having a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film is formed.

  Next, as shown in FIG. 9B, a resist pattern 6 having a strip-like (slit-like) diffusion layer pattern is formed on the ONO film 3 using a known lithography technique. Then, the exposed ONO film 3 is removed by etching using a known etching technique using the resist pattern 6 as an etching mask.

  Next, as shown in FIG. 9C, N-type impurities such as arsenic are ion-implanted using the resist pattern 6 as an ion implantation mask, and then the resist pattern 6 is removed.

  Next, as shown in FIG. 9D, the entire surface is thermally oxidized. By this thermal oxidation, an insulating film 13 on the diffusion layer having a thickness of about 110 nm is formed on the diffusion layer 2.

  Next, as shown in FIG. 9E, as the conductive layer 14, a polysilicon having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are continuously grown, and a known lithography technique and a dry etching technique are used. To form a word line.

  By the above manufacturing method, the bit line of the NROM cell composed of the diffusion layer 2 is formed on the silicon substrate 1, and the information charge writing / erasing region is formed by the ONO film 3. A word line is arranged orthogonal to the bit line, and the basic structure of the NROM cell is completed.

Next, the basic operation of the MONOS transistor, which is the basic structure of the NROM cell, will be described. In the write operation of information charges (here, electrons), for example, as shown in FIG. 10A, the silicon substrate 1 and the first diffusion layer 2a are fixed to the ground potential, and the V _W of the second diffusion layer 2b is 3V. In addition, the V _GW of the gate electrode 15 is set to about 5V. When such a voltage is applied, an electron flow (channel current) is generated from the first diffusion layer 2a as the source to the second diffusion layer 2b as the drain, and channel hot electrons (CHE) are generated in the vicinity of the second diffusion layer 2b. ), And a part thereof is captured by the trapping region 17 of the silicon nitride film (second insulating film 3b) across the barrier of the silicon oxide film (first insulating film 3a) below the ONO film 3. Thus, in the writing of electrons, information charges are accumulated in a region near the end of the second diffusion layer 2b of the silicon nitride film.

Next, in the read operation of information, as shown in FIG. 10 (b), conversely, the V _R of the first diffusion layer 2a second diffusion layer 2b is fixed to the ground potential as a source, as the drain 1. a 5V, _{V GR} of the gate electrode 15 is set at approximately 3V. Here, the silicon substrate 1 is at ground potential. In this case, in the case of logic 1 in which electrons are written in the trapping region 17, no current flows between the first diffusion layer 2a and the second diffusion layer 2b. On the other hand, in the case of logic 0 in which no electrons are written in the capture region 17, a current flows between the first diffusion layer 2a and the second diffusion layer 2b. In this way, the write information can be read.

Next, in the information erasing operation, in the structure shown in FIG. 10A, for example, the silicon substrate 1 and the first diffusion layer 2a are fixed to the ground potential, the V _E of the second diffusion layer 2b is 5V, The V _GE of the electrode 16 is set to about −5V. When such a voltage is applied, it is generated by band-to-band-tunneling (BTBT) by band bending at the end of the second diffusion layer 2b and in a region overlapping with the gate electrode. Holes are injected into the trapping region 17 to erase information charges.

  In this erasing operation, holes generated in the BTBT are pushed in the direction of the channel region, and run through the pn junction depletion layer formed by the p-type channel region and the n-type diffusion layer 2 to be in a high energy state. The degree to which the holes are accelerated depends on the state of the depletion layer of the pn junction, that is, the drain-substrate voltage. If there is no cause (negative charge or negative gate voltage) that the generated hole is attracted to the gate electrode 15 side, this hole goes out as a substrate current.

In the case of the MONOS type cell, in the state where data writing is completed, since a mass of electrons exists in the silicon nitride film (second insulating film 3b) near the drain, the hole moves toward the mass of electrons. Holes that form an electric field line, receive a force along the electric field lines, and reach a high energy state that can exceed the energy barrier of Si / SiO ₂ are injected into the silicon nitride film and recombine with electrons. As this recombination phenomenon progresses, the number of electrons trapped in the silicon nitride film decreases, so the number of lines of electric force going from holes to electrons also decreases, and holes are injected into the ONO film 3. Driving force decreases. As a result, in the MONOS type cell using this write / erase method, the over-erase problem which is a problem in the normal FG type cell does not occur in principle.

US Pat. No. 5,768,192 US Pat. No. 5,966,603

  However, in the conventional MNOS type or MONOS type nonvolatile semiconductor memory device described above, in the formation of the diffusion layer insulating film 13 by the thermal oxidation described above, biting called a bird's beak in which the oxide film grows in the lateral direction increases. When this bite increases, the dimension between the diffusion layers (for example, between the first diffusion layer 2a and the second diffusion layer 2b) is reduced, and a short channel is likely to occur. This limits the miniaturization of the NROM cell and restricts the high density or high integration of the NROM.

  In addition, the conventional manufacturing method has a problem that the band structure of the silicon nitride film changes due to the warp of the ONO film 3 at the end portion of the insulating film 13 on the diffusion layer due to bird's beak, and the information charge retention characteristics deteriorate. Further, since various processes such as resist pattern formation, peeling, and thermal oxidation are performed after the ONO film 3 is formed and before the conductive layer 14 serving as the word line is formed thereon, the word line There is also a problem that the interface characteristics of the / ONO film 3 cannot be kept good and the reliability of the device is lowered.

  The present invention has been made in view of the above-mentioned problems, and its main purpose is to achieve miniaturization and high density by suppressing the short channel due to bird's beak without complicating the manufacturing process, An object of the present invention is to provide a manufacturing method of a MNOS type or MONOS type nonvolatile semiconductor memory device capable of reducing the operating voltage and improving the charge retention characteristics.

  In order to achieve the above object, the manufacturing method of the present invention includes a laminated structure including a silicon oxide film and a silicon nitride film on a semiconductor substrate, or silicon fine particles (silicon nano dots on at least a part of the silicon oxide film). ) Distributed structure, a diffusion layer serving as a bit line and a conductive layer serving as a word line are formed, and information is stored using a charge captured by the insulating film. In the manufacturing method of the device, after the insulating film is formed, a first conductive layer is formed on the insulating film, and the diffusion layer forming impurity is implanted through the first conductive layer and the insulating film, A second conductive layer is deposited on the first conductive layer to form the conductive layer having a two-layer structure.

  In the present invention, the first conductive layer on the diffusion layer, or the insulating film and the first conductive layer may be converted into an oxide film by thermal oxidation or radical oxidation.

  In the present invention, a mask pattern made of a first silicon nitride film is formed on the first conductive layer upon the impurity implantation, and the mask pattern is formed by depositing and etching back a second silicon nitride film. A sidewall film having a predetermined thickness is formed on the sidewall, and impurity implantation is performed through the first conductive layer and the insulating film using the mask pattern in which the opening width is defined by the sidewall. You can also.

  Further, in the manufacturing method of the present invention, silicon fine particles (silicon nano dots) are distributed on a semiconductor substrate, a laminated structure including a silicon oxide film and a silicon nitride film, or at least a part of the silicon oxide film. A method of manufacturing a nonvolatile semiconductor memory device in which an insulating film having a structure is formed, a diffusion layer to be a bit line and a conductive layer to be a word line are formed, and information is stored using charges captured by the insulating film Then, after forming the insulating film, a first conductive layer is formed on the insulating film, and after removing the first conductive layer in the diffusion layer forming region, the impurity for forming the diffusion layer through the insulating film Implantation is performed, and a second conductive layer is deposited on the first conductive layer to form the two-layered conductive layer.

  In the present invention, after the impurity implantation, before the second conductive layer is deposited, the insulating film on the diffusion layer is removed, and at least on the diffusion layer, the insulating film, and the first conductive layer. An oxide film having a thickness smaller than that of the insulating film can be formed on the side wall.

  Further, in the manufacturing method of the present invention, silicon fine particles (silicon nano dots) are distributed on a semiconductor substrate, a laminated structure including a silicon oxide film and a silicon nitride film, or at least a part of the silicon oxide film. A method of manufacturing a nonvolatile semiconductor memory device in which an insulating film having a structure is formed, a diffusion layer to be a bit line and a conductive layer to be a word line are formed, and information is stored using charges captured by the insulating film After forming the insulating film, a first conductive layer is formed on the insulating film, and after removing the first conductive layer and the insulating film in the diffusion layer forming region, the diffusion layer forming region and the An oxide film having a thickness smaller than that of the insulating film is formed on the insulating film and the side wall of the first conductive layer. Impurity implantation for forming the diffusion layer is performed through the oxide film, and on the first conductive layer. A second conductive layer is deposited to form a two-layer structure And forms a Kishirube conductive layer.

  In the present invention, the insulating film is an ON film in which a silicon oxide film and a silicon nitride film are stacked in this order, or an ONO film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order. It is preferable to become.

  As described above, according to the present invention, the first conductive layer (polysilicon or amorphous silicon or the like) is deposited immediately after the formation of the insulating film having a laminated structure such as the ONO film, and the ONO film and the first conductive layer (or the ONO film). ) By performing ion implantation from above to form a diffusion layer, it is not necessary to form an insulating film on the diffusion layer by thermal oxidation, and bird's beak, which has been a problem of the prior art, can be suppressed. Deterioration of charge retention characteristics due to film warpage can be prevented. Further, by leaving the ONO film and the first conductive layer at least above the channel region, the interface between the ONO film and the first conductive layer that becomes a part of the word line can be stabilized, and the reliability of the nonvolatile semiconductor memory device can be improved. Can be improved.

  As described above, the manufacturing method of the MNOS type or MONOS type nonvolatile semiconductor memory device of the present invention has the following effects.

  The first effect of the present invention is that the bird's beak which has been a problem in the prior art can be suppressed, and the miniaturization limit of the NROM type cell can be relaxed. The reason is that the bit line surface is not directly oxidized except in the fifth embodiment, and also in the fifth embodiment, the oxidation time is shortened by using the radical oxidation technique.

  Further, since the warp (mechanical stress) due to bird's beak is suppressed and the silicon nitride film as the charge storage layer has a flat structure, the charge retention characteristics can be improved. In addition, since a silicon nitride film is not formed on the silicon layer, the process can be prevented from becoming complicated.

  The second effect of the present invention is that the interface characteristics (reliability) of the word line / ONO film can be improved. This is because a silicon layer that becomes a part of the word line is formed immediately after the ONO film is formed, and at least the silicon layer in the channel region is left without being removed.

  The third effect of the present invention is that the breakdown voltage between the bit line and the word line can be improved and the parasitic capacitance can be reduced. This is because in the fourth to sixth embodiments, an oxide film obtained by thermally oxidizing or radically oxidizing the silicon layer is formed immediately above the bit line region.

  Further, the fourth effect of the present invention is that punch-through associated with higher density can be prevented. The reason is that in the sixth embodiment, arsenic implantation is performed after the sidewall nitride film is formed on the side wall of the hard mask, so that the implantation region can be accurately controlled and the effective dimension of the channel region can be controlled. This is because the length can be increased by about twice the thickness of the sidewall.

  The sixth effect of the present invention is that the BTBT hole generation efficiency can be improved. The reason is that, in the seventh and eighth embodiments, after the ONO film on the diffusion layer is removed, an oxide film thinner than the ONO film is formed, and the tunnel phenomenon can be efficiently caused even at a low voltage. Because.

  As shown in the prior art, in a conventional MNOS type or MONOS type nonvolatile semiconductor memory device having an insulating film having a laminated structure, when the insulating film is formed on the diffusion layer by thermal oxidation, the lateral direction of the oxide film As a result of this growth, bird's beaks are generated, which tends to cause a short channel, and there is a problem that high density and high integration are restricted.

  To solve this problem, the inventor of the present application forms a silicon layer on the ONO film composed of the third insulating film / second insulating film / first insulating film in the prior application (Japanese Patent Application No. 2002-089139), and A silicon nitride film is formed thereon, and the lateral growth of the insulating film on the diffusion layer is suppressed by the stress of the silicon layer and the silicon nitride film. The structure and manufacturing method described in this prior application will be described with reference to FIG.

  First, as shown in FIG. 11A, a first insulating film 3a is formed of a silicon oxide film having a thickness of about 4 nm grown by radical oxidation or thermal oxidation of the silicon substrate 1, and a thickness of about 7 nm is formed by a CVD method. A silicon nitride film is formed, and the surface of the silicon nitride film is changed into a silicon oxide film having a thickness of about 4 nm by thermal oxidation or radical oxidation. In this way, the second insulating film 3b having a thickness of about 5 nm and the third insulating film 3c having a thickness of about 4 nm are formed, and the ONO film 3 having a three-layer structure is formed.

  Further, a silicon layer 4 made of amorphous or polycrystalline silicon film containing a high concentration N-type impurity with a film thickness of about 30 nm is deposited by CVD so as to cover the third insulating film 3c. Then, a silicon nitride film 16 which is an antioxidant film having a thickness of about 50 nm is formed on the surface of the silicon layer 4 by a CVD method. Thereafter, a resist pattern 6 having a slit-like diffusion layer pattern is formed on the silicon nitride film 16 using a known lithography technique.

  Next, as shown in FIG. 11B, the silicon nitride film 16, the silicon layer 4, the third insulating film 3c, and the second insulating film 3b are sequentially etched away using a known dry etching technique to form an opening. To do. Thereafter, N-type impurities such as arsenic are ion-implanted using the resist pattern 6 as an ion implantation mask, and then the resist pattern 6 is removed. Then, heat treatment is performed to form a diffusion layer 2 that becomes a bit line on the surface of the silicon substrate 1.

  Next, as shown in FIG. 11C, the entire surface is thermally oxidized as in the conventional technique. By this thermal oxidation, an insulating film 13 on the diffusion layer having a thickness of about 100 nm is formed on the surface of the diffusion layer 2. Thereafter, the slit-like silicon nitride film 16 is removed by etching.

  Next, as shown in FIG. 11D, a polysilicon film containing a high-concentration N-type impurity and a tungsten silicide film having a film thickness of about 150 nm are deposited on the entire surface as shown in FIG. Processing is performed using a lithography technique and a dry etching technique to form a conductive film 14 to be a word line. In this word line forming step, the slit-like silicon layer 4 is also processed to form the gate electrode 16.

  In this manner, the bit line of the NROM cell is formed in the diffusion layer 2 on the silicon substrate 1, and information charges are written / written by the first insulating film 3a, the second insulating film 3b, and the third insulating film 3c having the ONO structure. An erase region is formed, and a word line 14 is formed by a conductive film 14 orthogonal to the bit line, thereby completing the basic structure of the NROM cell.

  In this structure, in the thermal oxidation process for forming the insulating film 13 on the diffusion layer, the silicon nitride film 16 gives a large compressive stress to the silicon layer 4 and can suppress the diffusion of oxygen as an oxidizing agent in the lateral direction. Bird's beak can be suppressed. Further, by suppressing the warpage of the ONO film 3 using the stress, it is possible to suppress the deterioration of the charge retention characteristics due to the change in the band structure of the silicon nitride film that is the second insulating film 3b. However, in the manufacturing method described in the prior application, compared to the conventional method shown in FIG. 9, at least the silicon layer 4 and the silicon nitride film 16 are formed and patterned, and the process becomes complicated. There is a problem.

  Although the biting can be reduced as compared with the conventional method, the basic configuration is that the diffusion layer insulating film 13 is formed on the diffusion layer 2 by thermal oxidation is the same. Since it becomes a competition with the lateral diffusion of oxygen in the insulating film 3a, it is not possible to completely suppress the biting, and it can sufficiently cope with further miniaturization and higher density of the nonvolatile semiconductor memory device. Can not do it.

  In addition, the increase in the thickness of the ONO film 3 at the end of the insulating layer 13 on the diffusion layer due to the lateral diffusion of oxygen causes a problem that the BTBT hole generation efficiency is lowered and the information charge erasing characteristic is deteriorated.

  This problem will be described in detail with reference to FIG. 10. For example, when a bias such as a gate voltage of 0 V, a substrate voltage of 0 V, and a drain voltage of 5 V is applied, electrons in the gate electrode accumulate at the interface with the gate oxide film, Electrons in the vicinity of the interface between the diffusion layer 2 and the gate oxide film are separated from this interface, and an extremely thin depletion layer is formed. The width of the depletion layer depends strongly on the impurity concentration of the diffusion layer 2 and the applied voltage. If this width is thin enough to cause a tunnel phenomenon (about 3 nm), the bending of the band of the depletion layer formed in the diffusion layer 2 may cause the electrons near the top of the valence band to move to the conduction band across the forbidden band. In this case, holes are formed in the valence band and electrons are generated in the conduction band. The electrons transferred to the conduction band are sucked out by the drain voltage, and the holes formed in the valence band move in the direction of the channel region. Thereby, holes are generated by BTBT. However, when the impurity concentration of the diffusion layer 2 and the bias conditions are the same, when the thickness of the ONO film 3 is increased, most of the applied voltage is applied to the ONO film 3, so that the band is bent. As a result, tunneling is less likely to occur. Therefore, if more holes are to be generated, that is, if it is desired to increase the BTBT hole generation efficiency, the thickness of the oxide film may be reduced. However, in the above-described method, oxygen is diffused in the lateral direction. As a result, an increase in the ONO film 3 at the end of the diffusion layer upper insulating film 13 occurs, and the BTBT hole generation efficiency decreases.

  Therefore, the present invention employs a process in which a silicon layer is formed immediately after the ONO film is formed, and arsenic is implanted from the silicon layer (or on the ONO film). This eliminates the need for heat treatment for forming the insulating film on the diffusion layer. As a result, bird's beak can be suppressed and deterioration of charge retention characteristics due to warping of the ONO film can be prevented. In addition, since it is possible to prevent an increase in the ONO film at the end of the diffusion layer upper insulating film 13, it is possible to prevent a reduction in BTBT hole generation efficiency.

  Further, in the above manufacturing method, a process is employed in which at least the silicon layer on the ONO film in the channel region is left as it is. As a result, the ONO film / silicon layer interface can be stabilized and the reliability can be improved.

  Further, instead of forming the insulating film on the diffusion layer by ordinary thermal oxidation, the silicon layer or the ONO film is radically oxidized. Thereby, a pressure | voltage resistance can be improved, suppressing a bird's beak.

  In order to describe the above-described embodiment of the present invention in more detail, examples of the present invention will be described with reference to the drawings. In the first and second embodiments, a silicon layer is formed after the ONO film is formed, and ion implantation is performed on the ONO film and the silicon layer. In the third embodiment, the silicon layer is left only on the channel region. In the fourth and fifth embodiments, the silicon layer or ONO film above the diffusion layer is further oxidized to improve the breakdown voltage between the bit line / word line. In this embodiment, a configuration for increasing the effective channel length and a configuration for increasing the BTBT hole generation efficiency in the seventh and eighth embodiments will be described. In each of the following embodiments, a case where an ONO film is used as an insulating film having a stacked structure will be described. However, the present invention is not limited to the following embodiment, and a silicon oxide film and a silicon nitride film are stacked in this order. When an insulating film having a structure in which silicon fine particles (silicon nanodots) are distributed in at least a part of a silicon oxide film, or a structure in which these films are repeatedly laminated, a multilayer structure having the same function, or a silicon oxide film is used. Can be applied similarly.

  First, a method for manufacturing a nonvolatile semiconductor memory device according to a first example of the present invention will be described with reference to FIG. FIG. 1 is a process cross-sectional view illustrating a method of manufacturing a MONOS type nonvolatile semiconductor memory device according to the present embodiment, showing a cross section along a word line. Note that this embodiment describes a structure in which a silicon layer is formed on an ONO film and is left as it is, which is the most basic structure of the nonvolatile semiconductor memory device according to the present invention.

  First, as shown in FIG. 1A, a silicon oxide film (first insulating film 3a) having a thickness of about 4 nm is formed on a silicon substrate 1 by radical oxidation or thermal oxidation, and a CVD method or the like is used thereon. Then, a silicon nitride film (second insulating film 3b) having a thickness of about 7 nm is formed, and further, the silicon nitride film is subjected to radical oxidation or thermal oxidation, and a silicon oxide film (third insulating film) having a thickness of about 4 nm is formed on the surface. Change to 3c). The third insulating film 3c may be deposited using a CVD technique such as HTO. The same applies to the other embodiments. In this way, the ONO film 3 having a three-layer structure of the third insulating film 3c / second insulating film 3b / first insulating film 3a is formed. In the case of adopting a silicon nanodot structure, after forming a silicon oxide film by radical oxidation or thermal oxidation, silicon fine particles having a diameter of about 3 to 5 nm may be discretely formed using a CVD method or the like. .

  Note that the thickness and manufacturing method of each insulating film constituting the ONO film 3 are not particularly limited. However, when holes are generated by BTBT as described above, the bending of the band decreases as the oxide film becomes thicker. , Tunneling is less likely to occur. Therefore, in order to increase the BTBT hole generation efficiency, it is preferable to reduce the thickness of the ONO film 3.

  Subsequently, as the first conductive layer so as to cover the third insulating film 3c using the CVD method, an amorphous silicon film having a film thickness of about 10 to 50 nm and containing non-doped or high concentration N-type impurities or A polycrystalline silicon film or a polycrystalline or amorphous silicon or silicon compound (hereinafter referred to as a silicon layer 4) such as a polycrystalline or amorphous silicon germanium film is formed. In this way, by immediately covering the ONO film 3 with the silicon layer 4 after the ONO film 3 is formed, it is possible to stabilize the ONO film 3 / silicon layer 4 interface, and to maintain information charge retention characteristics and device reliability. Can be improved.

  An HTO (High Temperature Oxide) or LTO (Low Temperature Oxide) 5 having a thickness of about 10 nm may be formed on the silicon layer 4. This film is provided in order to remove the resist due to the lift-off effect by adding a wet etch of the oxide film when the resist is difficult to peel off by high concentration arsenic implantation.

  Next, as shown in FIG. 1B, a slit-shaped diffusion layer pattern is formed on the HTO or LTO 5 (or on the silicon layer 4 when the HTO or LTO 5 is not formed) using a known lithography technique. A resist pattern 6 is formed. Here, in the method described in the prior application, the silicon nitride film 16 is formed on the silicon layer 4 before the resist pattern 6 is formed, and the stress generated by the difference in the thermal expansion coefficient between the silicon layer 4 and the silicon nitride film 16 is used. Although the growth of the insulating film 13 on the diffusion layer was suppressed, in this embodiment, since it is not necessary to form the insulating film 13 on the diffusion layer, the formation of the silicon nitride film 16 can be omitted. In comparison, the manufacturing process can be simplified.

  Next, in the method shown in the conventional example or the method described in the prior application, the opening was formed by etching the ONO film 3 or the silicon layer 4 using the resist pattern 6, but in this embodiment, FIG. As shown in c), without etching the HTO or LTO 5, the silicon layer 4 and the ONO film 3, an N-type impurity such as arsenic is directly ion-implanted from these films using the resist pattern 6 as an ion implantation mask. After the pattern 6 is removed, heat treatment is further performed to form the diffusion layer 2 to be a bit line. By performing ion implantation from the silicon layer 4 and the ONO film 3 in this manner, it is not necessary to form a new insulating film on the diffusion layer 2 and the occurrence of bird's beaks due to thermal oxidation can be prevented.

  Next, as shown in FIG. 1D, as the second conductive layer 7, for example, a refractory metal silicide such as polysilicon having a thickness of about 50 nm and tungsten silicide having a thickness of about 100 nm is deposited on the entire surface. Using a known lithography technique and dry etching technique, a word line is formed by processing into a slit shape in a direction perpendicular to the bit line. In this word line forming step, the silicon layer 4 is also processed to form a gate electrode.

  By the above manufacturing method, the bit line of the NROM cell is formed on the silicon substrate 1 by the diffusion layer 2, and the ONO film 3 having the three-layer structure including the first insulating film 3a, the second insulating film 3b, and the third insulating film 3c is used. A region for writing / erasing information charges is formed. Then, a word line having a two-layer structure (first conductive layer 4 and second conductive layer 7) is disposed on the ONO film 3, and the basic structure of the NROM cell of this embodiment is completed.

  Thus, by performing ion implantation through the ONO film 3 and the silicon layer 4 and not forming a new insulating film on the diffusion layer 2, the bird's beak in the conventional technique can be suppressed, and the ONO film 3 Since no warpage occurs, it is possible to prevent deterioration of charge retention characteristics due to a change in the band structure of the silicon nitride film. Further, by forming the silicon layer 4 immediately after the ONO film 3 is formed and leaving it as it is, the interface between the ONO film 3 and the silicon layer 4 can be stabilized, and the reliability can be improved.

  Next, a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. This embodiment describes a structure for solving the problem of resist stripping caused by high-concentration arsenic implantation, and other configurations are the same as those of the first embodiment.

  First, as in the first embodiment, a first insulating film 3a is formed on a silicon substrate 1 by radical oxidation or thermal oxidation, and a second insulating film 3b is formed thereon using a CVD method or the like. A third insulating film 3c is formed on the surface of the silicon nitride film by oxidation or thermal oxidation, and an ONO film 3 having a three-layer structure of third insulating film 3c / second insulating film 3b / first insulating film 3a is formed.

  Subsequently, as shown in FIG. 2A, after the silicon layer 4 is formed as the first conductive layer 4 using the CVD method, a thick insulating film (silicon having a thickness of about 200 nm serving as a hard mask for ion implantation is formed. An oxide film or silicon nitride film 9) is formed.

  Next, as shown in FIG. 2B, a slit-like resist pattern (not shown) is formed on the silicon oxide film or silicon nitride film 9 using a known lithography technique, and a known dry etching is performed. Using the technique, the exposed silicon oxide film or silicon nitride film 9 is removed to form a hard mask 9a to be a diffusion layer pattern. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 2 (c), N-type impurities such as arsenic are ion-implanted directly from the silicon layer 4 using the hard mask 9a as an ion implantation mask, and the hard mask 9a is hardened using a known dry etching or wet etching technique. After removing the mask 9a, heat treatment is further performed to form the diffusion layer 2 to be a bit line. As described above, by using the hard mask 9a made of the silicon oxide film or the silicon nitride film 9, the hard mask 9a after the arsenic implantation can be easily removed, and resist peeling failure can be prevented.

  Next, as in the first embodiment, as the second conductive layer 7, for example, polysilicon and refractory metal silicide such as tungsten silicide are deposited on the entire surface, and a known lithography technique and dry etching technique are used. Thus, the basic structure of the NROM cell of this embodiment is completed.

  Thus, according to the method of this embodiment, in addition to the effects of the first embodiment, by using the hard mask 9a made of a silicon oxide film or a silicon nitride film instead of the resist pattern as a mask for ion implantation. In addition, resist peeling failure after ion implantation can be prevented.

  Next, a method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention is described with reference to FIG. FIG. 3 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. This embodiment is characterized in that high-concentration arsenic is injected through an ONO film, and the other configuration is the same as that of the second embodiment.

  First, as in the second embodiment, an ONO film 3 is formed by sequentially forming a silicon oxide film, a silicon nitride film, and a silicon oxide film on the silicon substrate 1. Subsequently, after the silicon layer 4 is formed as the first conductive layer, a silicon oxide film or a silicon nitride film 9 serving as a hard mask for ion implantation is formed (see FIG. 3A).

  Next, as shown in FIG. 3B, a slit-like resist pattern is formed on the silicon oxide film or silicon nitride film 9 using a known lithography technique, and is diffused using a known dry etching technique. After the hard mask 9a to be a layer pattern is formed, the resist pattern is removed.

  Next, as shown in FIG. 3C, the silicon layer 4 exposed by a known dry etching technique is removed using a hard mask 9a, and subsequently, as shown in FIG. 3D, the hard mask 9a is removed. N-type impurities such as arsenic are ion-implanted from the ONO film 3 using 9a as an ion implantation mask, the hard mask 9a is removed using a known dry etching technique, and then a heat treatment is performed to form a diffusion layer 2 that becomes a bit line. Form. Here, in the first or second embodiment, it is necessary to increase the acceleration energy of ion implantation in order to perform arsenic implantation through the silicon layer 4, but in this embodiment, the diffusion layer formation region Since the silicon layer 4 is removed, the acceleration energy can be lowered. As a result, the hard mask can be thinned, so that the hard mask removal process can be simplified (time reduction). Since the silicon layer on the channel region remains, the interface between the ONO film 3 and the silicon layer 4 in that region can be kept stable.

  Next, as shown in FIG. 3E, polysilicon and a refractory metal silicide such as tungsten silicide are deposited on the entire surface as the second conductive layer 7, and using a known lithography technique and dry etching technique. A word line is formed to complete the basic structure of the NROM cell of this embodiment. Here, since the silicon layer 4 is left to stabilize the interface between the ONO film 3 and the silicon layer 4 in the channel region, the thickness of the conductive layer differs between the diffusion layer region and the channel region. Before forming the two conductive layers 7, the silicon layer 4 can be thinned or removed by a dry etching technique, and in that case, the flatness can be improved.

  Thus, according to the method of this embodiment, in addition to the effect of the second embodiment, the acceleration energy of ion implantation is lowered by removing the silicon layer 4 in the diffusion layer forming region before ion implantation. You can also

  Next, a method of manufacturing the nonvolatile semiconductor memory device according to the fourth example of the invention is described with reference to FIG. FIG. 4 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. The present embodiment is characterized in that the withstand voltage between the bit line and the word line is improved and the parasitic capacitance is reduced, and other configurations are the same as those in the second embodiment.

  First, as shown in FIG. 4A, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on a silicon substrate 1 to form an ONO film 3. Subsequently, after a silicon layer 4 is formed as a first conductive layer by using a CVD method, a thick silicon nitride film 10 having a thickness of about 200 nm is formed as a hard mask for ion implantation. In this embodiment, since the silicon layer 4 is oxidized using this hard mask in a later step, the silicon nitride film 10 is used.

  Next, as shown in FIG. 4B, a slit-like resist pattern is formed on the silicon nitride film 10 using a known lithography technique, and becomes a diffusion layer pattern using a known dry etching technique. After the hard mask 10a is formed, the resist pattern is removed.

  Next, as shown in FIG. 4C, N-type impurities such as arsenic are ion-implanted from above the silicon layer 4 using the hard mask 10a as an ion implantation mask, and heat treatment is performed to form a diffusion layer 2 that becomes a bit line. To do.

  Here, in the second embodiment, the hard mask 9a is removed thereafter to form the second conductive layer 7. However, in this embodiment, the withstand voltage between the bit line and the word line is improved and the parasitic capacitance is reduced. In order to reduce the thickness, the silicon layer 4 is oxidized by thermal oxidation to form a polysilicon oxide film 11 on the diffusion layer 2 (see FIG. 4D). At that time, immediately before the oxidation of the silicon layer 4 is completed, the oxidized species enter from the third insulating film 3c of the ONO film 3 and the polysilicon oxide film 11 to form a small bird's beak in the silicon layer 4 in the channel region. Compared with the conventional method, the time is much shorter, so it can be said that there is no practical problem.

  Next, as shown in FIG. 4E, as the second conductive layer 7, polysilicon and a refractory metal silicide such as tungsten silicide are deposited on the entire surface, and a known lithography technique and dry etching technique are used. A word line is formed to complete the basic structure of the NROM cell of this embodiment.

  Thus, even in the method of this embodiment, the bird's beak can be suppressed by not directly thermally oxidizing the diffusion layer 2, and the third insulation of the ONO film 3 is oxidized by oxidizing the silicon layer 4 in the diffusion layer region. By changing the film 3c to the thick polysilicon oxide film 11, the withstand voltage between the bit line and the word line can be improved and the parasitic capacitance can be reduced.

  Next, a method for manufacturing a nonvolatile semiconductor memory device according to a fifth example of the present invention is described with reference to FIG. FIG. 5 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. This embodiment is characterized in that a silicon nitride film whose Si-N bond is weakened by high concentration arsenic implantation is oxidized, and the other configuration is the same as that of the fourth embodiment.

  First, as in the fourth embodiment, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on the silicon substrate 1 to form the ONO film 3. Subsequently, after the silicon layer 4 is formed as the first conductive layer using the CVD method, a silicon nitride film 10 serving as a hard mask for ion implantation is formed (see FIG. 5A).

  Next, a slit-like resist pattern is formed on the silicon nitride film 10 using a known lithography technique, and a hard mask 10a serving as a diffusion layer pattern is formed using a known dry etching technique. Remove. Subsequently, N type impurities such as arsenic are ion-implanted from above the silicon layer 4 using the hard mask 10a as an ion implantation mask, and heat treatment is performed to form the diffusion layer 2 to be a bit line (FIGS. 5B and 5C). )reference).

  Here, in the fourth embodiment, the silicon layer 4 is oxidized by thermal oxidation to form the polysilicon oxide film 11. However, in the method of the present invention, ion implantation is performed through the ONO film 3. The Si—N bond of the silicon nitride film of the ONO film 3 is weakened by the concentration of arsenic implantation. Therefore, in this embodiment, as shown in FIG. 5D, when the silicon layer 4 is oxidized, the silicon nitride film is oxidized to form a polysilicon oxide film 11a thicker than the fourth embodiment. It is to be noted that radical oxidation technology can be used for the oxidation, the oxidation rate of the silicon layer 4 and the silicon nitride film can be made substantially equal by using radical oxidation active oxygen, and the occurrence of bird's beaks by shortening the oxidation time. Can be suppressed as much as possible.

  Next, as shown in FIG. 5E, polysilicon and a refractory metal silicide such as tungsten silicide are deposited on the entire surface as the second conductive layer 7, and a known lithography technique and dry etching technique are used. A word line is formed to complete the basic structure of the NROM cell of this embodiment.

  As described above, according to the method of the present embodiment, by forming the polysilicon oxide film 11a thicker than the fourth embodiment in the diffusion layer region, the withstand voltage between the bit line and the word line is improved, and The parasitic capacitance can be further reduced.

  Next, a method for manufacturing a nonvolatile semiconductor memory device according to a sixth example of the present invention is described with reference to FIG. FIG. 6 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. This embodiment is characterized in that the dimensions of the diffusion layer region are controlled, and other configurations are the same as those in the fourth embodiment.

  First, as in the fourth embodiment, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on the silicon substrate 1 to form the ONO film 3. Subsequently, a silicon layer 4 is formed as a first conductive layer by using a CVD method, and then a silicon nitride film 10 serving as a hard mask for ion implantation is formed. Next, a slit-like resist pattern is formed on the silicon nitride film 10 using a known lithography technique, and a hard mask 10a serving as a diffusion layer pattern is formed using a known dry etching technique. Is removed (see FIG. 6A).

  Here, in the fourth embodiment, arsenic ions are implanted using the hard mask 10a as a mask. However, in this method, when miniaturization of the nonvolatile semiconductor memory device is required, the channel length is further shortened and punch-through occurs. There is a fear. Therefore, in this embodiment, a silicon nitride film is formed on the entire surface by CVD or the like and etched back to form a sidewall nitride film 12 having a thickness of about 20 to 50 nm on the side wall of the hard mask 10a. Dimension control is performed (see FIG. 6B).

  Next, as shown in FIG. 6C, N-type impurities such as arsenic are ion-implanted from above the silicon layer 4 using the hard mask 10a and the sidewall nitride film 12 as an ion implantation mask, and heat treatment is performed to form bit lines and A diffusion layer 2 is formed. The length of the diffusion layer 2 can be arbitrarily set by changing the thickness of the sidewall nitride film 12.

  Next, as shown in FIG. 6D, after the silicon layer 4 sandwiched between the sidewall nitride films 12 is oxidized by thermal oxidation to form a polysilicon oxide film 11, the hard mask 10a and the sidewall nitride films are formed. 12 is removed by wet etching, and as shown in FIG. 6E, a refractory metal silicide such as polysilicon and tungsten silicide is deposited on the entire surface as the second conductive layer 7, and a known lithography technique and dry etching are performed. The word line is formed using the technology, and the basic structure of the NROM cell of this embodiment is completed. Note that the polysilicon oxide film 11 of FIG. 6D may not be formed, and the silicon layer 4 may be left on the entire surface.

  Thus, according to the method of this example, in addition to the effect of the fourth example, the side wall nitride film 12 can limit the arsenic implantation region, increasing the effective channel length, Punch through can be suppressed.

  Next, a method for manufacturing a nonvolatile semiconductor memory device according to the seventh embodiment of the present invention is described with reference to FIG. FIG. 7 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. The present embodiment is characterized in that the insulating film in the diffusion layer region is thinned to improve the BTBT hole generation efficiency.

  First, as shown in FIG. 7A, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on a silicon substrate 1 to form an ONO film 3. Subsequently, a silicon layer 4 is formed as a first conductive layer by using a CVD method, and then a silicon nitride film 10 serving as a hard mask for ion implantation is formed. Next, a slit-like resist pattern is formed on the silicon nitride film 10 using a known lithography technique, and a hard mask 10a serving as a diffusion layer pattern is formed using a known dry etching technique. Remove. Next, the exposed silicon layer 4 is removed by a known dry etching technique using the hard mask 10a.

  Next, as shown in FIG. 7B, N type impurities such as arsenic are ion-implanted from the ONO film 3 using the hard mask 10a as an ion implantation mask, and a heat treatment is performed to form a diffusion layer 2 to be a bit line. To do. At that time, it is preferable to perform sufficient annealing after ion implantation in order to suppress the growth and oxidation of arsenic when an oxide film is formed on the diffusion layer 2 in a later step.

  Here, in the above-described embodiment, at least the ONO film 3 is left without being removed. As described above, when the impurity concentration of the diffusion layer 2 and the bias condition are the same, when the ONO film 3 becomes thick, most of the applied voltage is increased. Since it is applied to the ONO film 3, the bending of the band is reduced, and as a result, the tunnel phenomenon hardly occurs and the BTBT hole generation efficiency is lowered. Therefore, in this embodiment, as shown in FIG. 7C, the ONO film 3 is removed using a hard mask 10a by a known dry etching technique. Since the silicon layer 4 and the ONO film 3 on the channel region remain, the stabilization of the interface between the silicon substrate 1, the ONO film 3, and the silicon layer in that region can be maintained.

  Next, as shown in FIG. 7D, an oxide film 8 having a thickness smaller than that of the ONO film 3 is formed by thermal oxidation at least on the diffusion layer region and on the side walls of the ONO film 3 and the silicon layer 4. . In addition, a tunnel phenomenon can be caused with a smaller applied voltage, and the BTBT hole generation efficiency can be increased. Thereafter, as shown in FIG. 7E, after the hard mask 10a is wet-etched, polysilicon and a refractory metal silicide such as tungsten silicide are deposited on the entire surface as the second conductive layer 7, and a known lithography technique is used. The word line is formed using the dry etching technique, and the basic structure of the NROM cell of this embodiment is completed.

  As described above, in the method of this embodiment, the ONO film 3 on the diffusion layer 2 is removed, and instead an oxide film thinner than the ONO film 3 is formed, whereby the BTBT hole generation efficiency can be increased. Although an oxide film is formed on the diffusion layer 2 by thermal oxidation, the bird's beak can be suppressed because the film thickness is thin.

  Next, a method for manufacturing a nonvolatile semiconductor memory device in accordance with the eighth embodiment of the present invention is described with reference to FIG. FIG. 8 is a process sectional view showing the method of manufacturing the MONOS type nonvolatile semiconductor memory device according to this example. This embodiment is characterized in that arsenic ions are implanted after forming an oxide film, and the other configuration is the same as that of the seventh embodiment.

  First, similarly to the seventh embodiment, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on the silicon substrate 1 to form an ONO film 3. Subsequently, a silicon layer 4 is formed as a first conductive layer by using a CVD method, and then a silicon nitride film 10 serving as a hard mask for ion implantation is formed. Next, a slit-like resist pattern is formed on the silicon nitride film 10 using a known lithography technique, and a hard mask 10a serving as a diffusion layer pattern is formed using a known dry etching technique. Remove. Next, the silicon layer 4 exposed by a known dry etching technique is removed using the hard mask 10a (see FIG. 8A).

  Here, arsenic ions are implanted in the seventh embodiment. However, if an oxide film is formed after arsenic implantation, it may be difficult to control the film thickness. Therefore, in this embodiment, as shown in FIG. 8B, the ONO film 3 is removed using a hard mask 10a by a known dry etching technique, and subsequently, by thermal oxidation as shown in FIG. An oxide film 8 having a thickness smaller than that of the ONO film 3 is formed at least on the diffusion layer region and on the side walls of the ONO film 3 and the silicon layer 4.

  Next, as shown in FIG. 8D, N type impurities such as arsenic are ion-implanted from above the oxide film 8 using the hard mask 10a as an ion implantation mask, and a heat treatment is performed to form a diffusion layer 2 to be a bit line. To do. At that time, in order to prevent diffusion of arsenic, the annealing is preferably performed at a temperature of approximately 950 ° C. or less in a nitrogen or oxygen atmosphere.

  Next, as shown in FIG. 8E, after the hard mask 10a is wet-etched, polysilicon and refractory metal silicide such as tungsten silicide are deposited on the entire surface as the second conductive layer 7, and known lithography is performed. The word line is formed using the technique and the dry etching technique, and the basic structure of the NROM cell of this embodiment is completed.

  Thus, in the method of the present embodiment, since the arsenic ion implantation is performed after forming the oxide film 8 thinner than the ONO film 3 on the diffusion layer 2, the film of the oxide film 8 than the seventh embodiment. Thickness controllability can be improved.

It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device which concerns on 1st Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 2nd Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 3rd Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 4th Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 5th Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 6th Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 7th Example of this invention. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device based on the 8th Example of this invention. It is process sectional drawing which shows the manufacturing method of the conventional MONOS type non-volatile semiconductor memory device. FIG. 6 is a diagram for explaining information charge writing, reading, and erasing operations in a MONOS type nonvolatile semiconductor memory device. It is process sectional drawing which shows the manufacturing method of the MONOS type non-volatile semiconductor memory device which concerns on a prior application.

Explanation of symbols

1 Silicon substrate 2 Diffusion layer (bit line)
2a 1st diffusion layer 2b 2nd diffusion layer 3 ONO film 3a 1st insulating film 3b 2nd insulating film 3c 3rd insulating film 4 1st conductive layer (silicon layer)
5 HTO or LTO
6 resist pattern 7 second conductive layer 8 oxide film 9 silicon oxide film or silicon nitride film 9a hard mask 10 silicon nitride film 10a hard mask 11, 11a polysilicon oxide film 12 sidewall nitride film 13 oxide film on diffusion layer 14 conductive layer (Word line)
15 Gate electrode 16 Silicon nitride film 17 Trapping region

Claims (7)

An insulating film having a laminated structure including a silicon oxide film and a silicon nitride film or a structure in which silicon fine particles (silicon nano dots) are distributed on at least a part of the silicon oxide film is formed on a semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device, wherein a diffusion layer to be a line and a conductive layer to be a word line are formed, and information is stored using charges captured by the insulating film,
After the formation of the insulating film, a first conductive layer is formed on the insulating film, an impurity for forming the diffusion layer is implanted through the first conductive layer and the insulating film, and a first conductive layer is formed on the first conductive layer. A method for manufacturing a nonvolatile semiconductor memory device, comprising depositing two conductive layers to form the conductive layer having a two-layer structure.   2. The nonvolatile semiconductor according to claim 1, wherein the first conductive layer on the diffusion layer, or the insulating film and the first conductive layer are converted into an oxide film by thermal oxidation or radical oxidation. A method for manufacturing a storage device. In the impurity implantation,
Forming a mask pattern made of a first silicon nitride film on the first conductive layer;
A sidewall film having a predetermined thickness is formed on the side wall of the mask pattern by depositing and etching back a second silicon nitride film,
3. The nonvolatile semiconductor memory device according to claim 1, wherein impurities are implanted through the first conductive layer and the insulating film using the mask pattern in which an opening width is defined by the sidewall. Manufacturing method. An insulating film having a laminated structure including a silicon oxide film and a silicon nitride film or a structure in which silicon fine particles (silicon nano dots) are distributed on at least a part of the silicon oxide film is formed on a semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device, wherein a diffusion layer to be a line and a conductive layer to be a word line are formed, and information is stored using charges captured by the insulating film,
After forming the insulating film, a first conductive layer is formed on the insulating film, and after removing the first conductive layer in the diffusion layer forming region, impurity implantation for forming the diffusion layer is performed through the insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising depositing a second conductive layer on the first conductive layer to form the conductive layer having a two-layer structure. After the impurity implantation and before depositing the second conductive layer,
Removing the insulating film on the diffusion layer;
5. The nonvolatile semiconductor memory device according to claim 4, wherein an oxide film having a thickness smaller than that of the insulating film is formed at least on the diffusion layer and on the side walls of the insulating film and the first conductive layer. Manufacturing method. An insulating film having a laminated structure including a silicon oxide film and a silicon nitride film or a structure in which silicon fine particles (silicon nano dots) are distributed on at least a part of the silicon oxide film is formed on a semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device, wherein a diffusion layer to be a line and a conductive layer to be a word line are formed, and information is stored using charges captured by the insulating film,
After forming the insulating film, a first conductive layer is formed on the insulating film, and after removing the first conductive layer and the insulating film in the diffusion layer forming region, the diffusion layer forming region, the insulating film, and An oxide film having a thickness smaller than that of the insulating film is formed on the side wall of the first conductive layer, and impurity implantation for forming the diffusion layer is performed through the oxide film, and a second layer is formed on the first conductive layer. A method for manufacturing a nonvolatile semiconductor memory device, comprising depositing a conductive layer to form the conductive layer having a two-layer structure.   The insulating film is composed of an ON film in which a silicon oxide film and a silicon nitride film are stacked in this order, or an ONO film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order. A method for manufacturing a nonvolatile semiconductor memory device according to claim 1.

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