JP2007067038A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which leak of charge from a floating gate electrode is suppressed and has high writing efficiency, and to provide the manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device 100 is provided with a plurality of assist gate electrodes AG which are formed on a main surface of a semiconductor substrate 110 through a gate insulating film 120 and form inversion layers in the semiconductor substrate 110, a plurality of floating gate electrodes FG formed in parts positioned between a plurality of assist gate electrodes AG on the main surface of the semiconductor substrate 110 through the gate insulating film 120, a control gate electrode CG formed on the floating gate electrodes FG from the assist gate electrodes AG, and n+impurity regions ND formed in parts between a plurality of the floating gate electrodes FG in the semiconductor substrate 110. The gate insulating film 120 has the gate insulating films 121 and 122 different in barrier height. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a charge storage floating gate electrode and a manufacturing method thereof.

2. Description of the Related Art Conventionally, a semiconductor device having a nonvolatile memory cell is known.
For example, in Japanese Patent Laying-Open No. 2005-85903 (Patent Document 1), a semiconductor device having a nonvolatile memory cell having an assist gate electrode for forming an inversion layer on a semiconductor substrate together with a floating gate electrode and a control gate electrode. It is disclosed. Here, the floating gate electrode is a charge storage electrode. Non-Patent Documents 1 and 2 also disclose semiconductor devices having the same structure as described above.
JP 2005-85903 A JP 2004-158810 A Y. Sasago et.al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2F2 / bit and programming throughput of 10 MB / s”, IEDM Dig.Tech.Papers, 2003, p.823-826 H. Kurata et.al., “Self-Boosted Charge Injection for 90-nm-Node 4-Gb Multilevel AG-AND Flash Memories Programmable at 16 MB / s”, 2004 Symposium on VLSI Circuits Digest of Technical Papers, 2004, p. .72-73

  In the nonvolatile memory cell as described above, it is important to improve the data writing speed. On the other hand, in Japanese Patent Application Laid-Open No. 2004-158810 (Patent Document 2), the use of a gate insulating film having a barrier height lower than that of a silicon oxide film as a tunnel insulating film located under the floating gate electrode improves writing efficiency. Is disclosed. However, by reducing the barrier height of the tunnel insulating film, there is a problem that charge leakage from the floating gate electrode is likely to occur.

  Further, from a viewpoint different from the above, with the miniaturization of the assist gate electrode, the width of the inversion layer formed under the assist gate electrode is reduced, and as a result, the resistance of the inversion layer as a wiring increases. There is a problem of doing.

  The present invention has been made in view of the above problems. That is, an object of the present invention is to provide a semiconductor device in which charge leakage from a floating gate electrode is suppressed and writing efficiency is high, and a method for manufacturing the same. Another object of the present invention is to provide a semiconductor device in which resistance of an inversion layer formed under an assist gate electrode is suppressed, and a method for manufacturing the same.

  In one aspect, a semiconductor device according to the present invention includes a semiconductor substrate, an assist gate electrode formed on a main surface of the semiconductor substrate via a gate insulating film, and capable of forming an inversion layer on the semiconductor substrate. A plurality of floating gate electrodes for charge storage formed on the main surface of the semiconductor substrate between the plurality of assist gate electrodes via a gate insulating film, and from the assist gate electrode to the floating gate electrode A control gate electrode provided via an insulating film and an impurity region formed in a portion located between a plurality of floating gate electrodes in a semiconductor substrate. The gate insulating films located under the floating gate electrode Have different first and second parts.

  In another aspect, the semiconductor device according to the present invention includes, in another aspect, a semiconductor substrate having a groove formed on the main surface, and a charge storage first electrode formed on both sides of the groove on the main surface of the semiconductor substrate via a gate insulating film. A first gate electrode; a second gate electrode formed on the main surface of the semiconductor substrate from within the trench portion via a gate insulating film; and a second gate electrode provided on the second gate electrode from the first gate electrode via the insulating film. 3 gate electrodes.

  In one aspect, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive film on a main surface of a semiconductor substrate via a first gate insulating film, and a step of patterning the first conductive film. Reducing the width of the first insulating film, forming the first insulating film on the patterned sidewall of the first conductive film, patterning the first gate insulating film using the first insulating film as a mask, A step of exposing the patterned first gate insulating film; and a second gate insulating film having a barrier height higher than that of the first gate insulating film at a portion where the first gate insulating film is removed from the main surface of the semiconductor substrate. Forming a second conductive film on the sidewall of the first insulating film from the first and second gate insulating films, and forming an impurity region in a portion of the semiconductor substrate adjacent to the second conductive film. Process and And forming a second insulating film over the conductive film, forming a third conductive film on the second insulating film, and a step of patterning the third conductive film.

  In another aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming a groove portion on the main surface of the semiconductor substrate, and the first conductive film is formed on the main surface of the semiconductor substrate from the inside of the groove portion via a gate insulating film. Forming the first conductive film, forming the first insulating film on the sidewall of the first conductive film, and forming the second insulating film on the sidewall of the first insulating film from the main surface of the semiconductor substrate. Forming a conductive film; forming a second insulating film on the second conductive film; forming a third conductive film on the second insulating film; and patterning the third conductive film. Prepare.

  According to the present invention, in one aspect, in a semiconductor device, write efficiency can be improved while suppressing leakage of electric charges from a floating gate electrode. In another aspect, the resistance of the inversion layer formed under the assist gate electrode can be suppressed.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below. Note that the same or corresponding parts are denoted by the same reference numerals, and the description thereof may not be repeated.

(Embodiment 1)
FIG. 1 is a top view of the semiconductor device according to the first embodiment. Referring to FIG. 1, a semiconductor device 100 according to the present embodiment is an AG (Assist Gate) -AND type flash memory (nonvolatile semiconductor memory device), and has a memory cell region (FIG. 1) and a peripheral circuit portion arranged around the memory cell region. The memory cell array portion includes a floating gate electrode FG (first gate electrode) which is an isolated pattern for charge accumulation, and an assist gate electrode AG (second gate electrode) for forming an inversion layer as a bit line on the semiconductor substrate. And a control gate electrode CG (third gate electrode) as a word line. On both sides of the assist gate electrode AG, n + impurity regions ND as bit lines are formed. That is, in the semiconductor device 100, the inversion layer formed by the assist gate electrode AG and the n + impurity region ND are used as bit lines. The control gate electrode CG is formed on the assist gate electrode AG from the floating gate electrode FG. The assist gate electrode AG and the control gate electrode CG are formed so as to intersect (substantially orthogonal) each other.

  The assist gate electrode AG and the control gate electrode CG are each connected to an upper layer wiring (not shown) via a contact portion (not shown). When a voltage is applied to the assist gate electrode AG, an inversion layer (not shown) as a source / drain is formed immediately below the assist gate electrode AG on the semiconductor substrate.

2 and 3 are a sectional view taken along line II-II and a sectional view taken along line III-III in FIG. 1, respectively. Referring to FIG. 2, assist gate electrode AG and floating gate electrode FG are formed on a semiconductor substrate 110 made of, for example, silicon via a gate insulating film 120. The gate insulating film 120 includes gate insulating films 121 and 122. An n + impurity region ND (impurity diffusion layer) is formed in a portion adjacent to the floating gate electrode FG in the semiconductor substrate 110. An insulating film 130 made of, for example, a SiO ₂ film is formed on the assist gate electrode AG and between the floating gate electrode FG and the assist gate electrode AG. An insulating film 140 that is an ONO (Oxide-Nitride-Oxide) film having a stacked structure of an oxide film-nitride film-oxide film is formed over the floating gate electrode FG and the assist gate electrode AG. A control gate electrode CG including a polysilicon film and a silicide film and extending in the arrow DR1 direction (see FIG. 1) is formed on the insulating film 140, and an insulating film 160 is formed on the control gate electrode CG. . Referring to FIG. 3, an insulating film 170 is formed between a plurality of control gate electrodes CG arranged in the extending direction of assist gate electrode AG (the direction of arrow DR2). An interlayer insulating film and an upper wiring (both not shown) are formed so as to cover the insulating films 160 and 170.

  Incidentally, there is a demand for improving the efficiency of hot electron injection into the floating gate electrode FG in a data write operation described later. On the other hand, in this embodiment, an insulating film having a low barrier height is used as the gate insulating film 121 to be a tunnel insulating film.

  On the other hand, there is a demand for suppressing leakage of charges accumulated in the floating gate electrode FG. In contrast, in the present embodiment, an insulating film having a high barrier height is used as the gate insulating film 122 located between the floating gate electrode FG and the n + impurity region ND.

  As described above, in the semiconductor device 100, the barrier heights of the gate insulating films 121 and 122 located under the floating gate electrode FG are different from each other, and the barrier height of the gate insulating film 122 is higher than the barrier height of the gate insulating film 121. Further, the barrier height of the insulating film 150 on the n + impurity region ND is approximately the same as the barrier height of the gate insulating film 122 and is higher than the barrier height of the gate insulating film 121.

More specifically, the gate insulating film 122 and the insulating film 150 are made of, for example, a SiO ₂ film, and the gate insulating film 121 is made of an insulating film having a barrier height lower than that of the SiO ₂ film. Examples of the insulating film having a barrier height lower than that of the SiO ₂ film include Al ₂ O ₃ , SiN, HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ , TaN, HfAlO, ZrAlO and the like can be mentioned. For example, when an Al ₂ O ₃ film having the same thickness is used instead of the SiO ₂ film, the barrier height is reduced from 3.5 (eV) to 2.8 (eV).

  As described above, by relatively increasing the barrier height of the gate insulating film 122 and the insulating film 150, the insulating property between the floating gate electrode FG and the n + impurity region ND that is the bit line can be kept high. , Leakage of electric charges from the floating gate electrode FG can be suppressed. On the other hand, the write efficiency to the floating gate electrode FG can be improved by lowering the barrier height of the gate insulating film 121 that becomes the tunnel insulating film.

  Next, writing, reading and erasing operations of the semiconductor device 100 which is a flash memory will be described with reference to FIGS.

  Data writing is performed by a source side hot electron injection method. Thereby, efficient data writing is realized at high speed with low current. Each memory cell can store multi-value data. This multi-value storage is realized by changing the write time for each individual memory cell while keeping the write voltage applied to the control gate electrode constant, thereby forming memory cells having different threshold levels. For example, four or more values such as “00” / “01” / “10” / “11” can be stored. Therefore, the function of two or more memory cells can be realized with one memory cell. As a result, the flash memory can be downsized.

  At the time of data writing, a voltage of about 16 V, for example, is applied to the control gate electrode CG to which the selected memory cell is connected. Then, for example, a voltage of about −2 V is applied to the other control gates CG. Further, a voltage of, for example, about 4.5 V is applied to n + impurity region ND serving as the drain in the selected memory cell. Here, a voltage of about 0 V, for example, is applied to an n + impurity region ND that becomes a source in the selected memory cell (for example, an n + impurity region ND adjacent to the n + impurity region ND that becomes a drain), while an unselected memory cell For example, a voltage of about 2 V is applied to the n + impurity region ND serving as the source in FIG. Thereby, in the selected memory cell, a write current flows from the drain to the source, and the charge accumulated in the n + impurity region ND on the source side is injected into the floating gate electrode FG through the gate insulating film 121. (Arrows in FIG. 2). On the other hand, in the non-selected memory cell, no current flows from the drain to the source, and no charge is injected into the floating gate electrode FG. Therefore, data is selectively written into a predetermined memory cell.

  Here, a voltage of about 0 V to 1 V, for example, is applied to the assist gate electrode AG formed between the n + impurity regions ND serving as the source / drain in the selected memory cell. Thereby, an inversion layer (not shown) is formed on the main surface of the semiconductor substrate 110 located under the assist gate AG. The inversion layer efficiently generates hot electrons during a data write operation, and assists in writing data at a high speed with a low channel current to the floating gate electrode FG in the selected memory cell. As a result, during the data write operation, a large potential drop occurs between the assist gate electrode AG and the floating gate electrode FG, and hot electrons can be efficiently generated. Then, high-speed writing can be performed with a low channel current.

  In the data read operation, a voltage of about 2V to 5V, for example, is applied to the control gate electrode CG to which the selected memory cell is connected, and a voltage of about −2V, for example, is applied to the other control gate electrodes CG. In addition, a voltage of, for example, about 4.5 V is applied to the assist gate electrode AG for forming the drain in the selected memory cell. Thereby, an inversion layer serving as a drain in the selected memory cell is formed. On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode AG for forming the drain in the non-selected memory cell. Thereby, in the non-selected memory cell, the inversion layer serving as the drain is not formed. As a result, isolation between the selected memory cell and the non-selected memory cell is realized. Further, a voltage of, for example, about 0V is applied to the n + impurity diffusion layer ND serving as the source in the selected memory cell, and a voltage of, for example, about 1V is applied to the inversion layer serving as the drain in the selected memory cell. Here, since the threshold voltage changes depending on the amount of charge accumulated in the floating gate electrode FG in the selected memory cell, the data of the memory cell is discriminated from the state of the current flowing between the n + impurity region ND and the inversion layer. be able to.

  In the semiconductor device 100, an n + impurity region ND is used as a bit line that becomes a source during a read operation. Generally, the resistance of the impurity diffusion layer (for example, about 700 kΩ or more and about 800 kΩ or less) is lower than the resistance of the inversion layer (for example, about 3 to 4 MΩ). Can be reduced. As a result, the threshold voltage is suppressed from changing depending on the position of the selected memory cell. And the reliability of the read operation is improved.

  In the data erasing operation, a negative voltage (for example, about −16 V) is applied to the selected word line, while a positive voltage is applied to the semiconductor substrate 110. Note that a voltage of about 0 V is applied to the assist gate electrode AG, and no inversion layer is formed. As a result, charges are discharged from the floating gate electrode FG to the semiconductor substrate 110. The emission is performed by FN (Fowler Nordheim) tunnel emission. With the above operation, data in a plurality of memory cells are erased collectively.

  Next, a method for manufacturing the flash memory will be described. 4 to 11 are cross-sectional views showing first to eighth steps in the method of manufacturing a semiconductor device according to the present embodiment, respectively.

Referring to FIG. 4, gate insulating film 121 (first gate insulating film) made of, for example, an Al ₂ O ₃ film is formed on semiconductor substrate 110. The gate insulating film 121 becomes a tunnel insulating film that allows charges to pass during data writing / erasing. Then, a conductive film AG0 (first conductive film) made of polycrystalline silicon or the like is formed on the gate insulating film 121 using a CVD method or the like so as to have a thickness of about 50 to 70 nm. Then, as shown in FIG. 5, the conductive film AG0 is patterned to form the assist gate electrode AG.

Referring to FIG. 6, an insulating film 130 (first insulating film) made of, for example, a SiO ₂ film is formed so as to cover the upper surface and side walls of assist gate electrode AG. The insulating film 130 is formed by, for example, forming a SiO ₂ film by the CVD method and then patterning the SiO ₂ film. Next, as shown in FIG. 7, the gate insulating film 121 is patterned using the insulating film 130 as a mask. In FIG. 7, the insulating film 130 and the gate insulating film 121 have a width B0.

  Referring to FIG. 8, for example, wet etching is performed on insulating film 130 so that the side wall of insulating film 130 is retreated, for example, by about 20 nm to 30 nm, and its width is reduced from B0 to B. As a result, the patterned gate insulating film 121 is exposed.

Referring to FIG. 9, a gate insulating film 122 (second gate insulating film) made of, for example, a SiO ₂ film is formed at a portion where the semiconductor substrate 110 is exposed by removing the gate insulating film 121. Thereafter, a conductive film FG0 (second conductive film) having a thickness of about 20 to 40 nm and made of polycrystalline silicon or the like is formed on the insulating film 130 from the gate insulating films 121 and 122 by using a CVD method or the like. The The conductive film FG0 is a conductive film for the floating gate electrode FG. Thereafter, as shown in FIG. 10, the conductive film FG0 is etched back. At this time, the conductive film FG0 remains on the sidewall of the insulating film 130. Note that an insulating film as an offset spacer at the time of impurity implantation described later may be formed on the sidewall of the conductive film FG0.

Referring to FIG. 11, n-type impurities such as phosphorus (P) are ion-implanted into semiconductor substrate 110 from between a plurality of conductive films FG 0 remaining on semiconductor substrate 110. Thereby, an n + impurity region ND as a bit line is formed. The ion implantation is performed, for example, under conditions of 10 KeV and 1 × 10 ¹⁴ / cm ⁻² .

Referring to FIGS. 2 and 3 again, an insulating film 150 (third insulating film) made of, for example, a SiO ₂ film is formed on n + impurity region ND. Then, an insulating film 140 (second insulating film) is formed so as to cover the insulating films 130 and 150 and the conductive film FG0. The insulating film 140 has an oxide film-nitride film-oxide film stacked structure (ONO film structure) having thicknesses of about 5 nm, 8 nm, and 5 nm, respectively.

A conductive film CG0 (third conductive film) is formed on the insulating film 140. The conductive film CG0 is a conductive film for the control gate electrode CG. Further, an insulating film 160 made of, for example, a SiO ₂ film is formed on the conductive film CG0. After the insulating film 160 is formed, the conductive film CG0 is patterned to form the control gate electrode CG.

  Then, the insulating film 140 and the conductive film FG0 are patterned using the control gate electrode CG as a mask to form a floating gate electrode FG that is an isolated pattern. Thereafter, an insulating film 170 is embedded between the patterned control gate electrodes CG.

  The above contents are summarized as follows. That is, the semiconductor device 100 according to the present embodiment includes a semiconductor substrate 110 and a plurality of semiconductor devices 110 formed on the main surface of the semiconductor substrate 110 via the gate insulating film 120 as shown in FIG. And a plurality of assist gate electrodes AG that can be formed on the main surface of the semiconductor substrate 110, and a plurality of floating gates that are formed between the plurality of assist gate electrodes AG via the gate insulating film 120. The gate electrode FG, the control gate electrode CG provided on the floating gate electrode FG from the assist gate electrode AG to the floating gate electrode FG via the insulating film 140, and the portion located between the plurality of floating gate electrodes FG in the semiconductor substrate 110 are formed. n + impurity region ND and “other insulating film” formed on n + impurity region ND , And an insulating film 150 and the gate insulating film 120 located under the floating gate electrode FG, and a gate insulating film 121 and 122 serving as the barrier height is different, "the first and second portions" together. More specifically, the gate insulating film 122 is positioned on the n + impurity region ND side with respect to the gate insulating film 121, and the barrier height of the gate insulating film 122 is higher than the barrier height of the gate insulating film 121.

  According to the above configuration, it is possible to improve the writing efficiency to the floating gate electrode FG while suppressing the leakage of charges from the floating gate electrode FG.

  In the semiconductor device 100, the barrier height of the insulating film 150 formed on the n + impurity region ND is set higher than the barrier height of the gate insulating film 121, thereby suppressing the leakage of charges from the floating gate electrode FG. At the same time, it is possible to prevent data from being written to the unintended floating gate electrode FG due to charges passing through the insulating film 150 during data writing.

For example, when an Al ₂ O ₃ film is used as the gate insulating film 121 and an SiO ₂ film is used as the gate insulating film 122, the voltage applied to the n + impurity region ND at the time of data writing is changed from about 4.5V to 3.3V. It is also possible to lower it to the extent. Thereby, junction leakage from the n + impurity region ND to the semiconductor substrate 110 can be reduced.

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, the conductive film AG0 as the “first conductive film” is formed on the main surface of the semiconductor substrate 110 via the gate insulating film 121 as the “first gate insulating film”. 4 (FIG. 4), patterning the conductive film AG0 (FIG. 5), and forming an insulating film 130 as a “first insulating film” on the sidewall of the patterned conductive film AG0 (FIG. 5). 6), a step of patterning the gate insulating film 121 using the insulating film 130 as a mask (FIG. 7), a step of exposing the patterned gate insulating film 121 by reducing the width of the insulating film 130, and the main of the semiconductor substrate 110 A gate insulating film 122 as a “second gate insulating film” having a barrier height higher than that of the gate insulating film 121 is formed on the surface where the gate insulating film 121 is removed. A step (FIG. 8, FIG. 8), a step (FIGS. 9 and 10) of forming a conductive film FG0 as a “second conductive film” on the side wall of the insulating film 130 from the gate insulating films 121 and 122; 110, an n + impurity region ND is formed in a portion adjacent to the conductive film FG0 (FIG. 11), an insulating film 150 as a “third insulating film” is formed on the n + impurity region ND, and the conductive film FG0. A step of forming an insulating film 140 as a “second insulating film”, a step of forming a conductive film CG0 as a “third conductive film” on the insulating film 140, and a step of patterning the conductive film CG0 (above) 2 and 3).

(Embodiment 2)
FIG. 12 is a top view of the semiconductor device according to the second embodiment. Referring to FIG. 12, a semiconductor device 200 according to the present embodiment is a modification of the semiconductor device according to the first embodiment, in that assist gate electrodes AG are formed on both sides of floating gate electrode FG. Features. In the semiconductor device 200, the inversion layer formed by the assist gate electrode AG is used as a bit line.

  13 and 14 are a sectional view taken along line XIII-XIII and a sectional view taken along line XIV-XIV in FIG. 12, respectively. Referring to FIG. 13, an assist gate electrode AG and a floating gate electrode FG are formed on a semiconductor substrate 210 made of silicon, for example, via a gate insulating film 220. The gate insulating film 220 includes gate insulating films 221 and 222. An insulating film 230 is formed on the side wall of the assist gate electrode AG. An insulating film 240 that is an ONO (Oxide-Nitride-Oxide) film having a stacked structure of an oxide film, a nitride film, and an oxide film is formed over the assist gate electrode AG from the floating gate electrode FG. A control gate electrode CG including a polysilicon film and a silicide film and extending in the direction of arrow DR1 (see FIG. 12) is formed on the insulating film 240, and an insulating film 260 is formed on the control gate electrode CG. . Referring to FIG. 14, an insulating film 270 is formed between a plurality of control gate electrodes CG arranged in the extending direction of assist gate electrode AG (the direction of arrow DR2). Then, an interlayer insulating film and an upper layer wiring (both not shown) are provided so as to cover the insulating films 260 and 270.

  There is a demand for reducing the resistance of the inversion layer formed under the assist gate electrode AG. 29 and 30 are diagrams for explaining an increase in inversion layer resistance. In the example shown in FIGS. 29 and 30, the assist gate electrode AG is formed on the semiconductor substrate 10 via the gate insulating film 20. In general, there is a region where the inversion layer IL is not formed at the end in the width direction of the assist gate electrode AG. Therefore, as shown in FIG. 29, when the gate length of the assist gate electrode AG is AgW, the width of the inversion layer IL is AgW-2R. The width (R) of the region where the inversion layer IL is not formed is substantially constant regardless of the gate length of the assist gate electrode AG. Therefore, as shown in FIG. 30, when the gate length of the assist gate electrode AG is set to AgW / S by scaling, the width of the inversion layer IL is AgW / S-2R. As described above, when the semiconductor device is scaled, there arises a problem that the resistance of the inversion layer IL increases more than the scaling ratio (S). On the other hand, in the present embodiment, as shown in FIG. 13, the groove 211 is formed in the semiconductor substrate 210, and the assist gate electrode AG is formed in the groove 211, thereby the gate length of the assist gate electrode AG. While suppressing an increase in the thickness of the inversion layer IL, the effective width of the inversion layer IL is expanded to reduce the resistance of the inversion layer IL. Therefore, it is possible to achieve both scaling of the semiconductor device and suppression of increase in inversion layer resistance.

  Assist gate electrode AG is formed on the main surface of semiconductor substrate 210 from within trench 211. That is, the width of assist gate electrode AG located above the main surface of semiconductor substrate 210 is wider than the width of trench 211. This makes it easier to form the inversion layer IL up to the vicinity of the main surface of the semiconductor substrate 210 (A portion in FIG. 13) as compared with the case where the assist gate electrode AG is simply formed in the trench 211. .

  Note that it is preferable that every other assist gate electrode AG as described above is formed as shown in FIGS. By doing in this way, generation | occurrence | production of the punch through by having formed the groove part 211 can be suppressed.

  Next, writing, reading, and erasing operations of the semiconductor device 200 that is a flash memory will be described with reference to FIGS.

  In the data write operation, a voltage of about 15 V, for example, is applied to the control gate electrode CG to which the selected memory cell is connected, and a voltage of, for example, about −2 V is applied to the other control gate electrodes CG. Further, a voltage of about 5 V, for example, is applied to the assist gate electrode AG for forming the source in the selected memory cell, and the assist gate electrode AG for forming the drain (for example, the assist gate electrode adjacent to the assist gate electrode AG for forming the source) For example, a voltage of about 8V is applied to AG). As a result, an inversion layer IL serving as a source / drain is formed on the main surface of the semiconductor substrate 210 facing these assist gate electrodes AG. On the other hand, a voltage of about −2 V, for example, is applied to assist gate electrodes AG other than those described above, and no inversion layer is formed on the main surface of semiconductor substrate 210 facing these assist gate electrodes AG. . Thereby, isolation between the selected memory cell and the non-selected memory cell is performed. Further, a voltage of, for example, about 4.5 V is applied to the bit line connected to the inversion layer serving as the drain in the selected memory cell. Here, for example, a voltage of about 0 V is applied to the bit line connected to the inversion layer serving as the source in the selected memory cell, while the bit line connected to the inversion layer serving as the source in the non-selected memory cell is applied to For example, a voltage of about 2V is applied. As a result, a write current flows from the drain to the source in the selected memory cell, and charges accumulated in the inversion layer on the source side are injected into the floating gate electrode FG via the gate insulating film 222. On the other hand, in the non-selected memory cell, no current flows from the drain to the source, and no charge is injected into the floating gate electrode FG. Through the above operation, data is selectively written into a predetermined memory cell. Note that the floating gate electrode FG can store multivalued data as in the first embodiment.

  In the data read operation, an operation opposite to the write operation is performed. Here, a voltage of about 2 to 5 V, for example, is applied to the control gate electrode CG to which the selected memory cell is connected, and a voltage of about −2 V, for example, is applied to the other control gate electrode CG. A voltage of about 4 V, for example, is applied to the assist gate electrode AG for source / drain formation in the selected memory cell. Thereby, the source / drain in the selected memory cell is formed. On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode AG for forming the source / drain in the unselected memory cell. As a result, in the non-selected memory cell, the inversion layer serving as the source / drain is not formed. As a result, isolation between the selected memory cell and the non-selected memory cell is realized. Here, a voltage of about 1 V, for example, is applied to the bit line to which the inversion layer serving as the drain in the selected memory cell is connected. On the other hand, a voltage of about 0 V, for example, is applied to the other bit lines. Further, a voltage of about 0 V, for example, is applied to the bit line connected to the inversion layer serving as the source in the selected memory cell. Here, the threshold voltage of the selected memory cell changes depending on the state of the accumulated charge in the floating gate electrode FG. Therefore, the data of the memory cell can be determined from the state of current flowing between the source and drain of the selected memory cell. With the above operation, a read operation can be performed on a multi-value storage memory cell.

  In the data erasing operation, a negative voltage (for example, about −16 V) is applied to the selected word line, while a positive voltage is applied to the semiconductor substrate 210. Note that a voltage of about 0 V is applied to the assist gate electrode AG, and no inversion layer is formed. As a result, charges are released from the floating gate electrode FG to the semiconductor substrate 210. The emission is performed by FN (Fowler Nordheim) tunnel emission. With the above operation, data in a plurality of memory cells are erased collectively.

  Next, a method for manufacturing the flash memory will be described. 15 to 27 are cross-sectional views showing first to thirteenth steps in the method of manufacturing a semiconductor device according to the present embodiment, respectively.

  Referring to FIG. 15, an insulating film 215 made of, for example, a silicon nitride film is formed on a semiconductor substrate 210, and a resist mask RM is formed on the insulating film 215. Then, the insulating film 215 and the semiconductor substrate 210 are etched using the resist mask RM as a mask. As a result, as shown in FIG. 16, a groove 211 is formed in the semiconductor substrate 210, and an opening 216 is formed in the insulating film 215.

  Referring to FIG. 17, for example, wet etching is performed on insulating film 215 to retract the side wall of insulating film 215 by, for example, about 5 nm. Next, as shown in FIG. 18, a gate insulating film 211 is formed on the semiconductor substrate 210 located in the opening 216 so as to have a thickness of, for example, about 5 nm in terms of a silicon dioxide equivalent film thickness. The gate insulating film 211 is formed by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method. Then, a conductive film AG0 (first conductive film) made of polycrystalline silicon or the like is formed over the gate insulating film 211 and the insulating film 215 in the trench 211 using a CVD (Chemical Vapor Deposition) method or the like. The conductive film AG0 is a conductive film for the assist gate electrode AG. Next, the insulating film 215 obtained by etching the conductive film AG0 is exposed, and then the insulating film 215 is removed by etching. As a result, as shown in FIG. 19, the conductive film AG0 is patterned to form the assist gate electrode AG.

Referring to FIG. 20, a gate insulating film 222 made of, for example, a SiO ₂ film having a thickness of about 10 nm is formed at a portion where the insulating film 215 is removed and the semiconductor substrate 210 is exposed. The gate insulating film 222 becomes a tunnel insulating film that allows charges to pass during data writing / erasing.

Referring to FIG. 21, an insulating film 230 (first insulating film) made of, for example, a SiO ₂ film is formed so as to cover the upper surface and side walls of assist gate electrode AG.

  Referring to FIG. 22, conductive film FG0 (second conductive film) made of polycrystalline silicon or the like is formed from gate insulating film 222 to insulating film 230 by using a CVD method or the like. The conductive film FG0 is a conductive film for the floating gate electrode FG. Thereafter, as shown in FIG. 23, the conductive film FG0 is etched back.

  Referring to FIG. 24, an insulating film 240 (second insulating film) is formed so as to cover conductive film FG0 from insulating film 230. The insulating film 240 has an oxide film-nitride film-oxide film stacked structure (ONO film structure) having thicknesses of about 5 nm, 8 nm, and 5 nm, respectively. Then, a portion where the insulating film 240 is absent and the gate insulating film 222 is exposed is formed in a region located between the plurality of conductive films FG0.

  Referring to FIG. 25, an assist gate electrode AG made of, for example, polycrystalline silicon and an insulating film 250 made of, for example, a silicon nitride film are formed in the portion where gate insulating film 222 is exposed.

Referring to FIG. 13 again, conductive film CG0 (third conductive film) including a polysilicon film and a silicide film is formed on insulating film 240. The conductive film CG0 is a conductive film for the control gate electrode CG. Furthermore, an insulating film 260 made of, for example, a SiO ₂ film is formed on the conductive film CG0. After the insulating film 260 is formed, the conductive film CG0 is patterned to form the control gate electrode CG. 26 and 27, insulating film 240 and conductive film FG0 are patterned using patterned control gate electrode CG as a mask to form floating gate electrode FG that is an isolated pattern. Thereafter, an insulating film 270 is embedded between the patterned control gate electrodes CG.

  The above contents are summarized as follows. That is, as shown in FIG. 13, the semiconductor device 200 according to the present embodiment includes a semiconductor substrate 210 having a groove 211 formed on the main surface and gate insulating films on both sides of the groove 211 on the main surface of the semiconductor substrate 210. A floating gate electrode FG as a “first gate electrode” for charge storage formed through 222 and a “second gate” formed on the main surface of the semiconductor substrate 210 from within the trench 211 through a gate insulating film 221. An assist gate electrode AG as a “gate electrode” and a control gate electrode CG as a “third gate electrode” provided from the floating gate electrode FG to the assist gate electrode AG via an insulating film 240 are provided.

  According to the above configuration, the resistance of the inversion layer IL formed under the assist gate electrode AG can be suppressed.

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, the step of forming the groove 211 on the main surface of the semiconductor substrate 210 (FIGS. 15 and 16) and the gate on the main surface of the semiconductor substrate 210 from the groove 211 are performed. A step of forming a conductive film AG0 as a “first conductive film” through the insulating film 221 (FIGS. 17 and 18), a step of patterning the conductive film AG0 (FIG. 19), and a sidewall of the conductive film AG0 Step of forming insulating film 230 as “first insulating film” (FIGS. 20 and 21) and conductive film FG0 as “second conductive film” from the main surface of semiconductor substrate 210 to the sidewall of insulating film 230 22 (FIGS. 22 and 23), an insulating film 240 as a “second insulating film” on the conductive film FG0 (FIG. 24), and a “third conductive film” on the insulating film 240. Forming a conductive film CG0 as Patterning the conductive film CG0 (or, 13, 14) and a.

(Embodiment 3)
FIG. 28 is a cross-sectional view of the semiconductor device according to the third embodiment. Referring to FIG. 28, semiconductor device 300 according to the present embodiment is a combination of characteristic portions of semiconductor devices 100 and 200 according to the first and second embodiments. That is, the semiconductor device 300 includes a semiconductor substrate 310 having a groove 311 formed on the main surface, a plurality of semiconductor devices 310 formed on the main surface of the semiconductor substrate 310 via the gate insulating film 320, and an inversion layer formed on the semiconductor substrate 310. An assist gate electrode AG that can be formed, and a plurality of charge storage floating gate electrodes FG that are formed on the main surface of the semiconductor substrate 310 between the plurality of assist gate electrodes AG via the gate insulating film 320. The n + impurity region ND formed in a portion located between the plurality of floating gate electrodes FG in the semiconductor substrate 310, the insulating film 350 formed on the n + impurity region ND, and the floating gate electrode FG from above the assist gate electrode AG. And a control gate electrode CG provided via an insulating film 340 The gate insulating film 320 located under the floating gate electrode FG has first and second portions 321 and 322 which barrier height are different from each other. More specifically, the second portion 322 of the gate insulating film 320 is positioned on the n + impurity region ND side with respect to the first portion 321, and the barrier height of the second portion 322 is higher than the barrier height of the first portion 321.

  According to the above configuration, the effects of both of the semiconductor devices 100 and 200 according to the first and second embodiments can be obtained. That is, according to the present embodiment, in the semiconductor device 300, the write efficiency to the floating gate electrode FG is improved while suppressing the leakage of charges from the floating gate electrode FG, and the semiconductor device 300 is formed under the assist gate electrode AG. The resistance of the inversion layer IL to be applied can be suppressed.

  Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a top view of a semiconductor device according to a first embodiment of the present invention. It is II-II sectional drawing in FIG. It is III-III sectional drawing in FIG. It is sectional drawing which showed the 1st process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 2nd process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 3rd process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 4th process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 5th process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 6th process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 7th process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 8th process in the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is XIII-XIII sectional drawing in FIG. It is XIV-XIV sectional drawing in FIG. It is sectional drawing which showed the 1st process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 2nd process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 3rd process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 4th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 5th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 6th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 7th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 8th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 9th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 10th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 11th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 12th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 13th process in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. It is FIG. (1) explaining increase of inversion layer resistance. FIG. 6 is a diagram (part 2) for explaining an increase in inversion layer resistance;

Explanation of symbols

  100, 200, 300 Semiconductor device, 110, 210, 310 Semiconductor substrate, 120, 121, 122, 220, 221, 222, 320, 321, 322 Gate insulating film, 130, 140, 150, 160, 170, 215, 230 , 240, 250, 260, 270, 330, 340, 350, 360 Insulating film, 211, 311 Groove part, 216 opening part, AG assist gate electrode, CG control gate electrode, FG floating gate electrode, AG0, CG0, FG0 conductive film , IL inversion layer, DN n + impurity region.

Claims (9)

A semiconductor substrate;
A plurality of assist gate electrodes formed on the main surface of the semiconductor substrate via a gate insulating film and capable of forming an inversion layer on the semiconductor substrate;
A plurality of floating gate electrodes for charge accumulation formed on the main surface of the semiconductor substrate via a gate insulating film in a portion located between the plurality of assist gate electrodes;
A control gate electrode provided on the floating gate electrode via an insulating film from the assist gate electrode;
An impurity region formed in a portion located between the plurality of floating gate electrodes in the semiconductor substrate,
The semiconductor device, wherein the gate insulating film located under the floating gate electrode includes first and second portions having different barrier heights. The second portion of the gate insulating film is located on the impurity region side with respect to the first portion;
The semiconductor device according to claim 1, wherein a barrier height of the second portion is higher than a barrier height of the first portion. Further comprising another insulating film formed on the impurity region,
The semiconductor device according to claim 1, wherein a barrier height of the other insulating film is higher than a barrier height of the first portion. Grooves are formed on the main surface of the semiconductor substrate,
4. The semiconductor device according to claim 1, wherein the assist gate electrode is formed on the main surface of the semiconductor substrate from within the groove. 5. A semiconductor substrate having a groove formed on the main surface;
A charge storage first gate electrode formed on both sides of the groove on the main surface of the semiconductor substrate via a gate insulating film;
A second gate electrode formed on the main surface of the semiconductor substrate through the gate insulating film from within the trench,
A semiconductor device comprising: a third gate electrode provided on the second gate electrode through an insulating film from the first gate electrode. Forming a first conductive film on a main surface of a semiconductor substrate via a first gate insulating film;
Patterning the first conductive film;
Forming a first insulating film on a sidewall of the patterned first conductive film;
Patterning the first gate insulating film using the first insulating film as a mask;
Reducing the width of the first insulating film to expose the patterned first gate insulating film;
Forming a second gate insulating film having a barrier height higher than that of the first gate insulating film on a portion of the main surface of the semiconductor substrate where the first gate insulating film is removed;
Forming a second conductive film on the sidewalls of the first insulating film from the first and second gate insulating films;
Forming an impurity region in a portion of the semiconductor substrate adjacent to the second conductive film;
Forming a second insulating film on the second conductive film;
Forming a third conductive film on the second insulating film;
And a step of patterning the third conductive film. A step of forming a third insulating film on the impurity region;
The method for manufacturing a semiconductor device according to claim 6, wherein a barrier height of the third insulating film is higher than a barrier height of the first gate insulating film. Further comprising forming a groove in the main surface of the semiconductor substrate;
The method for manufacturing a semiconductor device according to claim 6, wherein the first conductive film is formed on the main surface of the semiconductor substrate from within the groove. Forming a groove in the main surface of the semiconductor substrate;
Forming a first conductive film on the main surface of the semiconductor substrate from within the trench via a gate insulating film;
Patterning the first conductive film;
Forming a first insulating film on a sidewall of the first conductive film;
Forming a second conductive film from a main surface of the semiconductor substrate on a sidewall of the first insulating film;
Forming a second insulating film on the second conductive film;
Forming a third conductive film on the second insulating film;
And a step of patterning the third conductive film.

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