JP2007157927A - Non-volatile semiconductor memory device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device which is capable of reducing capacitance between floating gates, restraining the threshold voltage of a selected memory cell from varying, and preventing a cleaning liquid etc. from penetrating into a gap by blocking both the ends of the gap, and to provide a method of manufacturing the same. <P>SOLUTION: The non-volatile semiconductor memory device 100 includes a memory cell region RMC and a peripheral circuit region RT. Furthermore, the non-volatile semiconductor memory device 100 is equipped with a semiconductor substrate 1, a first and a second floating gate FG formed through the intermediary of a first insulating film, a first and a second control electrode CG formed through the intermediary of a second insulating film, a third insulating film formed on the first control gate CG, a fourth insulating film formed on the second control gate CG, a gap GA formed between the first floating gate FG and second floating gate FG, and a fifth insulating film which blocks the gap GA at the end sides of the first and second control gate CG. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In general, an electrically writable / erasable nonvolatile semiconductor memory device includes a plurality of floating gate electrodes formed on a main surface of a semiconductor substrate, and a control gate electrode formed on the floating gate electrode. Is known. In recent years, with the high integration of semiconductor integrated circuits, the size between floating gates has become narrower, and a large capacitance has been easily generated between adjacent floating gates. For this reason, there has been a problem due to so-called capacitive coupling in which the threshold voltage at the time of reading of the floating gate varies depending on the potential of the surrounding floating gate.

  Therefore, conventionally, a nonvolatile semiconductor memory device in which capacitive coupling between adjacent floating gates is suppressed has been proposed. For example, Japanese Patent Laid-Open No. 2000-100766 discloses a nonvolatile semiconductor memory device in which a cavity is formed between adjacent floating gates and between adjacent control gates, and silicon oxide between adjacent floating gates and between adjacent control gates. A nonvolatile semiconductor memory device in which an insulating film having a lower relative dielectric constant is formed is described.

  Japanese Patent Laid-Open No. 2002-76299 discloses a semiconductor substrate having a surface, a groove formed on the main surface of the semiconductor substrate, a first insulating film embedded in the groove, and a gap on the first insulating film. An opening formed in the first insulating film that exposes the surface of the semiconductor substrate located immediately below the region sandwiched between the two conductive layers, and the opening embedded in the opening. In addition, a semiconductor device including a second insulating film formed so as to cover two conductive layers and a void formed in an opening embedded by the second insulating film is described.

Furthermore, in the semiconductor device described in Japanese Patent Application Laid-Open No. 2004-349549, a semiconductor device in which a gap is formed between transistors is described. In the semiconductor device described in Japanese Patent Application Laid-Open No. 2002-110791, a gap is formed between the wirings.
JP 2000-100766 A JP 2002-76299 A JP 2004-349549 A JP 2002-110791 A

  In the nonvolatile semiconductor memory device and the semiconductor device, there is no description about a means for closing the formed gap. Therefore, in the nonvolatile semiconductor memory device and the semiconductor device, there arises a problem that the cleaning liquid enters the gap portion in the cleaning step after the gap portion is formed.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the capacitance between floating gates so that the threshold voltage of a selected memory cell is stored in the adjacent floating gate. A non-volatile semiconductor memory device and a method for manufacturing the same capable of suppressing fluctuations depending on the amount and suppressing the penetration of a cleaning solution or the like into the gap by closing both ends of the formed gap provide.

  A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device having a memory cell region having a memory cell and a peripheral circuit region having a control transistor capable of controlling application of a voltage to the memory cell, A semiconductor substrate; a first floating gate and a second floating gate formed on a main surface of the semiconductor substrate via a first insulating film; and a second insulating film formed on the first and second floating gates. The first control gate and the second control gate, the third insulating film formed on the first control gate, and the second control gate are formed so as to be in contact with or close to the third insulating film. Below the fourth insulating film, the third insulating film, and the fourth insulating film, at least the first floating gate and the second floatin A gap formed between the gate and the upper surface of the third insulating film and the fourth insulating film, covering a contact portion between the third insulating film and the fourth insulating film; And a fifth insulating film that closes the gap on the end side of the second control gate.

  A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a memory cell region having a memory cell and a peripheral circuit region having a control transistor capable of controlling application of a voltage to the memory cell. A method of forming a first floating gate and a second floating gate on a main surface of a semiconductor substrate via a first insulating film, and a second insulating film on the first and second floating gates. Forming a first control gate and a second control gate via the first control gate, forming a third insulating film on the first control gate, and forming a fourth insulating film on the second control gate; A step of forming a gap below the third insulating film and the fourth insulating film, and the first and second of the first and second control gates. Comprising at longitudinal end portion of the cement Roll gates, and forming a fifth insulating film so as to close the gap portion.

  In the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention, the threshold voltage of the selected memory cell can be prevented from fluctuating due to the amount of charge accumulated in the adjacent floating gate. Thus, it is possible to prevent the cleaning liquid or the like from entering the formed gap.

(Embodiment 1)
The nonvolatile semiconductor memory device 100 according to the first embodiment will be described with reference to FIGS. In the first embodiment, for example, an example in which the present invention is applied to a single 4 Gbit AND type flash memory will be described.

  1 is a plan view of a main part of the flash memory according to the first embodiment, FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a sectional view taken along line III-III in FIG.

The semiconductor substrate 1 on which the flash memory according to the first embodiment is formed is made of, for example, p-type silicon (Si) single crystal, and an active region 1A, an isolation region 1B, and a main surface (device formation surface) Is formed. The isolation region 1B is, for example, a trench type isolation region called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation). That is, an insulating film such as silicon oxide (SiO ₂ or the like) is buried in a groove dug in the main surface of the semiconductor substrate 1.

  The nonvolatile semiconductor memory device 100 includes a memory cell region RMC having a plurality of memory cells MC formed on the main surface of the semiconductor substrate 1 and a plurality of control transistors AGTr for controlling whether a voltage is supplied to the memory cells MC. A peripheral circuit region RT, and a connection region RC formed between the peripheral circuit region RT and the memory cell region RMC.

  On the main surface of the semiconductor substrate 1 where the memory cell region RMC is located, there are a plurality of control gates CG, a plurality of assist gates AG extending in a direction crossing the control gate CG, and a position between the assist gates AG. A plurality of floating gates FG formed on the main surface of the semiconductor substrate 1 positioned on the main surface of the semiconductor substrate 1 and below the control gate CG are formed. Further, a voltage is applied to the floating gate FG and the assist gate AG on the main surface of the semiconductor substrate 1 where the memory cell region RMC is located. A memory cell MC having an inversion layer to be formed and a control gate CG is formed.

  At one end of the control gate CG, a wide portion CGa is formed in which a contact CT5 to which a voltage is applied to the control gate CG is formed. The control gate CG is arranged so that the wide portions CGa formed in the two adjacent control gates CG are located on the same end side. For this reason, a set of wide portions CGa made up of two wide portions CGa are alternately arranged on one end side and the other end side of the control gate CG.

  In the control gate CG, the end on the wide portion CGa side is located closer to the peripheral portion of the memory cell region RMC than the end facing the wide portion CGa. Between the control gates CG arranged in this way, a gap GA is formed along the control gate CG, and both ends of the gap GA are formed by an insulating film 4 formed above the control gate CG. It is blocked. Therefore, a gap GA is formed between the floating gates FG adjacent in the direction in which the assist gate AG extends, and the capacitance formed between the floating gates FG adjacent in the direction in which the assist gate AG extends. Has been reduced.

  Therefore, even if the charge in the floating gate FG adjacent to the selected floating gate FG in the extending direction of the assist gate AG varies, the threshold voltage of the selected memory cell MC varies. Is suppressed.

  The assist gate AG has a rectangular shape in which each planar shape extends in one direction. The assist gates AG are arranged in parallel along a direction intersecting with the direction in which the assist gate AG extends at a predetermined interval. The width of the assist gate AG is about 65 nm, for example. The interval between adjacent assist gates AG is, for example, about 115 nm. The assist gate AG is disposed so that most of the assist gate AG overlaps the active region 1A in a plane. When a desired voltage is applied to the assist gate AG, an n-type inversion layer is formed on the main surface of the semiconductor substrate 1 located under the assist gate AG. This n-type inversion layer is a portion for forming a bit line (a source and a drain of the memory cell MC).

  On the main surface of the semiconductor substrate 1 where the peripheral circuit region RT is located, a wiring AGL is formed that extends in a direction intersecting with the direction in which the assist gate AG extends and to which ends of the plurality of assist gates AG are connected. Has been. An assist gate AG not connected to the wiring AGL is arranged on the main surface of the semiconductor substrate 1 located on the memory cell region RMC side from the main surface of the semiconductor substrate 1 where the wiring AGL is located. The wiring AGL is formed with a contact CT1 for applying a voltage to the wiring AGL and the assist gate AG connected to the wiring AGL, and the end of the assist gate AG not connected to the wiring AGL is also connected to the wiring AGL. A contact CT4 for applying a voltage to the assist gate AG is formed.

  Then, on the main surface of the semiconductor substrate 1 located on the opposite side of the memory cell region RMC with respect to the main surface of the semiconductor substrate 1 where the wiring AGL is located, the main surface of the semiconductor substrate 1 located under the assist gate AG A control transistor AGTr for controlling whether to apply a voltage to the inversion layer formed on the surface is formed.

  Furthermore, on the main surface of the semiconductor substrate 1 located on the opposite side of the memory cell region RAG with respect to the main surface of the semiconductor substrate 1 where the control transistor AGTr is located, the semiconductor substrate 1 located under the assist gate AG is arranged. A contact CT3 for applying a voltage to the inversion layer formed on the main surface is formed.

  FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and is a cross-sectional view between the control gates CG in the memory cell region RMC. As shown in FIG. 2, on the main surface of the semiconductor substrate 1 where the memory cell region RMC is located, there are a plurality of assist gates AG formed via an insulating film 8 and located between the assist gates AG. A floating gate FG formed via the insulating film 2 on the main surface of the semiconductor substrate 1 and a control gate CG formed via the insulating film 10 are formed on the floating gate FG.

The assist gate AG is made of, for example, a low-resistance polycrystalline silicon film, and the thickness in the direction perpendicular to the main surface of the semiconductor substrate 1 is, for example, about 50 nm. The insulating film 8 formed on the main surface of the semiconductor substrate 1 located under the assist gate AG is made of, for example, silicon oxide, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 8.5 nm. An insulating film 9 made of silicon oxide is formed on the side surface of the assist gate AG. An insulating film 18 made of, for example, silicon nitride (Si ₃ N ₄ or the like) is formed on the upper surface of the assist gate AG.

  The floating gate FG is a data charge storage layer of the memory cell MC, and is formed of, for example, low-resistance polycrystalline silicon. The floating gate FG is formed in a rectangular shape when viewed in plan. The width of the floating gate FG in the direction in which the assist gate AG extends is about 90 nm, for example, and the width in the direction in which the control gate CG extends is about 65 nm, for example.

  The insulating film 2 formed on the main surface of the semiconductor substrate 1 formed under the floating gate FG functions as a tunnel insulating film of the memory cell MC. For example, a silicon oxynitride film (SiON) or the like For example, about 9 nm in terms of silicon dioxide equivalent film thickness.

  An insulating film 16 made of a silicon oxide film or the like is formed between the floating gate FG and the assist gate AG. An insulating film 10 is formed between the control gate CG and the floating gate FG. The insulating film 10 is formed of, for example, a so-called ONO film in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked from the lower layer. The thickness of the insulating film 10 is a silicon dioxide equivalent film thickness, for example, about 16 nm.

The control gate CG is, for example, a laminate of a conductive film CGa made of low-resistance polycrystalline silicon and a refractory metal silicide film CGb such as tungsten silicide (WSi _x ) formed on the upper surface of the conductive film CGa. It is formed by a film. An insulating film 3 made of, for example, a silicon oxide film is formed on the upper surface of the control gate CG.

  3 is a cross-sectional view taken along line III-III in FIG. As shown in FIG. 3, a dummy floating gate FGD is formed on the main surface of the semiconductor substrate 1 where the connection region RC adjacent to the memory cell region RMC is located via the insulating film 2. Unlike the other floating gates FG, this dummy floating gate FGD does not function as a part of the memory cell MC. The dummy floating gate FGD extends from the peripheral portion of the memory cell region RMC to the connection region RC. An insulating film 4 made of an HDP (High Density Plasma) film or the like is formed on the upper surface of the dummy floating gate FGD.

  Further, on the main surface of the semiconductor substrate 1 where the peripheral circuit region RT adjacent to the connection region RC is located, the wiring AGL is formed on the main surface of the semiconductor substrate 1 adjacent to the wiring AGL via the insulating film 2. A contact CT3 for applying a voltage to the gate electrode SG of the control transistor AGTr and the inversion layer formed under the assist gate AG shown in FIG. 2 is formed.

  The wiring AGL is formed on the main surface of the semiconductor substrate 1 via the insulating film 2, and an insulating film 18 made of a silicon nitride film or the like is formed on the upper surface of the wiring AGL. An insulating film 12 made of a silicon oxide film or the like is formed on the upper surface of the insulating film 18, and an insulating film 3 made of a silicon oxide film or the like is formed on the upper surface of the insulating film 12. Yes. An insulating film 4 made of an HDP film or the like is formed on the upper surface of the insulating film 3. A contact CT1 for applying a voltage to the wiring AGL is connected to the wiring AGL, and a wiring M1 is connected to the upper end of the contact CT1. When a voltage is applied to the contact CT1, a voltage is applied to the wiring AGL and the assist gate AG connected to the wiring AGL in FIGS. 1 and 2, and the assist gate AG is connected to the wiring AGL and the wiring AGL. An inversion layer is formed on the main surface of semiconductor substrate 1 located under AG. A sidewall 50 made of a silicon oxide film or the like is formed on the side surfaces of the wiring AGL and the insulating films 18, 3 and 4.

  The control transistor AGTr includes a gate electrode SG made of polycrystalline silicon or the like, an impurity region 51 formed on the main surface of the semiconductor substrate 1 adjacent to the main surface of the semiconductor substrate 1 where the gate electrode SG is located, 54. The impurity region 51 functions as a source or drain of the control transistor AGTr, and extends from the gate electrode SG to the connection region RC. The impurity region 51 extends from the control transistor AGTr to below the assist gate AG shown in FIG. 1, and is electrically connected to an inversion layer formed under the assist gate AG.

The impurity region 54 also functions as a source or drain of the control transistor AGTr, and includes an n ⁻ -type impurity region 53 and an n ⁺ -type impurity region 54 having a higher concentration than the impurity region 53. For example, arsenic (As) is introduced into the impurity regions 53 and 52. A contact CT3 is connected to the main surface of the semiconductor substrate 1 on which the upper surface of the impurity region 52 is located.

  For this reason, when the control transistor AGTr is turned on, the voltage applied to the contact CT3 is applied to the inversion layer formed under the assist gate AG shown in FIG. 1 via the control transistor AGTr.

  An insulating film 12 made of a silicon oxide film or the like is formed on the upper surface of the gate electrode SG, and an insulating film 3 is formed on the upper surface of the insulating film 12. Further, an insulating film 4 made of an HDP film or the like is formed on the upper surface of the insulating film 3. On both side surfaces of the gate electrode SG and the insulating films 18, 12, 3, and 4, sidewalls 50 made of, for example, a silicon oxide film are formed.

  On the main surface of the semiconductor substrate 1 where the memory cell region RMC is located, a floating gate (first floating gate) FGA formed via an insulating film 2 and a floating gate (second floating gate) adjacent to the floating gate FGA are formed. A floating gate FG including a gate) FGB and a dummy floating gate FGD formed in the periphery of the memory cell region RMC on the connection region RC side is formed.

  A control gate (first control gate) CGA formed through the insulating film 10 is formed on the floating gate FGA, and a control gate (second control gate) CGB is formed on the floating gate FGB. Is formed. The width of the control gate CGA and the control gate CGB in the direction parallel to the main surface of the semiconductor substrate 1 is, for example, about 120 nm. The control gate CG is disposed on the side of the control gate CGA, the control gate CGB adjacent to the control gate CGA, and the memory cell region RMC on the side of the connection region RC, and is the dummy located closest to the connection region RC. Includes control gate CGD. The dummy control gate CGD has the same pattern as the other control gates CG, but no contact to which a voltage is applied is formed.

  An insulating film (third insulating film) 3A is formed on the upper surface of the control gate CGA, and an insulating film formed on the upper surface of the control gate CGB so as to be in contact with or close to the insulating film 3A. (Fourth insulating film) 3B is formed. The insulating film 3A and the insulating film 3B are formed so as to cover the control gates CGA and CGB, and the width in the direction parallel to the main surface of the semiconductor substrate 1 becomes thicker toward the upper end side of the control gates CGA and CGB. It is formed to become. For this reason, the insulating film 3A and the insulating film 3B bulge so as to be close to each other as they go upward. The upper end portions of the insulating films 3A and 3B have a thickness in the direction perpendicular to the main surface of the semiconductor substrate 1 from the upper end portions of the control gates CGA and CGB, for example, about 120 nm. The insulating film 3A and the insulating film 3B are in contact with or close to each other above the upper ends of the control gate CGA and the control gate CGB. When the insulating film 3A and the insulating film 3B are separated from each other, the main part of the semiconductor substrate 1 of the insulating film 3A and the insulating film 3B is the portion where the insulating film 3A and the insulating film 3B are closest to each other. The width in the direction parallel to the surface is about 20 nm.

  That is, when the insulating film 3A and the insulating film 3B are separated from each other, the side surfaces of the insulating films 3A and 3B are the control gates CGA and CGB in the portion where the insulating film 3A and the insulating film 3B are closest to each other. From one side surface of the semiconductor substrate 1, it protrudes about 50 nm in a direction parallel to the main surface of the semiconductor substrate 1.

  As described above, the insulating film 3A and the insulating film 3B are close to or in contact with each other, the contact portion between the insulating film 3A and the insulating film 3B, and the adjacent portion where the insulating film 3A and the insulating film 3B are closest to each other. A gap GA is formed further downward. For this reason, a gap GA is formed at least between the floating gate FGA and the floating gate FGB. Further, since the insulating film 3A and the insulating film 3B are in contact with or close to each other above the upper end of the control gate CG, the gap GA is also formed between the control gates CG. It is formed over the gate CG. Although insulating films 3A and 3B are slightly formed on the side surfaces of control gates CGA and CGB and floating gates FGA and FGB and also on the main surface of semiconductor substrate 1 located between floating gates FGA and FGB. The thickness is suppressed to about several nm. The insulating film 3 includes insulating films 3A and 3B formed in the memory cell region RMC, and is also formed in the connection region RC and the peripheral circuit region RT.

  An insulating film 4 made of an HDP film or the like is formed on the upper surface of the insulating film 3 located in the memory cell region RMC. The insulating film 4 is also formed in the memory cell region RMC, the connection region RC, and the peripheral circuit region RT.

  When the gap is formed between the insulating film 3A and the insulating film 3B, the insulating film 4 closes the gap, and when the insulating film 3A and the insulating film 3B are in contact with each other, It is formed so as to cover the contact portion between the insulating film 3A and the insulating film 3B. The thickness of the insulating film 4 in the direction perpendicular to the main surface of the semiconductor substrate 1 is, for example, the thickness in the direction perpendicular to the main surface of the semiconductor substrate 1 from the upper ends of the insulating films 3A and 3B. 400 nm or more and 500 nm or less.

  A portion of the insulating film 4 located in the memory cell region RMC is formed thicker than a portion of the insulating film 4 located in the connection region RC and the peripheral circuit region RT. The upper surface of the insulating film 4 located in the memory cell region RMC is located about 250 nm to 450 nm below the upper surface of the insulating film 4 located in the connection region RC and the peripheral circuit region RT. Therefore, the insulating film 4 has a step in the vicinity of the boundary region between the memory cell region RMC and the connection region RC. Of the surfaces of the dummy control gate CGD, the distance a between the side surface on the connection region RC side and the side surface of the step of the insulating film 4 in the direction parallel to the main surface of the semiconductor substrate 1 is, for example, about 40 nm. Yes.

  That is, of the surface of the insulating film 4 that covers the memory cell region RMC, the side surface 4a1 located in the direction orthogonal to the longitudinal direction of the control gate CG, and the connection region RC and the peripheral circuit most of the control gate CG. The distance a shown in FIG. 1 with respect to the dummy control gate CGD, which is the control gate CG closest to the side surface 4a1 and located closest to the side surface 4a1, is about 40 nm. In this way, the insulating film 4 is a portion that covers the memory cell region RMC and a portion that hangs down from the portion that covers the memory cell region RMC and covers at least a part of the connection region RC and the peripheral circuit region RT. And have.

  An interlayer insulating film 34 made of, for example, a silicon oxide film is formed on the upper surface of the insulating film 4 located in the connection region RC and the peripheral circuit region RT. Further, an insulating film 5 made of, for example, a silicon oxide film is formed on the upper surface of the interlayer insulating film 34 and on the upper surface of the insulating film 4 located in the memory cell region RMC. On the top, wirings M1 to M3 are formed.

  FIG. 4 is a cross-sectional plan view slightly above the main surface of the semiconductor substrate 1 at the end portion on the wide portion CGa side of the end portions of the control gates CGA and CGB shown in FIG.

  As shown in FIG. 4, control gates CGA and CGB and control gates CGC and CGD are formed on the main surface of the semiconductor substrate 1 so that the wide portions CGa are opposed to each other. The control gate CGC is formed on the main surface of the semiconductor substrate 1 opposite to the control gate CGA with respect to the control gate CGB. The control gate CGD is opposite to the control gate CGB with respect to the control gate CGA. Is formed on the main surface of the semiconductor substrate 1 located in Of the end portions of the control gates CGC and CGD, the wide gate portion is not formed at the end portion of the control gates CGA and CGB where the wide portion CGa is formed. The memory cell region RMC side shown in FIG.

  An insulating film 3 is formed on the surfaces of the control gates CGA, CGB, CGC, CGD, and gaps GA1, GA2, GA3, GA3, GA4 are provided between the control gates CGA, CGB, CGD, CGD, respectively. Is formed. These openings located at the ends of the gaps GA1, GA2, GA3, GA4 are respectively closed by the insulating film 4. Here, the gap GA3 formed between the control gate CGA and the control gate CGD and the gap GA1 formed between the control gate CGB and the control gate CGC are end portions of the control gates CGC and CGD. It extends to. On the other hand, the gap GA2 formed between the control gate CGA and the control gate CGB extends to the wide part CGa, and from the gaps GGA1 and GA3, the periphery of the memory cell region RMC shown in FIG. It extends to the department. That is, among the formed gaps GA1 to GA3, control gates CGA and CGB are formed on the main surface of the semiconductor substrate 1 adjacent to the gap GA2 extending to the most peripheral side of the memory cell region RMC. ing.

  The semiconductor substrate 1 includes the end surfaces CGa1 of the control gates CGA and CGB positioned in the longitudinal direction of the control gates CGA and CGB and the side surface 4a2 positioned in the longitudinal direction of the control gates CGA and CGB among the surfaces of the insulating film 4. The interval b in the direction parallel to the main surface is, for example, about 440 nm or more and about 460 nm, and preferably about 450 nm. Thus, by setting the distance b, the insulating film 4 can close the opening ends CG1a to CG3a of the gaps GA1 to GA3. In FIG. 1, the interval a is set to be smaller than the interval b, and the connection region RC is increased and the cell area is suppressed from increasing.

  A write operation, a read operation, and an erase operation of the nonvolatile semiconductor memory device 100 configured as described above will be described. FIG. 5 is a cross-sectional view of the nonvolatile semiconductor memory device 100 during a write operation. 5 and FIG. 1, a voltage of, for example, about 15V is applied to the control gate CG to which the selected memory cell MC is connected, and a voltage of, for example, about 0V is applied to the other control gates CG. Further, for example, about 1 V is applied to the assist gate A2G for forming the source of the selected memory cell MC, and the inversion functioning as the source is applied to the main surface of the semiconductor substrate 1 located under the assist gate AG2 for forming the source. Layer 23a is formed.

  Further, a voltage of, for example, about 7 V is applied to the drain formation assist gate AG3 of the selected memory cell MC to function as a drain on the main surface of the semiconductor substrate 1 located under the drain formation assist gate AG3. The inversion layer 23b to be formed is formed. Then, for example, a voltage of about 0V is applied to the other assist gate gates AG1 and AG4, and an inversion layer is formed on the main surface of the semiconductor substrate 1 located under the other assist gates AG1 and AG4. The selected memory cell MC is isolated from the non-selected memory cell MC. Then, for example, a voltage of about 7V is applied to the gate electrode SG of the control transistor AGTr, the control transistor AGTr is turned on, and a voltage of about 4V applied to the impurity region 54 shown in FIG. And applied to the inversion layer 23b.

  Then, for example, a voltage of about 0 V is applied to the inversion layer 23a functioning as a source. As a result, the charge accumulated in the n-type inversion layer 23a on the source side is allowed to flow as a certain channel current and efficiently injected into the floating gate FG via the insulating film 2 (constant charge injection method). Data is written to the memory cell MC at high speed. On the other hand, the drain current does not flow from the drain to the source of the non-selected memory cell MC so that data is not written. The amount of hot electrons injected into the floating gate FG of the selected memory cell MC can be reduced by changing the write time by keeping the voltage applied to the control gate CG to which the selected memory cell MC is connected constant. By changing it, it is possible to form a memory cell MC having several kinds of threshold levels and capable of storing multiple values. That is, four or more values such as “00” / “01” / “10” / “11” can be stored. For this reason, the function for two memory cells MC can be realized by one memory cell MC. Therefore, it is possible to reduce the size of the flash memory.

  FIG. 6 is a cross-sectional view of the nonvolatile semiconductor memory device 100 in the read operation. As shown in FIG. 6, when reading information in the selected memory cell MC, a voltage of about 2V to 5V is applied to the control gate CG to which the selected memory cell MC is connected, For example, a voltage of about 0 V is applied to the other control gate CG. Further, for example, a voltage of about 5 V is applied to the assist gate AG2 for forming the source and the assist gate AG3 for forming the drain of the selected memory cell MC. Thereby, an inversion layer 23a functioning as a source is formed on the main surface of the semiconductor substrate 1 located under the assist gate AG2, and the main surface of the semiconductor substrate 1 located under the assist gate AG3 functions as a drain. An inversion layer 23b is formed. Note that, for example, a voltage of about 0 V is applied to the other assist gates AG1 and AG4 to suppress the formation of an inversion layer on the main surface of the semiconductor substrate 1 located under the other assist gates AG1 and AG4. Then, the selected memory cell and the non-selected memory cell MC are isolated. Then, for example, a voltage of about 0V is applied to the inversion layer 23a, and about 1V is applied to the inversion layer 23b.

  At this time, the threshold voltage of the selected memory cell MC varies depending on the amount of charge accumulated in the floating gate FG of the selected memory cell MC, so that the current flowing between the inversion layer 23a and the inversion layer 23b. By sensing this, the data of the selected memory cell MC can be determined.

  Here, since the gap GA is formed between the floating gates FG adjacent in the direction in which the assist gate AG extends in FIGS. 1 and 3, the floating gate FG of the selected memory cell MC, The capacitance between the floating gate FG adjacent to the floating gate FG of the selected memory cell MC in the direction in which the assist gate AG extends is reduced. For this reason, even if the charge accumulated in the floating gate FG adjacent to the selected memory cell MC in the extending direction of the assist gate AG fluctuates, the threshold value of the selected memory cell MC It can suppress that a voltage fluctuates.

  FIG. 7 is a cross-sectional view of the nonvolatile semiconductor memory device 100 during the erase operation. As shown in FIG. 7, in the data erasing operation, a negative voltage is applied to the selected control gate CG to erase the data in the memory cells MC connected to the selected control gate CG at once. For example, a voltage of about −16 V is applied to the selected control gate CG, for example, a positive voltage is applied to the semiconductor substrate 1, and no voltage is applied to the assist gate AG, so that an inversion layer is formed. To be suppressed. In this way, by applying a voltage, the charges accumulated in the floating gate FG located under the selected control gate CG are discharged to the semiconductor substrate 1 through the insulating film 2, and a plurality of memory cells MC are thus obtained. Erase all data at once.

  Here, since the gap GA is formed between the control gates CG, the capacitance between the control gates CG is reduced, so that each control gate CG has a current and voltage in the adjacent control gate CG. Even if fluctuates, the electrical influence is suppressed to a small level. For this reason, in the various operations described above, a desired voltage can be applied to each control gate CG, and malfunctions can be reduced.

  A manufacturing process of the nonvolatile semiconductor memory device 100 configured as described above will be described. FIG. 8 is a plan view showing a first step in the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 8, isolation region 1 </ b> B that defines active region 1 </ b> A is formed on the main surface of semiconductor substrate 1. Isolation region 1 </ b> B is formed by embedding an insulating film made of, for example, silicon oxide in a groove formed in the main surface of semiconductor substrate 1. Then, after forming an n-type buried region by selectively introducing, for example, phosphorus (P) into the main surface of the semiconductor substrate 1 where the memory cell region RMC is located by a normal ion implantation method or the like, For example, boron (B) is selectively introduced into the main surface of the semiconductor substrate 1 in which the memory cell region RMC, the connection region RC, and the peripheral circuit region RT of the semiconductor substrate 1 are located by the ion implantation method of P In addition, for example, phosphorus (P) is selectively introduced into the semiconductor substrate 1 in which the peripheral circuit region RT is located to form an n-type well region.

  FIG. 9 is a plan view showing a second step of the manufacturing process of the nonvolatile semiconductor memory device 100, and FIG. 10 is a cross-sectional view taken along the line XX of FIG. It is sectional drawing of RT vicinity. 9 and 10, the main surface of the semiconductor substrate 1 where the impurity region 51 shown in FIG. 3 is exposed is exposed to the outside, and a photoresist pattern RP <b> 1 covering the main surface of the other semiconductor substrate 1 is formed. To do. Thereafter, for example, arsenic is ion-implanted into the main surface of the semiconductor substrate 1 to form an impurity region 51.

  FIG. 11 is a cross-sectional view showing a third step of the nonvolatile semiconductor memory device 100, and FIG. 12 is a cross-sectional view in the peripheral circuit region in the third step. As shown in FIGS. 11 and 12, an insulating film 8 made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 1 so as to have a thickness of about 8.5 nm in terms of silicon dioxide, for example. For example, after being formed by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method, a conductive film AGa made of, for example, low-resistance polycrystalline silicon is formed thereon by CVD so as to have a thickness of about 50 nm, for example. The insulating film 18 made of, for example, silicon nitride is deposited thereon by the CVD method or the like so as to have a thickness of about 70 nm, for example. Subsequently, an insulating film 12 made of, for example, silicon oxide is deposited on the insulating film 18 by, for example, a CVD method using, for example, TEOS (Tetraethoxysilane) gas, and then hardened made of, for example, low-resistance polycrystalline silicon. A mask film 26a is deposited by a CVD method or the like, and an antireflection film 27a made of, for example, silicon oxynitride (SiON) is deposited thereon by a plasma CVD method or the like. Thereafter, a resist pattern for forming the first electrode 4G is formed on the antireflection film 27a. Thereafter, using the resist pattern as an etching mask, the antireflection film 27a and the hard mask film 26a exposed therefrom are etched, and then the resist pattern is removed.

  FIG. 13 is a cross-sectional view showing a fourth step in the manufacturing process of the nonvolatile semiconductor memory device 100, and FIG. 14 is a plan view in the fourth step. FIG. 15 is a cross-sectional view in the peripheral circuit region RT. As shown in FIG. 13, the pattern of the assist gate AG shown in FIG. 1 is formed on the antireflection film 27a and the hard mask film 26a shown in FIG. 11, and the antireflection film 27a and the hard mask film 26a are formed. Is used as an etching mask to etch the insulating films 12 and 18 and the conductive film 4 exposed therefrom. As a result, an assist gate AG is formed on the main surface of the semiconductor substrate 1 as shown in FIG. As shown in FIG. 15, an impurity region 51 is formed on the main surface of the semiconductor substrate 1 where the peripheral circuit region RT is located. On the main surface of the semiconductor substrate 1, an insulating film 8 and The conductive film 4 includes an insulating film 10 formed on the upper surface of the conductive film 4, and an insulating film 12 formed on the upper surface of the insulating film 10.

  FIG. 16 is a cross-sectional view showing a fifth step in the manufacturing process of the nonvolatile semiconductor memory device 100. In FIG. 16, the main surface of the semiconductor substrate 1 is subjected to a thermal oxidation process such as an ISSG oxidation method. By this thermal oxidation treatment, an insulating film 9 made of, for example, a silicon oxide film is formed on the side surface of the assist gate AG. Subsequently, after an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate by, for example, a CVD method using TEOS gas, this is etched back. By this etch-back process, a sidewall-like edge film 16 is formed on the side surfaces of the assist gate AG and the insulating films 18 and 12. By forming the insulating film 16, the main surface of the semiconductor substrate 1 located between the assist gates AG is exposed to the outside.

  FIG. 17 is a cross-sectional view showing a sixth step in the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 17, first, an insulating film made of, for example, silicon oxide is formed on the main surface of semiconductor substrate 1, and then heat treatment (oxynitriding treatment) is performed in a gas atmosphere containing nitrogen (N). Thus, nitrogen is segregated at the interface between the insulating film and the semiconductor substrate 1 to form the insulating film 2 made of silicon oxynitride (SiON) on the main surface of the semiconductor substrate 1 located between the assist gates AG. The insulating film 2 is a film that functions as a tunnel insulating film of the memory cell MC, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 9 nm. Subsequently, a conductive film 6 made of, for example, low-resistance polycrystalline silicon is deposited on the main surface of the semiconductor substrate 1 by a CVD method or the like.

  Subsequently, the conductive film 6 formed on the main surface of the semiconductor substrate 1 is subjected to an etch back process or a chemical mechanical polishing (CMP) process by an anisotropic dry etching method. By this treatment, the conductive film 6 is filled on the main surface of the semiconductor substrate 1 located between the insulating films 16. FIG. 18 is a cross-sectional view showing a seventh step of the manufacturing process of nonvolatile semiconductor memory device 100. Then, dry etching is performed on the insulating film 12 and the insulating film 16 shown in FIG. At this time, the insulating film 18 is made to function as an etching stopper by increasing the etching ratio of silicon oxide and silicon nitride so that the silicon oxide is more easily etched than the silicon nitride film. , 16 are selectively removed. In this way, the conductive film 6 located above the insulating film 18 is exposed to the outside.

  FIG. 19 is a cross-sectional view showing an eighth step of the nonvolatile semiconductor memory device 100. As shown in FIG. 19, on the main surface of the semiconductor substrate 1, for example, an insulating film made of a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated from the lower layer by the CVD method to insulate. A film 10 is formed. Thereafter, on the upper surface of the insulating film 10, a conductive film CGa made of, for example, low-resistance polycrystalline silicon, and a conductive film made of a refractory metal silicide film, such as tungsten silicide, having a lower resistance than the conductive film CGa. CGb is deposited sequentially from the lower layer by the CVD method or the like. The conductive film CGa is about 100 to 150 nm, for example, and the thickness of the conductive film 5b is about 100 nm, for example. Thereafter, an insulating film 13 made of, for example, silicon oxide is deposited on the conductive film CGb by a CVD method using TEOS gas or the like, and then a hard mask film 26b made of, for example, low-resistance polycrystalline silicon is formed on the conductive film CGb by the CVD method. Further, an antireflection film 27b made of, for example, silicon oxynitride (SiON) is deposited thereon by a CVD method or the like.

  Next, a resist pattern for word line formation is formed on the antireflection film, and the antireflection film 27b and the hard mask film 26b are patterned using this as an etching mask, and then the resist pattern for word line formation is removed. Subsequently, the insulating film 13, the conductive film CGb, and the conductive film CGa exposed therefrom are etched using the remaining laminated film of the hard mask film and the antireflection film as an etching mask. Thereby, the control gate CG is formed.

  FIG. 20 is a cross-sectional view showing a ninth step of the manufacturing process of the nonvolatile semiconductor memory device 100, and is a cross-sectional view in the memory cell region RMC, the connection region RC, and the peripheral circuit region RT. As shown in FIG. 20, a conductive film 6 is formed on the main surface of the semiconductor substrate 1 where the memory cell region RMC is located via an insulating film 2, and on the upper surface of the conductive film 6 A control gate CG is formed through the insulating film 10. Among the control gates CG, the control gate CG formed closest to the connection region RC is a dummy control gate CGD, and does not function as the control gate CG without being applied with a voltage.

  As described above, when the control gate CG is formed by patterning the conductive films CGa and CGb, the dummy control gate CGD is also formed, so that the other control gate CG can be easily formed into a desired shape. That is, by forming the dummy control gate CGD in this way, in patterning the control gate CG in the region located closer to the center of the memory cell region RMC than the dummy control gate CGD, the semiconductor Variations in the distribution of the etchant applied on the main surface of the substrate 1 are less likely to occur. For this reason, the control gate CG located at the center of the memory cell region RMC can be formed in a desired shape from the dummy control gate CGD.

  The conductive film 6 extends from the main surface of the semiconductor substrate 1 where the memory cell region RMC is located to the main surface of the semiconductor substrate 1 where the connection region RC is located. A conductive film AGa is formed on the main surface of the semiconductor substrate 1 via the insulating film 2 at the boundary between the connection region RC and the peripheral circuit region RT. An insulating film 18 is formed on the upper surface of the conductive film 4, and the insulating film 12 is formed on the upper surface of the insulating film 18. Here, the insulating film 10 is formed on the upper surface of the conductive film 6 located under the control gate CG and on the upper surface of the insulating film 12.

  FIG. 21 is a cross-sectional view of the memory cell region RMC, the connection region RC, and the peripheral circuit region RT in the tenth step of the nonvolatile semiconductor memory device 100. As shown in FIG. 21, in the tenth step, the insulating film 10 is etched and removed. By this etching process, the insulating film 10 remains on the upper surface of the conductive film 6 located under the control gate CG, and the insulating film 10 located in the connection region RC and the peripheral circuit region RT is removed.

  FIG. 22 is a cross-sectional view showing an eleventh step of the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 22, a resist 30 having an opening in the memory cell region RMC is formed on the main surface of the semiconductor substrate 1. Then, using the control gate CG as a mask, the conductive film 6 is patterned to form the floating gate FG. Here, among the formed floating gates FG, the floating gate FG formed most on the connection region RC side is a dummy floating gate FGD and does not have a function of accumulating charges. The dummy floating gate FGD extends from the memory cell region RMC to the connection region RC.

  FIG. 23 is a cross-sectional view showing a twelfth process of the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 23, insulating film 3 is formed on the main surface of semiconductor substrate 1 by plasma CVD. This insulating film 3 is formed using a plasma CVD apparatus. Then, when the insulating film 3 is formed, the supply flow rate of the film forming gas of the plasma CVD apparatus is increased. By making the gas supply amount excessive, the burying property of the insulating film 3 is lowered, and the insulating film 3 is hardly embedded between the control gates CG and between the floating gates FG. For example, it is preferable to set the supply amount of N 2 O gas to 500 sccm or more and 600 sccm or less, and the gas supply amount of SiH 4 to about 3 sccm or more and 5 sccm or less.

  In particular, it is preferable to increase the N 2 O / SiH 4 ratio when forming the insulating film 3. By increasing the N 2 O / SiH 4 ratio, coverage can be deteriorated, and embeddability can be reduced. For example, the N2O / SiH4 ratio is preferably in the range of 1-2.

  Further, when forming the insulating film 3, the film forming temperature is set lower than usual. When the film formation temperature is set low, the surface reaction is stagnated, coverage can be reduced, and embeddability can be reduced. For example, the film forming temperature is preferably in the range of 200 ° C. or higher and 250 ° C. or lower.

  Further, the power of the plasma generation source is set low when the insulating film 3 is formed. By setting the power low, the plasma density decreases, radicals decrease, coverage decreases, and embeddability decreases. For example, the power of the plasma generation source is preferably in the range of about 125W to 925W.

Then, when the insulating film 3 is formed, the film forming pressure is lowered from the normal time. When the film formation pressure is reduced, the directivity of film formation is improved, and the formation of an insulating film on the side surface of the control gate CG and the side surface of the floating gate FG is suppressed. For example, the film forming pressure is preferably in the range of 10 ⁻² Torr to several torr.

  Furthermore, when forming the insulating film 3, it is preferable to reduce the bias applied between the main surface of the semiconductor substrate 1 and the electrode of the plasma CVD apparatus. For example, the bias between the electrode and the main surface of the semiconductor substrate 1 is set to about 0 W. Here, when the voltage applied to the semiconductor substrate 1 is low, in the process of forming the insulating film 3 by plasma CVD, ions in the atmosphere in the plasma CVD apparatus are applied to the particles in the formed insulating film 3. Even if the particles of the insulating film 3 collide and jump out of the insulating film 3, the particles of the insulating film 3 are easily pulled in the air without being pulled to the main surface side of the semiconductor substrate 1, The deposition on the main surface of the semiconductor substrate 1 is suppressed.

  For this reason, it can suppress that the insulating film 3 is deposited on the main surface of the semiconductor substrate 1 located between the control gate CG and the floating gate FG.

  The insulating film 3 thus formed is first deposited on the surface of the control gate CG on the upper end side of the control gate CG. Then, a new insulating film 3 is further formed on the surface of the insulating film 3 attached to the surface on the upper end side of the control gate CG. In this way, the insulating film 3 bulging so that the width in the direction parallel to the main surface of the semiconductor substrate 1 becomes wider toward the upper end of the control gate CG is formed. The insulating film 3 formed on the upper end of one control gate CG and the insulating film 3 formed on the upper end of the control gate CG adjacent to the one control gate CG are at least about 20 nm or more They are close to each other and are in contact with each other.

  By forming the insulating film 3 as described above, the gap GA is formed in the vicinity of the insulating film 3 formed at the upper end portion of the adjacent control gate CG or under the contact portion. Here, since the insulating film 3 formed on the adjacent control gate CG approaches or contacts above the control gate CG, the gap GA is formed at least between the floating gates FG. Further, the gap GA extends between the control gates CG and is formed to be closed above the upper end of the control gate CG. The insulating film 3 is also formed on the upper surface of the dummy floating gate FGD formed on the connection region RC and on the upper surface of the insulating film 12 formed in the peripheral circuit region RT.

  FIG. 24 is a cross-sectional view showing a thirteenth step of the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 24, an insulating film 4 made of an HDP film or the like is formed on the main surface of the semiconductor substrate 1 by a plasma CVD method. In this manner, by forming the insulating film 4 on the upper surface of the insulating film 3, it is possible to prevent the cleaning liquid from penetrating into the gap GA in the subsequent cleaning step.

  The insulating film 4 is deposited in a direction perpendicular to the main surface of the semiconductor substrate 1 from the upper end portion of the insulating film 3, for example, about 400 nm to 500 nm. This is because if the thickness of the insulating film 3 positioned on the insulating film 4 is less than 400 nm, the cleaning liquid may enter the gap GA in the subsequent cleaning process. Further, if the thickness is more than 500 nm, there is a problem that in the subsequent process, the photolithography exposure cannot be satisfactorily performed in the process of exposing the photoresist when patterning the peripheral circuit region RT. .

  The deposition temperature of the insulating film 4 is, for example, 300 ° C. or more and 500 ° C. or less, and the bias power is in the range of 2000 W or more and 4000 W or less. As described above, when the bias power is increased, the voltage applied to the semiconductor substrate 1 increases when the insulating film 4 is formed. Therefore, when ions in the plasma atmosphere collide with the particles in the insulating film 3 or the insulating film 4 and the particles of the insulating film 3 or the insulating film 4 jump out, the particles are moved to the semiconductor substrate 1 side. It is attracted and the gap formed between the insulating films 3 can be closed.

  The D / S ratio of the film formation conditions of the insulating film 4 is 3 or more so that the sputtering effect of the plasma CVD method is effectively used and the film formation time of the insulating film 4 is not long. 5 or less. Here, the D / S ratio is expressed as D / S ratio = 1 + D (deposition rate (nm / s)) / S (sputtering rate (nm / s)). This is because if the D / S ratio is smaller than 3, the rate at which the insulating film 4 is formed is reduced, and there is a problem that it takes time to form the film. Further, when the D / S ratio is greater than 5, the insulating film 4 is likely to enter the gap portion CG.

  FIG. 25 is a cross-sectional view showing a fourteenth step of manufacturing the nonvolatile semiconductor memory device 100. As shown in FIG. 25, a resist 31 is formed on the upper surface of the insulating film 4 located in the memory cell region RMC, and the insulating film 4 formed in the connection region RC and the peripheral circuit region RT is dry-etched. Then, the upper surface of the insulating film 4 formed on the main surface of the semiconductor substrate 1 in which the connection region RC and the peripheral circuit region RT are located is made higher than the upper surface of the insulating film 4 formed on the upper surface of the insulating film 3, for example, Lower by 250 nm or more and 450 nm or less. The thickness Lb in the direction perpendicular to the main surface of the semiconductor substrate 1 of the insulating film 4 located in the peripheral circuit region RT and the connection region RC is, for example, not less than 200 nm and not more than 300 nm. Thereafter, the main surface of the semiconductor substrate 1 is washed to remove the resist 31. At the time of this cleaning, since the insulating film 4 formed of a silicon oxide film having a higher density than the insulating film 3 is formed on the gap GA formed on the memory cell region RMC, the cleaning liquid is supplied to the gap GA. Infiltration into the inside is suppressed.

  Furthermore, since the thickness La of the insulating film 4 formed on the upper surface of the insulating film 3 in the direction perpendicular to the main surface of the semiconductor substrate 1 is, for example, 400 nm or more and 450 nm, the gap Infiltration of the cleaning liquid into the part GA is well suppressed. If the thickness is less than 400 nm, the cleaning liquid may penetrate into the gap GA. When the thickness is greater than 450 nm, the thickness of the insulating film 4 formed on the main surface of the semiconductor substrate 1 where the connection region RC and the peripheral circuit region RT are located is perpendicular to the main surface of the semiconductor substrate 1. This is because the amount of etching applied to the insulating film 4 becomes excessive in order to set Lb to 200 nm or more and 300 nm or less.

  FIG. 26 is a cross-sectional view showing a fifteenth step of the manufacturing process of the nonvolatile semiconductor memory device 100. As shown in FIG. 26, a resist 32 is deposited on the main surface of semiconductor substrate 1. Then, the resist 32 is subjected to an exposure process to form a pattern of the wiring AGL and the gate electrode SG on the resist 32, and then the insulating films 3, 4, 12, 11, 11 located in the peripheral circuit region RT and the connection region RC. Then, the conductive film 4 is patterned to form a wiring AGL and a gate electrode SG on the main surface of the semiconductor substrate 1.

  Here, in the fourteenth step, the difference between the upper surface of the insulating film 4 formed in the memory cell region RMC and the upper surface of the insulating film 4 formed on the connection region RC and the peripheral circuit region RT is 450 nm or less. Therefore, the inclination of the resist 32 formed at the boundary portion between the connection region RC and the memory cell region RMC is suppressed from becoming excessively steep. Thereby, the pattern of the wiring AGL and the gate electrode SG is suppressed from being formed on the inclined surface of the resist 32, and the wiring AGL and the gate electrode SG pattern to be formed on the flat surface of the resist 32 during the exposure process. Therefore, the pattern can be formed satisfactorily. Note that the thickness in the direction perpendicular to the main surface of the semiconductor substrate 1 of the insulating film 4 formed on the connection region RC and the peripheral circuit region RT is 200 nm or more and 300 nm or less. When the electrode SG is patterned, it is possible to prevent the conductive film AGa and the insulating films 18, 3, and 4 from being excessively thick and to form the gate electrode SG and the wiring AGL satisfactorily. it can.

FIG. 27 is a sectional view showing a sixteenth step of the manufacturing process of the nonvolatile semiconductor memory device 100, and FIG. 28 is a sectional view showing a seventeenth step. First, a mask having an opening corresponding to the impurity region 53 to be formed is formed on the main surface of the semiconductor substrate 1. Then, ions are implanted into the main surface of the semiconductor substrate 1 from above the mask, and on the main surface of the semiconductor substrate 1 located on the opposite side of the memory cell region RMC with respect to the main surface of the semiconductor substrate 1 where the gate electrode SG is located. Then, an n ⁻ type impurity region 53 is formed. After this impurity region 53 is formed, the main surface of the semiconductor substrate 1 is washed to remove the mask. During the cleaning for removing the mask, since the insulating film 4 having a higher density than the insulating film 3 is formed on the upper surface of the gap GA formed in the memory cell region RMC, the gap GA Infiltration of the cleaning liquid into the inside is suppressed.

Then, the insulating film 50 is embedded between the wiring AGL and the gate electrode SG by the CVD method using TEOS gas, and the insulating films 4, 3, 12 formed on the upper surfaces of the gate electrode SG and the gate electrode SG. A sidewall-like insulating film 50 is formed on the side surface of the substrate. Subsequently, an n ⁺ -type impurity region 52 is formed on the main surface of the semiconductor substrate 1 located on the side opposite to the memory cell region RMC with respect to the main surface of the semiconductor substrate 1 on which the gate electrode SG is located. An impurity region 54 that includes a region 53 and an impurity region 52 and functions as a source or a drain is formed. In this way, the control transistor AGTr is formed in the peripheral circuit region RT. Then, an interlayer insulating film 34 made of a silicon oxide film or the like is deposited on the main surface of the semiconductor substrate 1 by, for example, a plasma CVD method using TEOS gas. Then, dry etching is performed on the interlayer insulating film 34 formed on the memory cell region RMC.

  Then, as shown in FIGS. 3 and 28, first, CMP is performed on the upper surface of the interlayer insulating film 34 to remove the interlayer insulating film 34 formed on the memory cell region RMC, and the connection region RC and the peripheral region are removed. The interlayer insulating film 34 formed on the main surface of the semiconductor substrate 1 where the circuit region RT is located is flattened so that the upper surface of the interlayer insulating film 34 coincides with the upper surface of the insulating film 4 formed in the memory cell region RMC. Here, in the sixteenth step, by performing dry etching on the interlayer insulating film 34 located in the memory cell region RMC in advance, the amount of CMP applied to the interlayer insulating film 34 can be reduced, and the interlayer insulating film 34 can be satisfactorily obtained. The upper surface of the substrate can be flattened.

  Thereafter, the insulating film 5 is formed on the upper surface of the interlayer insulating film 34, and the contact CT1 reaching the upper surface of the wiring AGL, the contact CT2 reaching the upper surface of the gate electrode SG, and the impurity region 54 are located. A contact CT3 reaching the main surface of the semiconductor substrate 1 is formed. At this time, since the insulating film 10 which is a so-called ONO film is not formed on the peripheral circuit region RT and the connection region RC, the contact holes of the contacts CT1 to CT3 can be favorably formed. In this way, the nonvolatile semiconductor memory device 100 formed on the main surface of the semiconductor substrate 1 shown in FIG. 3 is formed.

(Embodiment 2)
With reference to FIGS. 29 to 32, another manufacturing method different from the method for manufacturing the nonvolatile semiconductor memory device 100 will be described. FIG. 29 is a cross-sectional view showing a ninth step after the eighth step of nonvolatile semiconductor memory device 100 shown in FIG. 29 and 19, the insulating film 10 located on the control gate CG located between the control gates CG is removed, and the conductive film 6 is patterned to form the floating gate FG and the dummy floating gate FGD.

  FIG. 30 is a cross-sectional view showing the tenth step of the nonvolatile semiconductor memory device 100. As shown in FIG. 30, a resist 40 is formed on the main surface of semiconductor substrate 1 on the main surface of semiconductor substrate 1 where memory cell region RMC is located, and peripheral circuit region RT and connection region RC are formed outside. Expose to the direction. Then, the insulating film 10 formed in the connection region RC and the peripheral circuit region RT is etched and removed.

  FIG. 31 is a cross-sectional view showing an eleventh step of nonvolatile semiconductor memory device 100. As shown in FIG. 31, an insulating film 3 is formed on the control gate CG, and an insulating film 4 made of an HDP film or the like is formed on the insulating film 3 by a plasma CVD method. FIG. 32 is a cross-sectional view showing a twelfth step of nonvolatile semiconductor memory device 100. As shown in FIG. 32, a resist 40 that covers memory cell region RMC and exposes connection region RC and peripheral circuit region RT to the outside is formed. Then, dry etching is performed on the insulating film 4 located in the peripheral circuit region RT and the connection region RC. Then, the nonvolatile semiconductor memory device 100 is formed through the same process as the manufacturing process of the nonvolatile semiconductor memory device 100 according to the first embodiment.

  Since the manufacturing method of such a nonvolatile semiconductor memory device 100 includes the same process as the manufacturing process of the nonvolatile semiconductor memory device 100 according to the first embodiment, the nonvolatile semiconductor memory according to the first embodiment. Actions and effects similar to those in the manufacturing process of the device 100 can be obtained.

(Embodiment 3)
With reference to FIGS. 33 and 34, still another method for manufacturing the nonvolatile semiconductor memory device 100 according to the third embodiment will be described. FIG. 33 is a cross-sectional view showing a ninth step after the eighth step of the nonvolatile semiconductor memory device 100 shown in FIG. 19, and FIG. 34 is a cross-sectional view showing the step after FIG. As shown in FIG. 33, floating gate FG and dummy floating gate FG are formed with insulating film 10 located in peripheral circuit region RT and connection region RC remaining.

  Then, the insulating film 3 is formed on the control gate CG, the gap GA is formed between the floating gates FG and between the control gates CG, and the insulating film 4 made of an HDP film or the like is further formed on the upper surface of the insulating film 3. Is formed by plasma CVD. As shown in FIG. 34, the insulating films 4 and 3 formed in the peripheral circuit region RT and the connection region RC and the insulating film 10 are etched and removed. At this time, when the insulating film 4 and the insulating film 3 are etched, a portion formed of the silicon oxide film in the insulating film 10 of the so-called ONO film is simultaneously etched. For this reason, a part of process required for removing the insulating film 10 can be omitted, and the number of processes can be reduced. Note that the manufacturing process of the nonvolatile semiconductor memory device 100 according to the third embodiment also includes the same process as the manufacturing process of the nonvolatile semiconductor memory device 100 according to the first embodiment. The same operations and effects as those of the manufacturing process of the nonvolatile semiconductor memory device 100 can be obtained.

(Embodiment 4)
A nonvolatile semiconductor memory device 400 and a method for manufacturing the same according to the fourth embodiment will be described with reference to FIGS. FIG. 35 is a cross-sectional view of the nonvolatile semiconductor memory device 400. In addition, about the structure similar to the non-volatile semiconductor memory device 100 which concerns on the said Embodiment 1, the same code is attached and the description is abbreviate | omitted. In the nonvolatile semiconductor memory device 400 according to the fourth embodiment, the insulating film 3 formed on the upper surface of the control gate CG is also formed in the connection region RC and the peripheral circuit region RT. An interlayer insulating film 34 is formed on the upper surface of the insulating film 3. A method for manufacturing the nonvolatile semiconductor memory device 400 according to the fourth embodiment will be described with reference to FIGS. The manufacturing process of the nonvolatile semiconductor memory device 400 is similar to the manufacturing process of the nonvolatile semiconductor memory device 100 according to the first embodiment up to the eighth process shown in FIG.

  FIG. 36 is a cross-sectional view showing a ninth step of the nonvolatile semiconductor memory device 400 after the step shown in FIG. In FIG. 36, a mask is formed so as to cover connection region RC and peripheral circuit region RT, control gate CG functions as a mask, conductive film 6 is etched, and floating gate FG and dummy floating gate FG are formed. Form. Then, after removing the mask covering the connection region RC and the peripheral circuit region RT, the conductive film 4 and the insulating films 18 and 12 are patterned to form the gate electrode SG and the wiring AGL. After that, the main surface of the semiconductor substrate 1 where the impurity region 53 to be formed is exposed to the outside and a mask covering the other region is formed to introduce impurities into the main surface of the semiconductor substrate 1, Impurity region 53 is formed.

  Then, an insulating film 50 is deposited, CMP is performed on the insulating film 50 to fill the insulating film 50 between the control gate CG and the floating gate FG, and a sidewall-like insulating film is formed on the side surface of the dummy control gate CGD. A film 50 is formed. At this time, the insulating film 50 is formed on the side surfaces of the wiring AGL and the insulating films 11 and 12 formed on the wiring AGL, and the insulating film 18 formed on the gate electrode SG and the gate electrode SG. , 12 are formed on the side surfaces of the sidewalls. An impurity region 53 is formed by introducing impurities into the main surface of the semiconductor substrate 1. In this way, the control transistor AGTr is formed in the peripheral circuit region RT.

  FIG. 37 is a cross-sectional view showing a tenth step of the manufacturing process of nonvolatile semiconductor memory device 400. As shown in FIG. 37, a resist 41 covering connection region RC and peripheral circuit region RT is formed. Then, in the insulating film 50 shown in FIG. 36, the insulating film 50 filled between the control gate CG and the floating gate FG is etched and removed. At this time, the insulating film 2 formed on the main surface of the semiconductor substrate 1 located between the floating gates FG is also removed, and the semiconductor substrate 1 located between the floating gates FG is exposed to the outside.

  FIG. 38 is a cross-sectional view showing an eleventh step of the manufacturing process of the nonvolatile semiconductor memory device 400. As shown in FIG. 38, the insulating film 3 is formed so as to cover the connection region RC and the peripheral circuit region RT, and the insulating film 3 is formed on the control gate CG so that the gap between the control gate CG and the floating gate FG. A gap GA is formed in Then, an interlayer insulating film 34 is deposited by plasma CVD. When the interlayer insulating film 34 is formed, the bias applied between the semiconductor substrate 1 and the electrode of the plasma CVD apparatus is set to about 0 to several watts. As described above, by reducing the bias applied between the electrode and the semiconductor substrate 1, the burying property of the interlayer insulating film 34 is deteriorated and formed between the insulating films 3 formed on the adjacent control gates CG. The interlayer insulating film 34 is prevented from entering the gap GA from the gap. For this reason, the gap GA can be satisfactorily extended from the main surface of the semiconductor substrate 1 to the upper surface of the control gate CG.

  When the interlayer insulating film 34 is formed, the control transistor AGTr and the wiring AGL are already formed, and a process of cleaning the resist formed when patterning the wiring AGL and the gate electrode SG of the control transistor AGTr, The cleaning process for removing the mask used when forming the impurity region 54 has already been completed. As described above, after the interlayer insulating film 34 is formed, the cleaning process is suppressed, and the cleaning liquid is suppressed from entering the gap GA. That is, since the necessity for providing the interlayer insulating film 34 with the function of preventing the penetration of the cleaning liquid is small, the necessity for forming the interlayer insulating film 34 densely is small. The bias applied between the electrode and the semiconductor substrate 1 can be reduced, and the interlayer insulating film 34 can be prevented from entering the gap GA.

  Although the embodiment of the present invention has been described above, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is suitable for a nonvolatile semiconductor memory device and a method for manufacturing the same.

FIG. 3 is a plan view of a main part of the flash memory according to the first embodiment. It is sectional drawing of the II-II line of FIG. It is sectional drawing of the III-III line of FIG. It is a plane sectional view slightly above the main surface of the semiconductor substrate. It is sectional drawing at the time of write-in operation | movement of a non-volatile semiconductor memory device. It is sectional drawing in the read-out operation | movement of a non-volatile semiconductor memory device. 6 is a cross-sectional view of the nonvolatile semiconductor memory device during an erasing operation. FIG. It is a top view which shows the 1st process of the manufacturing process of a non-volatile semiconductor memory device. It is a top view which shows the 2nd process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing in the XX line of FIG. It is sectional drawing which shows the 3rd process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing in the peripheral circuit area | region in a 3rd process. It is sectional drawing which shows the 4th process of the manufacturing process of a non-volatile semiconductor memory device. It is a top view in the 4th process. It is sectional drawing in the peripheral circuit area | region RT in a 4th process. It is sectional drawing which shows the 5th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 6th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 7th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 8th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 9th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing in the memory cell area | region RMC in the 10th process of the manufacturing process of a non-volatile semiconductor memory device, the connection area | region RC, and the peripheral circuit area | region RT. It is sectional drawing which shows the 11th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 12th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 13th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 14th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 15th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 16th process of the manufacturing process of a non-volatile semiconductor memory device. It is sectional drawing which shows the 17th process of the manufacturing process of a non-volatile semiconductor memory device. FIG. 29 is a cross-sectional view showing a ninth step of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment. It is sectional drawing which shows the 10th process of the manufacturing process of the non-volatile semiconductor memory device concerning Embodiment 2. FIG. FIG. 26 is a cross sectional view showing an eleventh process of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 26 is a cross sectional view showing a twelfth process of manufacturing a nonvolatile semiconductor memory device according to the second embodiment. FIG. 29 is a cross-sectional view showing a ninth step of the manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment. FIG. 34 is a cross-sectional view showing a step after the step shown in FIG. 33. FIG. 6 is a cross-sectional view of a nonvolatile semiconductor memory device according to a fourth embodiment. FIG. 29 is a cross-sectional view showing a ninth step of the manufacturing process of the nonvolatile semiconductor memory device in accordance with the fourth embodiment. FIG. 29 is a cross sectional view showing a tenth process of the manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 29 is a cross-sectional view showing an eleventh step of the manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment.

Explanation of symbols

  1A active region, 1B isolation region, 3 insulating film, 4a1, 4a2 side surface, 23a, 23b inversion layer, 34 interlayer insulating film, 100 nonvolatile semiconductor memory device, AG assist gate, CG control gate, FG floating gate, RC connection region , RMC Memory cell area, RT peripheral circuit area.

Claims (17)

A non-volatile semiconductor memory device having a memory cell region having a memory cell and a peripheral circuit region having a control transistor capable of controlling application of a voltage to the memory cell,
A semiconductor substrate;
A first floating gate and a second floating gate formed on the main surface of the semiconductor substrate via a first insulating film;
A first control gate and a second control gate formed on the first and second floating gates via a second insulating film;
A third insulating film formed on the first control gate;
A fourth insulating film formed on the second control gate and in contact with or close to the third insulating film;
A gap formed below the third insulating film and the fourth insulating film and at least between the first floating gate and the second floating gate;
Formed on the top surfaces of the third insulating film and the fourth insulating film, covers a contact portion between the third insulating film and the fourth insulating film, and ends of the first control gate and the second control gate On the side, a fifth insulating film closing the gap,
A non-volatile semiconductor memory device.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the gap is formed so as to reach between the first control gate and the second control gate. A plurality of control gates including the first and second control gates, and the fifth insulating film is formed to cover the memory cell region;
Of the surface of the fifth insulating film, a first side surface positioned in a direction orthogonal to the longitudinal direction of the control gate, and a main surface of the semiconductor substrate between the control gate and the first side surface closest to the first side surface The spacing in the parallel direction is
A direction parallel to the main surface of the semiconductor substrate of an end face of the control gate located in the longitudinal direction of the control gate and a second side face located in the longitudinal direction of the control gate among the surfaces of the fifth insulating film The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is smaller than the interval.   The thickness of the fifth insulating film located in the memory cell region in the direction perpendicular to the main surface of the semiconductor substrate is the thickness of the fifth insulating film located in the peripheral circuit region on the main surface of the semiconductor substrate. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed thicker than a thickness in a direction perpendicular to the vertical direction.   5. The nonvolatile memory according to claim 1, wherein a thickness of the fifth insulating film located in the memory cell region in a direction perpendicular to a main surface of the semiconductor substrate is 400 nm or more and 500 nm or less. Semiconductor memory device.   6. The nonvolatile semiconductor memory device according to claim 1, wherein the fifth insulating film has a higher density than the third insulating film and the fourth insulating film.   4. The nonvolatile semiconductor memory device according to claim 1, wherein an upper surface of the fifth insulating film is a flat surface extending from the memory cell region to the peripheral circuit region. 5.   8. The nonvolatile semiconductor memory device according to claim 7, wherein the fifth insulating film has a thickness in a direction perpendicular to a main surface of the semiconductor substrate of 500 nm to 600 nm. A method for manufacturing a nonvolatile semiconductor memory device, comprising: a memory cell region having a memory cell; and a peripheral circuit region having a control transistor capable of controlling application of a voltage to the memory cell,
Forming a first floating gate and a second floating gate on a main surface of a semiconductor substrate via a first insulating film;
Forming a first control gate and a second control gate on the first and second floating gates via a second insulating film;
A third insulating film is formed on the first control gate, and a fourth insulating film is formed on the second control gate, so that a gap is formed below the third insulating film and the fourth insulating film. Forming a step;
Forming a fifth insulating film so as to close the gap in the vicinity of the longitudinal ends of the first and second control gates of the first and second control gates;
A method for manufacturing a nonvolatile semiconductor memory device comprising:   The third insulating film, the fourth insulating film, and the fifth insulating film are formed by a plasma CVD (Chemical Vapor Deposition) method, and when forming the third insulating film and the fourth insulating film, the semiconductor The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein a voltage applied to the substrate is lower than a voltage applied to the semiconductor substrate when the fifth insulating film is formed.   The method of manufacturing a nonvolatile semiconductor memory device according to claim 10, further comprising a step of forming the control transistor after forming the fifth insulating film. The fifth insulating film is formed in the memory cell region and the peripheral circuit region;
Etching the fifth insulating film located in the peripheral circuit region, the peripheral circuit has a thickness in a direction perpendicular to the main surface of the semiconductor substrate of the fifth insulating film located in the memory cell region. 12. The control transistor according to claim 9, wherein the control transistor is formed by forming a thickness of the fifth insulating film located in a region in a direction perpendicular to a main surface of the semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the fifth insulating film is formed after forming the control transistor.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the control transistor is formed after removing the second insulating film located in the peripheral circuit region. Removing the fifth insulating film located in the peripheral circuit region after forming the first and second control gates;
15. The method of manufacturing a nonvolatile semiconductor memory device according to claim 14, wherein the first and second floating gates are formed after removing the fifth insulating film located in the peripheral circuit region.   Etching is performed on the third insulating film, the fourth insulating film, and the fifth insulating film located in the peripheral circuit region, and the second insulating film located in the peripheral circuit region is also removed to form the control transistor. The method of manufacturing a nonvolatile semiconductor memory device according to claim 14.   The nonvolatile semiconductor according to claim 14, wherein after forming the first and second control gates and forming the first and second floating gates, the second insulating film located in the peripheral circuit region is etched. A method for manufacturing a storage device.

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