JP2005064178A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a leak current which obviously appears when the gate length of a MONOS-type transistor is reduced can be reduced and erroneous deletion (disturbance) can be reduced, and to provide the manufacturing method of the device. <P>SOLUTION: In a non-volatile memory cell including a MONOS-type transistor Q<SB>1</SB>for memory and a MIS-type transistor Q<SB>2</SB>for cell selection, the length B of a charge accumulation film 16 is made shorter than that A of the gate electrode 20 of the MONOS-type transistor Q<SB>1</SB>. The charge accumulation film 16 is prevented from being formed below the end of the gate electrode 20. An oxide film below the end of the gate electrode 20 is made thick. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a rewritable nonvolatile semiconductor memory device and a technique effective when applied to the manufacturing technique.

  Electrically rewritable non-volatile semiconductor memory devices can be rewritten on-board, enabling product development time to be shortened and development efficiency to be improved. Applications are expanding to other tuning applications. Particularly in recent years, there is a great need for microcomputers with built-in EEPROM (Electrically Erasable Programmable Read Only Memory).

  Until now, an EEPROM using a polysilicon film as a charge storage film has been mainly used as an electrically rewritable nonvolatile semiconductor memory device.

  However, in an EEPROM using a polysilicon film as a charge storage film, if there is a defect in any part of the oxide film surrounding the polysilicon film, the charge storage film is a conductor. There is a problem that all the electrons that are sent out. In particular, it is considered that this problem will become more prominent when miniaturization progresses and the degree of integration increases.

Therefore, an MNOS (Metal Nitride Oxide Semiconductor) structure and a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure in which a silicon nitride film (Si ₃ N ₄ ) is used as a charge storage film instead of a polysilicon film are proposed. In this structure, electrons are stored in the discrete trap levels of the silicon nitride film, which is an insulator. Therefore, even if a defect occurs in some part of the charge storage film and abnormal leakage occurs, All the electrons stored in the storage film will not escape. For this reason, the reliability of data retention can be improved.

A nonvolatile semiconductor memory device using a MONOS transistor is described in, for example, Japanese Patent Laid-Open No. 06-077491 (Patent Document 1).
Japanese Patent Laid-Open No. 06-074991 (FIG. 1)

  The storage portion of the nonvolatile semiconductor memory device using the above-described MONOS transistor has a structure in which a large number of memory cells are arranged two-dimensionally. The two-dimensionally arranged memory cells are connected to each other through word lines and bit lines. In each memory cell, for example, a MONOS type transistor for memory and a MIS (Metal Insulator Semiconductor) transistor for selection for selecting the memory cell are formed.

  When a write operation, an erase operation, or a read operation is performed on such a memory cell, the memory cell selection MIS transistor is turned on to select the memory cell. Then, a target operation is performed by applying a set voltage to the source region, drain region, and gate electrode of the MONOS transistor in the selected memory cell.

  At this time, a predetermined voltage is applied to a non-selected memory cell other than the selected memory cell via a word line or a bit line. In this case, there is a problem that a leak current is generated at the pn junction in the non-selected memory cell. When such a leakage current increases, the performance and reliability of the nonvolatile semiconductor memory device are deteriorated. In particular, the leakage current at the pn junction increases as the sidewall length is reduced.

  In a non-selected memory cell in a state where data is written to the MONOS transistor (a state where electrons are stored in the charge storage film), hot holes with high energy induced by the leakage current tunnel through the gate insulating film. As a result, it is injected into the charge storage film to cause erroneous erasure (disturbance). In particular, as the sidewall length and gate length of the MONOS transistor are reduced, the above-described disturbance is likely to occur.

  An object of the present invention is to provide a semiconductor device capable of reducing a leakage current that appears remarkably when the sidewall length of a MONOS transistor is reduced.

  Another object of the present invention is to provide a semiconductor device capable of reducing the disturbance that appears remarkably when the sidewall length and gate length of the MONOS transistor are reduced.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of reducing leakage current.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of reducing disturbance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device of the present invention is a semiconductor device comprising a rewritable nonvolatile memory cell having a first field effect transistor for memory on a semiconductor substrate, wherein the first field effect transistor comprises: (a) the semiconductor A gate insulating film formed on the substrate; (b) a charge storage film formed on the gate insulating film; (c) a gate electrode formed on the charge storage film; and (d) the gate insulation. And a sidewall formed over each sidewall of the gate electrode, and in the gate length direction of the gate electrode, the length of the charge storage film is larger than the length of the gate electrode. It is characterized by being short.

  The method for manufacturing a semiconductor device of the present invention includes (a) a step of forming a first gate insulating film on a semiconductor substrate, (b) a step of forming a charge storage film on the first gate insulating film, (C) forming a first conductor film on the charge storage film; (d) patterning the first conductor film to form a first gate electrode; and (e) etching the charge storage film. Thus, a step of shortening the length of the charge storage film in the gate length direction as compared with the gate length of the first gate electrode is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The leakage current of the semiconductor device can be reduced. In addition, erroneous erasure can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  In the present embodiment, the present invention is applied to a semiconductor device including a plurality of nonvolatile memory cells including a MONOS transistor for memory and a MIS transistor for selecting a cell on a semiconductor substrate, and a manufacturing method thereof.

  The semiconductor device in this embodiment will be described with reference to the drawings. First, when a specific memory cell is selected and a write operation is performed, it will be described that a predetermined voltage (stress) is applied to a memory cell that is not selected.

Figure 1 is a circuit diagram showing a memory cell C _1-1 -C _2-4 which are arranged two-dimensionally. In Figure 1, a memory cell C _1-1 is composed of a MIS transistor Tr2a for MONOS type transistors Tr1a and cell selection for memory. Similarly, each of the memory cells _C1-2 to _C2-4 includes a MONOS transistor Tr1b to Tr1h for memory and a MIS transistor Tr2b to Tr2h for cell selection.

In the memory cell C _1-1 -C _1-4 arranged in the same row, the gate electrode of each of the MONOS transistor Tr1a~Tr1d are connected by one signal line (word line) WL2, MIS-type transistor The gate electrodes of Tr2a to Tr2d are also connected by a single signal line (word line) WL1. Similarly, in the memory cells C _{2-1 to} C _2-4 arranged in the same row, the gate electrodes of the MONOS transistors Tr1e to Tr1h are also connected by one signal line WL4, and the MIS transistors Tr2e to Tr2e are connected. The gate electrode of Tr2h is also connected by one signal line WL3.

Then, in the memory cell C _1-1 and the memory cell C _2-1 arranged in the same column, each of the source regions is connected by one signal line SL1 mutually, respective drain region to each other one The signal lines DL1 are connected. Similarly, the memory cells C _1-2 and the memory cell C _2-2 arranged in the same column are connected to the source region of each other by a signal line SL2, the signal line DL2 to each other of the drain region is connected ing. Further, in the memory cell C _1-3 and the memory cell C _2-3, by a signal line SL3 is connected the source region of one another, are connected to each other in the drain region by a signal line DL3, the memory cell C _1-4 And the memory cell C _2-4 have their source regions connected by a signal line SL4 and their drain regions connected by a signal line DL4.

The memory cell C _1-1 , the memory cell C _1-2 , the memory cell C _2-1 and the memory cell C _2-2 are formed on the same well, and a voltage is applied to the well by the signal line K1. It is to be applied. Further, the memory cell C _1-3 , the memory cell C _1-4 , the memory cell C _2-3, and the memory cell C _2-4 are formed on the same well, and the well is connected to the well by the signal line K2. A voltage is applied.

In such a memory cell C _1-1 -C _2-4 constructed in, with reference to FIG. 1 will be described an example of the case where by selecting the memory cell C _1-1 performs a write operation. As shown in FIG. 1, for selecting a memory cell C _1-1, applies a 1.5V to signal line WL1. Further, 1.5 V is applied to the signal line WL2, and -10.5 V is applied to the signal lines SL1, DL1, and K1. Then, a potential difference of 12.0 V is generated between the source region and the gate electrode of the MONOS transistor Tr1a in the memory cell C _1-1 (selected cell) with the gate electrode side being positive. When such a high potential difference occurs, electrons in the source region are injected into the charge storage film through the gate insulating film of the MONOS transistor Tr1a, and a write operation is performed. At this time, other memory cells C _1-2 which is connected to the signal line WL1, C _1-3, signal lines to the source and drain regions of the C _1-4 (non-selected cells not written) SL2～ A predetermined voltage is applied via SL4 and the signal line DL2, but the potential difference between the source region (or drain region) and the signal line WL1 is caused by the source region (or drain region) in the memory cell _C1-1 in which writing is performed. ) And the signal line WL1.

Further, the memory cell C _2-3, looking at the C _2-4, the signal line WL3 are applied 0V, it can be seen that the memory cell C _2-3, is C _2-4 a non-selected memory cells . However, the memory cells C _2-3, MONOS type transistor Tr1g in C _2-4, to the source region of Tr1h, the signal line SL3 and the signal line SL4 1.5V is applied to the well, the signal line K2 -10.5V is applied. Therefore, it can be seen that a potential difference of 12.0 V is generated at the pn junction between the source region and the well. Further, a voltage of −10.5 V is applied to the gate electrodes of the MONOS transistors Tr1g and Tr1h through the signal line WL4. For this reason, a potential difference of 12.0 V is generated between the gate electrode and the source region. Accordingly, in the memory cells C _2-3 and C _2-4 , a leak current is likely to occur between the source region and the well, and hot holes induced by the leak current are injected into the charge storage film in which electrons are stored. It can be seen that erroneous erasure may occur.

Next, an example of performing the erase operation by selecting the memory cell _C1-1 will be described with reference to FIG. As shown in FIG. 2, for selecting a memory cell C _1-1, applies a 1.5V to signal line WL1. Further, −8.5V is applied to the signal line WL2, and 1.5V is applied to the signal lines SL1 and K1. At this time, the signal line DL1 is brought into a floating state. Then, the potential difference positively MONOS transistor Tr1a well in the memory cell C _1-1 (source region) of the well (source region) side between the gate electrode 10.0V occurs. Therefore, when writing is performed in the MONOS transistor Tr1a, that is, when electrons are stored in the charge storage film, electrons in the charge storage film are tunneled through the gate insulating film and injected into the well side, and erased. Operation is performed.

It can be seen that a predetermined voltage (stress) is applied to the non-selected memory cell even when this erase operation is performed. However, the stress occurs in the memory cells C _2-3 and C _2-4 during the write operation. You can see that they are not.

Next, an example in which the memory cell _C1-1 is selected and the reading operation is performed will be described with reference to FIG. As shown in FIG. 3, a voltage of 2.0 V is applied to the signal line WL1. Further, 0 V is applied to the signal lines WL2, SL1, and K1, and 1.5 V is applied to the signal line DL1. Here, writing is performed in the MONOS type transistors Tr1a in the memory cell C _1-1, if the electrons into the charge storage film is accumulated, the threshold voltage of the MONOS transistor Tr1a is higher than 0V. For this reason, no current flows between the source region and the drain region of the memory cell _C1-1 . On the other hand, when writing is not performed in the MONOS transistor Tr1a (when electrons are not stored in the charge storage film), a current flows when 0 V is applied to the gate electrode. In this way, a reading operation can be performed.

Even when the read operation is performed, a predetermined voltage is applied to the non-selected memory cells, but it can be seen that the stress is not generated as much as the memory cells C _2-3 and C _2-4 during the write operation.

  As described above, when a specific memory cell is selected and a target operation is performed, it is understood that a predetermined voltage (stress) is applied to an unselected memory cell that is not selected. In particular, it can be seen that during a write operation, the stress applied to a predetermined unselected memory cell increases, and problems such as leakage current and erroneous erasure are likely to occur.

  Next, it is verified that as the sidewall length is reduced, the leakage current of the pn junction generated in the non-selected memory cell increases, and erroneous erasure (disturbance) of the non-selected memory cell to which data has been written is likely to occur. I tried. That is, in the non-selected memory cell of the nonvolatile memory cell having a relatively long sidewall length formed by the 0.35 μm process, the leakage current and the erroneous erasure that were not a problem were formed by the 0.18 μm process. In a non-selected memory cell of a nonvolatile memory cell having a relatively short side wall length, the reason why it becomes a problem was verified using simulation.

  FIG. 4 shows a result obtained by simulation of a leak current path (leak path) generated in a MONOS transistor having a long sidewall length and a region where the impact ionization phenomenon occurs most. In FIG. 4, the horizontal axis indicates the horizontal dimension, and the unit is μm. The vertical axis indicates the vertical dimension, and its unit is μm.

  The simulation was performed with the structure shown below. That is, as shown in FIG. 4, a gate insulating film, a charge storage film, an insulating film, and a gate electrode are stacked in order from the bottom on the well, and the side walls are formed over the side walls of the gate insulating film, the charge storage film, the insulating film, and the gate electrode. Form. And it was carried out with the structure which formed the source region under this side wall. In the structure shown in FIG. 4, the gate insulating film, the charge storage film, the insulating film, and the gate electrode are cut halfway.

  As can be seen from FIG. 4, in the MONOS transistor having a long sidewall length, the leakage current flows under the source region (so-called diffusion layer). For this reason, it can be seen that impact ionization in which electrons and holes are generated when electrons collide with the crystal lattice is most generated under the source region.

  On the other hand, FIG. 5 shows the result of simulating the path of the leakage current generated in the MONOS transistor having a short sidewall length and the region where the impact ionization phenomenon occurs most.

  As shown in FIG. 5, unlike the MONOS transistor having a long sidewall length, the leakage current flows near the surface of the semiconductor substrate. It can also be seen that impact ionization occurs most under the edge of the gate electrode where leakage current flows.

  FIG. 6 shows the electric field distribution of the MONOS transistor with a short sidewall length shown in FIG. That is, the electric field distribution is shown when a predetermined potential difference (stress) is generated between the gate electrode, the source region, the well, and the like of the MONOS transistor. Note that the unit of the electric field shown here is MV / cm.

  Referring to FIG. 6, it can be seen that the equal electric field lines are dense under the edge of the gate electrode, and the electric field is higher than the surrounding area. That is, it can be seen that electric field concentration occurs under the edge of the gate electrode. From this, it can be seen that the leakage current of the MONOS transistor having a short sidewall length flows in the region near the surface in the semiconductor substrate and below the end of the gate electrode where electric field concentration occurs.

  Here, electric field concentration occurs below the end of the gate electrode. For this reason, when a leak current flows under the end of the gate electrode, the amount of the leak current is considered to increase.

  Further, as shown in FIG. 5, the occurrence of the impact ionization phenomenon is maximum under the end portion of the gate electrode. For this reason, holes are easily generated by impact ionization under the end of the gate electrode. Some of the generated holes have high energy, which is called a hot hole.

  Some of these hot holes are injected into the charge storage film through the gate insulating film of the MONOS transistor. When writing is performed in the MONOS transistor, electrons are accumulated in the charge storage film. However, when hot holes are injected, the electrons accumulated in the charge storage film are lost. Erroneous erasure occurs. In particular, in this case, since the hot hole is generated in the semiconductor substrate below the end of the gate electrode and in the vicinity of the charge storage film, erroneous erasure occurs due to hot holes being injected into the charge storage film. It has become easier.

  As described above, in the MONOS transistor having a long sidewall length, a leakage current flows under the source region. Also, impact ionization phenomenon occurs most under the source region. Therefore, even if hot holes are generated by impact ionization, the distance from the charge storage film in which electrons are stored is far away, so that erroneous erasure due to hot hole injection is unlikely to occur.

  On the other hand, in the MONOS transistor having a short sidewall length, the leakage current flows through the place where the electric field concentration is occurring under the end of the gate electrode, and thus the amount of leakage current increases.

  Also, hot holes are likely to occur below the edge of the gate electrode near the charge storage film, and erroneous erasure due to injection of hot holes into the charge storage film is likely to occur.

  From these examination results, it can be seen that an increase in leakage current and erroneous erasure are problematic in a MONOS transistor having a short sidewall length.

  Next, the configuration of the nonvolatile memory cell in this embodiment will be described. FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory cell in the present embodiment. In FIG. 7, an element isolation region 11 is formed on a semiconductor substrate 10.

  An n-type well 13 is formed inside the semiconductor substrate 10, and a p-type well 14 is formed in the n-type well 13.

A non-volatile memory cell is formed in the memory cell forming region sandwiched between the element isolation regions 11 on the p-type well 14, and this non-volatile memory cell includes the MONOS transistor Q ₁ and the MIS. A type transistor Q ₂ is used. The MONOS transistor Q ₁ is a memory (memory) transistor that stores 1 bit, and the MIS transistor Q ₂ is a selection transistor for selecting each nonvolatile memory cell.

Next, the configurations of the MONOS transistor Q ₁ and the MIS transistor Q ₂ shown in FIG. 7 will be described.

First, the MONOS transistor Q ₁ has a configuration as shown below. That is, a gate insulating film (first gate insulating film) 15 is formed on a p-type well 14 formed in the semiconductor substrate 10, and a charge storage film 16 is formed on the gate insulating film 15. An insulating film 17 is formed on the charge storage film 16, and a gate electrode (first gate electrode) 20 made of a conductor film is formed on the insulating film 17.

  The gate electrode 20 has a laminated structure in which, for example, a cobalt silicide film 30 is formed as a silicide film on the polysilicon film 18 in order to reduce resistance. The silicide film is not limited to the cobalt silicide film 30 described above. For example, the silicide film may be formed of a titanium silicide film or a nickel silicide film instead of the cobalt silicide film 30.

  Subsequently, a sidewall 26a (first sidewall) made of an insulating film is formed across the sidewall of the gate electrode 20, the sidewall of the insulating film 17, the sidewall of the charge storage film 16, and the sidewall of the gate insulating film 15. The sidewall 26a is formed in order to make the MONOS transistor have an LDD (Lightly Doped Drain) structure.

  Low-concentration n-type impurity diffusion regions (extension regions) (impurity diffusion regions) 23 and 24 are formed in the p-type well 14 below the side wall 26a. The low-concentration n-type impurity diffusion regions 23 and 24 are The side wall 26a is formed so as to extend outward from below. The low-concentration n-type impurity diffusion regions 23 and 24 extend to the lower part of the gate electrode 20.

  High concentration n type impurity diffusion regions (diffusion layers) (impurity regions) 27 and 28 are formed in the low concentration n type impurity diffusion regions 23 and 24 outside the sidewall 26a. On the n-type impurity diffusion regions 27 and 28, for example, a cobalt silicide film 30 is formed as a silicide film for reducing the resistance.

  Compared with the low-concentration n-type impurity diffusion regions 23 and 24, the high-concentration n-type impurity diffusion regions 27 and 28 are doped with an n-type impurity such as phosphorus or arsenic at a high concentration. The diffusion region 23 and the high-concentration n-type impurity diffusion region 27 (including the cobalt silicide film 30) form a source region that is a semiconductor region of the MONOS transistor. Similarly, the low concentration n-type impurity diffusion region 24 and the high concentration n-type impurity diffusion region 28 form a drain region which is a semiconductor region of the MONOS transistor.

The gate insulating film 15 is formed of, for example, a silicon oxide film, and has a function as a tunnel insulating film in addition to a function as a gate insulating film. For example, the MONOS transistor Q ₁ injects electrons from the semiconductor substrate 10 through the gate insulating film 15 into the charge storage film 16 or stores electrons stored in the charge storage film 16 through the gate insulating film 15 into the semiconductor substrate. Data is stored or erased. Therefore, it can be seen that the gate insulating film 15 has a function as a tunnel insulating film for tunneling electrons.

  The charge storage film 16 is a film provided for storing charges contributing to data storage, and is formed of, for example, a silicon nitride film.

  Conventionally, a polysilicon film has been mainly used as the charge storage film 16, but when a polysilicon film is used as the charge storage film 16, if some part of the oxide film surrounding the charge storage film 16 is defective. Since the charge storage film 16 is a conductor, all charges accumulated in the charge storage film 16 may be lost due to abnormal leakage.

  Therefore, as described above, a silicon nitride film that is an insulator is used as the charge storage film 16. In this case, charges that contribute to data storage are accumulated in discrete trap levels (capture levels) existing in the silicon nitride film. Therefore, even if a defect occurs in a part of the oxide film surrounding the charge storage film 16, since charges are stored in discrete trap levels of the charge storage film 16, all charges are transferred from the charge storage film 16. There is no escape. For this reason, the reliability of data retention can be improved.

  For this reason, not only the silicon nitride film but also a film including discrete trap levels can be used as the charge storage film 16 to improve data retention reliability.

The following describes the shape of the MONOS transistor Q _1. MONOS-type transistor Q ₁ as described above is adapted to the gate insulating film 15 in this order from the bottom, were laminated charge storage film 16, insulating film 17 and the gate electrode 20 structure.

  Conventionally, in the MONOS transistor having such a stacked structure, the lengths of the stacked films are approximately equal in the gate length direction of the gate electrode. That is, the length of the gate insulating film, the length of the charge storage film, the length of the insulating film, and the length of the gate electrode in the gate length direction were substantially equal to each other.

On the other hand, in the MONOS transistor Q ₁ in this embodiment, as shown in FIG. 7, the length of the gate electrode 20 is different from that of other films, particularly the charge storage film 16, in the gate length direction. . That is, as shown in FIG. 7, the length B of the charge storage film 16 is shorter than the length A of the gate electrode 20 in the gate length direction. Further, the charge storage film 16 is configured not to be formed under both end portions of the gate electrode 20.

  Here, the difference A−B between the length A of the gate electrode 20 and the length B of the charge storage film 16 is 60 nm, for example, and the digging amount (A−B) / 2 under the gate electrode 20 is, for example, 30 nm.

As described above, in the MONOS transistor Q ₁ in this embodiment, the gate insulating film 15, the charge storage film 16, and the insulating film 17 that are short in the gate length direction are stacked in this order from the bottom, and on the insulating film 17. The gate electrode 20 having a long length in the gate length direction is formed, and the charge storage film 16 is not formed under both ends of the gate electrode 20. Therefore, the MONOS transistor of the present embodiment has a mushroom shape when only the gate insulating film 15, the charge storage film 16, the insulating film 17, and the gate electrode 20 are viewed. Therefore, for example, the distance between the end of the high-concentration n-type impurity diffusion region (impurity region) 27 in the gate length direction and the end of the charge storage film 16 is the end of the high-concentration n-type impurity diffusion region 27 in the gate length direction. This is longer than the distance from the end of the gate electrode 20 to the end of the gate electrode 20.

Further, in the MONOS transistor Q ₁ of the present embodiment, the lower ends of the gate electrode 20 are not substantially right-angled, but are gently chamfered as shown in FIG. It has a rounding shape that is formed by a simple curve. That is, an insulating film that is a part of the side wall 26a is formed under the end of the gate electrode 20. The insulating film has the same thickness as that of the gate insulating film 15, the charge storage film 16, and the insulating film 17. It is thicker than the film thickness. That is, since the bottom surface of the gate electrode 20 is rounded (bent) away from the semiconductor substrate 10, the distance from the end of the bottom surface to the semiconductor substrate 10 is larger than the distance from the center portion of the bottom surface to the semiconductor substrate 10. It has a structure that increases the distance.

Next, the configuration of the MIS transistor Q ₂ will be described. As shown in FIG. 7, the MIS transistor Q ₂ has a configuration as shown below. That is, a gate insulating film (second gate insulating film) 21 is formed on the p-type well 14 formed in the semiconductor substrate 10, and a gate electrode (second gate electrode) 22 is formed on the gate insulating film 21. Is formed.

The gate electrode 22 has a laminated structure in which, for example, a cobalt silicide film 30 is formed as a silicide film on the polysilicon film 22a in order to reduce the resistance. The gate electrode 22 is formed on the sidewalls of the gate electrode 22 and the gate insulating film 21. The side wall 26b is formed. In the MIS transistor Q ₂ , as in the MONOS transistor Q ₁ , the silicide film is not limited to the cobalt silicide film 30, and a titanium silicide film or a nickel silicide film may be used.

  Low-concentration n-type impurity diffusion regions 24 and 25 are formed in the p-type well 14 below the sidewall 26b, and the low-concentration n-type impurity diffusion regions 24 and 25 extend outward from below the sidewall 26b. It is formed to do.

  High-concentration n-type impurity diffusion regions 28 and 29 are formed in the low-concentration n-type impurity diffusion regions 24 and 25 outside the side wall 26b, and the high-concentration n-type impurity diffusion regions 28 and 29 are formed on the high-concentration n-type impurity diffusion regions 28 and 29. For example, a cobalt silicide film 30 is formed as a silicide film for reducing the resistance. This silicide film may also be a titanium silicide film or a nickel silicide film.

The source region of the MIS transistor Q ₂ is formed by the low-concentration n-type impurity diffusion region 24 and the high-concentration n-type impurity diffusion region 28 (including the cobalt silicide film 30). The drain region of the MIS transistor Q ₂ is formed by the n-type impurity diffusion region 29 (including the cobalt silicide film 30). Here, the low-concentration n-type impurity diffusion region 24 and the high-concentration n-type impurity diffusion region 28 are also the drain regions of the MONOS transistor Q ₁ described above. That is, as can be seen from FIG. 7, the low-concentration n-type impurity diffusion region 24 and the high-concentration n-type impurity diffusion region 28 are regions that electrically connect the MONOS transistor Q ₁ and the MIS transistor Q _2. .

In the MONOS transistor Q ₁ , the gate insulating film 15, the charge storage film 16, and the insulating film 17 are shorter in the gate length direction than the gate length of the gate electrode 20 as described above. On the other hand, in the MIS transistor Q ₂ , the gate length of the gate electrode 22 is substantially equal to the length of the gate insulating film 21 in the gate length direction. Accordingly, in the gate length direction, the length of the gate insulating film 15 of the MONOS transistor Q ₁ is shorter than that of the gate insulating film 21 of the MIS transistor Q ₂ . In addition, at the lower end of the gate electrode 20 of the MONOS transistor Q _1, the length of the gate insulating film 15, the charge storage film 16 and the insulating film 17 in the gate length direction is shorter than the gate length of the gate electrode 20. The side wall 26a is formed so as to be buried as much as the gap. Therefore, side wall width of the side wall 26a is longer than the side wall width of the MIS-type transistor Q ₂ sidewall 26b.

The MONOS transistor Q ₁ and the MIS transistor Q ₂ in the present embodiment are configured as described above. Next, according to the MONOS transistor Q ₁ of the present embodiment, the MONOS transistor Q ₁ and the MIS transistor Q ₂ are arranged under the end of the gate electrode 20. The fact that the electric field can be relaxed will be described.

First, the non-volatile memory cell including the MONOS transistor Q ₁ having a short sidewall length is a non-selected memory cell. The gate electrode 20 and the source region (low-concentration n-type impurity diffusion region) of the MONOS transistor Q ₁ shown in FIG. FIG. 8 shows the result of simulating the electric field distribution when a predetermined potential difference (stress) is generated between the high-concentration n-type impurity diffusion region 27), the p-type well 14, and the like.

  In FIG. 8, a charge storage film is not formed under the end of the gate electrode, but is dug, and a part of the side wall is formed in this dug. Looking at the electric field distribution when stress is applied under such conditions, it can be seen that the electric field concentration under the edge of the gate electrode is relaxed compared to the case shown in FIG.

  FIG. 6 shows the result of simulating the electric field distribution when a stress is applied to a MONOS transistor having a short sidewall length and having a normal gate electrode shape. is there. As can be seen from FIG. 6, the isoelectric lines are dense under the end of the gate electrode, and the maximum value of the electric field is 0.9 MV / cm. For this reason, it can be seen that electric field concentration occurs under the edge of the gate electrode.

On the other hand, as shown in FIG. 8, when simulating the MONOS transistor Q ₁ of the present embodiment, the isoelectric field below the end of the gate electrode is not dense compared to FIG. The maximum value is also 0.6 MV / cm, which is lower than 0.9 MV / cm. Therefore, according to the MONOS transistor Q ₁ of the present embodiment, it can be seen that electric field concentration under the end of the gate electrode can be prevented. That is, the length of the charge storage film is shorter than the length of the gate electrode in the gate length direction, the charge storage film is not formed under the end of the gate electrode, and the silicon oxide film is thickened under the end of the gate electrode. By doing so, the electric field concentration under the edge of the gate electrode can be reduced.

Next, the reason why the electric field concentration under the end of the gate electrode can be relaxed will be described. First, as shown in FIG. 7, in the MONOS transistor Q ₁ in the present embodiment, the length B of the charge storage film 16 is shorter than the length A of the gate electrode 20 in the gate length direction. . The charge storage film 16 is not formed under the end portion of the gate electrode 20 and is dug. The side wall 26a is buried so as to bury the dug portion. Part of is formed. In other words, the length of the side walls 26a MONOS-type transistor Q ₁ is are formed to be longer than the length of the sidewall 26b MIS transistor Q _2.

  By forming the charge storage film 16 to be shorter than the gate electrode 20 in this manner, the distance from the high concentration n-type impurity diffusion region 27 that is the source region is increased. Thus, the probability of hot hole injection can be reduced, and erroneous erasure of memory cells can be made difficult to occur.

Here, the charge storage film 16 is formed of, for example, a silicon nitride film, and the sidewalls 26a are formed of, for example, a silicon oxide film. Therefore, a silicon oxide film is formed under the end of the gate electrode 20 instead of the silicon nitride film. Since the dielectric constant of the silicon oxide film is lower than that of the silicon nitride film, it is formed in the semiconductor substrate 10 below the end of the gate electrode 20 when a predetermined voltage is applied to the gate electrode 20. The electric field is relaxed as compared with the case where the silicon nitride film is present under the end of the gate electrode 20. That is, the electric field can be reduced in the MONOS transistor Q ₁ in this embodiment as compared with the conventional MONOS transistor in which the silicon nitride film is formed under the end of the gate electrode. In the above description, the sidewall 26a is formed of a silicon oxide film and the charge storage film 16 is formed of a silicon nitride film. However, as a material constituting the sidewall 26a, the dielectric constant of the material constituting the charge storage film 16 is used. By using a material having a low dielectric constant, the electric field generated under the end of the gate electrode 20 can be relaxed.

In the state where writing is performed in the MONOS transistor Q ₁ , electrons are stored in the charge storage film 16. In this case, the MONOS transistor Q ₁ is in the same state as when a negative bias is applied, and the electric field in the semiconductor substrate 10 under the gate electrode 20 increases. However, according to the MONOS transistor Q ₁ in the present embodiment, the charge storage film 16 is not formed under the end of the gate electrode 20. Accordingly, electrons are not accumulated below the end portion of the gate electrode 20, so that the electric field in the semiconductor substrate 10 below the end portion of the gate electrode 20 can be relaxed.

Furthermore, in the MONOS transistor Q ₁ in the present embodiment, the lower ends of the gate electrode 20 are not substantially right-angled, but are gently chamfered as shown in FIG. It has a rounding shape that is formed by a simple curve. That is, the silicon oxide film is thick under the end of the gate electrode 20. Therefore, the distance between the semiconductor substrate 10 and the gate electrode 20 can be increased under the end of the gate electrode 20 as compared with a conventional MONOS transistor having a substantially right-angle shape. For this reason, the electric field in the semiconductor substrate 10 under the end of the gate electrode 20 can be relaxed.

Next, FIG. 9 shows the result of simulating the path of the leakage current flowing through the MONOS transistor Q ₁ and the region where impact ionization occurs most in the present embodiment.

As can be seen from FIG. 9, the leakage current does not flow near the surface of the semiconductor substrate below the edge of the gate electrode, but the leakage current flows in a region inside the semiconductor substrate far from the edge of the gate electrode. That is, as shown in FIG. 5, in the case of a conventional MONOS transistor having a short sidewall length and a normal gate electrode shape, the leakage current is below the end of the gate electrode. Near the surface of the semiconductor substrate. On the other hand, like the MONOS transistor Q ₁ in the present embodiment, the length of the charge storage film is made shorter than the length of the gate electrode in the gate length direction, and the charge storage film is formed below the end of the gate electrode. It can be seen that when the silicon oxide film is formed under the shape of the gate electrode and the thickness of the silicon oxide film is increased under the end of the gate electrode, the leakage current flows in a region inside the semiconductor substrate away from the bottom of the end of the gate electrode. As described above, the leakage current flows through the region inside the semiconductor substrate far from the bottom of the end of the gate electrode, as shown in FIG. 8, because the electric field concentration under the end of the gate electrode is relaxed. That is, since the electric field concentration under the edge of the gate electrode is relaxed, the leakage current hardly flows under the edge of the gate electrode, and the leakage current flows through a region inside the semiconductor substrate away from the edge of the gate electrode. It is.

Here, in the MONOS transistor Q ₁ of this embodiment, the electric field distribution (see FIGS. 8 and 9) in the vicinity of the pn junction through which the leak current flows is below the end of the gate electrode through which the leak current of the conventional MONOS transistor flows. Compared with the electric field distribution in the vicinity (see FIGS. 5 and 6), no electric field concentration occurs. Therefore, it can be seen that the amount of leakage current in the MONOS transistor Q ₁ of the present embodiment is smaller than the amount of leakage current of the conventional MONOS transistor shown in FIG.

Further, as shown in FIG. 9, it can be seen that the region where impact ionization occurs most is also inside the semiconductor substrate far from the end of the gate electrode, as compared with FIG. Therefore, according to the MONOS transistor Q ₁ of the present embodiment, the region where impact ionization occurs most can be separated from the bottom of the end of the gate electrode, so that hot holes generated by impact ionization tunnel the gate insulating film. Thus, injection into the charge storage film can be reduced. That is, erroneous erasure (disturbance) due to injection of hot holes into the charge storage film can be reduced.

In other words, in the MONOS transistor Q ₁ of the present embodiment, since the region under the end of the gate electrode is not the region where impact ionization occurs most, the generation of hot holes under the end of the gate electrode can be reduced. Erroneous erasure due to injection of holes into the charge storage film can be reduced.

In addition, according to the MONOS transistor Q ₁ of the present embodiment, since the charge storage film is not formed under the end of the gate electrode, the distance between the charge storage film and the region where impact ionization occurs most is set. Can be further separated. Therefore, erroneous erasure due to injection of hot holes into the charge storage film can be further reduced.

Next, a method for manufacturing a nonvolatile memory cell including the MONOS transistor Q ₁ of this embodiment will be described with reference to the drawings.

  First, as shown in FIG. 10, for example, a semiconductor substrate 10 in which a p-type impurity such as boron (B) is introduced into single crystal silicon is prepared. Next, the element isolation region 11 is formed on the main surface of the semiconductor substrate 10. The element isolation region 11 is made of, for example, a silicon oxide film, and is formed by an STI (Shallow Trench Isolation) method, a LOCOS (Local Oxidization Of Silicon) method, or the like. FIG. 10 shows the element isolation region 11 formed by the STI method in which a groove is formed in the semiconductor substrate 10 and a silicon oxide film is embedded in the formed groove.

  Next, after forming a silicon oxide film 12 on the main surface of the semiconductor substrate 10, an n-type well 13 is formed in the semiconductor substrate 10. The n-type well 13 is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 10 using a photolithography technique and an ion implantation method.

  Subsequently, a p-type well 14 is formed in the n-type well 13. The p-type well 14 is formed by introducing a p-type impurity into the semiconductor substrate 10 using a photolithography technique and an ion implantation method. Examples of the p-type impurity include boron and boron fluoride.

Next, after the silicon oxide film 12 formed on the semiconductor substrate 10 is removed, a gate insulating film (first gate insulating film) 15 is formed on the main surface of the semiconductor substrate 10 as shown in FIG. The gate insulating film 15 is made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. Then, a charge storage film 16 is formed on the gate insulating film 15. The charge storage film 16 is made of, for example, a silicon nitride film, and can be formed using a CVD (Chemical Vapor Deposition) method in which silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) are chemically reacted. Although an example in which a silicon nitride film is used as the charge storage film 16 is shown, the present invention is not limited to this, and a film including a trap level in a film such as a silicon oxynitride (SiON) film may be used.

Subsequently, an insulating film 17 is formed on the charge storage film 16. The insulating film 17 is made of, for example, a silicon oxide film, and can be formed by a CVD method in which silane gas and oxygen gas (O ₂ ) are chemically reacted. Note that when the MNOS transistor is formed, the insulating film 17 is not formed.

Next, a polysilicon film (first conductor film) 18 is formed on the insulating film 17. The polysilicon film 18 can be formed by, for example, a CVD method in which silane gas is thermally decomposed in nitrogen gas (N ₂ ). When the polysilicon film 18 is grown, a conductivity type impurity such as phosphorus is added. It should be noted that a conductivity type impurity such as phosphorus may be implanted into the polysilicon film 18 by using an ion implantation method after the polysilicon film 18 has been formed, not during the growth of the polysilicon film 18.

  Thereafter, a cap insulating film 19 is formed on the polysilicon film 18. The cap insulating film 19 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method. The cap insulating film 19 has a function of protecting the gate electrode 20 formed in a process described later.

  Subsequently, after applying a resist film on the cap insulating film 19, the resist film is patterned by exposing and developing the resist film. The patterning is performed so that the resist film remains in the region where the gate electrode 20 is to be formed. Then, a gate electrode (first gate electrode) 20 is formed by etching using the patterned resist film as a mask, as shown in FIG.

  Next, as shown in FIG. 13, light oxidation is performed to oxidize the side surface of the gate electrode 20 to form a silicon oxide film 20a. By performing this light oxidation longer than usual, the silicon oxide film 20a is formed inside the lower end portion of the gate electrode 20 so as to form a so-called bird's beak. By forming bird's beaks in this way, the edge of the gate electrode 20 can be rounded away from the semiconductor substrate 10 by etching a silicon oxide film 20a described later. For this reason, the distance between the end portion of the gate electrode 20 and the source region or the drain region formed in the semiconductor substrate 10 in a process described later can be increased. Therefore, the electric field concentration under the end of the gate electrode 20 can be reduced.

  Subsequently, as shown in FIG. 14, wet etching is performed to sequentially remove the silicon nitride film and the silicon oxide film. That is, the charge storage film (silicon nitride film) 16 formed at a place other than under the gate electrode 20 is removed, and then the cap insulating film 19 and the silicon oxide film 20a covering the gate electrode 20 and other than under the gate electrode 20 are removed. The gate insulating film 15 formed at the place is removed.

  Here, for example, a hot phosphoric acid solution is used to remove the charge storage film 16 made of the silicon nitride film, and the etching time with this hot phosphoric acid solution is longer than usual. In this way, by taking a long etching time, not only the charge storage film 16 formed in a region other than under the gate electrode 20 but also a part of the charge storage film 16 under the gate electrode 20 is dug and removed. be able to. For example, by setting the etching time with the hot phosphoric acid solution from 9 minutes to 18 minutes, the charge storage film 16 can be retracted by about 30 nm (0.03 μm) from both ends of the gate electrode 20.

  As described above, a structure in which the charge storage film 16 is shorter than the gate length of the gate electrode 20 and the charge storage film 16 is not formed under both ends of the gate electrode 20 can be formed.

  Further, by etching the silicon oxide film 20, the end portion of the gate electrode 20 has a gentle shape as if chamfered. That is, as described above, by removing the bird's beak formed by performing the light oxidation for a long time, the bottom shape of the gate electrode 20 is made to be less than the distance from the center of the bottom surface to the semiconductor substrate 10. The distance from the end portion to the semiconductor substrate 10 can be increased, and the end portion of the gate electrode 20 can be separated from the semiconductor substrate 10. Therefore, the electric field concentration under the end of the gate electrode 20 can be relaxed.

  Next, a gate insulating film (second gate insulating film) 21 is formed on the main surface of the semiconductor substrate 10. The gate insulating film 21 is made of, for example, a silicon oxide film, and can be formed by, for example, a thermal oxidation method. In addition, although the example which uses a silicon oxide film was shown as the gate insulating film 21, it is not restricted to this, For example, you may use the material (what is called a High-k film | membrane) whose dielectric constant is higher than a silicon oxide. For example, a film made of aluminum oxide, hafnium oxide, zirconium oxide, or the like may be used.

  Subsequently, a polysilicon film (second conductor film) is formed on the gate insulating film 21. The polysilicon film can be formed by, for example, a CVD method. Then, using a photolithography technique and an etching technique, a gate electrode (second gate electrode) 22 is formed as shown in FIG. 15, and the gate insulating film 21 is left only under the gate electrode 22.

  Next, as shown in FIG. 16, low-concentration n-type impurity diffusion regions (impurity diffusion regions) 23, 24, and 25 that are semiconductor regions are formed in the p-type well 14 by using a photolithography technique and an ion implantation method. Form. The low-concentration n-type impurity diffusion regions 23, 24, 25 are formed by introducing an n-type impurity such as phosphorus or arsenic into the p-type well 14 and then performing a heat treatment for activating the introduced n-type impurity. can do.

Subsequently, a silicon oxide film is formed on the main surface of the semiconductor substrate 10 by using, for example, a CVD method. Then, the formed silicon oxide film is anisotropically etched to form a sidewall (first sidewall) 26 a on the sidewall of the gate electrode 20, and a sidewall (second sidewall) 26 b on the sidewall of the gate electrode 22. Form. More specifically, the sidewall 26a is formed over the side walls of the gate insulating film 15, the charge storage film 16, the insulating film 17, and the gate electrode 20, and is formed so as to bury the dug portion below the end of the gate electrode 20. Has been. Further, the sidewall 26 b is formed over the sidewalls of the gate insulating film 21 and the gate electrode 22. That is, the length of the side walls 26a MONOS-type transistor Q _1, it is formed to be longer than the length of the MIS transistor Q ₂ sidewall 26b. Also, at the end of the gate electrode 20 of the MONOS type transistor Q _1, is formed as a silicon oxide film having a low dielectric constant is thicker than the silicon nitride film. In other words, the silicon nitride film is not formed at the end of the gate electrode 20 and the end of the gate electrode 20 has a rounded shape, so that the silicon oxide film at the end of the gate electrode 20 is thick. It has become.

  Thereafter, high-concentration n-type impurity diffusion regions 27, 28, and 29, which are semiconductor regions, are formed using a photolithography technique and an ion implantation method. In the high-concentration n-type impurity diffusion regions 27, 28 and 29, n-type impurities are introduced at a higher concentration than in the low-concentration n-type impurity diffusion regions 23, 24 and 25.

  Next, as shown in FIG. 7, for example, a cobalt film is formed on the main surface of the semiconductor substrate 10 as a refractory metal film. The cobalt film can be formed using, for example, a sputtering method or a CVD method. Thereafter, a cobalt silicide film 30 is formed by heat treatment. Then, the unreacted cobalt film is removed. The cobalt silicide film 30 is formed for reducing the resistance. Note that a titanium silicide film or a nickel silicide film may be formed by using a titanium film or a nickel film instead of the cobalt film as the refractory metal film.

In this way, the MONOS transistor Q ₁ and the MIS transistor Q ₂ of the present embodiment can be formed.

  Next, the wiring process will be briefly described. As shown in FIG. 7, a silicon nitride film 31 is formed on the main surface of the semiconductor substrate 10. The silicon nitride film 31 can be formed by, for example, a CVD method. Then, a silicon oxide film 32 is formed on the silicon nitride film 31. This silicon oxide film 32 can also be formed using, for example, the CVD method. Thereafter, the surface of the silicon oxide film 32 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, a contact hole 33 is formed in the silicon oxide film 32 by using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film 34 a is formed on the silicon oxide film 32 including the bottom surface and inner wall of the contact hole 33. The titanium / titanium nitride film 34a is formed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method.

  Next, a tungsten film 34 b is formed on the main surface of the semiconductor substrate 10 so as to fill the contact hole 33. The tungsten film 34b can be formed by using, for example, a CVD method. Then, the unnecessary titanium / titanium nitride film 34a and the tungsten film 34b formed on the silicon oxide film 32 are removed by using, for example, a CMP method, thereby forming the plug 35.

  Next, a titanium / titanium nitride film 36a, an aluminum film 36b, and a titanium / titanium nitride film 36c are sequentially formed on the silicon oxide film 32 and the plug 35. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique, and the wiring 37 is formed. Furthermore, although wiring is formed in the upper layer of the wiring 37, description in this specification is abbreviate | omitted.

As described above, a nonvolatile memory cell including the MONOS transistor Q ₁ of the present embodiment can be formed.

According to the MONOS transistor Q ₁ of the present embodiment, even when the length of the gate electrode 20 and the sidewall length of the sidewall 26a in the gate length direction are shortened, the electric field concentration below the end of the gate electrode 20 is reduced. Since it can be mitigated, leakage current can be reduced. In addition, since the generation of hot holes under the end of the gate electrode 20 can be reduced, it is possible to simultaneously reduce erroneous erasure.

That is, according to the nonvolatile memory cell including the MONOS transistor Q ₁ of the present embodiment, it is possible to improve device performance such as reducing leakage current and erroneous erasure while reducing the memory cell size.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Although the MONOS transistor has been described in the above embodiment, the present invention is not limited to this, and the present invention may be applied to, for example, an MNOS transistor.

  The present invention is used, for example, in the manufacturing industry for manufacturing IC cards that are nonvolatile semiconductor memory devices.

FIG. 5 is a circuit configuration diagram showing memory cells arranged two-dimensionally, and is a diagram describing voltages applied when a write operation is performed on a specific memory cell. FIG. 5 is a circuit configuration diagram showing memory cells arranged in a two-dimensional manner, and is a diagram describing voltages applied when performing an erase operation of a specific memory cell. FIG. 3 is a circuit configuration diagram showing memory cells arranged two-dimensionally, and is a diagram describing voltages applied when a specific memory cell is read. FIG. 5 is a diagram showing a path of leakage current generated in a MONOS transistor having a relatively long sidewall length and a region where impact ionization occurs most. FIG. 5 is a diagram showing a path of a leakage current generated in a MONOS transistor having a relatively short sidewall length and a region where an impact ionization phenomenon occurs most frequently. It is the figure which showed electric field distribution which arises in a MONOS type transistor with a comparatively short side wall length. It is sectional drawing which showed the non-volatile memory cell containing the MONOS type transistor in embodiment of this invention. It is a figure showing electric field distribution of a MONOS type transistor in an embodiment. It is the figure which showed the path | route of the leakage current which arises in the MONOS type transistor in embodiment, and the area | region where the impact ionization phenomenon generate | occur | produces most. It is sectional drawing which showed the manufacturing process of the semiconductor device in embodiment of this invention. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15;

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation region 12 Silicon oxide film 13 N-type well 14 P-type well 15 Gate insulating film (first gate insulating film)
16 Charge storage film 17 Insulating film 18 Polysilicon film (first conductor film)
19 Cap insulating film 20 Gate electrode (first gate electrode)
20a Silicon oxide film 21 Gate insulating film (second gate insulating film)
22 Gate electrode (second gate electrode)
23 Low-concentration n-type impurity diffusion region (impurity diffusion region)
24 Low-concentration n-type impurity diffusion region (impurity diffusion region)
25 Low-concentration n-type impurity diffusion region (impurity diffusion region)
26a side wall (first side wall)
26b Side wall (second side wall)
27 High-concentration n-type impurity diffusion region (impurity region)
28 High-concentration n-type impurity diffusion region (impurity region)
29 High-concentration n-type impurity diffusion region 30 Cobalt silicide film 31 Silicon nitride film 32 Silicon oxide film 33 Contact hole 34a Titanium / titanium nitride film 34b Tungsten film 35 Plug 36a Titanium / titanium nitride film 36b Aluminum film 36c Titanium / titanium nitride film 37 Wiring Q ₁ MONOS type transistor Q ₂ MIS type transistor

Claims (16)

A semiconductor device comprising a rewritable nonvolatile memory cell having a first field effect transistor for memory on a semiconductor substrate,
The first field effect transistor is:
(A) a gate insulating film formed on the semiconductor substrate;
(B) a charge storage film formed on the gate insulating film;
(C) a gate electrode formed on the charge storage film;
(D) a first sidewall formed over the respective sidewalls of the gate insulating film, the charge storage film, and the gate electrode;
The length of the charge storage film in the gate length direction of the gate electrode is shorter than the length of the gate electrode. The semiconductor device according to claim 1,
The first field effect transistor has an insulating film between the charge storage film and the gate electrode. The semiconductor device according to claim 1,
A semiconductor device, wherein the charge storage film is not formed under an end of the gate electrode. The semiconductor device according to claim 1,
A semiconductor device, wherein a part of the first sidewall is formed under an end portion of the gate electrode. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a dielectric constant of a material constituting the first sidewall is lower than a dielectric constant of a material constituting the charge storage film. The semiconductor device according to claim 1,
The semiconductor device, wherein the charge storage film is formed of a silicon nitride film, and the first sidewall is formed of a silicon oxide film. The semiconductor device according to claim 1,
The non-volatile memory cell further includes a second field effect transistor for selecting the non-volatile memory cell. The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein a length of the first sidewall of the first field effect transistor is longer than a length of the second sidewall of the second field effect transistor in a gate length direction. A semiconductor device comprising a plurality of rewritable nonvolatile memory cells having a field effect transistor for a memory on a semiconductor substrate,
The field effect transistor is
(A) a gate insulating film formed on the semiconductor substrate;
(B) a charge storage film formed on the gate insulating film;
(C) a gate electrode formed on the charge storage film;
(D) sidewalls formed over the respective sidewalls of the gate insulating film, the charge storage film, and the gate electrode;
(E) an impurity region formed in the semiconductor substrate, the impurity region formed in alignment with the sidewall,
A semiconductor device, wherein a distance from the impurity region to the charge storage film in a gate length direction is longer than a distance from the impurity region to the gate electrode in a gate length direction. The semiconductor device according to claim 9,
The nonvolatile memory cell includes a selected cell in which electrons are injected into the charge storage film and a non-selected cell in which electrons are not injected into the charge storage film,
The gate electrode of the selected cell and the gate electrode of the non-selected cell are connected to a word line, and in the write operation for injecting electrons into the selected cell, the word line and the impurity region in the selected cell A potential difference between the first and second word lines is larger than a potential difference between the word line and the impurity region in the non-selected cell. A semiconductor device including a first field effect transistor for forming a nonvolatile memory element and a second field effect transistor for selecting the nonvolatile memory element,
(A) a first gate insulating film of the first field effect transistor formed on a semiconductor substrate;
(B) a second gate insulating film of the second field effect transistor formed on the semiconductor substrate;
(C) a first sidewall of the first field effect transistor formed on the semiconductor substrate;
(D) having a second sidewall of the second field effect transistor formed on the semiconductor substrate;
In the gate length direction, the length of the first gate insulating film of the first field effect transistor is shorter than the length of the second gate insulating film of the second field effect transistor,
The semiconductor device according to claim 1, wherein a length of the first sidewall of the first field effect transistor is longer than a length of the second sidewall of the second field effect transistor in a gate length direction. A semiconductor device comprising a rewritable nonvolatile memory cell having a field effect transistor for memory on a semiconductor substrate,
The field effect transistor is
(A) a gate insulating film formed on the semiconductor substrate;
(B) a charge storage film formed on the gate insulating film;
(C) a gate electrode formed on the charge storage film;
The bottom surface of the gate electrode has a shape in which a distance from an end of the bottom surface to the semiconductor substrate is larger than a distance from a central portion of the bottom surface to the semiconductor substrate. (A) forming a first gate insulating film on the semiconductor substrate;
(B) forming a charge storage film on the first gate insulating film;
(C) forming a first conductor film on the charge storage film;
(D) patterning the first conductor film to form a first gate electrode;
And (e) etching the charge storage film to shorten the length of the charge storage film in the gate length direction compared to the gate length of the first gate electrode. Production method. A method of manufacturing a semiconductor device according to claim 13,
A method of manufacturing a semiconductor device, further comprising a step of forming an insulating film between the charge storage film and the first conductor film. 14. The method of manufacturing a semiconductor device according to claim 13, further comprising:
(F) forming a second gate insulating film on the semiconductor substrate;
(G) forming a second conductor film on the second gate insulating film;
(H) patterning the second conductor film and the second gate insulating film to form a second gate electrode, leaving the second gate insulating film only under the second gate electrode;
(I) forming an impurity diffusion region in the semiconductor substrate using the first gate electrode and the second gate electrode as a mask;
(J) forming first sidewalls extending over the respective sidewalls of the first gate insulating film, the charge storage film and the first gate electrode, and extending over the respective sidewalls of the second gate insulating film and the second gate electrode; And a step of forming a second sidewall. (A) forming a gate insulating film on the semiconductor substrate;
(B) forming a charge storage film on the gate insulating film;
(C) forming a conductor film on the charge storage film;
(D) patterning the conductor film to form a gate electrode;
(E) forming a bird's beak made of an insulating film at the lower end of the gate electrode;
(F) By removing the bird's beak, the shape of the bottom surface of the gate electrode increases the distance from the end of the bottom surface to the semiconductor substrate as compared to the distance from the center of the bottom surface to the semiconductor substrate. And a step of forming the semiconductor device.

Images