JP2005116582A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be reduced in prominent leakage current when the gate length of a MONOS transistor is shortened and can also be reduced in incorrect erasion (disturbing), and to provide its manufacturing method. <P>SOLUTION: In a nonvolatile memory cell which includes a MONOS transistor Q<SB>1</SB>for memory and a MIS transistor Q<SB>2</SB>for cell selection, a nitrogen introduced region 20 wherein nitrogen is introduced is formed in alignment with the gate electrode 8 of the MONOS transistor Q<SB>1</SB>. In other words, the nitrogen introduced region 20 wherein nitrogen is introduced is formed at least below the end of the gate electrode 8. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a rewritable nonvolatile semiconductor memory device and a technique effective when applied to the manufacturing technique.

Conventionally, in a MOS (Metal Oxide Semiconductor) type transistor, as a technique for preventing deterioration of a gate insulating film due to hot carrier injection, a technique for injecting nitrogen into a gate insulating film or a drain region has been disclosed (for example, a patent). Reference 1 and Patent Reference 2).
Japanese Patent Application Laid-Open No. 10-079506 (pages 4 to 5, FIGS. 3 to 6) JP 2000-004019 A (pages 12 to 13, FIG. 1)

  In recent years, there is a nonvolatile semiconductor memory device using a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor. The storage unit of this nonvolatile semiconductor memory device has a structure in which a large number of memory cells are arranged two-dimensionally, and the two-dimensionally arranged memory cells are connected to each other via word lines and bit lines. . In each memory cell, for example, a MONOS type transistor for memory and a MIS (Metal Insulator Semiconductor) transistor for selection for selecting the memory cell are formed.

  When a write operation, an erase operation, or a read operation is performed on such a memory cell, the memory cell selection MIS transistor is turned on to select the memory cell. Then, a target operation is performed by applying a set voltage to the source region, drain region, and gate electrode of the MONOS transistor in the selected memory cell.

  At this time, a predetermined voltage is applied to a non-selected memory cell other than the selected memory cell via a word line or a bit line. In this case, there is a problem that a large leak current is generated in a pn junction formed between the source region of the MONOS transistor in the non-selected memory cell and the semiconductor substrate, for example, due to a potential difference caused by application of a predetermined voltage. . Such a leakage current increases as the lateral scaling of the gate length, the sidewall length, and the like proceeds, leading to performance degradation and reliability degradation of the nonvolatile semiconductor memory device.

  In a non-selected memory cell in a state where writing is performed to the MONOS transistor (a state where electrons are stored in the charge storage layer), hot holes with high energy induced at the pn junction near the surface of the semiconductor substrate are formed. There is a problem in that data retention characteristics called “disturb” are deteriorated by tunneling through the gate insulating film and injected into the charge storage layer. Such disturbance is likely to occur as the lateral scaling of the gate length, sidewall length, etc. proceeds.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce a leakage current that appears remarkably when lateral scaling such as the gate length and sidewall length of a MONOS transistor is advanced.

  Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the disturbance that appears conspicuously when lateral scaling such as the gate length and sidewall length of the MONOS transistor is advanced.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device of the present invention includes: (a) a first insulating film formed on a semiconductor substrate; (b) a charge storage layer formed on the first insulating film; and (c) on the charge storage layer. A first conductor layer formed; (d) a first impurity region formed in the semiconductor substrate; and (e) a nitrogen introduction region formed in the semiconductor substrate.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: (a) a step of forming a first insulating film on the semiconductor substrate; (b) a step of forming a charge storage layer on the first insulating film; c) forming a first conductor layer on the charge storage layer; (d) introducing nitrogen into the semiconductor substrate by ion implantation to form a nitrogen introduction region; and (e) forming the semiconductor substrate on the semiconductor substrate. And forming a first impurity region by introducing impurities by ion implantation.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The leakage current of the semiconductor device can be reduced. Moreover, the occurrence of disturbance can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The first embodiment relates to a semiconductor device including a plurality of non-volatile memory cells each including a MONOS transistor for memory (an example of a MIS transistor) and a MIS transistor for selecting a cell on a semiconductor substrate, and a manufacturing method thereof. The invention is applied.

  The semiconductor device according to the first embodiment will be described with reference to the drawings. First, when a specific memory cell is selected and a write operation is performed, it will be described that a predetermined voltage (stress) is applied to a memory cell that is not selected.

Figure 1 is a circuit diagram showing a memory cell C _1-1 -C _2-4 which are arranged two-dimensionally. In Figure 1, a memory cell C _1-1 is composed of a MIS transistor Tr2a for MONOS type transistors Tr1a and cell selection for memory. Similarly, each of the memory cells _C1-2 to _C2-4 includes a MONOS transistor Tr1b to Tr1h for memory and a MIS transistor Tr2b to Tr2h for cell selection.

In the memory cell C _1-1 -C _1-4 arranged in the same row, the gate electrode of each of the MONOS transistor Tr1a~Tr1d are connected by one signal line (word line) WL2, MIS-type transistor The gate electrodes of Tr2a to Tr2d are also connected by a single signal line (word line) WL1. Similarly, in the memory cells C _{2-1 to} C _2-4 arranged in the same row, the gate electrodes of the MONOS transistors Tr1e to Tr1h are also connected by one signal line WL4, and the MIS transistors Tr2e to Tr2e are connected. The gate electrode of Tr2h is also connected by one signal line WL3.

Then, in the memory cell C _1-1 and the memory cell C _2-1 arranged in the same column, each of the source regions is connected by one signal line SL1 mutually, respective drain region to each other one The signal lines DL1 are connected. Similarly, the memory cells C _1-2 and the memory cell C _2-2 arranged in the same column are connected to the source region of each other by a signal line SL2, the signal line DL2 to each other of the drain region is connected ing. Further, in the memory cell C _1-3 and the memory cell C _2-3, by a signal line SL3 is connected the source region of one another, are connected to each other in the drain region by a signal line DL3, the memory cell C _1-4 And the memory cell C _2-4 have their source regions connected by a signal line SL4 and their drain regions connected by a signal line DL4.

The memory cell C _1-1 , the memory cell C _1-2 , the memory cell C _2-1 and the memory cell C _2-2 are formed on the same well, and a voltage is applied to the well by the signal line K1. It is to be applied. Further, the memory cell C _1-3 , the memory cell C _1-4 , the memory cell C _2-3, and the memory cell C _2-4 are formed on the same well, and the well is connected to the well by the signal line K2. A voltage is applied.

In such a memory cell C _1-1 -C _2-4 constructed in, with reference to FIG. 1 will be described an example of the case where by selecting the memory cell C _1-1 performs a write operation. As shown in FIG. 1, in order to select the memory cell C _1-1 applies a 1.5V to signal line WL1. Further, 1.5 V is applied to the signal line WL2, and -10.5 V is applied to the signal lines SL1, DL1, and K1. At this time, a potential difference of 12.0 V is generated between the source region of the MONOS transistor Tr1a in the memory cell C _1-1 (selected cell) and the gate electrode when the gate electrode side is positive. When such a high potential difference occurs, electrons in the source region are injected into the charge storage layer through the gate insulating film of the MONOS transistor Tr1a, and a write operation is performed. At this time, other memory cells C _1-2 which is connected to the signal line WL1, C _1-3, signal lines to the source and drain regions of the C _1-4 (non-selected cells not written) SL2～ SL4, but via a signal line DL2~DL4 predetermined voltage is applied, the potential difference between the source region (or drain region) and the signal line WL1, a source region of the memory cell C _1-1 of writing (or Both are lower than the potential difference 12V between the drain region) and the signal line WL1.

On the other hand, in the memory cells C _2-3 and C _2-4 , 0 V is applied to the signal line WL3 so that these cells are not selected. Further, the memory cell C _2-3, MONOS type transistor Tr1g in C _2-4, to the source region of Tr1h, the signal line SL3 and the signal line SL4 1.5V is applied to the well, the signal line K2 -10.5V is applied. Therefore, a potential difference of 12.0 V is generated at the pn junction between the source region and the well. Further, a voltage of −10.5 V is applied to the gate electrodes of the MONOS transistors Tr1g and Tr1h through the signal line WL4. For this reason, a potential difference of 12.0 V is generated between the gate electrode and the source region. When such a potential difference occurs, a large amount of leakage current is generated between the source region and the well, and hot holes induced by impact ionization are easily injected into the charge storage layer where electrons are stored. May occur.

Next, an example of performing the erase operation by selecting the memory cell _C1-1 will be described with reference to FIG. As shown in FIG. 2, for selecting a memory cell C _1-1, applies a 1.5V to signal line WL1. Further, −8.5V is applied to the signal line WL2, and 1.5V is applied to the signal lines SL1 and K1. Here, the signal line DL1 is in a floating state. At this time, between the MONOS type transistors Tr1a well (source region) and the gate electrode in the memory cell C _1-1, a potential difference of 10.0V is generated when a positive well (source region) side. When such a potential difference is generated and writing is performed in the MONOS transistor Tr1a, that is, when electrons are stored in the charge storage layer, the electrons in the charge storage layer pass through the gate insulating film. Since the tunnel exits to the well side, an erase operation is performed.

It can be seen that a predetermined voltage (stress) is applied to the non-selected memory cells also when this erase operation is performed, but the stress is higher than that of the memory cells C _2-3 and C _2-4 during the write operation. Is low.

Next, an example in which the memory cell _C1-1 is selected and the reading operation is performed will be described with reference to FIG. As shown in FIG. 3, for selecting a memory cell C _1-1, a voltage of 2.0V to the signal line WL1. Further, 0 V is applied to the signal lines WL2, SL1, and K1, and 1.5 V is applied to the signal line DL1. Here, if the electrons into the charge storage layer is performed writing in the MONOS type transistors Tr1a in the memory cell C _1-1 is stored, the threshold voltage of the MONOS transistor Tr1a is higher than 0V. For this reason, no current flows between the source region and the drain region of the memory cell _C1-1 . On the other hand, when writing is not performed in the MONOS transistor Tr1a (when electrons are not accumulated in the charge accumulation layer), a current flows when 0 V is applied to the gate electrode. In this way, the reading operation is performed.

When a read operation is performed, a predetermined voltage is applied to the non-selected memory cells, but the stress is lower than that of the memory cells C _2-3 and C _2-4 during the write operation.

  As described above, when a specific memory cell is selected and a target operation is performed, it is understood that a predetermined voltage (stress) is applied to an unselected memory cell that is not selected. In particular, it can be seen that during a write operation, the stress applied to a predetermined non-selected memory cell is large, and problems such as an increase in leakage current and occurrence of disturbance are likely to occur.

  Next, when the scaling in the gate length direction such as the gate length and the sidewall length is advanced, the leakage current at the pn junction of the non-selected memory cell increases, and disturbance occurs in the non-selected memory cell where data has been written. The cause of the problem was verified using simulation. As an example, a verification result when scaling the sidewall length will be described below.

  FIG. 4 shows a result obtained by simulating the region where the impact ionization occurs most and the path (leakage path) of the leakage current in the MONOS transistor having a long sidewall length. Here, impact ionization is a phenomenon in which a pair of electrons and holes are generated from a crystal lattice when electrons collide with each silicon crystal lattice in a semiconductor substrate made of silicon. Therefore, impact ionization is likely to occur at the location where the leak current is generated. In FIG. 4, the horizontal axis indicates the horizontal dimension, and the unit is μm. The vertical axis indicates the vertical dimension, and its unit is μm.

  The simulation was performed with the structure shown below. That is, as shown in FIG. 4, a gate insulating film, a charge storage layer, an insulating film, and a gate electrode are stacked on the well in order from the bottom, and the side walls extend across the side walls of the gate insulating film, the charge storage layer, the insulating film, and the gate electrode. Form. And it was carried out with the structure which formed the source region under this side wall. In the structure shown in FIG. 4, the gate insulating film, the charge storage layer, the insulating film, and the gate electrode are not shown in their entirety in the gate length direction for simplification of description, and only a part of them is shown. doing.

  As shown in FIG. 4, for a MONOS transistor having a long side wall length, impact ionization, that is, generation of an electron and hole pair due to collision between an electron and a crystal lattice, is separated from the gate electrode. It can be seen that there is the largest amount under the region, and the leak current also flows through the pn junction under the source region.

  On the other hand, FIG. 5 shows a simulation result of a region in which impact ionization occurs most frequently and a path (leakage path) of the leakage current in the MONOS transistor having a shorter sidewall length than the structure shown in FIG. It is shown.

  As shown in FIG. 5, unlike a MONOS transistor having a long sidewall length, impact ionization occurs most under the edge of the gate electrode, and the leak current is a pn junction near the surface of the semiconductor substrate under the edge of the gate electrode. It turns out that it is flowing through.

  FIG. 6 shows the electric field distribution of the MONOS transistor with a short sidewall length shown in FIG. That is, the electric field distribution is shown when a predetermined potential difference (stress) is generated between the gate electrode, the source region, the well, and the like of the MONOS transistor. Note that the unit of the electric field shown here is MV / cm.

  Referring to FIG. 6, it can be seen that the equal electric field lines are dense under the edge of the gate electrode, and the electric field is higher than the surrounding area. That is, it can be seen that electric field concentration occurs under the edge of the gate electrode. On the other hand, in the MONOS transistor having a long sidewall length, the position where the electric field concentrates is similarly below the end of the gate electrode (not shown).

  From this, it can be seen that in the MONOS transistor having a short sidewall length, the leakage current flows in a region where the electric field is concentrated. In the vicinity of the surface of the semiconductor substrate below the edge of the gate electrode where the electric field is concentrated, there are many crystal defects in the process due to dangling bonds of silicon and the like, and these are likely to be leakage paths. Therefore, it is considered that the amount of leakage current is likely to increase as compared with a MONOS transistor having a long sidewall length in which a leakage current flows through a pn junction under the source region.

  It can also be seen that impact ionization is often performed in a region where electric field concentration occurs in a MONOS transistor having a short sidewall length. For this reason, it is considered that holes are likely to be generated by impact ionization under the end of the gate electrode. Some of the generated holes have high energy, which is called a hot hole.

  Here, the inventor of the present application, based on the examination shown in FIGS. 4 to 6, uses a semiconductor in a non-selected memory cell in a state where electrons are accumulated in the MONOS transistor (a state where electrons are accumulated in the charge accumulation layer). For the first time, it has been found that hot holes with high energy induced at the pn junction near the substrate surface are injected into the charge storage layer through the gate insulating film, resulting in deterioration of data retention characteristics called disturb. It was. In particular, it has been found that such disturbances become more prominent as the lateral scaling of the gate length, sidewall length, etc. proceeds.

  That is, such hot holes may be injected into the charge storage layer through the gate insulating film of the MONOS transistor. Therefore, when hot holes are injected while writing is performed in the MONOS transistor, that is, when electrons are accumulated in the charge accumulation layer, the electrons accumulated in the charge accumulation layer are recombined. It may disappear and disturb may occur. In this case, it is considered that a hot hole is generated near the surface of the semiconductor substrate below the end of the gate electrode, and the leakage current passes through the vicinity of the charge storage layer. Therefore, in a MONOS transistor having a short sidewall length, hot holes are likely to be injected into the charge storage layer, that is, disturb is likely to occur.

  On the other hand, in a MONOS transistor having a long sidewall length, impact ionization occurs most under a source region far from the end of the gate electrode where the electric field is concentrated. A leak current also flows through the pn junction below the source current region. Therefore, even if hot holes are generated due to impact ionization, the distance from the charge storage layer where electrons are stored is far away, so that injection of hot holes into the charge storage layer is unlikely to occur, that is, disturbance is not likely to occur. Conceivable.

  From these examination results, it can be seen that in the MONOS transistor with a short sidewall length, the increase in leakage current and the disturb phenomenon are more problematic than the MONOS transistor with a long sidewall length.

Next, FIG. 7 shows a cross-sectional view of the MONOS transistor Q ₁ and the MIS transistors Q _{2 to} Q ₄ formed on the semiconductor chip according to the first embodiment. In FIG. 7, the left region indicates a memory cell formation region in an EEPROM (rewritable nonvolatile memory), and the right region indicates a peripheral circuit formation region.

As shown in FIG. 7, an element isolation region 2 for isolating elements is formed in the semiconductor substrate 1, and an n-type impurity is introduced into the semiconductor substrate 1 in the memory cell formation region. A well isolation layer 3 which is the formed region is formed. A p-type well 4 is formed on the well isolation layer 3, and a MONOS transistor Q ₁ and a MIS transistor Q ₂ are formed on the p-type well 4. The MONOS type transistor Q ₁ is a memory (memory) transistor that stores 1 bit, and the MIS type transistor Q ₂ is a selection transistor for selecting each memory cell.

A well isolation layer 3 is formed in the semiconductor substrate 1 in the peripheral circuit formation region, and a p-type well 10 is formed on the well isolation layer 3 in the nMIS type element formation region. An MIS transistor Q ₃ is formed on the p-type well 10. On the other hand, in the pMIS type element formation region, an n type well 11 is formed on the well isolation layer 3, and an MIS type transistor Q ₄ is formed on the n type well 11.

Next, description will be given of a configuration of the MONOS transistor Q ₁ and MIS-type transistors Q ₂ to Q ₄ shown in FIG.

First, the MONOS transistor Q ₁ formed in the memory cell formation region has the following configuration. That is, a gate insulating film (first insulating film) 5 is formed on a p-type well 4 formed in the semiconductor substrate 1, and a charge storage layer 6 is formed on the gate insulating film 5. An insulating film 7 is formed on the charge storage layer 6, and a gate electrode (first conductor layer) 8 made of a conductor film is formed on the insulating film 7. The gate electrode 8 has a laminated structure in which, for example, a cobalt silicide film 36 is formed as a silicide film on the polysilicon film 8a in order to reduce the resistance. LDD (Lightly In order to form a doped drain), for example, a sidewall (third insulating film) 28 made of an insulating film is formed. The silicide film formed on the polysilicon film 8a is not limited to the cobalt silicide film 36, and may be, for example, a titanium silicide film or a nickel silicide film.

  A nitrogen introduction region 20 is formed so as to extend from the vicinity of the surface of the semiconductor substrate 1 under the sidewall 28 to the outside. The nitrogen introduction region 20 is a low concentration n-type impurity diffusion region (first impurity) which is a semiconductor region. Regions) 21 and 22 are formed near the surface. That is, the maximum peak of nitrogen concentration in the nitrogen introduction region 20 is formed to be shallower than the maximum peak of impurity concentration in the low concentration n-type impurity diffusion regions 21 and 22. High concentration n type impurity diffusion regions (second impurity regions) 29 and 30 are formed in the low concentration n type impurity diffusion regions 21 and 22 and outside the sidewalls 28. For example, a cobalt silicide film 36 is formed on the diffusion regions 29 and 30 as a silicide film for reducing the resistance.

Here, the source region of the MONOS transistor Q ₁ is formed by the low-concentration n-type impurity diffusion region 21, the high-concentration n-type impurity diffusion region 29, and the cobalt silicide film 36 formed on the high-concentration n-type impurity diffusion region 29. The drain region of the MONOS transistor Q ₁ is formed by the low-concentration n-type impurity diffusion region 22, the high-concentration n-type impurity diffusion region 30, and the cobalt silicide film 36 formed on the high-concentration n-type impurity diffusion region 30. ing.

In the MONOS transistor Q ₁ configured as described above, since the nitrogen introduction region 20 is provided, it is possible to reduce leakage current and suppress disturbance. That is, when the gate length and the sidewall length are relatively shortened, the leakage current flows near the surface of the semiconductor substrate 1 below the end of the gate electrode 8 as shown in the simulation results.

  In the vicinity of the surface of the semiconductor substrate 1, there are a large number of crystal defects caused by dangling bonds (unbonded hands) of silicon, and these become leakage paths for leakage current. That is, near the termination of the low-concentration n-type impurity diffusion regions 21 and 22 on the channel formation region side (the end of the profile in the low-concentration n-type impurity diffusion regions 21 and 22), there are crystal defects caused by dangling bonds of silicon. There are many, and these become leak paths for leak current.

  However, in the first embodiment, nitrogen is introduced into the vicinity of the surface of the semiconductor substrate 1 below the sidewall 28 to bond nitrogen to the dangling bonds of silicon, thereby eliminating the dangling bonds. In addition, by introducing nitrogen, crystal defects are recovered by filling nitrogen into vacancies where atoms are not present at regular lattice points.

Therefore, according to the MONOS transistor Q ₁ in the first embodiment, it is possible to reduce the number of crystal defects that are likely to be a leakage path of the leakage current, and to reduce the leakage current.

  Furthermore, since leakage current under the end of the gate electrode 8 can be reduced, generation of hot holes under the end of the gate electrode 8 can be suppressed. That is, by reducing the leakage current, impact ionization due to the leakage current can be suppressed, and generation of hot holes can be suppressed. For this reason, it is possible to suppress the disturbance caused by hot holes generated under the end of the gate electrode 8 being tunneled through the gate insulating film 5 and injected into the charge storage layer 6.

As described above, according to the MONOS transistor Q ₁ of the first embodiment, by introducing nitrogen into the semiconductor substrate 1, the leakage current in the memory cell is reduced and the erroneous erasing characteristic is improved at the same time. be able to. Accordingly, it can be achieved improvement in the size reduction and the device characteristics of MONOS type transistor Q ₁ at the same time.

Next, the configuration of the MIS-type transistor Q ₂ for memory cell selection. In FIG. 7, the MIS transistor Q ₂ has a configuration as shown below. That is, a gate insulating film (second insulating film) 12 is formed on the p-type well 4, and a gate electrode (second conductor layer) 16 is formed on the gate insulating film 12.

  The gate electrode 16 has a structure in which a polysilicon film 14 and a cobalt silicide film 36 for reducing resistance are stacked.

A sidewall 28 is formed on the sidewalls on both sides of the gate electrode 16 so that the source region and the drain region of the MIS transistor Q ₂ have an LDD structure. In the p-type well 4 below the sidewall 28, Low-concentration n-type impurity diffusion regions 22 and 23, which are semiconductor regions, are formed.

  Inside the low-concentration n-type impurity diffusion regions 22 and 23, outside the sidewalls 28, high-concentration n-type impurity diffusion regions 30 and 31 that are semiconductor regions are formed. For example, a cobalt silicide film 36 is formed as a silicide film for reducing the resistance.

Next, the configuration of the MIS transistor Q ₃ formed in the peripheral circuit formation region will be described. In FIG. 7, in the MIS transistor Q ₃ , a gate insulating film 13 is first formed on a p-type well 10, and a gate electrode 17 is formed on the gate insulating film 13.

Since the MIS transistor Q ₃ formed as a peripheral circuit requires a relatively large current driving capability, the thickness of the gate insulating film 13 is larger than the thickness of the gate insulating film 12 of the MIS transistor Q _2. It is thin.

  The gate electrode 17 is formed of a polysilicon film 14 and a cobalt silicide film 36 formed on the polysilicon film 14, and the cobalt silicide film 36 is formed for reducing the resistance of the gate electrode 17.

  Sidewalls 28 are formed on the side walls on both sides of the gate electrode 17, and lightly doped n-type impurity diffusion regions 24 and 25, which are semiconductor regions, are formed below the sidewalls 28. High-concentration n-type impurity diffusion regions 32 and 33, which are semiconductor regions, are formed outside the low-concentration n-type impurity diffusion regions 24 and 25, and above the high-concentration n-type impurity diffusion regions 32 and 33, A cobalt silicide film 36 is formed.

Next, the configuration of the MIS transistor Q ₄ formed in the peripheral circuit formation region will be described. In FIG. 7, in the MIS transistor Q ₄ , a gate insulating film 13 is formed on the n-type well 11, and a gate electrode 18 is formed on the gate insulating film 13.

  The gate electrode 18 is formed of a polysilicon film 14 and a cobalt silicide film 36, and side walls 28 are formed on both side walls of the gate electrode 18.

  Low-concentration p-type impurity diffusion regions 26 and 27, which are semiconductor regions, are formed in the n-type well 11 below the sidewall 28, and the semiconductor region is located outside the low-concentration p-type impurity diffusion regions 26 and 27. High concentration p-type impurity diffusion regions 34 and 35, which are regions, are formed. A cobalt silicide film 36 is formed on the high concentration p-type impurity diffusion regions 34 and 35.

MONOS transistor Q ₁ and MIS-type transistors Q ₂ to Q ₄ in the first embodiment is configured as described above, a method for manufacturing the same will be described below with reference to the drawings.

  First, as shown in FIG. 8, for example, a semiconductor substrate 1 in which a p-type impurity such as boron (B) is introduced into single crystal silicon is prepared. Next, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. The element isolation region 2 is made of, for example, a silicon oxide film, and is formed by an STI (Shallow Trench Isolation) method, a LOCOS (Local Oxidization Of Silicon) method, or the like. FIG. 8 shows the element isolation region 2 formed by the STI method in which a groove is formed in the semiconductor substrate 1 and a silicon oxide film is embedded in the formed groove.

  Next, the well isolation layer 3 is formed in the semiconductor substrate 1. The well isolation layer 3 can be formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1 by, for example, ion implantation.

  Subsequently, the p-type well 4 is formed in the memory cell formation region (left region). The p-type well 4 can be formed, for example, by introducing a p-type impurity such as boron or boron fluoride into the memory cell formation region using a photolithography technique and an ion implantation method.

Next, a gate insulating film (first insulating film) 5 is formed on the entire main surface of the semiconductor substrate 1. The gate insulating film 5 is made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. Then, a charge storage layer 6 is formed on the gate insulating film 5. The charge storage layer 6 is made of, for example, a silicon nitride film, and can be formed using a CVD (Chemical Vapor Deposition) method in which silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) are chemically reacted. Although an example in which a silicon nitride film is used as the charge storage layer 6 is shown, the present invention is not limited to this. For example, a film including a trap level in a film such as a silicon oxynitride (SiON) film may be used. . Further, instead of the silicon nitride film, the charge storage layer 6 of the memory cell may be formed by so-called Si nanodots made of silicon spheres having a diameter of several nm. Even when such a silicon oxynitride film or Si nanodot is used, the same effect as in the present embodiment can be obtained.

Subsequently, an insulating film 7 is formed on the charge storage layer 6. The insulating film 7 is made of, for example, a silicon oxide film, and can be formed by a CVD method in which silane gas and oxygen gas (O ₂ ) are chemically reacted.

Next, a polysilicon film is formed on the insulating film 7. The polysilicon film can be formed by, for example, a CVD method in which silane gas is thermally decomposed in nitrogen gas (N ₂ ). When the polysilicon film is grown, a conductive impurity such as phosphorus is added. Note that a conductive impurity such as phosphorus may be implanted into the polysilicon film by using an ion implantation method after the formation of the polysilicon film is completed, not during the growth of the polysilicon film.

  Thereafter, a cap insulating film 9 is formed on the polysilicon film. The cap insulating film 9 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method. The cap insulating film 9 has a function of protecting the gate electrode 8 formed in a process described later.

  Subsequently, after applying a resist film on the cap insulating film 9, the resist film is patterned by exposing and developing the resist film. The patterning is performed so that the resist film remains in the region where the gate electrode 8 is to be formed. Then, a gate electrode (first conductor layer) 8 is formed by etching using the patterned resist film as a mask, as shown in FIG. 9, and the gate insulating film 5 and the charge storage layer 6 are formed only under the gate electrode 8. The insulating film 7 is left. Further, the cap insulating film 9 is left only on the gate electrode 8.

  Thereafter, as shown in FIG. 9, light oxidation is performed to oxidize the side surface of the gate electrode 8 to form a silicon oxide film 9a.

  Next, as shown in FIG. 10, a relatively thick gate insulating film (second insulating film) 12 is formed in the memory cell forming region of the semiconductor substrate 1 and relatively thin in the peripheral circuit forming region of the semiconductor substrate 1. A gate insulating film 13 is formed. The gate insulating film 12 and the gate insulating film 13 are made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method.

  Specifically, in order to form the insulating film 12 and the insulating film 13 having different thicknesses, for example, a silicon oxide film is first formed on the entire surface of the semiconductor substrate 1, and then the peripheral circuit is formed using a photolithography technique and an etching technique. The silicon oxide film formed in the formation region is removed. Then, by forming a silicon oxide film again on the entire surface of the semiconductor substrate 1, a relatively thick insulating film 12 is formed in the memory cell forming region, while a relatively thin insulating film 13 is formed in the peripheral circuit forming region. be able to.

  In addition, although the example which uses a silicon oxide film was shown as the gate insulating film 12 and the gate insulating film 13, it is not restricted to this, For example, using a material (what is called a High-k film) whose dielectric constant is higher than a silicon oxide. Also good. For example, a film made of aluminum oxide, hafnium oxide, zirconium oxide, or the like may be used.

  Subsequently, a polysilicon film 14 is formed on the gate insulating film 12 and the gate insulating film 13. The polysilicon film 14 can be formed by, for example, a CVD method. Note that after the polysilicon film is formed, a conductive impurity is implanted into the polysilicon film by using an ion implantation method. Specifically, n-type impurities such as phosphorus are introduced into the nMIS type transistor forming regions in the memory cell forming region and the peripheral circuit forming region, and p or the like such as boron is introduced into the pMIS type transistor forming region in the peripheral circuit forming region. Type impurities are introduced.

  Thereafter, a cap insulating film 15 is formed on the polysilicon film 14. The cap insulating film 15 is made of, for example, a silicon oxide film, and can be formed using, for example, a CVD method.

  Next, as shown in FIG. 11, the gate electrode (second conductor layer) 16 is formed in the memory cell formation region using the photolithography technique and the etching technique, and the gate electrode 17 and the peripheral circuit formation area are formed. A gate electrode 18 is formed. Thereafter, the exposed gate insulating film 12 and gate insulating film 13 are removed so that the gate insulating film 12 remains only under the gate electrode 16, and the gate insulating film only under the gate electrodes 17 and 18. 13 remains. At this time, the cap insulating film 9 formed on the gate electrode 8 and the silicon oxide film 9a formed on the side surface are also removed.

Subsequently, as shown in FIG. 12, nitrogen introduction region 20 is formed by introducing nitrogen into p-type well 4 in alignment with gate electrode 8. The nitrogen introduction region 20 can be formed using, for example, a photolithography technique and an ion implantation method. Although not shown, the resist film by photolithography, the region MIS transistor Q ₂ for memory cell selection are formed, the nMIS transistor Q ₃ forming region and pMIS transistor Q ₄ forming region of the peripheral circuit formation region Form to cover. Thereafter, nitrogen introduction region 20 is formed by introducing nitrogen into the semiconductor substrate by ion implantation. Specifically, the nitrogen introduction region 20 can be formed, for example, by introducing nitrogen having an energy of 20 KeV at a dose of 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 13, shallow low-concentration n-type impurity diffusion regions (first impurity regions) 21, 22, and 23 are formed in alignment with the gate electrode 8 and the gate electrode 16 in the memory cell formation region. The low-concentration n-type impurity diffusion regions 21, 22, and 23 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method. Similarly, low-concentration n-type impurity diffusion regions 24 and 25 are formed in alignment with the gate electrode 17 in the peripheral circuit formation region. Further, low-concentration p-type impurity diffusion regions 26 and 27 are formed in alignment with the gate electrode 18 in the peripheral circuit formation region. The low-concentration p-type impurity diffusion regions 26 and 27 can be formed by introducing a p-type impurity such as boron using a photolithography technique and an ion implantation method, for example.

  Subsequently, the introduced impurity is activated by annealing the semiconductor substrate 1. At this time, heat treatment is also applied to the nitrogen introduced into the semiconductor substrate 1, and nitrogen is bonded to dangling bonds that are present in the vicinity of the termination of the low-concentration n-type impurity diffusion regions 21 and 22 on the channel formation region side. . In addition, crystal defects are recovered by diffusing nitrogen into vacancies where atoms are not present at regular lattice points. Therefore, crystal defects caused by dangling bonds are compensated by nitrogen, and the leakage path of leakage current can be reduced. For this reason, the leakage current flowing through the pn junction can be reduced.

  Furthermore, since leakage current flowing under the end of the gate electrode 8 can be reduced, generation of hot holes under the end of the gate electrode 8 can be suppressed, and erroneous erasure can be prevented.

  Since many dangling bonds of silicon exist near the surface of the semiconductor substrate 1, a large amount of nitrogen combined with the dangling bonds exists near the surface of the semiconductor substrate 1. That is, the depth at which the nitrogen concentration is maximum (peak) in the nitrogen introduction region 20 is shallower than the depth at which the n-type impurity concentration is maximum in the low-concentration n-type impurity diffusion regions 21 and 22. To do.

  In the above description, the nitrogen-introduced region 20 is formed above the low-concentration n-type impurity diffusion regions 21 and 22, but in other words, the low-concentration n-type impurity diffusion region 21, It may be said that the upper part of 22 contains nitrogen.

  Next, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 by using, for example, a CVD method. Then, as shown in FIG. 14, the formed silicon oxide film is anisotropically etched to form sidewalls (third insulating films) 28 on the side walls of the gate electrodes 8 and 16-18.

  Subsequently, as shown in FIG. 15, high-concentration n-type impurity diffusion regions (second impurity regions) 29 to 33 which are semiconductor regions are formed using a photolithography technique and an ion implantation method. The high concentration n-type impurity diffusion regions 29 to 33 are doped with n-type impurities at a higher concentration than the low concentration n-type impurity diffusion regions 21 to 25. Similarly, high-concentration p-type impurity diffusion regions 34 and 35 that are semiconductor regions are formed. In the nitrogen introduction region 20, the depth at which the nitrogen concentration is maximum is shallower than the depth at which the n-type impurity concentration is maximum in the high-concentration n-type impurity diffusion regions 29 and 30.

  Next, as shown in FIG. 7, for example, a cobalt film is formed on the main surface of the semiconductor substrate 1 as a refractory metal film. The cobalt film can be formed using, for example, a sputtering method or a CVD method. Then, after the cobalt silicide film 36 is formed by performing heat treatment, the unreacted cobalt film is removed. The cobalt silicide film 36 is formed for reducing the resistance. Note that a titanium silicide film or a nickel silicide film may be formed by using a titanium film or a nickel film instead of the cobalt film as the refractory metal film.

In this way, the MONOS transistor Q ₁ and the MIS transistors Q _{2 to} Q ₄ of the _first embodiment can be formed.

  Next, the wiring process will be described. As shown in FIG. 7, a silicon nitride film 37 is formed on the main surface of the semiconductor substrate 1. The silicon nitride film 37 can be formed by, for example, a CVD method. Then, a silicon oxide film 38 is formed on the silicon nitride film 37. This silicon oxide film 38 can also be formed by using, for example, a CVD method. Thereafter, the surface of the silicon oxide film 38 is planarized by using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, a contact hole 39 is formed in the silicon oxide film 38 by using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film 40 a is formed on the silicon oxide film 38 including the bottom surface and inner wall of the contact hole 39. The titanium / titanium nitride film 40a is formed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method.

  Next, a tungsten film 40 b is formed on the main surface of the semiconductor substrate 1 so as to fill the contact hole 39. The tungsten film 40b can be formed by using, for example, a CVD method. Then, the unnecessary titanium / titanium nitride film 40a and tungsten film 40b formed on the silicon oxide film 38 are removed by using, for example, a CMP method, thereby forming the plug 41.

  Next, a titanium / titanium nitride film 42a, an aluminum film 42b, and a titanium / titanium nitride film 42c are sequentially formed on the silicon oxide film 38 and the plug 41. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique, and the wiring 43 is formed. Furthermore, although wiring is formed in the upper layer of the wiring 43, description in this specification is abbreviate | omitted.

As described above, the nonvolatile memory cell including the MONOS transistor Q ₁ and the MIS transistor Q ₂ and the peripheral circuit including the MIS transistor Q ₃ and the MIS transistor Q _{4 according} to the first embodiment are formed. Can do.

According to the MONOS transistor Q ₁ of the first embodiment, even if the length of the gate electrode 8 and the sidewall length of the sidewall 28 in the gate length direction are shortened, the crystal defects below the end of the gate electrode 8 are reduced. Can be compensated by nitrogen, so that leakage current can be reduced. In addition, since the generation of hot holes under the end of the gate electrode 8 can be reduced, disturbance can be suppressed at the same time.

That is, according to the nonvolatile memory cell including the MONOS transistor Q1 of the _first embodiment, it is possible to improve the device performance by reducing the leakage current and suppressing the disturbance while reducing the memory cell size.

(Embodiment 2)
Wherein in the first embodiment has described the case of providing only the nitrogen introduced region 20 in the MONOS type transistor Q ₁ included in the non-volatile memory cell, in the second embodiment, a cell selection in the nonvolatile memory cell A case where the nitrogen introduction region 20 is formed also in the MIS transistor Q ₂ will be described.

First, the steps from FIG. 8 to FIG. 11 are the same as those in the first embodiment. Subsequently, as shown in FIG. 16, nitrogen is introduced into the region aligned with the gate electrode 8 and the gate electrode 16 by using a photolithography technique and an ion implantation method to form a nitrogen introduction region 20. Although not shown, a resist film is formed by photolithography so as to cover the nMIS transistor formation region and the pMIS transistor formation region in the peripheral circuit formation region. Thereafter, nitrogen introduction region 20 is formed by introducing nitrogen into the semiconductor substrate by ion implantation. That is, in the first embodiment, nitrogen is introduced only into the region aligned with the gate electrode 8, but in this second embodiment, nitrogen is also introduced into the region aligned with the gate electrode 16. Therefore, the semiconductor region on the left side of the gate electrode 8 (source region of the MONOS transistor Q ₁ ), the semiconductor region between the gate electrode 8 and the gate electrode 16 (the drain region of the MONOS transistor Q ₁ , and the MIS transistor Q ₂ nitrogen inlet area 20 to the right side of the semiconductor region of the source region) and a gate electrode 16 (the drain region of the MIS transistor Q ₂₎ of are formed.

Then, as described in the first embodiment, the lightly doped n-type impurity diffusion regions 21 to 25 (not shown) and the lightly doped p-type impurity diffusion regions 26 and 27 ( After forming, an annealing process is performed. In this manner, not only can nitrogen be bonded to the silicon dangling bonds existing under the edge of the gate electrode 8, but also nitrogen can be bonded to the dangling bonds existing under the edge of the gate electrode 16. . In addition, vacancies under the ends of the gate electrodes 8 and 16 can be filled with nitrogen. For this reason, crystal defects can be reduced by nitrogen. Therefore, according to the second embodiment, not only the leakage current can be reduced and the erroneous erasure can be prevented in the MONOS transistor Q ₁ , but also the leakage current can be reduced in the MIS transistor Q ₂ for cell selection. be able to.

(Embodiment 3)
In the second embodiment, the case where the nitrogen introduction region 20 is formed only in the MONOS transistor Q ₁ and the cell selection MIS transistor Q ₂ in the nonvolatile memory cell has been described. In the third embodiment, Further, a case where the nitrogen introduction region 20 is formed also in the nMIS transistor Q ₃ of the peripheral circuit will be described.

  First, the steps from FIG. 8 to FIG. 11 are the same as those in the first embodiment. Subsequently, as shown in FIG. 17, nitrogen is introduced into the nMIS type transistor formation region in the memory cell formation region and the peripheral circuit formation region using the photolithography technique and the ion implantation method, thereby forming the nitrogen introduction region 20. To do. Although not shown, a resist film is formed by photolithography so as to cover the pMIS transistor formation region in the peripheral circuit formation region. Thereafter, nitrogen introduction region 20 is formed by introducing nitrogen into the semiconductor substrate by ion implantation. That is, the nitrogen introduction region 20 is formed in alignment with each of the gate electrode 8, the gate electrode 16, and the gate electrode 17.

Then, as described in the second embodiment, the low-concentration n-type impurity diffusion regions 21 to 25 (not shown) and the low-concentration p-type impurity diffusion regions 26 and 27 (using the photolithography technique and the ion implantation method). After forming, an annealing process is performed. In this way, leakage current can be reduced not only in the nonvolatile memory cell but also in the nMIS transistor Q ₃ of the peripheral circuit.

Here, in the peripheral circuit, the nitrogen introduction region 20 is formed only in the formation region of the nMIS transistor Q ₃ and the nitrogen introduction region 20 is not formed in the formation region of the pMIS transistor Q _4. by.

First, as in the case of the nMIS transistor Q ₃ , the case where the nitrogen introduction region 20 is provided also in the pMIS transistor Q ₄ will be considered. In this case, it is considered that nitrogen defects are bonded to silicon dangling bonds to reduce crystal defects caused by dangling bonds.

However, in the pMIS transistor Q ₄ , if there are many bonds of silicon and nitrogen at the interface between the gate insulating film (gate oxide film) 13 and the semiconductor substrate 1, the gate insulating film 13 caused by NBTI (Negative Bias Temperature Instability) There is a risk of lowering reliability.

  NBTI is a phenomenon in which Vth increases only by applying a negative voltage to the gate electrode of a pMIS transistor even at room temperature, and then returns when a positive voltage is applied, so holes (holes) are formed in the gate insulating film. This phenomenon is thought to be captured by the This is particularly noticeable in the oxide film, and there is a problem that Vth is increased only by applying a voltage between the gate electrode and the semiconductor substrate without passing a current between the source and drain of the pMIS transistor. In particular, this phenomenon appears remarkably when the polycrystalline silicon film constituting the gate electrode is p-type.

  Such a decrease in the reliability of the gate insulating film 13 due to NBTI applies a negative voltage as a stress to the gate electrode 18 so that holes are likely to gather near the interface between the gate insulating film (gate oxide film) 13 and the semiconductor substrate 1. It happens when you do. As the generation mechanism, the mechanism described below is considered to be effective. FIG. 33 shows the model. There is a lot of hydrogen that compensates for dangling bonds of silicon at the interface between the gate insulating film 13 and the semiconductor substrate 1, but when holes are collected there, silicon atoms and holes are combined, and the hydrogen is stabilized in an activated state. . At this time, a positive interface trap due to silicon is formed. Further, the activated hydrogen collides with oxygen in the silicon oxide film forming the gate insulating film 13, and forms a positive fixed charge in the silicon oxide film by an electrochemical reaction. These positive interface traps and fixed charges are considered to cause a decrease in the reliability of the gate insulating film 13.

In this embodiment, when the nitrogen introduction region 20 is provided so that many bonds of silicon and nitrogen exist at the interface between the gate insulating film (gate oxide film) 13 and the semiconductor substrate 1, the activated hydrogen is converted into silicon oxide. Nitrogen atoms collide with oxygen atoms in the film, and traps are formed in the vicinity of the interface between the gate insulating film 13 and the semiconductor substrate 1. Therefore, it is considered that when a large number of bonds of silicon atoms and nitrogen atoms exist at the interface between the gate insulating film (gate oxide film) 13 and the semiconductor substrate 1, a decrease in reliability of the gate insulating film 13 due to NBTI is accelerated. For these reasons, in order to prevent the reliability of the gate insulating film 13 from decreasing, the nitrogen introduction region 20 is not formed in the pMIS transistor Q ₄ .

In this manner, not only can nitrogen be bonded to the silicon dangling bonds existing under the ends of the gate electrodes 8 and 16 as in the second embodiment, but also dang existing under the ends of the gate electrode 17. Nitrogen can be bonded to the ring bond. In addition, vacancies under the ends of the gate electrodes 8, 16, and 17 can be filled with nitrogen. For this reason, crystal defects can be reduced by nitrogen. Therefore, according to the third embodiment, in the MONOS type transistor Q ₁ , not only the leakage current can be reduced and the erroneous erasure can be prevented, but also the MIS type transistor Q ₂ for cell selection, and further the nMIS type of the peripheral circuit. it can be reduced leakage current in the transistor Q _3.

  In the fifth and sixth embodiments described later, a nitrogen introduction region is not formed in the pMIS transistor of the peripheral circuit for the same reason as in the third embodiment.

(Embodiment 4)
In the first to third embodiments, as shown in the manufacturing process of FIG. 12 (FIG. 16 or FIG. 17) and FIG. 13, nitrogen is first introduced to form the nitrogen introduction region 20, and then the shallow semiconductor region. The low concentration n-type impurity diffusion regions 21 to 25 are formed. After the low concentration impurity diffusion regions 21 to 25 are formed, nitrogen is introduced to form the nitrogen introduction region 20 and annealing is performed. May be. That is, it is formed by the manufacturing process in the order of FIG. 13 and FIG. 12 (FIG. 16 or 17). In such a case, since the ion implantation for forming the low concentration n-type impurity diffusion regions 21 to 25 can be performed first, the damage to the semiconductor substrate that occurs during the ion implantation and the low concentration n-type impurity diffusion are performed. Even if a crystal defect or the like due to dangling bonds on the surfaces of the regions 21 to 25 occurs, it can be compensated for by the subsequent nitrogen introduction step, so the same effects as in the first to third embodiments described above. In addition to the above-described first to third embodiments, the leakage current can be further reduced and the erroneous erasure characteristic can be prevented from being deteriorated.

(Embodiment 5)
FIG. 18 shows a cross-sectional view of the nonvolatile memory cells C ₁ and C ₂ and the MIS transistors Q ₅ and Q _{6 in} the fifth embodiment formed on the semiconductor chip. In FIG. 18, the left region is a memory cell formation region, and the right region is a peripheral circuit formation region.

  First, a first buried layer 52 into which an n-type impurity is introduced is formed in the semiconductor substrate 50, and a second buried layer 53 into which an n-type impurity is introduced is formed in the first buried layer 52. ing. The first buried layer 52 and the second buried layer 53 are provided to electrically insulate the semiconductor substrate 50 from a well described later.

In the memory cell formation region, a p-type well 54 into which p-type impurities are introduced is formed in the semiconductor substrate 50 on the first buried layer 52, and the nonvolatile memory cell C ₁ and the p-type well 54 are formed on the p-type well 54. nonvolatile memory cell C ₂ is formed.

On the other hand, in the peripheral circuit formation region, an element isolation region 51 that separates the formation region of the nMIS transistor Q _{5 and} the formation region of the pMIS transistor Q ₆ is formed on the first buried layer 52. A p-type well 54 is formed in the nMIS transistor Q ₅ formation region isolated by the element isolation region 51, and an n-type well 55 is formed in the pMIS transistor Q ₆ formation region. An MIS transistor Q ₅ is formed on the p-type well 54 in the peripheral circuit formation region, and an MIS transistor Q ₆ is formed on the n-type well 55.

Next, the configuration of the nonvolatile memory cell C ₁ will be described. The nonvolatile memory cell C ₁ has a gate insulating film (first insulating film) 56 on the p-type well 54, and a charge storage layer 57 for storing charges is formed on the gate insulating film 56. . A first gate electrode 59 is formed on the charge storage layer 57 via an insulating film 58, and the non-volatile memory cell C is formed by the gate insulating film 56, the charge storage layer 57, the insulating film 58 and the first gate electrode 59. _One memory unit (first MIS) is formed.

  Subsequently, a cap insulating film 60 is formed on the first gate electrode 59, and sidewalls (third insulating films) 64 are formed on both side walls of the first gate electrode 59. A gate insulating film (second insulating film) 65 is formed so as to extend outward from a region in contact with one side wall 64, and a second gate electrode 69 is formed on the gate insulating film 65. .

The second gate electrode 69 has a shape partially overlying the first gate electrode 59, and is formed of a polysilicon film 67 and a cobalt silicide film 89. A sidewall 81 is formed on the sidewall of the second gate electrode 69. The second gate electrode 69 and the gate insulating film 65 form a memory cell selection unit (second MIS) that selects the nonvolatile memory cell C ₁ .

  Next, a nitrogen introduction region 61 into which nitrogen is introduced is formed so as to extend outward from below the sidewalls 64 formed on both sidewalls of the first gate electrode 59. That is, the nitrogen introduction region 61 is formed on the surface of the p-type well 54 in alignment with the first gate electrode 59.

  A nitrogen introduction region 61 is formed under the sidewall 64 on the side where the second gate electrode 69 is not applied (on the first gate electrode 59 side). This nitrogen introduction region 61 is a low concentration that is a semiconductor region. It is formed near the surface of n-type impurity diffusion region 62 and extends outward.

    A high-concentration n-type impurity diffusion region 82, which is a semiconductor region, is formed in the low-concentration n-type impurity diffusion region 62 and outside the sidewall 64. A cobalt silicide film 89 is formed on the upper part.

  On the other hand, of the sidewall 81 formed on the side wall of the second gate electrode 69, a nitrogen introduction region 61 is formed below the sidewall 81 formed on the p-type well 54. A low-concentration n-type impurity diffusion region 76 that is a semiconductor region is formed under 61. A high-concentration n-type impurity diffusion region 83 is formed outside the low-concentration n-type impurity diffusion region 76, and an upper portion of the high-concentration n-type impurity diffusion region 83 is used to reduce resistance. A cobalt silicide film 89 is formed.

  Here, in the nitrogen introduction region 61, the depth at which the concentration of nitrogen becomes maximum is such that the concentration of the n-type impurity in the low-concentration n-type impurity diffusion regions 62 and 76 and the high-concentration n-type impurity diffusion regions 82 and 83 is respectively. It is shallower than the maximum depth.

Since the nonvolatile memory cell C ₂ has the same configuration as the nonvolatile memory cell C ₁ , the description thereof is omitted.

In the nonvolatile memory cell C ₁ in the fifth embodiment, since the nitrogen introduction region 61 is formed as described above, the dangling bonds existing under the end portions of the first gate electrode 59 and the second gate electrode 69 are not formed. Nitrogen can be bound. Moreover, nitrogen can be filled in the vacancy defects. Therefore, crystal defects formed near the surface of the semiconductor substrate 50 under the ends of the first gate electrode 59 and the second gate electrode 69 can be recovered by nitrogen.

In the nonvolatile memory cell C ₁ , the gate length of the first gate electrode 59 and the sidewall length of the sidewall 64 are short. At this time, the leakage current flowing in the nonvolatile memory cell C ₁ flows in the vicinity of the surface below the end of the first gate electrode 59, but if there is a crystal defect in the vicinity of the surface of the semiconductor substrate 50, the defective portion tends to be a leakage path. .

However, in the nonvolatile memory cell C ₁ in the fifth embodiment, the crystal defects formed near the surface of the semiconductor substrate 50 are recovered by nitrogen as described above. Therefore, the leakage current can be reduced, the generation of hot holes due to the leakage current can be suppressed, and the erroneous erasure due to the injection of hot holes into the charge storage layer 57 can also be suppressed. Further, since the crystal defects can be similarly recovered by nitrogen under the end portion of the second gate electrode 69, the leakage current can be reduced.

  In other words, according to the fifth embodiment, it is possible to improve device characteristics such as reduction of leakage current and reduction of erroneous erasure while reducing the memory cell size.

Next, the configuration of the MIS transistors Q ₅ and Q ₆ formed in the peripheral circuit formation region is substantially the same as the configuration of the MIS transistors Q ₃ and Q ₄ described in the first embodiment. Therefore, different points will be described.

In the MIS transistor Q ₅ in the _fifth embodiment, unlike the MIS transistor Q ₃ described in the first embodiment, a nitrogen introduction region 75 is formed so as to extend from below the sidewall 81. Yes. Therefore, in the MIS transistor Q ₅ in the peripheral circuit, the crystal defect under the end of the gate electrode 71 can be compensated by nitrogen, so that the leakage current can also be reduced in the peripheral circuit.

The nonvolatile memory cells C ₁ and C ₂ and the MIS transistors Q ₅ and Q _{6 in the fifth} embodiment are configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 19, an element isolation region 51 is formed on the peripheral circuit formation region of the semiconductor substrate 50. The element isolation region 51 is made of, for example, a silicon oxide film, and is formed by an STI method, a LOCOS method, or the like. FIG. 19 shows an element isolation region 51 formed by the STI method in which a groove is formed in the semiconductor substrate 50 and a silicon oxide film is embedded in the formed groove.

  Next, the first buried layer 52 and the second buried layer 53 are formed in the semiconductor substrate 50. The first buried layer 52 and the second buried layer 53 can be formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 50 using a photolithography technique and an ion implantation method.

  Subsequently, a p-type well 54 is formed in the memory cell formation region and the nMIS transistor formation region in the peripheral circuit formation region by using a photolithography technique and an ion implantation method. The p-type well 54 can be formed by introducing a p-type impurity such as boron or boron fluoride. Similarly, an n-type well 55 is formed by introducing an n-type impurity such as phosphorus or arsenic into the pMIS transistor formation region in the peripheral circuit formation region.

  Next, a gate insulating film (first insulating film) 56 is formed on the entire main surface of the semiconductor substrate 50. The gate insulating film 56 is made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. Then, a charge storage layer 57 is formed on the gate insulating film 56. The charge storage layer 57 is made of, for example, a silicon nitride film, and can be formed by using, for example, a CVD method. Although an example in which a silicon nitride film is used as the charge storage layer 57 is shown, the present invention is not limited to this, and a film including a trap level in a film such as a silicon oxynitride (SiON) film may be used.

  Subsequently, an insulating film 58 is formed on the charge storage layer 57. The insulating film 58 is made of, for example, a silicon oxide film, and can be formed by, for example, a CVD method. Then, a polysilicon film is formed on the insulating film 58. The polysilicon film can be formed by, for example, a CVD method. Thereafter, a cap insulating film 60 is formed on the polysilicon film. The cap insulating film 60 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method.

  Next, after forming a resist film on the cap insulating film 60, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains only in the region where the first gate electrode 59 is formed. Then, the first gate electrode 59 is formed by etching using the patterned resist film as a mask.

Subsequently, as shown in FIG. 20, nitrogen is introduced into the memory cell formation region to form a nitrogen introduction region 61. The nitrogen introduction region 61 can be formed using, for example, a photolithography technique and an ion implantation method. Although not shown, a resist film is formed by a photolithography technique so as to cover the peripheral circuit formation region. Thereafter, nitrogen introduction region 61 is formed by introducing nitrogen into the semiconductor substrate by ion implantation. That is, the nitrogen introduction region 61 is formed in a region aligned with the first gate electrode 59 using the cap insulating film 60 as a mask. Specifically, the nitrogen introduction region 61 can be formed, for example, by introducing nitrogen having an energy of 20 KeV at a dose of 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 21, shallow low-concentration n-type impurity diffusion regions (first impurity regions) 62 and 63 are formed in the memory cell formation region. The low-concentration n-type impurity diffusion regions 62 and 63 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method.

  Thereafter, the introduced impurity is activated by annealing the semiconductor substrate 50. At this time, heat treatment is also applied to the nitrogen introduced into the semiconductor substrate 50, and nitrogen is bonded to dangling bonds existing in the vicinity of the surface of the semiconductor substrate 50. In addition, the crystal defects are recovered by diffusing nitrogen into the vacancy defects. Thus, since the crystal defects are compensated by nitrogen, the leakage current can be reduced. Further, since leakage current flowing under the end of the first gate electrode 59 can be reduced, generation of hot holes under the end of the first gate electrode 59 can be suppressed, and erroneous erasure can be prevented.

  Subsequently, after a silicon oxide film is formed on the semiconductor substrate 50 by using, for example, a CVD method, the silicon oxide film is anisotropically etched to form sidewalls (third) on the sidewalls of the first gate electrode 59. Insulating film) 64 is formed.

  Next, as shown in FIG. 22, a relatively thick gate insulating film (second insulating film) 65 is formed in the memory cell forming region of the semiconductor substrate 50 and relatively thin in the peripheral circuit forming region of the semiconductor substrate 50. A gate insulating film 66 is formed. The gate insulating film 65 and the gate insulating film 66 are made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. In addition, although the example which uses a silicon oxide film was shown as the gate insulating film 65 and the gate insulating film 66, it is not restricted to this, For example, a High-k film | membrane may be sufficient.

  Subsequently, a polysilicon film 67 is formed on the gate insulating film 65 and the gate insulating film 66. The polysilicon film 67 can be formed using, for example, a CVD method. Then, a cap insulating film 68 is formed on the polysilicon film 67 by using, for example, a CVD method.

  Then, after forming a resist film on the cap insulating film 68, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains in the gate electrode formation region.

  Subsequently, as shown in FIG. 23, the second gate electrode 69, the gate electrode 71, and the gate electrode 73 are formed by etching using the patterned resist film as a mask. In other words, the second gate electrode 69 that is partially on the first gate electrode 59 is formed in the memory cell formation region, and the gate electrode 71 and the gate electrode 73 are formed in the peripheral circuit formation region.

Next, as shown in FIG. 24, a nitrogen introduction region 75 is formed in alignment with the gate electrode 71 in the nMIS transistor formation region in the peripheral circuit formation region. The nitrogen introduction region 75 is formed by introducing nitrogen into the p-type well 54 using, for example, a photolithography technique and an ion implantation method. Although not shown, a resist film is formed by photolithography so as to cover the pMIS type transistor formation region in the memory cell formation region and the peripheral circuit region. Thereafter, nitrogen introduction region 75 is formed by introducing nitrogen into the semiconductor substrate by ion implantation. That is, the nitrogen introduction region 75 is formed in a region aligned with the nMIS transistor gate electrode 71 using the cap insulating film 68 as a mask. Specifically, the nitrogen introduction region 75 can be formed, for example, by introducing nitrogen having an energy of 20 KeV at a dose of 10 ¹⁵ / cm ² .

  Subsequently, as shown in FIG. 25, low-concentration n-type impurity diffusion regions 76, 77, 78 and low-concentration p-type impurity diffusion regions 79, 80 are formed. The low-concentration n-type impurity diffusion regions 76 to 78 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method. 80 can be formed by introducing a p-type impurity such as boron or boron fluoride.

Thereafter, an annealing process is performed to activate the introduced conductive impurities. At this time, heat treatment is also applied to the previously introduced nitrogen. Therefore, nitrogen introduced into the nMIS transistor forming region in the peripheral circuit forming region is bonded to the dangling bond of silicon,
Crystal defects caused by dangling bonds can be recovered. For this reason, the leakage current in the peripheral circuit can be reduced.

  Subsequently, as shown in FIG. 18, after forming a silicon oxide film on the semiconductor substrate 50 by using, for example, a CVD method, anisotropic etching is performed, whereby the second gate electrode 69, the gate electrode 71, and the gate electrode are formed. A side wall 81 is formed on the side wall 73.

  Next, high-concentration n-type impurity diffusion regions 82 to 86 and high-concentration p-type impurity diffusion regions 87 and 88 are formed in the semiconductor substrate 50. The high-concentration n-type impurity diffusion regions 82 to 86 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method. 88 can be formed by introducing a p-type impurity such as boron or boron fluoride. Thereafter, annealing is performed to activate the introduced conductive impurities.

  Thereafter, for example, a cobalt film is formed as a refractory metal film on the main surface of the semiconductor substrate 50 as shown in FIG. The cobalt film can be formed using, for example, a sputtering method or a CVD method. Then, after the cobalt silicide film 89 is formed by performing heat treatment, the unreacted cobalt film is removed. The cobalt silicide film 89 is formed for reducing the resistance. Note that a titanium silicide film or a nickel silicide film may be formed by using a titanium film or a nickel film instead of the cobalt film as the refractory metal film.

In this manner, the nonvolatile memory cells C ₁ and C ₂ and MIS type transistors Q ₅ and Q ₆ of the _fifth embodiment can be formed.

  Next, the wiring process will be described with reference to FIG. First, after a silicon nitride film 90 is formed on the semiconductor substrate 50, a silicon oxide film 91 is formed on the silicon nitride film 90. The silicon nitride film 90 and the silicon oxide film 91 can be formed using, for example, a CVD method.

  Subsequently, the surface of the silicon oxide film 91 is polished and planarized by using, for example, a CMP method. Then, a contact hole 92 that opens the silicon oxide film 91 and the silicon nitride film 90 is formed by using a photolithography technique and an etching technique.

  Thereafter, a titanium / titanium nitride film 93 a is formed on the main surface of the semiconductor substrate 50. The titanium / titanium nitride film 93a can be formed by using, for example, a sputtering method.

  Next, a tungsten film 93 b is formed on the main surface of the semiconductor substrate 50 so as to fill the contact hole 92. The tungsten film 93b can be formed by using, for example, a CVD method. Then, an unnecessary titanium / titanium nitride film 93a and tungsten film 93b formed on the silicon oxide film 91 are removed by using, for example, a CMP method, thereby forming a plug 94.

  Subsequently, a titanium / titanium nitride film 95a, an aluminum film 95b, and a titanium / titanium nitride film 95c are sequentially formed on the silicon oxide film 91 and the plug 94. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form a wiring 96. Further, a wiring is formed in an upper layer of the wiring 96, but the description in this specification is omitted.

  According to the fifth embodiment, by reducing the length of the first gate electrode 59 and the sidewall length of the sidewall 64 in the gate length direction, the leakage current is below the end of the first gate electrode 59 and the semiconductor substrate. Even in the case of flowing in the vicinity of the surface of 50, the crystal defect under the end of the first gate electrode 59 can be compensated by nitrogen, so that the leakage current can be reduced. In addition, since the generation of hot holes under the end portion of the first gate electrode 59 can be reduced, it is possible to achieve the reduction of erroneous erasure at the same time.

That is, according to the nonvolatile memory cell C ₁ of the fifth embodiment, it is possible to improve device performance such as reduction of leakage current and erroneous erasure while reducing the memory cell size.

  Similarly, since nitrogen is also introduced under the second gate electrode 69 and the sidewall 81, it is generated between the low-concentration n-type impurity diffusion region 76 formed under the sidewall 81 and the p-type well 54. Leakage current can also be reduced.

Further, in the fifth embodiment, since the nitrogen introduction region 75 is also formed in the nMIS transistor Q ₅ among the transistors constituting the peripheral circuit, the leakage current in the peripheral circuit can also be reduced.

In the fifth embodiment, the nitrogen introduction region 75 is also formed in the nMIS transistor Q ₅ in the peripheral circuit. However, the nitrogen introduction region 75 may not be formed in the transistor in the peripheral circuit.

  Further, similarly to the above-described fourth embodiment, the low-concentration n-type impurity diffusion regions 62 and 63 can be formed first, and the nitrogen introduction region 61 can be formed later. Further, the low-concentration n-type impurity diffusion regions 76, 77, 78 can be formed first, and the nitrogen introduction region 75 can be formed later. Even when the nitrogen introduction regions 61 and 75 are formed in this way, the same effect as in the fourth embodiment can be obtained.

(Embodiment 6)
FIG. 26 shows a cross-sectional view of nonvolatile memory cells C ₃ and C ₄ and MIS type transistors Q ₇ and Q _{8 in} the sixth embodiment formed on a semiconductor chip. In FIG. 26, the left region is a memory cell formation region, and the right region is a peripheral circuit formation region.

First, in the memory cell formation region, a buried layer 102 into which an n-type impurity is introduced is formed in the semiconductor substrate 100, and a p-type well 103 into which a p-type impurity is introduced into the semiconductor substrate 100 on the buried layer 102. Is formed. A nonvolatile memory cell C ₃ and a nonvolatile memory cell C ₄ are formed on the p-type well 103. The buried layer 102 is provided to electrically insulate the semiconductor substrate 100 and the p-type well 103.

On the other hand, in the peripheral circuit formation region, an element isolation region 101 that separates the formation region of the nMIS transistor Q _{7 and} the formation region of the pMIS transistor Q ₈ is formed on the semiconductor substrate 100. Then, the nMIS transistor Q ₇ forming region isolated by the element isolation region 101, p-type well 103 is formed, the pMIS transistor Q ₈ forming region, n-type well 104 is formed. An MIS transistor Q ₇ is formed on the p-type well 103 in the peripheral circuit formation region, and an MIS transistor Q ₈ is formed on the n-type well 104.

Next, the configuration of a nonvolatile memory cell C _3. In the nonvolatile memory cell C ₃ , a gate insulating film (second insulating film) 105 is formed on the p-type well 103, and a second gate electrode 109 is formed on the gate insulating film 105. The second gate electrode 109 is
The polysilicon film 107 and the cobalt silicide film 135 for reducing the resistance are formed. The gate insulating film 105 and the second gate electrode 109 form a cell selection portion (second MIS) of the nonvolatile memory cell C _3. The

  Subsequently, a sidewall 135a is formed on the right side wall of the second gate electrode 109, and a first gate electrode 116 having a sidewall shape is formed on the left side wall. The first gate electrode 116 is formed of a polysilicon film 116a and a cobalt silicide film 135 for reducing resistance.

  Three insulating layers are formed between the sidewall-shaped first gate electrode 116 and the p-type well 103 and between the first gate electrode 116 and the sidewall of the second gate electrode 109. That is, a gate insulating film (first insulating film) 113 is formed in contact with the side walls of the p-type well 103 and the second gate electrode 109, and a charge storage layer 114 is formed on the gate insulating film 113. An insulating film 115 is formed on the charge storage layer 114, and a first gate electrode 116 having a sidewall shape is formed on the insulating film 115.

The gate insulating film 113, the charge storage layer 114, the insulating film 115 and the first gate electrode 116, the memory portion of the nonvolatile memory cell C ₃ (first MIS) is formed. A sidewall 135 a is formed outside the first gate electrode 116.

  Next, a nitrogen introduction region 110 is formed so as to extend outward from below both ends of the second gate electrode 109. A low concentration n-type impurity diffusion region (first impurity region) 111 and an n-type impurity diffusion region 118, which are semiconductor regions, are formed below the nitrogen introduction region 110, and the low concentration n-type impurity diffusion region 111 is formed. An n-type impurity diffusion region 117, which is a semiconductor region, is formed on the outside. A high-concentration n-type impurity diffusion region 128 that is a semiconductor region is formed outside the n-type impurity diffusion region 117. On the other hand, a high-concentration n-type impurity diffusion region 129 that is a semiconductor region is formed outside the n-type impurity diffusion region 118.

  Here, in the nitrogen introduction region 110, the depth at which the concentration of nitrogen becomes maximum is low in the low-concentration n-type impurity diffusion region 111, the n-type impurity diffusion regions 117 and 118, and the high-concentration n-type impurity diffusion regions 128 and 129. Each is shallower than the depth at which the concentration of the n-type impurity is maximum.

A cobalt silicide film 135 is formed on the high-concentration n-type impurity diffusion regions 128 and 129 and outside the sidewall 135a in order to reduce the resistance. Since the nonvolatile memory cell C ₄ has the same configuration as the nonvolatile memory cell C ₃ , the description thereof is omitted.

In the nonvolatile memory cell C ₃ in the sixth embodiment, since the nitrogen introduction region 110 is formed as described above, the dangling bonds existing under the end portions of the first gate electrode 116 and the second gate electrode 109 are not formed. Nitrogen can be bound. Moreover, nitrogen can be filled in the vacancy defects. Therefore, since crystal defects that are likely to be leak paths can be recovered by nitrogen, the leak current of the nonvolatile memory cell C ₃ can be reduced. In addition, since leakage current can be reduced, generation of hot holes due to leakage current can be suppressed, and erroneous erasure due to injection of hot holes into the charge storage layer 114 can be prevented.

Next, the configuration of the MIS transistors Q ₇ and Q ₈ formed in the peripheral circuit formation region is the same as that of the MIS transistors Q ₅ and Q ₆ described in the fifth embodiment. Therefore, the description is omitted.

The nonvolatile memory cells C ₃ and C ₄ and the MIS transistors Q ₇ and Q ₈ in the sixth embodiment are configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 27, the element isolation region 101 is formed on the peripheral circuit formation region of the semiconductor substrate 100. The element isolation region 101 is made of, for example, a silicon oxide film, and is formed by an STI method, a LOCOS method, or the like. 27 shows an element isolation region 101 formed by the STI method in which a groove is formed in the semiconductor substrate 100 and a silicon oxide film is embedded in the formed groove.

  Next, a buried layer 102 is formed in the memory cell formation region of the semiconductor substrate 100. The buried layer 102 can be formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 100 using a photolithography technique and an ion implantation method.

  Subsequently, a p-type well 103 is formed in the memory cell formation region and the nMIS-type transistor formation region in the peripheral circuit formation region by using a photolithography technique and an ion implantation method. The p-type well 103 can be formed, for example, by introducing a p-type impurity such as boron or boron fluoride. Similarly, an n-type well 104 is formed by introducing an n-type impurity such as phosphorus or arsenic into the pMIS transistor formation region in the peripheral circuit formation region.

  Subsequently, a relatively thick gate insulating film (second insulating film) 105 is formed in the memory cell formation region of the semiconductor substrate 100, and a relatively thin gate insulating film 106 is formed in the peripheral circuit formation region of the semiconductor substrate 100. . The gate insulating film 105 and the gate insulating film 106 are made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. In addition, although the example which uses a silicon oxide film was shown as the gate insulating film 105 and the gate insulating film 106, it is not restricted to this, For example, a High-k film | membrane may be sufficient.

  Next, a polysilicon film 107 is formed over the gate insulating film 105 and the gate insulating film 106. The polysilicon film 107 can be formed using, for example, a CVD method. Then, a cap insulating film 108 is formed on the polysilicon film 107 by using, for example, a CVD method.

  Then, after forming a resist film on the cap insulating film 108, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains only in the gate electrode formation region in the memory cell formation region. Then, the second gate electrode 109 is formed by etching using the patterned resist film as a mask.

Subsequently, as shown in FIG. 28, nitrogen is introduced into the memory cell formation region to form a nitrogen introduction region 110. The nitrogen introduction region 110 can be formed using, for example, a photolithography technique and an ion implantation method. Specifically, the nitrogen introduction region 110 can be formed, for example, by introducing nitrogen having an energy of 20 KeV at a dose of 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 29, shallow low-concentration n-type impurity diffusion regions (first impurity regions) 111 and 112 are formed in the memory cell formation region. The low-concentration n-type impurity diffusion regions 111 and 112 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method.

  Thereafter, the introduced impurity is activated by annealing the semiconductor substrate 100. At this time, heat treatment is also applied to the nitrogen introduced into the semiconductor substrate 100, and nitrogen bonds to dangling bonds that exist in the vicinity of the surface of the semiconductor substrate 100. In addition, the crystal defects are recovered by diffusing nitrogen into the vacancy defects.

  Next, a gate insulating film (first insulating film) 113 is formed on the semiconductor substrate 100. The gate insulating film 113 is made of, for example, a silicon oxide film, and can be formed by, for example, a thermal oxidation method. Then, the charge storage layer 114 is formed over the gate insulating film 113. The charge storage layer 114 is made of, for example, a silicon nitride film, and can be formed using, for example, a CVD method. Although an example in which a silicon nitride film is used as the charge storage layer 114 is shown, the present invention is not limited to this, and a film including a trap level in a film such as a silicon oxynitride (SiON) film may be used.

  Subsequently, an insulating film 115 is formed over the charge storage layer 114. The insulating film 115 is made of, for example, a silicon oxide film, and can be formed by, for example, a CVD method. Then, a polysilicon film is formed on the insulating film 115. The polysilicon film can be formed by, for example, a CVD method. Thereafter, the formed polysilicon film is anisotropically etched to form the first gate electrode 116 having a sidewall shape on the side wall of the second gate electrode 109.

  Next, as shown in FIG. 30, the first gate electrode 116 formed on one side wall of the second gate electrode 109 is formed on one side wall by using a photolithography technique and an etching technique. The first gate electrode 116, the exposed gate insulating film 113, the charge storage layer 114, and the insulating film 115 are removed.

  Thereafter, n-type impurity diffusion regions 117, 118, and 119 are formed by using a photolithography technique and an ion implantation method. The n-type impurity diffusion regions 117, 118, and 119 are formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 100.

  Subsequently, as shown in FIG. 31, a cap insulating film 120 is formed on the semiconductor substrate 100. The cap insulating film 120 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method. Then, after a resist film is applied on the cap insulating film 120, the resist film is patterned by exposure and development. The patterning is performed so that the resist film remains only in the gate electrode formation region in the peripheral circuit formation region.

  Next, gate electrodes 121 and 122 are formed in the peripheral circuit formation region by etching using the patterned resist film as a mask.

Subsequently, as shown in FIG. 32, a nitrogen introduction region 123 is formed in the nMIS transistor formation region in the peripheral circuit formation region by using a photolithography technique and an ion implantation method. The nitrogen introduction region 123 is formed by introducing nitrogen in alignment with the gate electrode 121. Specifically, the nitrogen introduction region 123 can be formed, for example, by introducing nitrogen having an energy of 20 KeV at a dose of 10 ¹⁵ / cm ² .

  Thereafter, low-concentration n-type impurity diffusion regions 124 and 125 are formed in the nMIS transistor formation region. The low-concentration n-type impurity diffusion regions 124 and 125 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method. Similarly, low-concentration p-type impurity diffusion regions 126 and 127 are formed in the pMIS transistor formation region.

  Next, an annealing process is performed to activate the introduced conductive impurities. At this time, heat treatment is also applied to the previously introduced nitrogen. Therefore, nitrogen introduced into the nMIS transistor forming region in the peripheral circuit forming region is bonded to the dangling bond of silicon and crystal defects caused by the dangling bond can be recovered.

  Subsequently, as shown in FIG. 26, a silicon oxide film is formed on the semiconductor substrate 100 by using, for example, a CVD method, and then anisotropic etching is performed to form a sidewall 135a.

  Next, high-concentration n-type impurity diffusion regions 128 to 132 and high-concentration p-type impurity diffusion regions 133 and 134 are formed in the semiconductor substrate 100. The high-concentration n-type impurity diffusion regions 128 to 132 can be formed by introducing an n-type impurity such as phosphorus or arsenic using, for example, a photolithography technique and an ion implantation method, and the high-concentration p-type impurity diffusion region 133, 134 can be formed by introducing a p-type impurity such as boron or boron fluoride. Thereafter, annealing is performed to activate the introduced conductive impurities.

  Thereafter, as shown in FIG. 26, for example, a cobalt film is formed as a refractory metal film on the main surface of the semiconductor substrate 100. The cobalt film can be formed using, for example, a sputtering method or a CVD method. Then, after the cobalt silicide film 135 is formed by performing heat treatment, the unreacted cobalt film is removed. The cobalt silicide film 135 is formed for reducing the resistance. Note that a titanium silicide film or a nickel silicide film may be formed by using a titanium film or a nickel film instead of the cobalt film as the refractory metal film.

In this way, the nonvolatile memory cells C ₃ and C ₄ and MIS type transistors Q ₇ and Q ₈ of the sixth embodiment can be formed.

  Next, the wiring process will be described with reference to FIG. First, after a silicon nitride film 136 is formed on the semiconductor substrate 100, a silicon oxide film 137 is formed on the silicon nitride film 136. The silicon nitride film 136 and the silicon oxide film 137 can be formed using, for example, a CVD method.

  Subsequently, the surface of the silicon oxide film 137 is polished and planarized by using, for example, a CMP method. Then, a contact hole 138 opening the silicon nitride film 136 and the silicon oxide film 137 is formed by using a photolithography technique and an etching technique.

  Thereafter, a titanium / titanium nitride film 139 a is formed on the main surface of the semiconductor substrate 100. The titanium / titanium nitride film 139a can be formed by using, for example, a sputtering method.

  Next, a tungsten film 139 b is formed on the main surface of the semiconductor substrate 100 so as to fill the contact hole 138. The tungsten film 139b can be formed by using, for example, a CVD method. Then, the unnecessary titanium / titanium nitride film 139a and the tungsten film 139b formed on the silicon oxide film 137 are removed by using, for example, a CMP method, thereby forming the plug 140.

  Subsequently, a titanium / titanium nitride film 141a, an aluminum film 141b, and a titanium / titanium nitride film 141c are sequentially formed on the silicon oxide film 137 and the plug 140. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique, and the wiring 142 is formed. Further, a wiring is formed in an upper layer of the wiring 142, but the description in this specification is omitted.

  According to the sixth embodiment, even when the leakage current flows under the end of the first gate electrode 116 and near the surface of the semiconductor substrate 100, the crystal defects under the end of the first gate electrode 116 are removed from the nitrogen. Therefore, the leakage current can be reduced. In addition, since generation of hot holes under the end portion of the first gate electrode 116 can be reduced, reduction of erroneous erasure can be achieved at the same time.

  Further, since the nitrogen introduction region 110 is also provided under the end portion of the second gate electrode 109, crystal defects around the end portion of the second gate electrode 109 can be recovered by nitrogen. Therefore, the leakage current under the end of the second gate electrode 109 can be reduced.

Further, since the nitrogen introduction region 123 is also provided in the MIS transistor Q ₇ in the peripheral circuit, the leakage current in the peripheral circuit can also be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Similarly to the idea of the fourth embodiment described above, the low concentration n-type impurity diffusion regions 111 and 112 can be formed first, and the nitrogen introduction region 110 can be formed later. Even when the nitrogen introduction region 110 is formed in this manner, the same effect as in the fourth embodiment can be obtained.

  Although the MONOS transistor has been described in the above embodiment, the present invention is not limited to this, and the present invention may be applied to, for example, an MNOS transistor.

  The present invention is used, for example, in the manufacturing industry for manufacturing IC cards that are nonvolatile semiconductor memory devices.

FIG. 3 is a circuit configuration diagram showing memory cells arranged two-dimensionally, and is a diagram describing voltages applied when a write operation is performed on a specific memory cell. FIG. 5 is a circuit configuration diagram showing memory cells arranged in a two-dimensional manner, and is a diagram describing voltages applied when performing an erase operation of a specific memory cell. FIG. 3 is a circuit configuration diagram showing memory cells arranged two-dimensionally, and is a diagram describing voltages applied when a specific memory cell is read. FIG. 5 is a diagram showing a path of leakage current generated in a MONOS transistor having a relatively long sidewall length and a region where impact ionization occurs most. FIG. 5 is a diagram showing a path of a leakage current generated in a MONOS transistor having a relatively short sidewall length and a region where an impact ionization phenomenon occurs most frequently. It is the figure which showed electric field distribution which arises in a MONOS type transistor with a comparatively short side wall length. 1 is a cross-sectional view showing a nonvolatile memory cell and a peripheral circuit in Embodiment 1 of the present invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 1 of this invention. FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 3 of this invention. It is sectional drawing which showed the non-volatile memory cell and peripheral circuit in Embodiment 5 of this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 5 of this invention. FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 19; FIG. 21 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; It is sectional drawing which showed the non-volatile memory cell and peripheral circuit in Embodiment 6 of this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 6 of this invention. FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 31; It is a figure for demonstrating degradation by NBTI.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Well isolation layer 4 P-type well 5 Gate insulating film (1st insulating film)
6 Charge storage layer 7 Insulating film 8 Gate electrode (first conductor layer)
8a Polysilicon film 9 Cap insulating film 9a Silicon oxide film 10 P-type well 11 N-type well 12 Gate insulating film (second insulating film)
13 Gate insulating film 14 Polysilicon film 15 Cap insulating film 16 Gate electrode (second conductor layer)
17 Gate electrode 18 Gate electrode 20 Nitrogen introduction region 21 Low-concentration n-type impurity diffusion region (first impurity region)
22 Low-concentration n-type impurity diffusion region (first impurity region)
23 Low-concentration n-type impurity diffusion region (first impurity region)
24 Low-concentration n-type impurity diffusion region 25 Low-concentration n-type impurity diffusion region 26 Low-concentration p-type impurity diffusion region 27 Low-concentration p-type impurity diffusion region 28 Side wall (third insulating film)
29 High-concentration n-type impurity diffusion region (second impurity region)
30 High-concentration n-type impurity diffusion region (second impurity region)
31 High-concentration n-type impurity diffusion region (second impurity region)
32 High-concentration n-type impurity diffusion region 33 High-concentration n-type impurity diffusion region 34 High-concentration p-type impurity diffusion region 35 High-concentration p-type impurity diffusion region 36 Cobalt silicide film 37 Silicon nitride film 38 Silicon oxide film 39 Contact hole 40a Titanium / Titanium nitride film 40b Tungsten film 41 Plug 42a Titanium / titanium nitride film 42b Aluminum film 42c Titanium / titanium nitride film 43 Wiring 50 Semiconductor substrate 51 Element isolation region 52 First buried layer 53 Second buried layer 54 p-type well 55 n-type well 56 Gate insulation film (first insulation film)
57 charge storage layer 58 insulating film 59 first gate electrode (first conductor layer)
60 Cap insulating film 61 Nitrogen introduction region 62 Low-concentration n-type impurity diffusion region (first impurity region)
63 Low-concentration n-type impurity diffusion region (first impurity region)
64 sidewall (third insulating film)
65 Gate insulating film (second insulating film)
66 Gate insulating film 67 Polysilicon film 68 Cap insulating film 69 Second gate electrode (second conductor layer)
71 Gate electrode 73 Gate electrode 75 Nitrogen introduction region 76 Low-concentration n-type impurity diffusion region (first impurity region)
77 Low-concentration n-type impurity diffusion region 78 Low-concentration n-type impurity diffusion region 79 Low-concentration p-type impurity diffusion region 80 Low-concentration p-type impurity diffusion region 81 Side wall 82 High-concentration n-type impurity diffusion region (second impurity region)
83 High-concentration n-type impurity diffusion region (second impurity region)
84 High-concentration n-type impurity diffusion region (second impurity region)
85 High-concentration n-type impurity diffusion region 86 High-concentration n-type impurity diffusion region 87 High-concentration p-type impurity diffusion region 88 High-concentration p-type impurity diffusion region 89 Cobalt silicide film 90 Silicon nitride film 91 Silicon oxide film 92 Contact hole 93a Titanium / Titanium nitride film 93b Tungsten film 94 Plug 95a Titanium / titanium nitride film 95b Aluminum film 95c Titanium / titanium nitride film 96 Wiring 100 Semiconductor substrate 101 Element isolation region 102 Buried layer 103 P type well 104 N type well 105 Gate insulating film (second film) Insulating film)
106 Gate insulating film 107 Polysilicon film 108 Cap insulating film 109 Second gate electrode (second conductor layer)
110 Nitrogen introduction region 111 Low-concentration n-type impurity diffusion region (first impurity region)
112 Low-concentration n-type impurity diffusion region (first impurity region)
113 Gate insulating film (first insulating film)
114 charge storage layer 115 insulating film 116 first gate electrode (first conductor layer)
116a Polysilicon film 117 n-type impurity diffusion region 118 n-type impurity diffusion region 119 n-type impurity diffusion region 120 cap insulating film 121 gate electrode 122 gate electrode 123 nitrogen introduction region 124 low-concentration n-type impurity diffusion region 125 low-concentration n-type impurity Diffusion region 126 Low-concentration p-type impurity diffusion region 127 Low-concentration p-type impurity diffusion region 128 High-concentration n-type impurity diffusion region (second impurity region)
129 High concentration n-type impurity diffusion region (second impurity region)
130 High-concentration n-type impurity diffusion region (second impurity region)
131 High-concentration n-type impurity diffusion region 132 High-concentration n-type impurity diffusion region 133 High-concentration p-type impurity diffusion region 134 High-concentration p-type impurity diffusion region 135 Cobalt silicide film 135a Side wall (third insulating film)
136 Silicon nitride film 137 Silicon oxide film 138 Contact hole 139a Titanium / titanium nitride film 139b Tungsten film 140 Plug 141a Titanium / titanium nitride film 141b Aluminum film 141c Titanium / titanium nitride film 142 Wiring Q ₁ MONOS type transistor Q ₂ MIS type transistor Q ₃ MIS transistor Q ₄ MIS transistor Q ₅ MIS transistor Q ₆ MIS transistor Q ₇ MIS transistor Q ₈ MIS transistor C ₁ nonvolatile memory cell C ₂ nonvolatile memory cell C ₃ nonvolatile memory cell C ₄ nonvolatile Memory cell

Claims (21)

(A) a first insulating film formed on a semiconductor substrate;
(B) a charge storage layer formed on the first insulating film;
(C) a first conductor layer formed on the charge storage layer;
(D) a first impurity region formed in the semiconductor substrate;
(E) a nitrogen introduction region formed in the semiconductor substrate;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, further comprising:
(F) a second insulating film formed on the semiconductor substrate;
(G) a second conductor layer formed on the second insulating film;
Have
The semiconductor device, wherein the first impurity region and the nitrogen introduction region are formed in the semiconductor substrate between the first conductor layer and the second conductor layer. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the maximum concentration peak of the nitrogen introduction region is formed at a position shallower than the maximum concentration peak of the first impurity region. The semiconductor device according to claim 1,
A third insulating film formed on a sidewall of the first conductor layer;
A second impurity region formed on the semiconductor substrate and formed at a higher concentration than the impurity concentration of the first impurity region;
Have
The semiconductor device according to claim 1, wherein the nitrogen introduction region is formed at least under the third insulating film. The semiconductor device according to claim 4,
The maximum concentration peak of the nitrogen introduction region is formed at a position shallower than the maximum concentration peaks of the first impurity region and the second impurity region. The semiconductor device according to claim 1,
A semiconductor device, wherein data is written by injecting electrons into the charge storage layer. The semiconductor device according to claim 1,
A semiconductor device, wherein the charge storage layer is formed of a silicon nitride film. (A) a charge storage layer formed on a semiconductor substrate;
(B) a first conductor layer formed on the charge storage layer;
(C) a first impurity region formed in the semiconductor substrate;
Have
The semiconductor device, wherein the first impurity region contains nitrogen. A semiconductor device including a nonvolatile memory cell having a first MIS and a second MIS,
(A) a first insulating film of the first MIS formed on a semiconductor substrate;
(B) a charge storage layer formed on the first insulating film;
(C) a first gate electrode of the first MIS formed on the charge storage layer;
(D) a second insulating film of the second MIS formed on the semiconductor substrate;
(E) a second gate electrode of the second MIS formed on the second insulating film;
(F) a first impurity region formed in the semiconductor substrate;
(G) a nitrogen introduction region formed on the semiconductor substrate at least between the first gate electrode and the second gate electrode;
A semiconductor device comprising: The semiconductor device according to claim 9.
A third insulating film formed on a sidewall of the first gate electrode;
A second impurity region formed on the semiconductor substrate and formed at a higher concentration than the impurity concentration of the first impurity region;
Have
The semiconductor device according to claim 1, wherein the first impurity region and the nitrogen introduction region are formed under the third insulating film. The semiconductor device according to claim 9.
A semiconductor device, wherein data is written by injecting electrons into the charge storage layer. The semiconductor device according to claim 9.
A semiconductor device, wherein the charge storage layer is formed of a silicon nitride film. A method of manufacturing a semiconductor device comprising the following steps:
(A) forming a first insulating film on the semiconductor substrate;
(B) forming a charge storage layer on the first insulating film;
(C) forming a first conductor layer on the charge storage layer;
(D) introducing nitrogen into the semiconductor substrate by ion implantation to form a nitrogen introduction region;
(E) A step of forming a first impurity region by introducing impurities into the semiconductor substrate by ion implantation. In the manufacturing method of the semiconductor device according to claim 13,
The method of manufacturing a semiconductor device, wherein the maximum concentration peak of the nitrogen introduction region is formed to be shallower than the maximum concentration peak of the first impurity region. The method of manufacturing a semiconductor device according to claim 13, further comprising: (f) forming a third insulating film on a sidewall of the first conductor layer;
(G) forming a second impurity region having a higher concentration than the first impurity region by introducing an impurity into the semiconductor substrate in alignment with the third insulating film;
Have
The method of manufacturing a semiconductor device, wherein the nitrogen introduction region is formed at least under the third insulating film. In the manufacturing method of the semiconductor device according to claim 15,
A method of manufacturing a semiconductor device, wherein the maximum concentration peak of the nitrogen introduction region is formed to be shallower than the maximum concentration peaks of the first impurity region and the second impurity region. 14. The method of manufacturing a semiconductor device according to claim 13, further comprising:
(F) forming a second insulating film on the semiconductor substrate;
(G) forming a second conductor layer on the second insulating film;
Have
The method of manufacturing a semiconductor device, wherein the steps (d) and (e) are performed after the steps (a), (b), (c), (f), and (g). 14. The method of manufacturing a semiconductor device according to claim 13, further comprising:
(F) forming a second insulating film on the semiconductor substrate;
(G) forming a second conductor layer on the second insulating film;
Have
The steps (d) and (e) are performed after the steps (a), (b) and (c) and before the steps (f) and (g). Method. 14. The method of manufacturing a semiconductor device according to claim 13, further comprising:
(F) forming a second insulating film on the semiconductor substrate;
(G) forming a second conductor layer on the second insulating film;
Have
The steps (d) and (e) are performed after the steps (f) and (g) and before the steps (a), (b) and (c). Method. In the manufacturing method of the semiconductor device according to claim 13,
The method of manufacturing a semiconductor device, wherein the step (d) is performed before the step (e). In the manufacturing method of the semiconductor device according to claim 13,
The method for manufacturing a semiconductor device, wherein the step (e) is performed before the step (d).

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