JP2011096772A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance of a semiconductor device having a nonvolatile memory. <P>SOLUTION: The semiconductor device includes the nonvolatile memory NVM1 arranged on a silicon substrate 1. The nonvolatile memory NVM1 includes a memory gate insulating film MI1 and a memory gate electrode MG1 formed sequentially on the silicon substrate 1. The memory gate insulating film MI1 is formed of three-layer laminated insulating film of a lower barrier film BB1 mainly containing silicon oxide, a charge retention film CS1 mainly containing silicon nitride, and an upper barrier film TB1 mainly containing silicon oxynitride. Especially a ratio of the silicon oxide out of the silicon oxynitride in the upper barrier film TB1 is higher than 0.46 and is lower than 0.92. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to a semiconductor device having a nonvolatile memory.

  LSI (Large Scale Integrated Circuit) integrated with semiconductor elements is used to control various systems, and is an infrastructure that supports society. Since the operation of an LSI is based on performing arithmetic processing according to a program, in many cases, it is an essential condition that the program can be stored. As a semiconductor element for this purpose, there is an LSI in which an integrated circuit composed of a field effect transistor (hereinafter simply referred to as MIS transistor) having a MIS (Metal-Insulator-Semiconductor) structure and a non-volatile memory which is one of semiconductor memories. It is becoming important. In order to use LSI for various applications, it is necessary to change the program so that it can be rewritten, and a nonvolatile memory that can be rewritten and that retains stored information even when the semiconductor device is turned off is installed. Is desired.

  As a typical nonvolatile memory, there are a so-called floating gate type memory and a memory using an insulating film as a charge storage layer. Among the latter, non-volatile memories of the type in which insulating films are stacked and charges are accumulated at their interfaces and charge trap levels (traps) in the films form a new conductive layer like floating type memories. There is no need. From this advantage, a nonvolatile memory can be formed with good consistency with a process of forming an integrated circuit based on an existing complementary metal-oxide-semiconductor (CMOS) configuration.

  As the insulating film that can be a charge storage layer as described above, a stacked film in which the upper and lower sides of the silicon nitride film are sandwiched between the silicon oxide films is applied because both charge retention characteristics and rewrite characteristics can be achieved. Such a nonvolatile memory including a laminated insulating film in which a silicon nitride film is sandwiched between silicon oxide films is called a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory.

  A typical example of the MONOS type memory is a two-transistor cell in which a memory transistor and a selection transistor are connected in series. The memory transistor uses an FN (Fowler-Nordheim) tunnel current and a direct tunnel current generated by applying (biasing) a potential difference between the channel and the gate electrode, so that charge is injected and released over the entire surface of the channel. It has become.

  Such a non-volatile memory is required to have good charge injection / discharge performance for information rewriting at high speed, while being required to have sufficient charge retention characteristics for information retention. Such a request is one cause of various problems. More specifically, for example, if the laminated insulating film is made thick in order to ensure charge retention characteristics, it becomes difficult to inject charges for writing / erasing, and the time for writing / erasing operations exceeds the practical range.

  On the other hand, for example, in US Pat. No. 6,215,148 (Patent Document 1), instead of releasing charges, two kinds of charges (electrons and holes (also referred to as holes)) having different signs are used as hot carriers. A technique for rewriting stored information by injection is disclosed. By performing hot carrier injection, charge injection can be performed efficiently even with a thick insulating film. According to this method, electrons and holes can be locally and alternately injected. Therefore, it is possible to create different charge injection states at the ends of the planar MOS transistor in the channel direction, that is, in the vicinity of the source and drain, and read out the charge information.

  Further, for example, US Pat. No. 5,969,383 (Patent Document 2) and US Pat. No. 6,477,084 (Patent Document 3) disclose a nonvolatile memory called a split gate structure as another example of the MONOS type memory. .

  Also, for example, Japanese Patent Laying-Open No. 2005-347679 (Patent Document 4) discloses a technique for forming a top silicon oxide film using ozone oxidation not containing hydrogen in the process of forming a MONOS type memory. Yes.

  Further, for example, Japanese Patent Application Laid-Open No. 2008-270343 (Patent Document 5) discloses a nonvolatile semiconductor memory device having a structure using a silicon oxynitride film as a charge storage film.

  Further, for example, in “IEEE ELECTRON DEVICE LETTERS” VOL.29, ISSUE8, pp.920-922, 2008 (Non-Patent Document 1), the charge trapping capability can be maintained. Reference is made to the conditions of the silicon nitride film.

US Pat. No. 6,215,148 US Pat. No. 5,969,383 US Pat. No. 6,477,084 JP 2005-347679 A JP 2008-270343 A

"IEEE ELECTRON DEVICE LETTERS" VOL.29, ISSUE8, pp.920-922, 2008

  In the MONOS type memory by the hot carrier system examined by the present inventors, the structure of the MIS transistor is basically applied. More specifically, in the MONOS type memory investigated by the present inventors, a silicon oxide film used as a gate insulating film in a normal MIS transistor is a three-layer insulating film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The stacked insulating film portion is used as a charge storage layer. In addition, as a configuration method of the memory array, a structure in which the source / drain is formed under a thick element isolation oxide film, a structure in which the source / drain is formed in a line shape in the extending direction of the gate electrode, and the like are considered. It has been. In any memory array, when attention is paid to one memory cell, in many cases, the basic memory cell operation is the same.

  Here, in the case of a carrier injection method using hot carriers, even if the insulating film (silicon oxide film) between the silicon substrate and the silicon nitride film as the charge holding film is thick, the injection can be performed efficiently. it can. This is because the hot carrier energy has energy comparable to the magnitude of the barrier potential of the insulating film measured from above the band edge of silicon. Therefore, by adopting the hot carrier injection method in the MONOS type memory, it is possible to realize a nonvolatile memory that achieves both good charge retention characteristics and high-efficiency rewriting characteristics.

  However, further studies by the present inventors have revealed that the MONOS type memory employing the carrier injection method using hot carriers has the following problems. That is, it has been found that the threshold voltage varies and varies. According to the verification by the present inventors, in the MONOS type memory, hot carriers in a high energy state are injected into the charge retention film from the substrate side through the insulating film, so that the interface between the substrate and the insulating film is obtained. Has been found to cause a number of defects.

  Then, carriers are trapped (trapped) by such interface defects, which causes a variation in threshold voltage. Since the defect level (interface level) formed at the interface recovers with time, the S value (subthreshold swing value) of the memory transistor gradually decreases from the state immediately after the writing and erasing operations, and is large. One cause of threshold fluctuation.

  In particular, since the band offset of silicon oxide film, which is a gate insulating film directly above the channel, with respect to silicon is higher with respect to holes than with electrons, higher energy is required for hot hole injection. For this reason, defects generated at the interface between the channel and the insulating film become more prominent during hot hole injection.

  As described above, since the MONOS type memory by the hot carrier injection method examined by the present inventors causes variations in threshold voltage and time fluctuation, it is impossible to realize high performance of an LSI equipped with such a MONOS type memory. It turns out that it has a problem.

  Therefore, an object of the present invention is to provide a technique for improving the performance of a semiconductor device having a nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A plurality of inventions are disclosed in the present application. An outline of an embodiment of the invention will be briefly described as follows.

  A semiconductor device having a nonvolatile memory disposed on a semiconductor substrate, wherein the nonvolatile memory includes a first gate insulating film formed on the semiconductor substrate and a first gate formed on the first gate insulating film. Electrode. The first gate insulating film is composed of a laminated film including three layers of a first barrier film, a charge holding film, and a second barrier film in order from the side closer to the semiconductor substrate. The first barrier film is an insulating film mainly composed of silicon oxide, the charge retention film is an insulating film mainly composed of silicon nitride, and the second barrier film is an insulating film mainly composed of silicon oxynitride. In particular, in the second barrier film, the ratio of silicon oxide in silicon oxynitride is greater than 0.46 and not greater than 0.92.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the performance of a semiconductor device having a nonvolatile memory can be improved.

FIG. 3 is a cross-sectional view of main parts of the semiconductor device according to the first embodiment of the present invention, from the left along the A1-A1 line, the B1-B1 line, and the C1-C1 line of the main part plan view of FIG. It is principal part sectional drawing seen in the arrow direction. 1 is a main part plan view of a semiconductor device according to a first embodiment of the present invention; It is explanatory drawing for demonstrating operation | movement of the semiconductor device of Embodiment 1 of this invention. FIG. 4 is another explanatory diagram for explaining the same operation as that described with reference to FIG. 3. It is explanatory drawing for demonstrating other operation | movement of the semiconductor device of Embodiment 1 of this invention. FIG. 6 is another explanatory diagram for explaining an operation similar to the operation described with reference to FIG. 5. It is a graph for demonstrating the characteristic of the semiconductor device of Embodiment 1 of this invention. It is a graph for demonstrating the other characteristic of the semiconductor device of Embodiment 1 of this invention. It is a graph for demonstrating the further another characteristic of the semiconductor device of Embodiment 1 of this invention. FIG. 3 is a cross-sectional view of main parts during the manufacturing process of the semiconductor device according to the first embodiment of the present invention, from the left, A1-A1 line, B1-B1 line, and C1-C1 of the main part plan view of FIG. It is principal part sectional drawing seen in the arrow direction along the location applicable to a line. FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; It is a graph for demonstrating the further another characteristic of the semiconductor device of Embodiment 1 of this invention. FIG. 3 is a cross-sectional view of main parts of a semiconductor device according to a second embodiment of the present invention, from the left along the A1-A1 line, B1-B1 line, and C1-C1 line of the main part plan view of FIG. It is principal part sectional drawing seen in the arrow direction. FIG. 3 is a cross-sectional view of main parts during a manufacturing process of a semiconductor device according to a second embodiment of the present invention, from the left, A1-A1 line, B1-B1 line, and C1-C1 of the main part plan view of FIG. It is principal part sectional drawing seen in the arrow direction along the location applicable to a line. FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; It is a graph for demonstrating the characteristic of the semiconductor device of Embodiment 2 of this invention. 29 is a cross-sectional view of a main part of the semiconductor device according to the third embodiment of the present invention, the left is the A2-A2 line of the main part plan view of FIG. 29, and the right is B2-B2 of the main part plan view of FIG. It is principal part sectional drawing seen in the arrow direction along the line. It is a principal part top view of the semiconductor device which is Embodiment 3 of this invention. 29 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention during the manufacturing process, wherein the left side is the A2-A2 line of the major part plan view of FIG. 29 and the right is the major part plan view of FIG. It is principal part sectional drawing seen in the arrow direction along the location applicable to line B2-B2. FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; It is a principal part top view of the semiconductor device which the present inventors examined. 41 is a main-portion cross-sectional view of the semiconductor device shown in FIG. 40, taken along the line Ax-Ax in the arrow direction. FIG. It is explanatory drawing for demonstrating operation | movement of the semiconductor device which the present inventors examined. It is explanatory drawing for demonstrating other operation | movement of the semiconductor device which the present inventors examined. It is explanatory drawing for demonstrating other operation | movement of the semiconductor device which the present inventors examined. It is explanatory drawing for demonstrating other operation | movement of the semiconductor device which the present inventors examined. It is a principal part top view of the other semiconductor device which the present inventors examined. FIG. 47 is a main-portion cross-sectional view of the semiconductor device shown in FIG. FIG. 47 is another equivalent circuit diagram of the semiconductor device shown in FIG. 46, which is another semiconductor device studied by the present inventors. 46 is another semiconductor device investigated by the present inventors, and is another equivalent circuit diagram of the semiconductor device shown in FIG. 46. FIG. It is explanatory drawing for demonstrating operation | movement of the other semiconductor device which the present inventors examined. It is explanatory drawing for demonstrating other operation | movement of the other semiconductor device which the present inventors examined. It is explanatory drawing for demonstrating the characteristic of the other semiconductor device which the present inventors examined.

  Components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, first, the problems found in the semiconductor device having the structure studied by the present inventors will be described in detail.

  First, the structure of the semiconductor device studied by the present inventors will be described with reference to FIGS. FIG. 40 shows a plan view of the main part of the semiconductor device, and FIG. 41 shows a cross-sectional view of the main part viewed in the direction of the arrow along the Ax-Ax line. In these drawings, some insulating films and contact mechanisms are omitted.

  The nonvolatile memory NVMa included in the semiconductor device first examined by the present inventors is formed on a p-type silicon substrate 100. The nonvolatile memory NVMa has a pair of diffusion layers 200 and 300, a memory gate insulating film 400, and a memory gate electrode 500 that constitute a source / drain. The memory gate electrode 500 is disposed on the silicon substrate 100 with the memory gate insulating film 400 interposed therebetween, and a pair of diffusion layers 200 and 300 are formed on the silicon substrate 100 below both side walls of the memory gate electrode 500. A contact 600 is formed on the diffusion layers 200 and 300 and the memory gate electrode 500.

  Here, the memory gate insulating film 400 has a laminated structure of three insulating films. More specifically, the memory gate insulating film 400 has a three-layer stacked structure of a lower silicon oxide film 401, a silicon nitride film 402, and an upper silicon oxide film 403 in order from the side closer to the silicon substrate 100. The memory gate insulating film 400 becomes a charge storage film, and a memory operation can be realized by transferring charges. As described above, the semiconductor device first studied by the present inventors is a MONOS type memory having a single gate structure including one gate electrode (memory gate electrode 500). Hereinafter, the operation method will be described in detail.

  42 to 45 are explanatory diagrams for explaining the operation of the nonvolatile memory NVMa. These drawings show portions corresponding to the cross-sectional view of the main part of FIG.

  The write operation of the nonvolatile memory NVMa that is a MONOS type memory having a single gate structure will be described with reference to FIG. At the time of writing, 15 V is applied to the memory gate electrode 500 (word line WL), 0 V is applied to the diffusion layer 200 (first bit line BL1), and 5 V is applied to the diffusion layer 300 (second bit line BL2). At this time, the electrons EN accelerated by the electric field of the channel enter a hot carrier state and are injected into the memory gate insulating film 400 near the end of the diffusion layer 300 to which a positive voltage is applied. The electrons EN injected into the memory gate insulating film 400 are captured (trapped) by a defect level of the silicon nitride film 402 and held in the memory gate insulating film 400. As a method for generating such hot carriers, a method using an avalanche phenomenon, a method using substrate bias acceleration, and the like are known. If the nonvolatile memory NVMa is viewed as an n-channel MIS transistor, the threshold voltage of the transistor increases in a state where electrons EN are injected into the memory gate insulating film 400 as described above. Thereby, the charge accumulation state can be identified. The read operation will be described in detail later.

  The erase operation of the nonvolatile memory NVMa, which is a MONOS type memory having a single gate structure, will be described with reference to FIG. At the time of erasing, -6V is applied to the memory gate electrode 500 (word line WL), 0V is applied to the diffusion layer 200 (first bit line BL1), and 6V is applied to the diffusion layer 300 (second bit line BL2). At this time, holes HL are generated at the end of the diffusion layer 300 due to a band-to-band tunneling (BTBT) phenomenon. Then, the holes HL are accelerated by the potential difference between the diffusion layer 300 and the silicon substrate 100, so that the holes HL are injected into the memory gate insulating film 400. If the nonvolatile memory NVMa is viewed as an n-channel MIS transistor, the threshold voltage of the transistor drops in a state where holes HL are injected into the memory gate insulating film 400 as described above. Thereby, the charge accumulation state can be identified. That is, as described above, if the state in which the threshold voltage is increased is set as the write state, the state in which the threshold voltage is decreased can be classified as the erased state. The read operation will be described in detail later.

  The read operation of the nonvolatile memory NVMa that is a MONOS type memory having a single gate structure will be described with reference to FIG. At the time of reading, 3V is applied to the memory gate electrode 500 (word line WL), 1V is applied to the diffusion layer 200 (first bit line BL1), and 0V is applied to the diffusion layer 300 (bit line BL2). Under this condition, the drain current ID is measured in the nonvolatile memory NVMa as an n-channel MIS transistor. Here, when electrons EN are injected near the end of the diffusion layer 300 in the memory gate insulating film 400 (the writing state in FIG. 42), the threshold voltage is high and the drain current ID is very small. On the other hand, when holes HL are injected near the end of the diffusion layer 300 in the memory gate insulating film 400 (the erased state in FIG. 43), the threshold voltage is low and a large drain current ID flows. In this way, the writing state or erasing state of the nonvolatile memory NVMa can be read.

  In the case of the MONOS type memory having the single gate structure as described above, the level of the threshold voltage is strongly influenced by the charge injected into the end of the diffusion layer on the source side at the time of reading, and at the end of the diffusion layer on the drain side. It is not so strongly dependent on the charge state. Therefore, one memory cell can also be used as a 2-bit storage element by using the above-described diffusion layer 200 and diffusion layer 300 interchangeably. FIG. 45 shows a state in which holes HL are held at the end on the diffusion layer 200 side and electrons EN are held at the end on the diffusion layer 300 side in the memory gate insulating film 400. In this state, for example, 3V is applied to the memory gate electrode 500 (word line WL), 0V is applied to the diffusion layer 200 (first bit line BL1), and 1V is applied to the diffusion layer 300 (second bit line BL2). At this time, since the charge state of the memory gate insulating film 400 in the vicinity of the diffusion layer 200 on the source side is reflected in the drain current ID, the state in which holes HL are injected, that is, the erased state is read out. If the voltages applied to both diffusion layers 200 and 300 are reversed, the charge state of the memory gate insulating film 400 in the vicinity of the diffusion layer 300 can be read.

  In addition, the structure of the semiconductor device studied by the present inventors will be described with reference to FIGS. FIG. 46 shows a plan view of the main part of the semiconductor device, and FIG. 47 shows a cross-sectional view of the main part viewed in the direction of the arrow along the Ay-Ay line. In these drawings, some insulating films and contact mechanisms are omitted.

  The non-volatile memory NVMb included in the semiconductor device examined next by the present inventors is formed on a p-type silicon substrate 100. The nonvolatile memory NVMb includes a pair of n-type semiconductor regions constituting the source / drain, such as diffusion layers 200 and 300, a memory gate insulating film 400, a memory gate electrode 500, a select gate insulating film 700, and a select gate electrode 800. Have. The memory gate electrode 500 is disposed on the silicon substrate 100 via the memory gate insulating film 400, and the selection gate electrode 800 is disposed on the silicon substrate 100 via the selection gate insulating film 700. Further, the memory gate electrode 500 and the select gate electrode 800 are arranged adjacent to each other on the silicon substrate 100. However, the memory gate insulating film 400 is disposed between the memory gate electrode 500 and the selection gate electrode 800 so that they are insulated from each other. A pair of diffusion layers 200 and 300 are formed on the silicon substrate 100 below the side walls on the side where the memory gate electrode 500 and the selection gate electrode 800 are not adjacent to each other. A contact 600 is formed on the diffusion layers 200 and 300, the memory gate electrode 500 and the selection gate electrode 800.

  Here, the memory gate insulating film 400 has a laminated structure of three insulating films. More specifically, the memory gate insulating film 400 has a three-layer stacked structure of a lower silicon oxide film 401, a silicon nitride film 402, and an upper silicon oxide film 403 in order from the side closer to the silicon substrate 100. The memory gate insulating film 400 becomes a charge storage film, and a memory operation can be realized by transferring charges. Note that the selection gate insulating film 700 is a silicon oxide film. Thus, the semiconductor device first examined by the present inventors is a MONOS type memory having a split gate structure including two gate electrodes (memory gate electrode 500 and select gate electrode 800). Hereinafter, the operation method will be described in detail.

  The split gate MONOS type memory basically has two MIS transistors (a memory transistor 510 and a selection transistor 810) based on an n-channel type MIS transistor, and the memory transistors are stacked vertically next to the selection transistor. Linked in state. FIG. 48 shows this state with an equivalent circuit. FIG. 49 shows an equivalent circuit showing a circuit configuration of a memory cell array using the memory cell. Each of the gate electrodes (memory gate electrode 500 and selection gate electrode 800) of the memory transistor 510 and the selection transistor 810 has a selection gate word line SGL (represented by reference numerals SGL0 to SGL3 in the drawing) and a memory. They are connected by a gate word line MGL (represented by reference numerals MGL0 to MGL3 in the figure). Further, the diffusion layer 200 on the selection transistor 810 side is connected by a bit line BL (represented by reference numerals BL0 and BL1 in the figure), and the diffusion layer 300 on the memory transistor 510 side is connected to a source line SL (in the figure). (Represented by symbols SL0 and SL1).

  The basic operation of such a nonvolatile memory NVMb includes four states: (1) write operation, (2) erase operation, (3) hold, and (4) read operation. However, the names of these four states are used as representative ones, and the reverse names can be used for writing and erasing. Although the operation will be described using typical ones, various operations are considered as the operation of the MONOS type memory having the split gate structure. Here, a memory cell constituted by two n-channel type MIS transistors (memory transistor 510 and selection transistor 810) will be described. However, even a memory cell constituted by two p-channel type MIS transistors is in principle. Can be described as a similar operation.

  The write operation of the nonvolatile memory NVMb, which is a split-gate structure MONOS type memory, will be described with reference to FIG. In the write operation, a positive potential is applied to the diffusion layer 300 on the memory gate electrode 500 side, and the same ground potential as that of the silicon substrate 100 is applied to the diffusion layer 200 on the selection gate electrode 800 side. By applying a high gate overdrive voltage to the memory gate electrode 500 with respect to the silicon substrate 100, the channel under the memory gate electrode 500 is turned on (an inversion layer is formed in the silicon substrate 100 under the memory gate electrode 500). ). Here, by setting the voltage of the selection gate electrode 800 to a value higher by 0.1 to 0.2 V than the specified threshold voltage, this is also turned on (an inversion layer is formed on the silicon substrate 100 under the selection gate electrode 800). To form). At this time, since the strongest electric field is generated in the vicinity of the boundary between the gate electrodes 500 and 800, many hot electrons are generated. The hot electrons are attracted to the positive potential of the memory gate electrode 500 and injected into the memory gate insulating film 400. Further, as shown in the main part 900 under the memory gate electrode 500, an electron EN and a hole HL (electron hole pair) are generated by impact ionization, and the electron EN of these is also a positive potential of the memory gate electrode 500. And is injected into the memory gate insulating film 400. The above phenomenon is referred to as source side injection (SSI).

  As a feature of hot electron injection by the SSI method, since the electric field is concentrated near the boundary between the memory gate electrode 500 and the selection gate electrode 800, electrons EN are concentratedly injected into the end portion of the memory gate insulating film 400 on the selection gate electrode 800 side. May be. For example, in the floating gate type memory, the charge holding layer is formed of a conductive film. However, in the MONOS type memory, charges are accumulated in the insulating film. Combining these two characteristics, the MONOS type memory having the split gate structure holds electrons EN in a very narrow area. In a state where the electrons EN are held in the memory gate insulating film 400, the threshold voltage of the memory transistor 510 that is an n-channel MIS transistor increases. This state is referred to as a write state.

  The erase operation of the nonvolatile memory NVMb, which is a MONOS type memory having a split gate structure, will be described with reference to FIG. In the erase operation, a negative potential is applied to the memory gate electrode 500 and a positive potential is applied to the diffusion layer 300 on the memory gate electrode 500 side. As a result, strong inversion occurs in a region where the memory gate electrode 500 and the diffusion layer 300 in the vicinity of the end of the diffusion layer 300 overlap, thereby causing a BTBT phenomenon and generating a hot hole (hole HL). Let In this memory cell, the generated holes are accelerated in the channel direction, drawn by the negative bias of the memory gate electrode 500, and injected into the memory gate insulating film 400. Further, as shown in the main part 901, the generated holes HL can generate secondary electron-hole pairs. Of these electron-hole pairs, the hole HL is also attracted to the negative potential of the memory gate electrode 500 and injected into the memory gate insulating film 400. That is, the threshold voltage of the memory transistor 510 that has been increased by the charge of the electrons EN is decreased by the injection of the holes HL by the above-described write operation. This state is referred to as an erased state.

  At the time of charge retention, the charge is retained as the charge of carriers injected into the memory gate insulating film 400. In the memory gate insulating film 400 composed of three layers of silicon oxide film / silicon nitride film / silicon oxide film, electric charges are held at a defect level or the like in the silicon nitride film. In addition, the silicon oxide film sandwiching the silicon nitride film has a high potential barrier, and the charge is well retained.

  At the time of reading, a positive potential is applied to the diffusion layer 200 on the selection gate electrode 800 side, and a positive potential is applied to the selection gate electrode 800. Thereby, the selection transistor 810 is turned on. Here, the memory gate electrode 500 has an appropriate memory gate potential (for example, a threshold voltage in the write state and a threshold voltage in the erase state) that can determine the difference in threshold voltage of the memory gate electrode 500 given by the write / erase state. Intermediate potential). Thereby, it can be read as a drain current whether the memory gate insulating film 400 is in a state where electrons EN are accumulated (write state) or in a state where charges are canceled by the holes HL (erasure state).

  Here, as described above, in the operation method by carrier injection using hot carriers, the insulating film (lower silicon oxide film 401) between the silicon substrate 100 and the silicon nitride film 402 serving as the charge storage layer is thick. However, the injection can be performed efficiently. This is because the hot carrier energy has energy comparable to the barrier potential of the insulating film measured from the silicon band. However, it has been found that injecting carriers in a high energy state from the substrate side through the insulating film causes a large number of defects at the interface between the silicon substrate 100 and the lower silicon oxide film 401. The carrier trapped in the defect during the read operation is one cause of the variation in threshold voltage. In addition, since the defect level (interface level) generated at the interface recovers with time, the subthreshold swing value (S value) of the memory transistor 510 gradually decreases from the state immediately after writing and erasing. Thus, it has been found that it also causes variation in threshold voltage. In particular, since the band offset (potential barrier) for the lower silicon oxide film 401, which is the memory gate insulating film 400 immediately above the channel, is higher for the holes HL than for the electrons EN, hot hole injection Requires higher energy than hot electron injection. Therefore, when hot hole injection is employed, damage to the interface between the channel and the lower silicon oxide film 401 becomes more serious than when hot electron injection is employed.

  As described above, since the MONOS type memory by the hot carrier injection method examined by the present inventors causes variations in threshold voltage and time fluctuation, it is impossible to realize high performance of an LSI equipped with such a MONOS type memory. It turns out that it has a problem. Then, the present inventors further examined the cause of the increase in the interface state and found the following.

  Usually, the memory gate insulating film 400 of the MONOS type memory has a barrier potential on the silicon nitride film 402 from the viewpoint of preventing charge transfer (intrinsic leakage) between the silicon nitride film 402 and the memory gate electrode 500. An upper silicon oxide film 403 made of a high silicon oxide film is disposed. In particular, as a silicon oxide film on the silicon nitride film 402 in the split gate structure MONOS type memory, in addition to a small number of defects, an L-shaped portion including the side wall of the selection gate electrode 800 can be oxidized conformally. Therefore, it is desirable to form the upper silicon oxide film 403. As a method for meeting such a demand, according to the study by the present inventors, ISSG (In Situ Stream Generation) oxidation that is easy to wrap around a corner portion such as an L-shaped portion is applied. However, in order to form the upper silicon oxide film 403 having a thickness of 4 to 5 nm or more on the silicon nitride film 402 while satisfying the practical throughput by this ISSG oxidation method, the processing temperature is increased and the processing temperature is increased. It is necessary to increase the hydrogen concentration of

However, it is clear from further studies by the present inventors that the step of forming the upper silicon oxide film 403 by the ISSG oxidation method having a high processing temperature and high hydrogen concentration is one cause of the above problem. Became. That is, in the ISSG oxidation at a high temperature and a high hydrogen concentration, hydrogen goes around to the interface between the silicon substrate 100 and the lower silicon oxide film 401. Such hydrogen can replace the bond between silicon and oxygen in the lower silicon oxide film 401 and can generate an excessive bond between silicon and hydrogen. The reaction of ISSG oxidation is H ₂ + O ₂ → O ^* + OH + H, which generates oxygen radicals, but also generates unreacted hydrogen. This hydrogen diffusion is believed to be facilitated by strong ISSG oxidation conditions.

  When the lower silicon oxide film 401 in the MONOS type memory has a bond of silicon and hydrogen as described above, the following phenomenon may occur. For example, during a memory write operation, high energy hot carriers pass through the lower silicon oxide film 401. At this time, hydrogen is desorbed in the bond between silicon and hydrogen excessively contained in the lower silicon oxide film 401, and dangling bonds (unbonded hands) are generated in the remaining silicon. Such a dangling bond becomes a carrier trap level, and causes a variation or fluctuation of the threshold voltage as described above. In particular, a hot hole having a large effective mass and requiring injection with high energy is more likely to break the bond between silicon and hydrogen and has a greater influence.

  As described above, according to further studies by the present inventors, the step of forming the upper silicon oxide film 403 by the ISSG oxidation method at a high temperature and a high hydrogen concentration is an interface that causes variations and fluctuations in the threshold voltage of the MONOS type memory. It turned out to be one cause to increase the level. Note that the present inventors also studied a method of forming the upper silicon oxide film 403 by an ozone oxidation method that does not contain hydrogen. Although this method can reduce the formation of excess silicon-hydrogen bonds as in ISSG oxidation, it has been found that the progress of ozone oxidation on the silicon nitride film 402 is slow and impractical.

  Further, the following problems in the MONOS type memory have been clarified by the study of the present inventors from another viewpoint. As described above, when rewriting a MONOS type memory having a split gate structure using the SSI method and the BTBT method, electrons EN are injected into the memory gate insulating film 400 from the channel below the selection gate electrode 800, and the holes HL are Implanted into the memory gate insulating film 400 from the vicinity of the diffusion layer 300 on the memory gate electrode 500 side. Therefore, the injection position of electrons EN in the memory gate insulating film 400 at the time of writing operation is different from the injection position of holes HL at the time of erasing operation. Accordingly, as the rewriting operation is repeated, the unerased (remaining carriers) of the electrons EN and holes HL are accumulated.

  FIG. 52 is an explanatory diagram for explaining this situation. FIG. 52 shows the memory gate insulation when the write operation is performed after performing the rewrite operation many times in the nonvolatile memory NVMb which is the MONOS type memory having the split gate structure described with reference to FIGS. The charge distribution in the film 400 is shown. The electron EN is represented by a charge distribution 902, and the hole HL is represented by a charge distribution 903. As a result of the rewriting operation, the charge distribution 902 of the injected electrons EN spreads on the select gate electrode 800 side of the memory gate insulating film 400. However, in addition to the charge distribution 902 of the electrons EN, the charge distribution 903 of holes HL that are residual carriers also spreads on the diffusion layer 300 side in the memory gate insulating film 400. This is because, as described above, during the rewrite operation, carriers are injected and accumulated in positions distant from each other in the memory gate insulating film 400, respectively. It has been found that such residual carriers diffuse over time and can cause a temporal variation in threshold voltage by recombination (pair annihilation) of electrons EN and holes HL.

  As a result of further studies by the present inventors, the ease of diffusion of carriers trapped in the memory gate insulating film 400 also depends on the formation method of the upper silicon oxide film 403 on the silicon nitride film 402. Became. That is, when the upper silicon oxide film 403 is formed by thermally oxidizing the silicon nitride film 402 by an ISSG oxidation method, a dry oxidation method, a wet oxidation method, an ozone oxidation method, or the like, the silicon nitride film 402 and the upper silicon oxide film are formed. A transition layer may be formed at the interface with the film 403. This transition layer has a large number of defects (such as dangling bonds), and it has been found that the movement of carriers is promoted through these defects. Therefore, the fluctuation of the threshold voltage becomes larger in a short time.

  Based on the above, in the first embodiment, in the nonvolatile memory using the hot carrier injection method with a high operating speed, the interface deterioration after rewriting is small, and the localization and movement of charges can be suppressed. A semiconductor device having a non-volatile memory will be described. Such a semiconductor device solves the above-described problems and provides a technique for improving the performance of a semiconductor device having a nonvolatile memory.

  The semiconductor device according to the first embodiment will be described with reference to FIGS. The semiconductor device according to the first embodiment has a nonvolatile memory NVM1 disposed on a silicon substrate (semiconductor substrate) 1 made of single crystal silicon. FIG. 1 shows a cross-sectional view of a main part of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment. FIG. 2 is a plan view of the main part of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment. In particular, in the main part plan view of FIG. 2, cross-sectional views of main parts viewed in the direction of the arrows along the lines A <b> 1-A <b> 1, B <b> 1-B <b> 1, and C <b> 1-C <b> 1 are shown in order from the left side in FIG. . In these drawings, some insulating films and contact mechanisms are omitted. Further, in the plan view of FIG. 2, some members are hatched for convenience, but do not have a special meaning in terms of structure. In addition, the cross-sectional view of the main part viewed along the line A1-A1 in FIG. 1 shows the nonvolatile memory NVM1 of the first embodiment for two cells. FIG. 2 shows a state in which a plurality of nonvolatile memories NVM1 of the first embodiment are arranged in an array.

  In the silicon substrate 1, an active region is defined by an isolation portion 2 having a structure (Shallow Trench Isolation: STI structure) in which a silicon oxide film is embedded in a shallow groove. A p well 3 that is a p-type semiconductor region is formed on the main surface of the silicon substrate 1. The nonvolatile memory NVM1 included in the semiconductor device of the first embodiment is disposed in the p well 3 in these active regions on the silicon substrate 1. The nonvolatile memory NVM1 included in the semiconductor device according to the first embodiment has components as will be described in detail below.

  A memory gate insulating film (first gate insulating film) MI1 is formed on the silicon substrate 1. The memory gate insulating film MI1 is composed of a laminated film composed of three layers of insulating films. More specifically, the memory gate insulating film MI1 is, in order from the side closer to the silicon substrate 1, the lower barrier film (first barrier film) BB1, the charge holding film CS1, and the upper barrier film (second barrier film) TB1. Consists of. Here, the lower barrier film BB1 is made of an insulating film mainly composed of silicon oxide. The charge holding film CS1 is made of an insulating film mainly composed of silicon nitride. The upper barrier film TB1 is made of an insulating film having a smaller band gap (forbidden band width) than that of silicon oxide. As an example, the upper barrier film TB1 is made of an insulating film mainly composed of silicon oxynitride. The effect that the nonvolatile memory NVM1 of the first embodiment has the memory gate insulating film MI1 made of such a laminated film, and the detailed specifications and effects of the memory gate insulating film MI1 will be described in detail later. To do.

  A memory gate electrode (first gate electrode) MG1 is formed on the memory gate insulating film MI1. In other words, the memory gate electrode MG1 is disposed on the silicon substrate 1 via the memory gate insulating film MI1. In other words, the memory gate insulating film MI1 is disposed between the memory gate electrode MG1 and the silicon substrate 1. The memory gate electrode MG1 is a conductor film mainly composed of polycrystalline silicon (also referred to as polysilicon) and reduced in resistance by containing impurities. In particular, the memory gate electrode MG1 of the first embodiment includes a donor impurity and has an n-type conductivity type. The memory gate electrode MG1 is arranged so as to extend in one direction on the silicon substrate 1 and to cross a plurality of active regions across the isolation part 2. In this way, the plurality of nonvolatile memories NVM1 share the memory gate electrode MG1.

  On the silicon substrate 1, a selection gate insulating film (second gate insulating film) SI1 is further formed. The selection gate insulating film SI1 is made of an insulating film mainly composed of silicon oxide. A selection gate electrode (second gate electrode) SG1 is formed on the selection gate insulating film SI1. In other words, the select gate electrode SG1 is disposed on the silicon substrate 1 via the select gate insulating film SI1. In other words, the select gate insulating film SI1 is disposed between the select gate electrode SG1 and the silicon substrate 1. The selection gate electrode SG1 is a conductor film mainly composed of polycrystalline silicon and reduced in resistance by containing impurities. The selection gate electrode SG1 is arranged so as to extend in one direction on the silicon substrate 1, particularly along the extending direction of the memory gate electrode MG1 described above. They are arranged so as to intersect the active region. In this way, the plurality of nonvolatile memories NVM1 share the selection gate electrode SG1.

  Here, on the silicon substrate 1, the memory gate electrode MG1 is arranged at a position adjacent to the selection gate electrode SG1. However, the memory gate insulating film MI1 disposed between the memory gate electrode MG1 and the silicon substrate 1 is similarly and integrally disposed between the memory gate electrode MG1 and the selection gate electrode SG1, It is electrically insulated. In other words, the memory gate electrode MG1 is disposed on one side wall of the selection gate electrode SG1 via the memory gate insulating film MI1. In other words, the memory gate insulating film MI1 is integrally disposed from between the memory gate electrode MG1 and the silicon substrate 1 to between the memory gate electrode MG1 and the select gate electrode SG1.

  As described above, the nonvolatile memory NVM1 included in the semiconductor device according to the first embodiment is a so-called split gate MONOS type memory having two gate electrodes arranged adjacent to each other while being insulated from each other. . The nonvolatile memory NVM1 further includes the following components.

  As a source / drain mechanism for transferring charges in the nonvolatile memory NVM1, two types of impurity diffusion regions 4 and 5 are formed on the main surface side of the silicon substrate 1. More specifically, the low concentration diffusion region 4 is formed in the silicon substrate 1 at the lower side of the side where the memory gate electrode MG1 and the selection gate electrode SG1 are not adjacent to each other. Further, a high concentration diffusion region 5 is formed in the silicon substrate 1 at the same lower side of each of the gate electrodes MG1 and SG1 and at a position away from the low concentration diffusion region 4. Each of the diffusion regions 4 and 5 is an n-type semiconductor region containing a donor impurity. Their donor impurity concentration is lower in the low-concentration diffusion region 4 than in the high-concentration diffusion region 5. Further, the depth seen from the main surface of the silicon substrate 1 is shallower in the low concentration diffusion region 4 than in the high concentration diffusion region 5. Moreover, the low concentration diffusion region 4 and the high concentration diffusion region 5 are in contact with each other at the end portions and are electrically connected. This low concentration diffusion region 4 is called an LDD (Lightly doped drain) structure in the source / drain mechanism, and functions as a so-called extension region.

  On the main surface of the silicon substrate 1, sidewall spacers 6 are arranged so as to cover the side walls where the memory gate electrode MG1 and the selection gate electrode SG1 are not adjacent to each other. The sidewall spacer 6 is formed at a position covering at least the low concentration diffusion region 4 formed in the silicon substrate 1. The sidewall spacer 6 is made of, for example, an insulating film mainly composed of silicon oxide, an insulating film mainly composed of silicon nitride, or a laminated film thereof.

  The above are the main components of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment. The semiconductor device of the first embodiment further includes the following components.

  A metal silicide layer 7 is formed on the surfaces of the memory gate electrode MG 1, the select gate electrode SG 1, and the high concentration diffusion region 5. The metal silicide layer 7 is a compound of metal and silicon and is a low resistance member. The metal silicide layer 7 is provided to reduce the contact resistance between the constituent elements of the nonvolatile memory NVM1 and a contact member to be described later and realize ohmic connection. The metal silicide layer 7 is made of, for example, cobalt silicide or nickel silicide.

  An interlayer insulating film 8 is formed on the silicon substrate 1 so as to cover the components arranged on the silicon substrate 1 described above. The interlayer insulating film 8 is made of, for example, an insulating film mainly composed of silicon oxide. Further, the interlayer insulating film 8 may include a silicon nitride film as an etching stop film at the bottom.

  A contact plug CP1 is formed so as to penetrate the interlayer insulating film 8 in the film thickness direction. The contact plug CP1 is in electrical contact with each component of the nonvolatile memory NVM1 by contacting the metal silicide layer 7. The contact plug CP1 is made of a metal such as tungsten, aluminum, or copper, for example. Further, a barrier conductor film for preventing mutual diffusion and chemical reaction may be provided between the contact plug CP1 and the interlayer insulating film 8 and the metal silicide layer 7. On the interlayer insulating film 8, a metal wiring MW1 electrically connected to the contact plug CP1 is formed. The metal wiring MW1 has a desired wiring pattern for configuring the nonvolatile memory NVM1 as a circuit. The metal wiring MW1 is made of a metal such as aluminum or copper, for example. Further, a barrier conductor film for preventing mutual diffusion and chemical reaction may be provided between the metal wiring MW1 and the interlayer insulating film 8. The interlayer insulating film 8, the contact plug CP1, and the metal wiring MW1 as described above may be repeatedly arranged on the upper portion to have a multilayer wiring structure (not shown).

  The above is the structure of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment and the wiring structure for realizing the circuit configuration. In particular, the nonvolatile memory NVM1 is a MONOS type memory having a so-called split gate structure, and its operation method is the same as that described with reference to FIGS. That is, a memory operation is realized using a threshold voltage that is changed by generating hot carriers and injecting them into the memory gate insulating film MI1.

  Here, as described above, in the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, the upper barrier film TB1 is mainly composed of silicon oxynitride in the memory gate insulating film MI1 formed of the three-layer laminated insulating film. It consists of an insulating film. This is because the upper silicon oxide film 403 is an insulating film mainly composed of silicon oxide in the nonvolatile memory studied by the present inventors (for example, the nonvolatile memory NVMb described with reference to FIG. 47). On the other hand, the configuration is different. In the semiconductor device according to the first embodiment, by applying an insulating film mainly composed of silicon oxynitride as the upper barrier film TB1 of the nonvolatile memory NVM1, it is possible to reduce the variation in threshold voltage during the memory operation. The reason will be described in detail below.

  In the nonvolatile memory NVM1 of the first embodiment, the upper barrier film TB1 constituting the memory gate insulating film MI1 is made of a silicon oxynitride film, thereby reducing unerased carriers at the time of rewriting and the memory gate insulating film Carrier localization occurring in MI1 can be reduced. FIGS. 3 and 4 are explanatory diagrams of the write operation of the nonvolatile memory NVM1 of the first embodiment. Each figure shows the behavior of the electrons EN or holes HL during the write operation of the nonvolatile memory NVM1 and the charge distributions D1 and D2 after the write operation.

  As shown in FIG. 3, considering only the injection of electrons EN into the memory gate insulating film MI1 by the SSI method described above, the charge of the electrons EN in the vicinity of the boundary with the selection gate electrode SG1 in the memory gate insulating film MI1. Distribution D1 is biased. Here, in the nonvolatile memory NVM1 of the first embodiment, charge transfer between the memory gate electrode MG1 and the memory gate insulating film MI1 is facilitated during the write operation. As a result, as shown in FIG. 4, the charge distribution D2 after the write operation spreads in the lateral direction in the memory gate insulating film MI1, and is compared with the case where the distribution of only the electron EN is considered (charge distribution D1 in FIG. 3). And smooth. This phenomenon will be described in more detail below.

  As described above, during a write operation by the SSI method in the MONOS type memory having the split gate structure, a high positive voltage is applied to the memory gate electrode MG1 to draw hot electrons into the memory gate insulating film MI1. Here, an insulator having a band gap smaller than that of a silicon oxide film, such as a silicon oxynitride film, makes it easier for electrons EN and holes HL to cross the potential barrier. In consideration of these, in the nonvolatile memory NVM1 of the first embodiment, the holes HL in the memory gate electrode MG1 to which a positive potential is applied exceed the upper barrier film TB1 made of a silicon oxynitride film, and the memory gate It becomes easy to be injected into the insulating film MI1 (charge holding film CS1). Similarly, the electrons EN injected into the memory gate insulating film MI1 (charge holding film CS1) also easily escape to the memory gate electrode MG1 over the upper barrier film TB1. In the write operation by the SSI method, the amount of electrons EN injected into the memory gate insulating film MI1 (charge holding film CS1) on the side close to the select gate electrode SG1 is large, so that the electric field in the vicinity thereof becomes strong. Therefore, particularly on the selection gate electrode SG1 side where charges are likely to be localized, injection of holes HL of the memory gate insulating film MI1 from the memory gate electrode MG1 and electron EN from the memory gate insulating film MI1 to the memory gate electrode MG1 Emission is likely to occur, and the charge distribution D2 has a flat shape.

  The same explanation can be applied to the erase operation. 5 and 6 are explanatory diagrams of the erase operation of the nonvolatile memory NVM1 of the first embodiment. Each figure shows the behavior of the electrons EN or holes HL during the erase operation of the nonvolatile memory NVM1 and the charge distributions D3 and D4 after the erase operation.

  As shown in FIG. 5, considering only the injection of the holes HL generated by the above-described BTBT method into the memory gate insulating film MI1, the holes HL are formed in the memory gate insulating film MI1 near the diffusion regions 4 and 5. The charge distribution D3 is biased. Here, with the nonvolatile memory NVM1 of the first embodiment, charge transfer between the memory gate electrode MG1 and the memory gate insulating film MI1 is facilitated during the erase operation. As a result, as shown in FIG. 6, the charge distribution D4 after the erase operation spreads in the horizontal direction in the memory gate insulating film MI1, and the distribution of only the holes HL is considered (charge distribution D3 in FIG. 5). Compared to smooth. This phenomenon will be described in more detail below.

  As described above, at the time of erasing operation in the MONOS type memory having the split gate structure, a high negative voltage is applied to the memory gate electrode MG1, and a high positive voltage is applied to the diffusion regions 4 and 5, resulting in the BTBT phenomenon. The holes HL are drawn into the memory gate insulating film MI1. Here, an insulator having a band gap smaller than that of a silicon oxide film, such as a silicon oxynitride film, makes it easier for electrons EN and holes HL to cross the potential barrier. Considering these, in the nonvolatile memory NVM1 of the first embodiment, the electrons EN in the memory gate electrode MG1 biased to a negative potential exceed the upper barrier film TB1 made of a silicon oxynitride film, and the memory gate It becomes easy to be injected into the insulating film MI1 (charge holding film CS1). Similarly, the holes HL injected into the memory gate insulating film MI1 (charge holding film CS1) also easily escape to the memory gate electrode MG1 over the upper barrier film TB1. Further, in the erasing operation by the BTBT method, since the injection amount of holes HL into the memory gate insulating film MI1 (charge holding film CS1) on the side close to the diffusion regions 4 and 5 is large, the electric field in the vicinity thereof becomes strong. Therefore, particularly in the vicinity of diffusion regions 4 and 5 where charges are likely to be localized, injection of electrons EN from memory gate electrode MG1 into memory gate insulating film MI1 and hole HL from memory gate insulating film MI1 to memory gate electrode MG1. Is likely to occur, and the charge distribution D4 has a flat shape.

  As described above, according to the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, the upper barrier film TB1 of the memory gate insulating film MI1 is a silicon oxynitride film, so that the local distribution of charge distribution after the rewrite is performed. The presence (unerased) can be reduced. Therefore, it is possible to reduce the phenomenon in which localized charges diffuse and electrons and holes disappear with time. As a result, fluctuations in the threshold voltage during operation of the MONOS memory having the split gate structure can be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be improved.

  The above is an effect explained from the structural feature that the upper barrier film TB1 is a silicon oxynitride film. Actually, it is also caused by the feature in the manufacturing method of the semiconductor device of the first embodiment. There is an effect to. The effects resulting from the manufacturing characteristics will be described in detail later.

  The present inventors have examined in detail the composition of the silicon oxynitride film as the upper barrier film TB1 that can exhibit the above-described effects.

Here, the composition of the silicon oxynitride film can be represented by the content ratio of silicon oxide and silicon nitride in the silicon oxynitride film. In particular, in the present specification, the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is determined by using silicon dioxide (SiO ₂ ) and trisilicon tetranitride (Si ₃ N ₄ ) constituting silicon oxynitride (SiON). Of these, it is shown as the proportion of silicon dioxide. In other words, the composition ratio x is the concentration of silicon (Si) bonded to oxygen (O), and the composition of silicon oxynitride is (SiO ₂ ) _x (Si ₃ N ₄ ) _1-x (where the composition ratio x is 0). This is expressed as 1 or less. When silicon oxynitride is displayed in a ternary system (Si _a N _b O _c ), the relationship between the composition ratio x and the composition ratios a, b, and c is a = (3-2x) / (7− 4x), b = (4-4x) / (7-4x), c = 2x / (7-4x). When the composition ratio x = 0, silicon nitride is used, and when the composition ratio x = 1, silicon oxide is used.

  Further, since the composition of the silicon oxynitride film is almost proportional to the refractive index, the refractive index RI of silicon oxynitride may be expressed in place of the composition ratio x of silicon oxynitride. According to the verification by the present inventors, in the case of the composition ratio x = 0 (silicon nitride) of silicon oxynitride defined as described above, the refractive index RI = 2.0, and the composition ratio x of silicon oxynitride When = 1 (silicon oxide), the refractive index RI = 1.46. That is, the composition ratio x can be expressed approximately as (refractive index RI-2) / (1.46-2). Hereinafter, the composition of the silicon oxynitride film as the upper barrier film TB1 is shown by both the composition ratio x and the refractive index RI defined as described above.

  FIG. 7 is a graph showing the variation characteristics of the threshold voltage when the composition of the upper barrier film TB1 in the memory gate insulating film MI1 is changed in the nonvolatile memory NVM1 of the first embodiment. . More specifically, the change in threshold voltage over time (charge retention characteristics) after rewriting 1000 times under the same conditions at room temperature in a verification sample having an upper barrier film TB1 having a different composition is shown. In order to clarify a significant difference in a short time, the time change of the threshold voltage is measured at 150 ° C. A characteristic P01 is a characteristic when the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 constituting the memory gate insulating film MI1 is 0.787 (refractive index RI is 1.575) and the film thickness is 9 nm. Show. Similarly, the characteristic P02 is shown when the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is 0.55 (refractive index RI is 1.7) and the film thickness is 9 nm. Similarly, the characteristic P03 is shown when the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is 0.37 (refractive index RI is 1.8) and the film thickness is 9 nm. Similarly, a case where the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is 1 (refractive index RI is 1.46, that is, a silicon oxide film) and the film thickness is about 5 nm is shown as a characteristic P04. Other structures and specifications are substantially the same. For example, among other configurations of the memory gate insulating film MI1, the silicon oxide film as the lower barrier film BB1 is 4 nm, and the silicon nitride film as the charge holding film CS1 is 5 to 10 nm. It is.

  In the characteristic P01 (composition ratio x = 0.787, refractive index RI = 1.575) and the characteristic P02 (composition ratio x = 0.55, refractive index RI = 1.7), the time variation of the threshold voltage is alleviated. I can see that As described above, the upper barrier film TB1 of the memory gate insulating film MI1 is made of a silicon oxynitride film, so that the effect of localizing charges during repeated rewriting is reduced. This is an effect explained from the structural feature that the upper barrier film TB1 is a silicon oxynitride film, and is actually due to the feature in the method of manufacturing the semiconductor device of the first embodiment. There is also an effect. The effects resulting from the manufacturing characteristics will be described in detail later.

  On the other hand, in the characteristic P03 (composition ratio x = 0.37, refractive index RI = 1.8), the threshold voltage varies according to the conventional structure (silicon oxide film having the composition ratio x = 1 and refractive index RI = 1.46). It can be seen that the fluctuation is similar to or larger than the characteristic P04. This is because, in the characteristic P03, since the ratio of silicon oxide in the upper barrier film TB1 is small and the ratio of silicon nitride is large, the height of the potential barrier with respect to the retained charge is too low. That is, if the ratio of silicon nitride in the upper barrier film TB1 increases and the potential barrier becomes lower, the charges trapped in the charge holding film CS1 of the memory gate insulating film MI1 leak to the memory gate electrode MG1 side. . Hereinafter, such a phenomenon is referred to as intrinsic charge leakage. When such intrinsic charge leakage becomes dominant, it becomes difficult to satisfy practical specifications of the nonvolatile memory NVM1. This is an influence explained from the structural feature that the upper barrier film TB1 is a silicon oxynitride film, and in fact, there is also an influence caused by the feature of the manufacturing method. The influence resulting from the manufacturing characteristics will be described in detail later.

  Based on the verification results as described above, the inventors of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment do not cause intrinsic charge leakage to be a dominant cause of retention deterioration, but the threshold voltage. The conditions for obtaining the effect of reducing the fluctuation of the above were verified in more detail.

  First, during the writing and erasing operations in the nonvolatile memory NVM1 of the first embodiment, the effect of reducing the localization of the charge distribution by injecting reverse polarity carriers from the memory gate electrode MG1 as described above is exhibited. The condition was verified. As a result, the above-described effects can be obtained when the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 constituting the memory gate insulating film MI1 is 0.92 or less (refractive index RI is 1.5 or more). It was.

  Next, in the memory operation in the nonvolatile memory NVM1 of the first embodiment, conditions were verified so that intrinsic charge leakage does not become the main cause of deterioration of retention characteristics. As a result, when the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 constituting the memory gate insulating film MI1 is larger than 0.46 (the refractive index RI is smaller than 1.75), the nonvolatile memory It was found that the reliability of NVM1 can be secured.

  To summarize the above, in the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, in order to obtain the effect of reducing the fluctuation of the threshold voltage without causing intrinsic charge leakage as a dominant cause of retention deterioration. The composition ratio x of the silicon oxynitride film as the upper barrier film TB1 of the memory gate insulating film MI1 is larger than 0.46 and not larger than 0.92 (refractive index RI is not smaller than 1.5 and 1. It must be smaller than 75). Under such conditions, as described above, the performance of the semiconductor device having a nonvolatile memory can be improved.

  Further, considering the resistance to the disturb mode received by the non-selected cells during the array operation, it is preferable that the above-described intrinsic charge leakage is made lower. The disturb mode received by non-selected cells during array operation is, for example, when a certain memory cell is written, a voltage is also applied to the memory gate of the cell that is not the write target, and the stored charge is released to the gate. This is a mode in which erroneous writing or erroneous erasure is caused by the occurrence of uninjected charge injection. In view of such resistance to the disturb mode, in order to utilize the effect of improving the retention characteristics stably, the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is 0.55 or more (refractive index The RI is more preferably 1.7 or less. In addition, under such a condition that the composition ratio x is 0.55 or less (refractive index RI is 1.7 or less), it is also in a range where the composition ratio dependency in the variation characteristic of the threshold voltage is not recognized (see FIG. 7 above). ). Therefore, there is an advantage that the variation in composition that occurs when a large number of memories are formed does not affect the characteristics. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  The inventor also performed detailed verification on the film thickness of the upper barrier film TB1. FIG. 8 is a graph showing the variation characteristics of the threshold voltage when the thickness of the upper barrier film TB1 in the memory gate insulating film MI1 is changed in the nonvolatile memory NVM1 of the first embodiment. Yes. More specifically, the change in threshold voltage over time (charge retention characteristics) after rewriting 1000 times under the same conditions at room temperature in the verification sample having the upper barrier film TB1 having different film thicknesses is shown. In order to clarify a significant difference in a short time, a change in threshold voltage is measured at 150 ° C. A characteristic when the film thickness of the upper barrier film TB1 constituting the memory gate insulating film MI1 is 12 nm is shown as a characteristic P05. Similarly, a characteristic when the film thickness of the upper barrier film TB1 is 9 nm is shown as a characteristic P06. Similarly, a characteristic when the thickness of the upper barrier film TB1 is 6 nm is shown as a characteristic P07. In the verification sample so far, the composition ratio x of the silicon oxynitride film as the upper barrier film TB1 is 0.55 (refractive index RI is 1.7). Further, a characteristic when the upper barrier film TB1 is a silicon oxide film (composition ratio x = 1, refractive index RI = 1.46) and the film thickness is 5 nm is shown as a characteristic P08. Other structures and specifications are substantially the same. For example, among other configurations of the memory gate insulating film MI1, the silicon oxide film as the lower barrier film BB1 is 4 nm, and the silicon nitride film as the charge holding film CS1 is 5 to 10 nm. It is.

  In the characteristic P05 (film thickness 12 nm) and the characteristic P06 (film thickness 9 nm), the threshold voltage variation characteristics are almost the same. On the other hand, in the characteristic P07 (film thickness 6 nm), the threshold voltage varies greatly. This indicates that the function as a barrier is weakened by further reducing the thickness of the upper barrier film TB1 made of a silicon oxynitride film having a lower potential barrier than that of the silicon oxide film. That is, by reducing the thickness of the upper barrier film TB1 made of a silicon oxynitride film, a component in which the charge trapped in the memory gate insulating film MI1 leaks to the memory gate electrode starts to be seen. According to further verification by the present inventors, such intrinsic charge leakage becomes dominant when the thickness of the upper barrier film TB1 is made thinner than 5 nm, and the threshold voltage variation characteristic is the same as that of the conventional silicon oxide. The characteristic is similar to or worse than the characteristic P08 in which the film is applied to the upper barrier film TB1. Therefore, the thickness of the upper barrier film TB1 made of the silicon oxynitride film is more preferably 5 nm or more. With such a film thickness, the fluctuation of the threshold voltage of the MONOS memory having the split gate structure can be further reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  Furthermore, as described above, it is more preferable to set the thickness of the upper barrier film TB1 in the memory gate insulating film MI1 to 9 nm or more, since an intrinsic charge leak is hardly seen. Thereby, the above-mentioned disturbance tolerance can be further improved. In addition, under such a condition that the film thickness is 9 nm or more, the film thickness dependence in the variation characteristic of the threshold voltage is not recognized (see FIG. 8 above). Therefore, there is an advantage that variations in film thickness that occurs when a large number of memories are formed do not affect the characteristics. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  The above has described the results of verification by the present inventors on the lower limit of the thickness of the upper barrier film TB1 made of the silicon oxynitride film in the nonvolatile memory NVM1 of the first embodiment. The upper limit of the film thickness of the upper barrier film TB1 can be defined by the erase speed of the nonvolatile memory NVM1. From this point of view, the contents verified by the inventors about the film thickness of the upper barrier film TB1 of the nonvolatile memory NVM1 of Embodiment 1 will be described in detail.

  An advantage of applying the MONOS type memory having the split gate structure is that the stored information can be read at a high speed. By capturing a large amount of holes in the erase state, even if the voltage applied to the memory gate electrode MG1 is 0 V during reading, if the selection gate electrode SG1 that can be switched on / off at a low voltage is turned on, a large read current can be obtained. Is obtained. Therefore, high-speed reading can be performed without increasing the voltage of the memory gate electrode MG1 during reading.

  For example, the microcontroller is required to have a high speed and an operating frequency of 100 Mhz or more, and the read current of the nonvolatile memory NVM1 for realizing it requires about 10 μA or more per cell. On the other hand, when a 3.3V system is used as the power supply voltage and I / O (input / output) system, the junction breakdown voltage of the 3.3V high voltage MIS transistor is about 6 to 7V. From such a viewpoint, a voltage that can be used for erasing is about ± 6 V, which is an approximate upper limit.

  Therefore, FIG. 9 shows an equivalent oxide thickness (Equivalent Oxide) of the memory gate insulating film MI1 when hot hole erasing is performed by the BTBT method with the voltage of the memory gate electrode MG1 set to −6V and the voltages of the diffusion regions 4 and 5 set to 6V. A graph showing the relationship between Thickness (EOT) and erase time is shown. Here, the equivalent oxide film thickness is a value obtained by converting the thickness of the insulating film into an electrical film thickness equivalent to a silicon oxide (silicon dioxide) film using a relative dielectric constant. For example, an insulator (dielectric) whose relative dielectric constant is 10 times that of silicon oxide has an equivalent oxide thickness of 1 nm when the physical thickness is 10 nm. Note that the relative dielectric constant of silicon nitride is about twice that of silicon oxide. The erase time is a current of 83.3 μA / μm or more when the voltage of the memory gate electrode MG1 is −1V, the voltage of the selection gate electrode SG1 is 1.5V, the drain voltage is 1V, and the source voltage is 0V. It is defined by the erase time required to flow between the source and drain. This is a specification that, in a MONOS type memory having a split gate structure, when reading a cell having a transistor width of 0.12 μm or more, a current of 10 μA or more per cell can be sufficiently secured with a voltage of 0 V of the memory gate electrode MG1. This is a current value necessary for high-speed operation of the module.

  According to the study by the present inventors, it is desirable that the product specifications of a flash memory mounted on a microcontroller or the like can be erased in about 1 second per 1 Mbyte. Further, in order to perform restrictions such as the upper limit value of the erasing current that can be flowed at one time and finer operations, erasing is often performed in units of about 4 kbit. Under this condition, in order to erase 1 Mbyte in 1 second, it is desirable that 1 (second) ÷ 8 (Mbit) × 4 (kbit) = 500 μsec or less per 1 bit.

  As shown in FIG. 9, the total thickness of the memory gate insulating film MI1 is equal to or less than the equivalent oxide film thickness of 17.5 nm, and the time required for erasing is 500 μsec or less, which satisfies the above condition. Therefore, in the nonvolatile memory NVM1 of the first embodiment, it is more preferable that the total thickness of the memory gate insulating film MI1 is 17.5 nm or less in terms of equivalent oxide thickness. Thereby, it is possible to realize a MONOS type memory having a split gate structure in which the erase operation is faster. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In the MONOS type memory having the split gate structure, the silicon oxide film disposed below the stacked structure memory gate insulating film starts to show intrinsic charge leakage due to the direct tunnel phenomenon when it becomes thinner than 4 nm. There is. Further, in Non-Patent Document 1, it is mentioned that a silicon nitride film disposed as a charge retention layer of a memory gate insulating film having a laminated structure has a weak charge trapping capability from about 4 nm (equivalent oxide thickness 2 nm) or less. Yes. Therefore, when the equivalent oxide thickness of the entire memory gate insulating film MI1 included in the nonvolatile memory NVM1 of the first embodiment is 17.5 nm or less, the equivalent oxide thickness of the upper barrier film TB1 is equal to that of the lower barrier film BB1. It is more preferable that 4 nm and 2 nm of the charge holding film are subtracted to be 11.5 nm or less.

  In the above description, in the nonvolatile memory NVM1 of the first embodiment, the memory gate electrode MG1 is mainly composed of polycrystalline silicon, includes donor impurities, and has n-type conductivity. The above-described effects are similarly effective regardless of the impurity concentration of the memory gate electrode MG1. However, in the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, it is more preferable that the impurity concentration contained in the memory gate electrode MG1 is lower than the impurity concentration contained in the selection gate electrode SG1. The reason will be described below.

  By reducing the impurity concentration of the memory gate electrode MG1, the impurity concentration in the vicinity of the interface with the memory gate insulating film MI1 is also reduced. Thereby, a depleted gate can be applied. When the gate is depleted, the electric field generated in the upper and lower barrier films TB1 and BB1 in the charge holding state is weaker than when the gate is not depleted. This is because an electric field is also generated in a portion having a low impurity concentration in the gate. Therefore, the charge retention characteristics can be further improved. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In order to form such a memory gate electrode MG1, for example, the memory gate electrode MG1 is formed using polycrystalline silicon (non-doped polycrystalline silicon) to which impurities are not intentionally added. At this time, the memory gate electrode MG1 has an impurity concentration that is close to that of an intrinsic semiconductor. However, since the memory gate electrode MG1 is applied as an ion implantation mask when forming the diffusion regions 4 and 5 and the like, the memory gate electrode MG1 contains impurities to the extent introduced by the ion implantation. A method for forming the memory gate electrode MG1 and the diffusion regions 4 and 5 will be described in detail later.

  A manufacturing method of the semiconductor device according to the first embodiment provided with the nonvolatile memory NVM1 having the above effects will be described with reference to FIGS. 10 to 21 are fragmentary cross-sectional views of the region corresponding to FIG. 1 during the manufacturing process.

  First, as shown in FIG. 10, the isolation portion 2 having the STI structure is formed on the main surface of the silicon substrate 1. The separation unit 2 forms a shallow groove on the surface of the silicon substrate 1 by a photolithography method and an etching method, and the silicon oxide is volumetrically formed by a thermal oxidation method, a chemical vapor deposition (CVD) method, or the like. It is formed by embedding silicon oxide in a shallow groove by applying a mechanical and mechanical polishing (CMP) method. The isolation | separation part 2 is formed on the silicon substrate 1 so that the area | region which forms a non-volatile memory and another element may be prescribed | regulated. The region on the silicon substrate 1 thus defined by the separation unit 2 is called an active region (active region) or the like.

  Thereafter, a p-well 3 is formed on the silicon substrate 1. Here, a region where the p-well 3 is not formed is covered with a photoresist film (not shown) formed by a photolithography method, and the silicon substrate 1 is subjected to ion implantation and heat treatment using this as a mask for ion implantation. 3 is formed. Since the p-well 3 is a p-type conductivity type semiconductor region, atoms (for example, boron) that become acceptor impurities are ion-implanted. Here, when adjusting the threshold voltage of the nonvolatile memory NVM1 to be formed, the impurity concentration of the channel may be adjusted by performing ion implantation on the surface of the active region of the silicon substrate 1 in this step.

  Next, as shown in FIG. 11, a selection gate insulating film SI1 is formed on the silicon substrate 1, and a selection gate electrode SG1 is formed on the selection gate insulating film SI1. For this purpose, for example, by thermally oxidizing the silicon substrate 1, a silicon oxide film 9 which is an insulating film mainly composed of silicon oxide is formed on the silicon substrate 1 with a thickness of about 2.5 nm, for example. Thereafter, a polycrystalline silicon film 10 (also referred to as polysilicon) is deposited on the silicon oxide film 9 by, for example, a CVD method or the like, for example, about 200 nm. Subsequently, the polycrystalline silicon film 10 and the silicon oxide film 9 are sequentially processed by a photolithography method, an etching method, or the like, thereby forming a selection gate electrode SG1 made of the polycrystalline silicon film 10, and made of the silicon oxide film 9. A selection gate insulating film SI1 is formed. Here, in order to adjust the conductivity type and conductivity of the selection gate electrode SG1, it is necessary to introduce a desired impurity into the polycrystalline silicon film 10 to be the selection gate electrode SG1. As a method for this, a polysilicon film 10 (doped polysilicon) into which impurities have been introduced in advance may be deposited by CVD, or after depositing the polysilicon film 10 and before processing, the impurities may be implanted by ion implantation. It may be introduced. Through the above steps, the selection gate insulating film SI1 is formed on the silicon substrate 1, and the selection gate electrode SG1 is formed thereon.

  Next, as shown in FIG. 12, in order to cover the main surface of the silicon substrate 1, a silicon oxide film (first barrier film) 11, which is an insulating film mainly composed of silicon oxide, and silicon nitride are sequentially formed. A silicon nitride film (charge holding film) 12 which is a main insulating film is formed. For this purpose, for example, the silicon substrate 1 is thermally oxidized to form a silicon oxide film 11 on the silicon substrate 1 with a thickness of about 4 to 5 nm, for example. At this time, the side walls and the upper surface of the selection gate electrode SG1 made of polycrystalline silicon are also oxidized, and the silicon oxide film 11 is formed. Thereafter, a silicon nitride film 12 is deposited, for example, about 5 to 10 nm so as to cover the silicon oxide film 11 by, eg, CVD. If the silicon oxide film 11 is thinner than about 4 nm, the injected charge leaks to the substrate side by the direct tunnel phenomenon. On the contrary, if the oxide film thickness is about 4 nm or more, it is difficult to leak to the substrate side except for carriers trapped in a very shallow trap in the nitride film and oxide film near the substrate surface. The silicon nitride film 12 is desirably 4 nm or more because the carrier trapping ability is reduced when the film thickness is thinner than 4 nm. The silicon oxide film 11 and the silicon nitride film 12 formed in this step are insulating films that become the lower barrier film BB1 and the charge holding film CS1 of the memory gate insulating film MI1, respectively, by processing described later. Specific processing steps will be described in detail later.

  Next, as shown in FIG. 13, a silicon oxynitride film (second barrier film) 13 which is an insulating film mainly composed of silicon oxynitride is formed so as to cover the silicon nitride film 12 formed on the silicon substrate 1. Form. Here, in the method of manufacturing the semiconductor device of the first embodiment, the silicon oxynitride film 13 is deposited by the CVD method. For example, the silicon oxynitride film 13 is deposited by CVD so that the composition ratio x is 0.55 (refractive index RI is 1.7) and the film thickness is about 9 nm. The silicon oxynitride film 13 formed in this step is an insulating film that becomes the upper barrier film TB1 of the memory gate insulating film MI1 by processing described later. Specific processing steps will be described in detail later.

  The effect obtained by forming such a silicon oxynitride film 13 as the upper barrier film TB1 is the same as that described with reference to FIGS. 1 to 9 described above, and redundant description thereof is omitted here. Further, regarding the difference in the effects that can be manifested by adjusting the composition ratio x (refractive index RI) and the film thickness of the silicon oxynitride film 13 formed as the upper barrier film TB1, the above-described FIGS. The same as described. In this step, the silicon oxynitride film 13 is formed as the upper barrier film TB1, but it is effective to select an insulating film having a band gap smaller than that of silicon oxide as the upper barrier film TB1. Among them, silicon oxynitride is more effective. The reason is also as described above.

  The semiconductor device manufacturing method of the first embodiment is characterized in that the silicon oxynitride film 13 as the upper barrier film TB1 is formed by the CVD method in the above-described steps. The effect of forming the silicon oxynitride film 13 as the upper barrier film TB1 by the CVD method will be described in detail later.

  In the subsequent process, as shown in FIG. 14, a polycrystalline silicon film 14 is formed so as to cover the silicon oxynitride film 13. Here, the polycrystalline silicon film 14 is formed by, eg, CVD. Thereafter, as shown in FIG. 15, the entire surface of the polycrystalline silicon film 14 is etched (etched back) so as to have selectivity in a direction perpendicular to the main surface of the silicon substrate 1. As a result, portions of the polycrystalline silicon film 14 that cover both side walls of the selection gate electrode SG1 are left, and the other portions are removed. Subsequently, the silicon oxynitride film 13, the silicon nitride film 12, and the silicon oxide film 11 are etched back. As a result, of the three insulating films, the portion covered with the polycrystalline silicon film 14, that is, the portion disposed between the polycrystalline silicon film 14 and the silicon substrate 1, and the polycrystalline silicon film 14 And the other portion is removed, leaving a portion disposed between the gate electrode SG1 and the selection gate electrode SG1.

  Next, as shown in FIG. 16, among the polycrystalline silicon film 14 and the laminated insulating film composed of the silicon oxide film 11, the silicon nitride film 12, and the silicon oxynitride film 13, on one side wall of the select gate electrode SG1. Remove the placed part. For this, first, a photoresist film 15 is formed by photolithography or the like so as to cover one side wall of the select gate electrode SG1 and expose the other side wall. Thereafter, etching is performed using the photoresist film 15 as an etching mask, so that an exposed portion of the polycrystalline silicon film 14 and a laminated insulating film composed of the silicon oxide film 11, the silicon nitride film 12, and the silicon oxynitride film 13 are formed. Remove. In this way, the memory gate electrode MG1 made of the polycrystalline silicon film 14 is formed. Further, a memory gate insulating film MI1 made of the silicon oxide film 11, the silicon nitride film 12, and the silicon oxynitride film 13 is formed. Here, the silicon oxide film 11 functions as the lower barrier film BB1, the silicon nitride film 12 functions as the charge holding film CS1, and the silicon oxynitride film 13 functions as the upper barrier film TB1. That is, by the above process, the memory gate insulating film MI1 composed of the silicon oxide film 11 as the lower barrier film BB1, the silicon nitride film 12 as the charge holding film CS1, and the silicon oxynitride film 13 as the upper barrier film TB1 is formed. Will be formed.

  More specifically, the memory gate insulating film MI1 and the memory gate electrode MG1 formed by the above process are arranged on the silicon substrate 1 in the following manner. That is, the memory gate insulating film MI1 is arranged so as to have the lower barrier film BB1, the charge holding film CS1, and the upper barrier film TB1 in order from the side closer to the silicon substrate 1. Further, the memory gate electrode MG1 is disposed on the memory gate insulating film MI1. In other words, the memory gate electrode MG1 is disposed on the silicon substrate 1 via the memory gate insulating film MI1. In other words, the memory gate insulating film MI1 is disposed between the memory gate electrode MG1 and the silicon substrate 1. In addition, on the silicon substrate 1, the memory gate electrode MG1 is disposed adjacent to the selection gate electrode SG1. However, the memory gate insulating film MI1 disposed between the memory gate electrode MG1 and the silicon substrate 1 is similarly and integrally disposed between the memory gate electrode MG1 and the selection gate electrode SG1, It is electrically insulated. In other words, the memory gate electrode MG1 is disposed on one side wall of the selection gate electrode SG1 via the memory gate insulating film MI1. In other words, the memory gate insulating film MI1 is integrally disposed from between the memory gate electrode MG1 and the silicon substrate 1 to between the memory gate electrode MG1 and the select gate electrode SG1.

  Here, in order to adjust the conductivity type and conductivity of the memory gate electrode MG1, it is necessary to introduce a desired impurity into the polycrystalline silicon film 14 to be the memory gate electrode MG1. As the method, in the step described with reference to FIG. 14, the polysilicon film 14 into which impurities are introduced may be deposited by the CVD method, or after the polysilicon film 14 is deposited and before processing, ion implantation is performed. Impurities may be introduced by the above. However, as described with reference to FIGS. 1 to 9, in the semiconductor device of the first embodiment, the impurity concentration contained in the memory gate electrode MG1 is lower than the impurity concentration contained in the selection gate electrode SG1. Is more preferable. The reason is as described above. From this point of view, the memory gate electrode MG1 having a lower impurity concentration than the selection gate electrode SG1 can be realized by forming the non-doped polycrystalline silicon film 14 in the process of FIG.

  In the subsequent step, as shown in FIG. 17, a low concentration diffusion region which is an n-type conductivity type semiconductor region is formed in the silicon substrate 1 at the lower side of the side where the memory gate electrode MG1 and the selection gate electrode SG1 are not adjacent to each other. 4 is formed. For this, a low concentration diffusion region 4 is formed by ion-implanting a donor impurity into the silicon substrate 1. At the time of this ion implantation, the selection gate electrode SG1 and the memory gate electrode MG1 previously formed on the silicon substrate 1 serve as an ion implantation mask, and donor impurities are not introduced into the silicon substrate 1 below both the gate electrodes SG1 and MG1. . That is, the low concentration diffusion region 4 is not formed in the silicon substrate 1 under both the gate electrodes SG1, MG1, but the low concentration diffusion region 4 is formed in the silicon substrate 1 under the side walls of the gate electrodes SG1, MG1.

  Next, as shown in FIG. 18, the side wall spacer 6 is formed so as to cover the side wall where the select gate electrode SG1 and the memory gate electrode MG1 are not adjacent to each other. For this purpose, first, an insulating film mainly composed of silicon oxide, for example, is deposited by CVD or the like so as to cover the silicon substrate 1. After that, by etching back the silicon oxide film, the sidewall spacer 6 that covers the sidewalls of the selection gate electrode SG1 and the memory gate electrode MG1 can be formed. As the side wall spacer 6, in addition to silicon oxide, silicon nitride or an insulating film mainly composed of a laminated film thereof may be used.

  Next, as shown in FIG. 19, the memory gate electrode MG <b> 1 and the selection gate electrode SG <b> 1 are the lower side silicon substrate 1 that is not adjacent to each other, and at a position farther from the low concentration diffusion region 4. A high concentration diffusion region 5 which is an n-type conductivity type semiconductor region is formed. For this, a high concentration diffusion region 5 is formed by ion implantation of a donor impurity into the silicon substrate 1. At the time of this ion implantation, the selection gate electrode SG1, the memory gate electrode MG1, and the side wall spacer 6 previously formed on the silicon substrate 1 serve as an ion implantation mask, and both the gate electrodes SG1, MG1 and the side wall spacers. No donor impurity is introduced into the lower silicon substrate 1. That is, the high concentration diffusion region 5 is not formed in the silicon substrate 1 under both the gate electrodes SG1 and MG1 and under the side wall spacers 6, but under the side walls of both the gate electrodes SG1 and MG1, A high concentration diffusion region 5 is formed in the silicon substrate 1 at a position separated by a distance.

  Here, comparing the low-concentration diffusion region 4 and the high-concentration diffusion region 5, the low-concentration diffusion region 4 ionizes donor impurities with a smaller dose than the high-concentration diffusion region 5 and with a low implantation energy. inject. Therefore, the low concentration diffusion region 4 is formed so as to be lower than the impurity concentration of the high concentration diffusion region 5 and shallower than the depth of the high concentration diffusion region 5. The low concentration diffusion region 4 and the high concentration diffusion region 5 are formed so as to be in contact with each other and electrically connected. As described above, a source / drain structure including the high concentration diffusion region 5 having the low concentration diffusion region 4 as an extension region is formed.

  Here, as described with reference to FIG. 17 to FIG. 19, the memory gate electrode MG1 formed in the previous step is used as an ion implantation mask when the low concentration diffusion region 4 and the high concentration diffusion region 5 are formed. As applied. Therefore, for example, even if the non-doped polycrystalline silicon film 14 (later memory gate electrode MG1) is formed in the process of FIG. 14, the low concentration diffusion region 4 and the high concentration diffusion region 5 are introduced into the memory gate electrode MG1. Thus, a donor impurity having an impurity concentration similar to that of the donor impurity is included. However, in the process described with reference to FIG. 11, the selection gate electrode SG1 is formed so as to include more donor impurities. Thereby, an effective structure as described above can be realized in which the memory gate electrode MG1 has a lower impurity concentration than the selection gate electrode SG1.

  As described above, the basic structure of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment can be formed. Below, the formation method of the electric power feeding mechanism for electrically feeding to non-volatile memory NVM1 is demonstrated.

  As a process subsequent to the above, as shown in FIG. 20, a metal silicide layer 7 is formed on the surfaces of the memory gate electrode MG <b> 1, the select gate electrode SG <b> 1, and the high concentration diffusion region 5. For this purpose, the metal silicide layer 7 is formed by a so-called salicide process. Specifically, first, a metal film made of, for example, cobalt or nickel is deposited by a sputtering method or the like so as to cover the silicon substrate 1. Thereafter, by performing heat treatment, a silicidation reaction occurs at a position where the metal film and silicon are in contact with each other, and the metal film and silicon are combined. This compound becomes a metal silicide film made of cobalt silicide, nickel silicide, or the like. Etching is then performed to remove the metal film that has not become a metal silicide film due to the silicide reaction, thereby forming the metal silicide layer 7. In the above process, the portions where the metal film and silicon are in contact are the surfaces of the memory gate electrode MG1, the select gate electrode SG1, and the high-concentration diffusion region 5, each made of silicon. Other portions made of silicon are covered with an insulating film or the like and do not contact the metal film. Therefore, the metal silicide layer 7 can be formed on the surfaces of the memory gate electrode MG1, the select gate electrode SG1, and the high concentration diffusion region 5 as described above.

  Next, as shown in FIG. 21, an interlayer insulating film 8 made of an insulating film mainly composed of silicon oxide is formed so as to cover the silicon substrate 1. For this purpose, for example, a silicon oxide film is deposited on the silicon substrate 1 by a CVD method or the like, and surface polishing is performed by a CMP method or the like, thereby forming an interlayer insulating film 8. Here, before the interlayer insulating film 8 is deposited, an etching stop film made of an insulating film mainly composed of silicon nitride may be formed as a lower layer (not shown). Thereafter, a contact plug CP1 that penetrates the interlayer insulating film 8 and reaches the metal silicide layer 7 and a metal wiring MW1 that is electrically connected to the contact plug CP1 on the interlayer insulating film 8 are formed. For this purpose, first, a contact hole is formed in the interlayer insulating film 8 by photolithography or etching, and a contact plug made of tungsten, aluminum, copper, or the like is deposited so as to be embedded therein. Thereafter, a metal film made of aluminum, copper, or the like is deposited on the interlayer insulating film 8, and is patterned to have a desired circuit pattern by a photolithography method, an etching method, or the like, thereby forming the metal wiring MW1. Here, a barrier metal film may be formed between the contact plug CP1 and the interlayer insulating film 8 and the metal silicide layer 7 or between the metal wiring MW1 and the interlayer insulating film 8 (not shown).

  As described above, the basic configuration of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment and its power feeding mechanism can be formed. Below, the effect of forming the non-volatile memory NVM1 by the above process will be described in detail.

  For example, in the manufacturing method studied by the present inventors, as the upper barrier film, an insulating film mainly composed of silicon oxide is formed by the ISSG oxidation method. As described above, according to such an ISSG oxidation method, the corner portion such as the L-shaped portion has good rounding and can be oxidized conformally. However, in order to form a silicon oxide film having a thickness of about 4 to 5 nm on the charge retention film CS1 made of the silicon nitride film 12 while satisfying the practical throughput by the ISSG oxidation method, the temperature during processing is set high. In addition, it has been found that the hydrogen concentration during the treatment needs to be high. Such hydrogen atoms in the silicon oxide film as the lower barrier film also replace good silicon-oxygen bonds in the film or at the silicon substrate interface with silicon-hydrogen bonds. As described above, in the bond between silicon and hydrogen existing in such a lower barrier film, the hydrogen is desorbed with the transfer of carriers for memory rewriting, resulting in a defect level for capturing carriers. . Since such a defect recovers with time, it causes a variation or variation in the threshold voltage of the nonvolatile memory.

In contrast, in the method of manufacturing the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, as described with reference to FIG. 13, the silicon oxynitride film 13 as the upper barrier film TB1 is formed by the CVD method. Form. In this CVD method, for example, dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) are used as source gases, and dinitrogen monoxide (N ₂ O) is added as an oxidant to the source gases. By limiting the flow rate of ammonia, the silicon oxynitride film 13 is formed as the upper barrier film TB1. Here, there is little generation of unreacted hydrogen and diffusion of the hydrogen to the interface between the silicon substrate 1 and the lower barrier film BB1. Therefore, a good bond between silicon and oxygen is maintained at the interface between the silicon oxide film 11 as the lower barrier film BB1 and the silicon substrate 1. Therefore, it is possible to reduce the generation of interface defects associated with the exchange of carriers during the rewrite operation of the nonvolatile memory NVM1. Therefore, in the nonvolatile memory NVM1 formed by the manufacturing method of the first embodiment, the change in the amount of interface defects with the passage of time is reduced, so that the variation in threshold voltage can also be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  From another viewpoint, when a silicon oxide film as an upper barrier film is formed by thermal oxidation using an ISSG oxidation method, a dry oxidation method, a wet oxidation method, an ozone oxidation method, or the like, a nitridation as a charge retention film is performed. It has been found that a transition layer can be formed at the interface between the silicon film and the silicon oxide film as the upper barrier film. And it has been found that such a transition layer has a number of defects such as dangling bonds, and the movement of carriers is promoted through these defects. Such carrier movement causes a variation or variation in the threshold voltage of the nonvolatile memory.

  In contrast, in the method of manufacturing the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment, as described above, the silicon oxynitride film 13 as the upper barrier film TB1 is formed by the CVD method. According to this method, it is possible to reduce the generation of the interface transition layer as seen when the silicon nitride film is thermally oxidized. Therefore, carriers captured by the silicon nitride film 12 as the charge holding film CS1 in the operation of the nonvolatile memory NVM1 are more difficult to diffuse. Therefore, in the nonvolatile memory NVM1 formed by the manufacturing method according to the first embodiment, the diffusion of the trapped carriers can be suppressed and the fluctuation of the threshold voltage can be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In addition, the inventors have also clarified an appropriate temperature range at the time of repairing interface defects by hydrogen annealing after forming the memory cell transistor and the peripheral circuit transistor. Hydrogen annealing is a technique for terminating defects at the interface between a gate insulating film and a substrate of a transistor, which are generated during film formation and other process steps such as impurity implantation and etching, with hydrogen. When hydrogen annealing is not performed, intrinsic interface defects generated during film formation and other process steps remain as they are, so that the amount of interface defects becomes very large. When the amount of interface defects is large, the channel portion of the memory cell and the peripheral circuit transistor has a high resistance, and the ON current is extremely reduced. In addition, threshold variation is caused by trapping charges in the interface defect between the memory cell and the peripheral circuit transistor. Therefore, it is necessary to repair interface defects by hydrogen annealing. Since the hydrogen annealing is a repair of interface defects that can be generated during the process, it is desirable to perform the hydrogen annealing as much as possible in the subsequent steps (after the formation of the memory cells and peripheral circuit transistors). A higher temperature hydrogen atmosphere is more effective for repairing defects.

  However, as described above, annealing in a high-temperature hydrogen atmosphere replaces good silicon-oxygen bonds with silicon-hydrogen bonds, resulting in an increase in interface defects that can be generated during rewriting. Invite. Therefore, it is necessary to perform hydrogen annealing in a temperature range in which only intrinsic interface defects that occur during film formation or other processes are terminated with hydrogen and a good bond between silicon and oxygen is not substituted.

  The vertical axis in FIG. 22 shows the threshold voltage after the non-volatile memory NVM1 is subjected to a write operation and left in a 150 ° C. atmosphere for 1000 seconds. The threshold voltage immediately after the write operation is the voltage V1. The horizontal axis indicates the temperature when heat treatment is performed in a hydrogen atmosphere after the formation of the memory cell. As can be seen from FIG. 22, when the heat treatment is performed at a temperature of about 400 ° C. to 450 ° C., the threshold voltage hardly varies. On the other hand, when heat treatment is performed at a temperature exceeding 550 ° C., the threshold voltage fluctuates. According to the verification by the present inventors, when the heat treatment is performed at a temperature exceeding 550 ° C., the threshold voltage fluctuates due to the formation of an excessive bond between silicon and hydrogen and the interface defect caused by the desorption. It is thought that. In addition, it is difficult to sufficiently recover the intrinsic defect at the interface between the select gate insulating film SI1 and the channel by heat treatment at less than 400 ° C. As described above, in the method of manufacturing the semiconductor device according to the first embodiment, it is more preferable to perform the heat treatment in the hydrogen atmosphere at a temperature of 400 ° C. or higher and 550 ° C. or lower. As a result, it is possible to repair the intrinsic interface defects of the memory cell transistor and the peripheral circuit portion transistor without replacing the favorable bond between silicon and oxygen with hydrogen. Therefore, the quality of the select gate insulating film SI1 can be improved, and the operation speed and drive capability of the nonvolatile memory NVM1 can be improved. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In the process of FIG. 14 described above, a non-doped polycrystalline silicon film 14 is formed as the polycrystalline silicon film 14 that will be the memory gate electrode MG1 in the subsequent processing, whereby a memory having a lower impurity concentration than the select gate electrode SG1. It has been described that the gate electrode MG1 is formed. Here, the effect of forming the above-described upper barrier film TB1 by the CVD method and the effect of performing the above-described heat treatment do not depend on the impurity concentration of the memory gate electrode MG1. In other words, even if the memory gate electrode MG1 is formed so as to have the same impurity concentration as that of the selection gate electrode MG1, the above-described effects can be similarly exhibited.

  However, in the method of manufacturing the semiconductor device according to the first embodiment, it is more preferable that the memory gate electrode MG1 is formed so as to have a lower impurity concentration than the selection gate electrode SG1. This is because by reducing the impurity concentration of the memory gate electrode MG1, the impurity concentration in the vicinity of the interface with the memory gate insulating film MI1 is also reduced. Thereby, a depleted gate can be applied. When the gate is depleted, the electric field generated in the upper and lower barrier films TB1 and BB1 in the charge holding state is weaker than when the gate is not depleted. This is because an electric field is also generated in a portion having a low impurity concentration in the gate. Therefore, the charge retention characteristics can be further improved. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

(Embodiment 2)
A structure of the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment will be described with reference to FIG. The nonvolatile memory NVM2 included in the semiconductor device according to the second embodiment has the same components as those of the nonvolatile memory NVM1 included in the semiconductor device according to the first embodiment, except for the configuration specifically described below. Structure. FIG. 23 is a cross-sectional view of a main part of the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment, and shows the same parts as those in FIG.

  The nonvolatile memory NVM2 included in the semiconductor device according to the second embodiment has a memory gate insulating film (first gate insulating film) MI2 having the following configuration in the memory gate of the nonvolatile memory NVM1 according to the first embodiment. Different from the insulating film MI1. The upper barrier film (second barrier film) TB2 constituting the memory gate insulating film MI2 of the nonvolatile memory NVM2 of the second embodiment is an insulating film mainly composed of silicon oxide. In other words, the memory gate insulating film MI1 of the nonvolatile memory NVM1 of the first embodiment has the upper barrier film TB1 made of a silicon oxynitride film, whereas the nonvolatile memory NVM2 of the second embodiment has The memory gate insulating film MI2 has an upper barrier film TB2 made of a silicon oxide film. Specifications of other components and structure of the memory gate insulating film MI2 are the same as those of the memory gate insulating film MI1 of the first embodiment.

  Thus, in the nonvolatile memory NVM2 of the second embodiment, the silicon oxide film (lower barrier film BB1), the silicon nitride film (charge holding film CS1), and the silicon oxide film (upper barrier film TB2) are used as the memory gate insulating film MI2. MONOS type memory having a split gate structure. This is structurally similar to the conventional nonvolatile memory (for example, the nonvolatile memory NVMb described with reference to FIGS. 46 to 52 described above) examined in advance by the present inventors. However, the non-volatile memory NVM2 included in the semiconductor device of the second embodiment is characterized by its manufacturing method. A method for manufacturing the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment will be described in detail below with reference to FIGS. 24 to 26 are cross-sectional views of main parts at the same positions as those in FIGS. 10 to 21, explaining the method of manufacturing the semiconductor device of the first embodiment, during the manufacturing process of the semiconductor device of the second embodiment. Is shown.

  First, as shown in FIG. 24, the isolation portion 2, the p-well 3, the select gate insulating film SI1, and the select gate electrode are formed on the silicon substrate 1 in the same manner as described with reference to FIGS. SG1, a silicon oxide film 11, and a silicon nitride film 12 are formed.

  Next, as shown in FIG. 25, a silicon oxide film (second barrier film) 16 is formed so as to cover the silicon nitride film 12. Thereafter, as shown in FIG. 26, in the same manner as described with reference to FIGS. 14 to 16, the lower barrier film BB1 made of the silicon oxide film 11, the charge holding film CS1 made of the silicon nitride film 12, and Then, a memory gate insulating film MI2 made of a three-layer laminated insulating film made of the upper barrier film TB2 made of the silicon oxide film 16, and a memory gate electrode MG1 covering the upper part thereof are formed. Subsequently, in the same manner as described with reference to FIGS. 17 to 21, the low concentration diffusion region 4, the sidewall spacer 6, the high concentration diffusion region 5, the metal silicide layer 7, the interlayer insulating film 8, and the contact plug. CP1 and metal wiring MW1 are formed. In this way, a semiconductor device having the nonvolatile memory NVM2 of the second embodiment is formed.

Here, the manufacturing method of the semiconductor device according to the second embodiment has the following characteristics in the method of forming the silicon oxide film 16 as the upper barrier film TB2 constituting the memory gate insulating film MI2. That is, in the manufacturing method of the semiconductor device of the second embodiment, the silicon oxide film 16 that is an insulating film mainly composed of silicon oxide is formed by the CVD method so as to cover the silicon nitride film 12 as the charge holding film CS1. To do. In particular, in the step of forming the silicon oxide film 16 by this CVD method, a gas containing silicon tetrachloride (SiCl ₄ ) or dichlorosilane (SiH ₂ Cl ₄ ) and dinitrogen monoxide (N ₂ O) is used. Typical reactions include SiH ₂ Cl ₄ + 3N ₂ O → SiO ₂ + H ₂ O + 3N ₂ + Cl ₂ and SiCl ₄ + 2N ₂ O → SiO ₂ + 2N ₂ + 2Cl ₂ . A silicon oxide film on which silicon oxide (SiO ₂ ) generated by such a reaction is deposited may be referred to as an HTO (High Temperature Oxide) film or the like. In other words, in the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment, the HTO film is applied as the upper barrier film TB2 that constitutes the memory gate insulating film MI2.

  For example, in the manufacturing method studied by the present inventors, as the upper barrier film, an insulating film mainly composed of silicon oxide is formed by the ISSG oxidation method. As described above, according to such an ISSG oxidation method, the corner portion such as the L-shaped portion has good rounding and can be oxidized conformally. However, in order to form a silicon oxide film having a thickness of about 4 to 5 nm on the charge retention film CS1 made of the silicon nitride film 12 while satisfying the practical throughput by the ISSG oxidation method, the temperature during processing is set high. In addition, it has been found that the hydrogen concentration during the treatment needs to be high. Such hydrogen atoms in the silicon oxide film as the lower barrier film also replace good silicon-oxygen bonds in the film or at the silicon substrate interface with silicon-hydrogen bonds. As described above, in the bond between silicon and hydrogen existing in such a lower barrier film, the hydrogen is desorbed with the transfer of carriers for memory rewriting, resulting in a defect level for capturing carriers. . Since such a defect recovers with time, it causes a variation or variation in the threshold voltage of the nonvolatile memory.

  On the other hand, in the method for manufacturing the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment, the silicon oxide film 16 that is silicon oxide (particularly, HTO film) formed by the CVD method is applied as the upper barrier film TB2. is doing. Here, since it is not based on the ISSG method, there is almost no generation of unreacted hydrogen and diffusion of the hydrogen to the interface between the silicon substrate 1 and the lower barrier film BB1. Therefore, a good bond between silicon and oxygen is maintained at the interface between the silicon oxide film 11 as the lower barrier film BB1 and the silicon substrate 1. Therefore, it is possible to reduce the generation of interface defects associated with the exchange of carriers during the rewrite operation of the nonvolatile memory NVM2. Therefore, in the nonvolatile memory NVM2 formed by the manufacturing method of the second embodiment, the change in the amount of interface defects with the passage of time is reduced, so that the variation in threshold voltage can also be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  Further, by applying the HTO film formed by the CVD method as the upper barrier film TB2, a transition layer is formed between the silicon nitride film 12 as the charge holding film CS1 and the silicon oxide film 16 as the upper barrier film TB2. Therefore, the ease of movement of trapped charges in the film can be reduced. Thereby, the fluctuation | variation of the threshold voltage during the memory operation of the nonvolatile memory NVM2 can be further reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  Furthermore, the other effect of forming the upper barrier film TB2 with the HTO film by the CVD method as described above can be exhibited during the array operation of the nonvolatile memory NVM2. This will be described in detail below.

  According to the study by the present inventors, there is a problem (disturb mode) that other memory cells are erroneously written and erased when writing to a certain memory cell during array operation of a MONOS type memory having a split gate structure. is there. For example, consider the case where the memory gate word line MGL0 and the memory gate word line MGL2 are bundled in the array configuration of FIG. 49 and the same voltage is applied to them. The memory gate word lines MGL may be bundled in order to speed up the memory write, erase and read operations and reduce the peripheral circuit area.

  When a write operation is performed on the memory cells selected by the bit line BL0 and the selection gate word line SGL0 by the SSI method, a positive high voltage is applied to the memory gate word line MGL0. At this time, a positive high voltage is also applied to the other memory gate word line MGL2 bundled together with the memory gate word line MGL0. Therefore, as the writing is sequentially performed, the disturb time (time during which a high voltage is applied to the memory gate) received by a certain non-selected cell becomes longer than the writing time of one cell. In particular, the greater the number of memory gate word lines MGL bundled, the longer the disturb time received by one unselected cell. When such an array configuration is assembled, the disturb resistance is improved as the barrier potential of the upper barrier film TB2 is higher. This is because even when a high voltage is applied to the memory gate, it is difficult to extract charges from the gate. When the upper barrier film TB2 is an HTO film, the barrier potential is sufficiently high, so that the disturbance as described above hardly occurs. Therefore, more memory gate word lines MGL can be bundled. Further, the writing unit can be made smaller. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  FIG. 27 shows retention characteristics of the nonvolatile memory NVM2 when an HTO film is applied as the silicon oxide film 16 to be the upper barrier film TB2. Here, the same write threshold voltage and erase threshold voltage are determined for each sample, and the threshold voltage change after 1000 times of the SSI write operation and the BTBT erase operation under the same conditions at room temperature is shown. Show. In order to clarify a significant difference in a short time, the retention characteristics are evaluated at a temperature of 150 ° C. The vertical axis represents the amount of change in the threshold voltage after being left at a temperature of 150 ° C. for 1 hour after the write operation to the nonvolatile memory NVM2. That is, the characteristic on the upper side of the figure indicates that the threshold voltage varies greatly. The horizontal axis shows the thickness of the silicon oxide film 16 as the upper barrier film TB2. In particular, FIG. 27 shows characteristics P09 to P11 when the method of forming the silicon oxide film 16 and the heat treatment after the formation are changed. More specifically, a characteristic when a silicon oxide film 16 made of an HTO film is formed as the upper barrier film TB2 by a CVD method and then heat-treated at 750 ° C. in a wet oxidizing atmosphere containing water vapor is defined as a characteristic P09. Show. The processing time is a time required to oxidize about 5 nm when oxidizing the silicon substrate. A characteristic P10 is shown as a characteristic when a silicon oxide film 16 made of an HTO film is formed as the upper barrier film TB2 by the CVD method and then heat-treated at about 1000 ° C. for 60 seconds in a nitrogen atmosphere. For comparison, a characteristic when a silicon oxide film is formed as the upper barrier film by the ISSG oxidation method is shown as a characteristic P11.

  According to FIG. 27, the threshold voltage fluctuation of the nonvolatile memory NVM2 is smaller when the silicon oxide film 16 made of the HTO film by the CVD method is used as the upper barrier film TB2 than when the silicon oxide film formed by the ISSG oxidation method is used. It can be seen that the retention characteristics can be improved. As described above, when the silicon oxide film 16 made of the HTO film by the CVD method is formed, it is difficult to cause defects in the lower barrier film BB1 by not introducing hydrogen as in ISSG oxidation. The effect of being able to do.

  Further, according to the study by the present inventors, it has been found that even when the HTO film is subjected to a heat treatment after deposition, charge leakage increases in the thin film region. Therefore, as the characteristic P09, when the thickness of the silicon oxide film 16 as the upper barrier film TB2 is less than 6 nm, the threshold voltage starts to increase. Therefore, when the silicon oxide film 16 made of an HTO film is applied as the upper barrier film TB2, it is more preferable to set the film thickness to 6 nm or more. On the other hand, as described in the first embodiment, from the viewpoint of practical erasing speed, the total thickness of the memory gate insulating film MI2 should be 17.5 nm or less in terms of equivalent oxide thickness (EOT). More preferred. In summary, in the nonvolatile memory NVM2 included in the semiconductor device of the second embodiment, the memory gate insulating film MI2 is formed so that the total thickness is 17.5 nm or less in terms of the equivalent oxide thickness, The silicon oxide film 16 as the upper barrier film TB2 is more preferably formed so as to have a thickness of 6 nm or more.

  Further, comparing the characteristics P09 and the characteristics P10, it can be seen that even when the same HTO film is formed as the silicon oxide film 16 of the upper barrier film TB2, the retention characteristics of the nonvolatile memory NVM2 are different depending on the heat treatment after the formation. . More specifically, it has been found that the retention characteristics are improved when the heat treatment is performed in a nitrogen atmosphere as compared with the case where the heat treatment is performed in a wet oxidation atmosphere after the HTO film is formed. This is an effect that the deterioration of the lower barrier film BB1 is further improved because the amount of hydrogen contained in the nitrogen atmosphere is further reduced compared to the wet oxidation atmosphere.

  However, even when heat treatment is performed in a wet oxidizing atmosphere, the amount of hydrogen present is very small, and only a small part of the bond between silicon and oxygen in the lower barrier film BB1 is replaced with hydrogen. Further, according to verification by the present inventors from another viewpoint, it was found that the etching resistance by hydrofluoric acid (HF) is improved by heat-treating the silicon oxide film 16 made of an HTO film in a wet oxidation atmosphere. . It was also found that the etching system for hydrofluoric acid can be improved by increasing the heat treatment time or increasing the temperature. This is an etching process when the memory gate electrode MG1 is formed in a sidewall shape of the selection gate electrode SG1, and side etching entering the silicon oxide film 16 as the upper barrier film TB2 can be reduced. This is effective in reducing the dimensional variation of the nonvolatile memory NVM2 in the entire surface of the silicon substrate 1 (in the wafer surface).

  In addition, the inventors further verified the heat treatment conditions for improving the quality of the HTO film as the silicon oxide film 16 of the upper barrier film TB2.

  As a result, when an HTO film is formed as the silicon oxide film 16 of the upper barrier film TB2 and then heat treatment is performed in a wet oxidizing atmosphere, single crystal silicon (for example, the silicon substrate 1) is formed at a temperature of 650 ° C. or higher and 900 ° C. or lower. It was found that the above-mentioned effect can be obtained by performing the heat treatment for a time period during which oxidation is performed for 1 nm or more and 10 nm or less. More preferably, it has been found that the above-described effects can be obtained more remarkably by performing the heat treatment at a temperature of 700 ° C. or higher for a time period during which single crystal silicon (for example, the silicon substrate 1) is oxidized by 3 nm or more.

  In addition, when heat treatment is performed in a nitrogen atmosphere after forming the HTO film as the silicon oxide film 16 of the upper barrier film TB2, the temperature is 800 ° C. or higher and 1100 ° C. or lower and the time is 10 seconds or longer and 120 seconds or shorter. It turned out that the above-mentioned effect is acquired by performing the said heat processing. More preferably, it has been found that the above-described effects can be obtained more significantly by performing the heat treatment at a temperature of 900 ° C. or higher.

(Embodiment 3)
In the first and second embodiments, the example in which the present invention is applied to the MONOS type memory having the split gate structure and the manufacturing method thereof has been described. The third embodiment shows an example in which the present invention is applied to a MONOS type memory having a single gate structure and a manufacturing method thereof.

  The structure of nonvolatile memory NVM3 included in the semiconductor device of the third embodiment will be described with reference to FIGS. FIG. 28 is a cross-sectional view of the main part of the nonvolatile memory NVM3, and FIG. 29 is a plan view of the main part of the nonvolatile memory NVM3. In particular, FIG. 28 shows a cross-sectional view of the main part viewed in the direction of the arrow along the line A2-A2 and the line B2-B2 in the main part plan view of FIG.

  The non-volatile memory NVM3 of the third embodiment has the same structure as the non-volatile memories NVM1 and NVM2 of the first and second embodiments except that the gate structure has the following characteristics. The duplicate description here is omitted.

  The nonvolatile memory NVM3 includes a memory gate insulating film (first gate insulating film) MI3 formed on the silicon substrate 1 and a memory gate electrode (first gate electrode) MG3 formed thereon. . The gate electrode constituting the nonvolatile memory NVM3 as the unit cell is only the memory gate electrode MG3, and does not have the selection gate electrode SG1 as in the first and second embodiments, for example. As described above, the basic structure of the nonvolatile memory NVM3 included in the semiconductor device according to the third embodiment is a MONOS type memory having a single gate structure. The structure and operation method of the MONOS type memory having a single gate structure examined in advance by the present inventors are as described in the nonvolatile memory NVMa described with reference to FIGS.

  The memory gate insulating film MI3 of the nonvolatile memory NVM3 of Embodiment 3 includes, in order from the side closer to the silicon substrate 1, the lower barrier film (first barrier film) BB3, the charge holding film CS3, and the upper barrier film (first barrier film). 2 barrier film) It consists of a three-layer laminated insulating film of TB3. In other words, the memory gate insulating film MI3 has a structure in which the charge holding film CS3 is sandwiched between the lower barrier film BB3 and the upper barrier film TB3. The lower barrier film BB3 is an insulating film mainly composed of silicon oxide, the charge retention film CS3 is an insulating film mainly composed of silicon nitride, and the upper barrier film TB3 is an insulating film mainly composed of silicon oxynitride.

  As a source / drain mechanism for transferring charges in the nonvolatile memory NVM3, two types of impurity diffusion regions 17 and 18 are formed on the main surface side of the silicon substrate 1. More specifically, the low concentration diffusion region 17 is formed in the silicon substrate 1 below the side of the memory gate electrode MG3. Further, a high concentration diffusion region 18 is formed in the silicon substrate 1 at the same lower side of the memory gate electrode MG3 and at a position farther from the low concentration diffusion region 17. Each of the diffusion regions 17 and 18 is an n-type semiconductor region containing donor impurities. Their donor impurity concentration is lower in the low concentration diffusion region 17 than in the high concentration diffusion region 18. Further, the depth seen from the main surface of the silicon substrate 1 is shallower in the low concentration diffusion region 17 than in the high concentration diffusion region 18. Further, the low concentration diffusion region 17 and the high concentration diffusion region 18 are in contact with each other at the end portions, and are electrically connected. This low concentration diffusion region 17 is called an LDD structure in the source / drain mechanism and functions as a so-called extension region.

  On the main surface of the silicon substrate 1, sidewall spacers 19 are arranged so as to cover the sidewalls of the memory gate electrode MG3. The sidewall spacer 19 is formed at a position that covers at least the low concentration diffusion region 17 formed in the silicon substrate 1. The sidewall spacer 19 is made of, for example, an insulating film mainly composed of silicon oxide, an insulating film mainly composed of silicon nitride, or a laminated film thereof.

  In addition to these, the nonvolatile memory NVM3 included in the semiconductor device according to the third embodiment has the same components as the nonvolatile memories NVM1 and NVM2 included in the semiconductor device according to the first and second embodiments.

  As described above, the nonvolatile memory NVM3 included in the semiconductor device according to the third embodiment has the insulating film mainly composed of silicon oxynitride as the upper barrier film TB3. This is the same as the upper barrier film TB1 of the nonvolatile memory NVM1 included in the semiconductor device of the first embodiment. Regarding the effect of the non-volatile memory NVM3, which is a MONOS type memory having a single gate structure, having a silicon oxynitride film as the upper barrier film TB3, the non-volatile type being a MONOS type memory having a split gate structure described in the first embodiment. This is similar to the effect of the volatile memory NVM1 having the silicon oxynitride film as the upper barrier film TB1. Briefly described, effects such as relaxation of charge localization associated with the rewrite operation and difficulty in forming a transition layer between the charge holding film CS3 and the upper barrier film TB3 can be obtained. . Thereby, fluctuations and variations in the threshold voltage in the nonvolatile memory NVM3 can be reduced. Further, in the nonvolatile memory NVM3 of the third embodiment, a more preferable composition and film thickness when applying a silicon oxynitride film as the upper barrier film TB3 are the same as the composition and film thickness described in the first embodiment. It is.

  However, in the MONOS type memory having the single gate structure of the nonvolatile memory NVM3 of the third embodiment, the localization of electric charges due to rewriting hardly occurs. For example, in the NROM type MONOS memory, when the write / erase operation described with reference to FIGS. 42 and 43 is performed, the electron injection position and the hole injection position are substantially the same position. Accordingly, the remaining charge (accumulation of residual carriers, charge localization) hardly occurs due to the shift of the injection position. Therefore, the necessity of lowering the barrier potential of the upper barrier film and facilitating the injection of charges from the memory gate electrode MG3 side in order to eliminate the localization of charges in the nonvolatile memory NVM3 of the third embodiment is as described above. It is not as high as the nonvolatile memory NVM1 of the first embodiment. Therefore, in the nonvolatile memory NVM3 of the third embodiment, the silicon oxynitride film as the upper barrier film TB3 has a composition x (the definition of the composition x is as described above) of 1, that is, silicon nitride. An insulating film mainly containing only silicon oxide not included may be used.

  As described above, according to the nonvolatile memory NVM3 of the third embodiment, the threshold voltage is applied to the MONOS memory having a single gate structure by applying the silicon oxynitride film as the upper barrier film TB3 of the memory gate insulating film MI3. Fluctuations and variations can be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  A method of manufacturing the semiconductor device according to the third embodiment including the nonvolatile memory NVM3 having the above effects will be described with reference to FIGS. 30 to 39 are fragmentary cross-sectional views of the region corresponding to FIG. 29 during the manufacturing process.

  First, as shown in FIG. 30, the isolation portion 2 and the p-well 3 are formed in the silicon substrate 1 in the same manner as described with reference to FIG. 10. Subsequently, as shown in FIG. 31, a silicon oxide film 11 and a silicon nitride film 12 are formed in the same manner as described with reference to FIG.

  Next, as shown in FIG. 32, a silicon oxynitride film (second barrier film) 20 that is an insulating film mainly composed of silicon oxynitride is formed so as to cover the silicon nitride film 12 formed on the silicon substrate 1. Form. Here, in the method of manufacturing the semiconductor device according to the third embodiment, the silicon oxynitride film 20 is deposited by the CVD method. For example, the silicon oxynitride film 20 is deposited by CVD so that the composition ratio x is 0.55 (refractive index RI is 1.7) and the film thickness is about 9 nm. The silicon oxynitride film 20 formed in this step is an insulating film that becomes the upper barrier film TB3 of the memory gate insulating film MI3 by processing described later. That is, the effect of forming the upper barrier film TB3 with the silicon oxynitride film 20 is as described above.

  Next, as shown in FIG. 33, a polycrystalline silicon film 21 is formed so as to cover the silicon oxynitride film 20. Here, the polycrystalline silicon film 21 is formed by, eg, CVD. After that, as shown in FIG. 34, a gate structure is formed by sequentially processing the polycrystalline silicon film 21, the silicon oxynitride film 20, the silicon nitride film 12, and the silicon oxide film 11 by a photolithography method, an etching method, or the like. To do. More specifically, the memory gate electrode MG3 made of the polycrystalline silicon film 21 is formed. Further, a memory gate insulating film MI3 made of the silicon oxide film 11, the silicon nitride film 12, and the silicon oxynitride film 20 is formed. Here, the silicon oxide film 11 functions as the lower barrier film BB3, the silicon nitride film 12 functions as the charge holding film CS3, and the silicon oxynitride film 20 functions as the upper barrier film TB3. That is, the silicon oxide film 11 as the lower barrier film BB3, the silicon nitride film 12 as the charge holding film CS3, and the silicon oxynitride film 20 as the upper barrier film TB3 are formed by the above steps.

  Here, in order to adjust the conductivity type and conductivity of the memory gate electrode MG3, it is necessary to introduce a desired impurity into the polycrystalline silicon film 21 to be the memory gate electrode MG3. In the process described with reference to FIG. 34, the polycrystalline silicon film 21 into which the impurity is introduced may be deposited by a CVD method, or after the polycrystalline silicon film 21 is deposited, the impurity is introduced by ion implantation before processing. May be.

  Next, as shown in FIG. 35, a low-concentration diffusion region 17 which is an n-type conductivity type semiconductor region is formed in the silicon substrate 1 on the lower side of the memory gate electrode MG3. For this, a low concentration diffusion region 17 is formed by ion-implanting a donor impurity into the silicon substrate 1. In this ion implantation, the memory gate electrode MG3 previously formed on the silicon substrate 1 serves as an ion implantation mask. That is, the low concentration diffusion region 17 is not formed in the silicon substrate 1 under the memory gate electrode MG3, but the low concentration diffusion region 17 is formed in the silicon substrate 1 under the side wall of the memory gate electrode MG3.

  Next, as shown in FIG. 36, sidewall spacers 19 are formed so as to cover the sidewalls of the memory gate electrode MG3. For this purpose, sidewall spacers 19 are formed in the same manner as described with reference to FIG.

  Next, as shown in FIG. 37, in the silicon substrate 1 on the lower side of the memory gate electrode MG3, a high concentration diffusion which is an n-type conductivity type semiconductor region is provided at a location far from the low concentration diffusion region 17. Region 18 is formed. For this, a high concentration diffusion region 18 is formed by ion implantation of donor impurities into the silicon substrate 1. In this ion implantation, the memory gate electrode MG3 and the side wall spacer 19 previously formed on the silicon substrate 1 serve as an ion implantation mask, and the silicon substrate 1 under the memory gate electrode MG3 and the side wall spacer 19 has a donor impurity. Is not introduced. That is, the high-concentration diffusion region 18 is not formed in the silicon substrate 1 under the memory gate electrode MG3 and under the side wall spacer 19, and is located under the side wall side of the memory gate electrode MG3 and separated by the side wall spacer 19. A high concentration diffusion region 18 is formed in the silicon substrate 1 at the position.

  Here, comparing the low-concentration diffusion region 17 and the high-concentration diffusion region 18, the low-concentration diffusion region 17 is smaller in dose than the high-concentration diffusion region 18, and donor impurities are ionized with a low implantation energy. inject. Accordingly, the low concentration diffusion region 17 is formed so as to be lower than the impurity concentration of the high concentration diffusion region 18 and shallower than the depth of the high concentration diffusion region 18. The low concentration diffusion region 17 and the high concentration diffusion region 18 are formed so as to be in contact with each other and to be electrically connected. As described above, the source / drain structure including the high concentration diffusion region 18 having the low concentration diffusion region 17 as the extension region is formed.

  As described above, the basic structure of the nonvolatile memory NVM3 included in the semiconductor device of the third embodiment can be formed. Below, the formation method of the electric power feeding mechanism for supplying electric power to the non-volatile memory NVM3 is demonstrated.

  As a subsequent process, a metal silicide layer 7 is formed on the surfaces of the memory gate electrode MG3 and the high concentration diffusion region 18, as shown in FIG. For this purpose, the metal silicide layer 7 is formed in the same manner as described with reference to FIG.

  Next, as shown in FIG. 39, the interlayer insulating film 8, the contact plug CP1, and the metal wiring MW1 are formed in the same manner as in the process of FIG.

  As described above, the basic configuration of the nonvolatile memory NVM3 included in the semiconductor device of the third embodiment and its power feeding mechanism can be formed.

  As described above, in the method of manufacturing the semiconductor device according to the third embodiment, the silicon oxynitride film 20 as the upper barrier film TB3 is formed by the CVD method. The effect of forming the silicon oxynitride film 20 as the upper barrier film TB3 by the CVD method is that the silicon oxynitride film 13 as the upper barrier film TB1 described in the first embodiment is formed by the CVD method. It is the same as the effect. To explain briefly again, the upper barrier film TB3 is formed by the CVD method, so that high-temperature and high-concentration hydrogen as in the ISSG oxidation method is not used, so that the lower barrier film BB3 is difficult to diffuse hydrogen. Can do. Thereby, it is possible to form the lower barrier film BB3 in which defects are not easily generated even in a plurality of rewrites.

  Further, when a silicon oxynitride film (that is, a silicon oxide film) having a composition ratio x of 1 is formed as the upper barrier film TB3, it is desirable to form an HTO film by the CVD method. The reason is the same as the effect obtained by applying the HTO film to the upper barrier film TB2 in the MONOS type memory having the split gate structure as described in the second embodiment.

  As described above, according to the method for forming the non-volatile memory NVM3 of the third embodiment, fluctuations and variations in threshold voltage can be further reduced in the MONOS memory having a single gate structure. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device including a memory cell.

1 Silicon substrate (semiconductor substrate)
2 Separation part 3 P well 4,17 Low concentration diffusion region 5,18 High concentration diffusion region 6,19 Side wall spacer 7 Metal silicide layer 8 Interlayer insulating film 9 Silicon oxide film 10, 14, 21 Polycrystalline silicon film 11 Silicon oxide Film (first barrier film)
12 Silicon nitride film (charge retention film)
13,20 Silicon oxynitride film (second barrier film)
15 Photoresist film 16 Silicon oxide film (second barrier film)
DESCRIPTION OF SYMBOLS 100 Silicon substrate 200,300 Diffusion layer 400 Memory gate insulating film 401 Lower silicon oxide film 402 Silicon nitride film 403 Upper silicon oxide film 500 Memory gate electrode 510 Memory transistor 600 Contact 700 Select gate insulating film 800 Select gate electrode 810 Select transistor BB1, BB3 Lower barrier film (first barrier film)
BL, BL0 Bit line BL1 First bit line (bit line)
BL2 Second bit line (bit line)
CP1 Contact plug CS1, CS3 Charge holding film D1, D2, D3, D4 Charge distribution EN Electron HL Hole ID Drain current MG1, MG3 Memory gate electrode (first gate electrode)
MGL, MGL0 to MGL3 Word line for memory gate MI1, MI2, MI3 Memory gate insulating film (first gate insulating film)
MW1 Metal wiring NVM1, NVM2, NVM3 Non-volatile memory NVMa, NVMb Non-volatile memory P01 to P10 Characteristics RI Refractive index SG1 Select gate electrode SGL, SGL0 to SGL3 Select gate word line SI1 Select gate insulating film (second gate insulating film)
SL, SL0, SL1 Source line TB1, TB2, TB3 Upper barrier film (second barrier film)
WL Word line x composition ratio

Claims (26)

A semiconductor device having a nonvolatile memory disposed on a semiconductor substrate,
The nonvolatile memory is
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
The first gate insulating film is constituted by a laminated film including three layers of a first barrier film, a charge holding film, and a second barrier film in order from the side closer to the semiconductor substrate,
The first barrier film is an insulating film mainly composed of silicon oxide,
The charge retention film is an insulating film mainly composed of silicon nitride,
The second barrier film is an insulating film mainly composed of silicon oxynitride,
In the second barrier film, a ratio of the silicon oxide in the silicon oxynitride is greater than 0.46 and not greater than 0.92. The semiconductor device according to claim 1,
The nonvolatile memory further includes:
A second gate insulating film formed on the semiconductor substrate;
A second gate electrode formed on the second gate insulating film,
The first gate electrode is disposed adjacent to the second gate electrode;
The first gate insulating film is integrally disposed from between the first gate electrode and the semiconductor substrate to between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode are electrically insulated by the first gate insulating film,
The semiconductor device according to claim 1, wherein the second gate insulating film is an insulating film mainly composed of silicon oxide. The semiconductor device according to claim 2,
In the second barrier film constituting the first gate insulating film, the ratio of the silicon oxide in the silicon oxynitride is 0.55 or more. The semiconductor device according to claim 2,
The total thickness of the first gate insulating film is 17.5 nm or less in terms of equivalent oxide thickness,
The semiconductor device according to claim 1, wherein the second barrier film constituting the first gate insulating film has a thickness of 5 nm or more. The semiconductor device according to claim 4.
2. The semiconductor device according to claim 1, wherein the second barrier film constituting the first gate insulating film has a thickness of 9 nm or more. The semiconductor device according to claim 2,
The first gate electrode and the second gate electrode are mainly composed of polycrystalline silicon,
The semiconductor device according to claim 1, wherein an impurity concentration contained in the first gate electrode is lower than an impurity concentration contained in the second gate electrode. The semiconductor device according to claim 1,
The nonvolatile memory is
An erasing operation is performed by injecting hot holes into the first gate insulating film. The semiconductor device according to claim 1,
The nonvolatile memory is
A write operation is performed by injecting hot electrons generated by accelerating charges in the channel into the first gate insulating film,
An erasing operation is performed by injecting hot holes generated by a band-to-band tunnel phenomenon between the diffusion layer formed on the semiconductor substrate and the semiconductor substrate into the first gate insulating film. Semiconductor device. The semiconductor device according to claim 2,
The nonvolatile memory is
A write operation is performed by a source side injection method in which hot electrons generated by creating a high electric field from the second gate electrode to the first gate electrode side are injected into the first gate insulating film,
Injecting hot holes generated by a band-band tunneling phenomenon between the diffusion layer formed in the semiconductor substrate below the side of the first gate electrode and the semiconductor substrate into the first gate insulating film. A semiconductor device characterized by performing an erasing operation. A method of manufacturing a semiconductor device including a step of forming a nonvolatile memory on a semiconductor substrate,
The step of forming the nonvolatile memory includes
(A) forming a first gate insulating film on the semiconductor substrate;
(B) forming a first gate electrode on the first gate insulating film;
In the step (a),
As the first gate insulating film, a first barrier film, a charge holding film, and a second barrier film are formed in order from the side closer to the semiconductor substrate, so that the first barrier film, the charge holding film, and Forming the first gate insulating film composed of a laminated film of three layers of the second barrier film;
Forming an insulating film mainly composed of silicon oxide as the first barrier film;
As the charge retention film, an insulating film mainly composed of silicon nitride is formed,
As the second barrier film, an insulating film mainly composed of silicon oxynitride is formed by chemical vapor deposition,
The method of manufacturing a semiconductor device, wherein the second barrier film is formed so that a ratio of the silicon oxide in the silicon oxynitride is greater than 0.46 and not more than 0.92. The method of manufacturing a semiconductor device according to claim 10.
The step of forming the nonvolatile memory further includes:
(C) forming a second gate insulating film on the semiconductor substrate;
(D) forming a second gate electrode on the second gate insulating film,
In the step (a), the step (b), the step (c) and the step (d),
The first gate electrode is formed adjacent to the second gate electrode,
The first gate insulating film is integrally disposed from between the first gate electrode and the semiconductor substrate to between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode are formed so as to be electrically insulated by the first gate insulating film,
In the step (c), an insulating film mainly containing silicon oxide is formed as the second gate insulating film. The method of manufacturing a semiconductor device according to claim 11.
The step of forming the nonvolatile memory further includes:
(E) having a step of performing heat treatment in a hydrogen atmosphere;
In the step (e), the heat treatment is performed at a temperature of 400 ° C. or higher and 550 ° C. or lower. In the manufacturing method of the semiconductor device according to claim 12,
The method (e) is performed after the step (b). 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (a),
The method of manufacturing a semiconductor device, wherein the second barrier film is formed so that a ratio of the silicon oxide in the silicon oxynitride is 0.55 or more. 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (a),
The first gate insulating film is formed so that the total thickness is 17.5 nm or less in terms of equivalent oxide thickness,
The method of manufacturing a semiconductor device, wherein the second barrier film is formed to have a thickness of 5 nm or more. In the manufacturing method of the semiconductor device according to claim 15,
In the step (a),
The method of manufacturing a semiconductor device, wherein the second barrier film is formed to have a thickness of 9 nm or more. 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (b) and the step (d),
Forming the first gate electrode and the second gate electrode from polycrystalline silicon;
In the step (b), the first gate is formed by forming the polycrystalline silicon having an impurity concentration lower than that of the polycrystalline silicon formed to form the second gate electrode in the step (d). A method of manufacturing a semiconductor device, comprising forming an electrode. A method of manufacturing a semiconductor device including a step of forming a nonvolatile memory on a semiconductor substrate,
The step of forming the nonvolatile memory includes
(A) forming a first gate insulating film on the semiconductor substrate;
(B) forming a first gate electrode on the first gate insulating film;
In the step (a),
As the first gate insulating film, a first barrier film, a charge holding film, and a second barrier film are formed in order from the side closer to the semiconductor substrate, so that the first barrier film, the charge holding film, and Forming the first gate insulating film composed of a laminated film of three layers of the second barrier film;
Forming an insulating film mainly composed of silicon oxide as the first barrier film;
As the charge retention film, an insulating film mainly composed of silicon nitride is formed,
As the second barrier film, an insulating film mainly composed of silicon oxide is formed by chemical vapor deposition,
In the chemical vapor deposition method for forming the second barrier film, a gas containing silicon tetrachloride or dichlorosilane and dinitrogen monoxide is used. The method of manufacturing a semiconductor device according to claim 18.
The step of forming the nonvolatile memory further includes:
(C) forming a second gate insulating film on the semiconductor substrate;
(D) forming a second gate electrode on the second gate insulating film,
In the step (a), the step (b), the step (c) and the step (d),
The first gate electrode is formed adjacent to the second gate electrode,
The first gate insulating film is integrally disposed from between the first gate electrode and the semiconductor substrate to between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode are formed so as to be electrically insulated by the first gate insulating film,
In the step (c), an insulating film mainly containing silicon oxide is formed as the second gate insulating film. In the manufacturing method of the semiconductor device according to claim 19,
The step of forming the nonvolatile memory further includes:
(E) after forming the second barrier film in the step (a), and performing a heat treatment in a wet oxidizing atmosphere;
In the step (e), the heat treatment is performed in the wet oxidation atmosphere at a temperature of 650 ° C. or higher and 900 ° C. or lower for a time during which the semiconductor substrate is oxidized by 1 nm or more and 10 nm or less. Method. The method of manufacturing a semiconductor device according to claim 20,
In the step (e), the heat treatment is performed in the wet oxidizing atmosphere at a temperature of 700 ° C. or higher for a time for oxidizing the semiconductor substrate by 3 nm or more. In the manufacturing method of the semiconductor device according to claim 19,
The step of forming the nonvolatile memory further includes:
(F) having a step of performing a heat treatment in a nitrogen atmosphere after forming the second barrier film in the step (a),
In the step (f), the heat treatment is performed in the nitrogen atmosphere at a temperature of 800 ° C. or higher and 1100 ° C. or lower for a time of 10 seconds or longer and 120 seconds or shorter. The method of manufacturing a semiconductor device according to claim 22,
In the step (f), the heat treatment is performed in the nitrogen atmosphere at a temperature of 900 ° C. or higher. In the manufacturing method of the semiconductor device according to claim 19,
In the step (a),
The first gate insulating film is formed so that the total thickness is 17.5 nm or less in terms of equivalent oxide thickness,
The method of manufacturing a semiconductor device, wherein the second barrier film is formed to have a thickness of 6 nm or more. In the manufacturing method of the semiconductor device according to claim 19,
The step of forming the nonvolatile memory further includes:
(G) having a step of performing a heat treatment in a hydrogen atmosphere;
In the step (g), the heat treatment is performed at a temperature of 400 ° C. or higher and 550 ° C. or lower. The method of manufacturing a semiconductor device according to claim 25,
The method (g) is performed after the step (b).

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