CN114335004A

CN114335004A - 1.5T SONOS device and preparation method thereof

Info

Publication number: CN114335004A
Application number: CN202210238753.0A
Authority: CN
Inventors: 程晨; 王彬; 徐凯; 吴李瑞
Original assignee: Jiangsu Peregrine Microelectronics Co ltd
Current assignee: Jiangsu Daoyuan Technology Group Co ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-04-12
Anticipated expiration: 2042-03-11
Also published as: CN114335004B

Abstract

The invention discloses a 1.5T SONOS device and a preparation method thereof, wherein an isolation effect is enhanced by depositing and filling silicon oxide nitride between a grid electrode of a storage tube and a grid electrode of a selection tube, and the risk of electric leakage between the grid electrodes of the storage tube and the selection tube is reduced; under the condition that the transverse length of a grid electrode of the storage tube and the thickness of silicon nitride in the ONO layer are not increased, a groove is formed on the surface of the substrate, the ONO layer is deposited, and the length of the ONO layer is increased, so that the device has good charge storage capacity, and the working performance of the device is improved.

Description

1.5T SONOS device and preparation method thereof

Technical Field

The invention relates to an SONOS device and a preparation method thereof, in particular to a 1.5T SONOS device and a preparation method thereof.

Background

Nonvolatile memory, which is an indispensable storage device in computers, plays an important storage function for processed information. Among nonvolatile memories, SONOS memories have characteristics of small cell size, good memory retention, low operating voltage, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) manufacturing processes.

SONOS (flash memory), which has a low operating voltage and better cmos process compatibility, is widely used in various embedded electronic products such as financial IC cards, automotive electronics, and the like. 2T (2-transistor, two transistors storing one bit of data) SONOS is favored for many applications due to its low power consumption. However, the inherent disadvantage of the 2T SONOS structure is its large chip area loss. The 2T SONOS structure comprises a common doped region, a source region and a drain region between two polysilicon gates, so that the polysilicon gates have larger spacing, and therefore, a larger area is occupied. Compared with 2T SONOS, the area of the 1.5T SONOS device is saved.

Chinese patent 201810984599.5 discloses a 1.5T SONOS device, as shown in fig. 1, including a substrate 1, a selection transistor gate oxide layer 2, an ONO layer 3, a selection transistor polysilicon gate 4, a storage transistor polysilicon gate 5, a first sidewall oxide layer 6, a first silicon nitride sidewall 7, a logic region transistor gate oxide layer 8, a second sidewall oxide layer 9, a second silicon nitride sidewall 10, a PN junction 11, a storage transistor drain terminal 12, a low-doped drain region 17 of a selection transistor source terminal, a selection transistor source terminal 18, a third polysilicon layer 19, and an isolation dielectric oxide layer 20. The polysilicon gate 4 of the select transistor and the polysilicon gate 5 of the storage transistor are isolated by a first side wall oxide layer 6. The ONO layer 3 is a silicon oxide-silicon nitride-silicon oxide layer from bottom to top, wherein the silicon nitride layer is a trapping layer, a trap in the trapping layer is used as a position for storing charges, the size of the trap determines the amount of stored charges, the silicon oxide layer at the bottom is a tunneling oxide layer, and the silicon oxide layer at the top is a blocking oxide layer. The device has the following problems:

1. select between tub polycrystalline silicon gate 4 and the storage pipe polycrystalline silicon gate 5 through 6 isolations of first side wall oxide layer, at the device during operation, select tub polycrystalline silicon gate 4 to apply the negative pressure, and storage pipe polycrystalline silicon gate 5 applies the malleation, can form pressure differential between the two, and this kind of pressure differential can reach about 12V, and long-time pressure differential can lead to 6 break-throughs of first side wall oxide layer, has degenerated the device performance, influences the reliability of device.

2. The transverse length of the ONO layer 3 is limited by the transverse length of the storage tube polysilicon gate 5, the device is more advanced, the storage device of an electronic product is expected to have smaller size and higher performance, the transverse length of the storage tube polysilicon gate 5 is continuously reduced, the transverse length of the ONO layer 3 is also continuously reduced, if the silicon nitride storage capacity is required to be continuously maintained, the thickness of the ONO layer is required to be increased, but the device is thin and tall due to the thickness increase, deposition etching and the like in the steps of the process are more difficult, the yield is lower, and the working performance of the device is influenced by the charge storage capacity of the silicon nitride in the ONO layer 3.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the prior art, the 1.5T SONOS device and the preparation method thereof are provided, the possibility of electric leakage between the grid electrode of the storage tube and the grid electrode of the selection tube is reduced, and the transverse length of the ONO layer is effectively increased, so that the device has better charge storage capacity.

The technical scheme is as follows: a preparation method of a 1.5T SONOS device comprises the following steps:

step 1: processing two grooves which are transversely spaced and arranged side by side on the surface of a P-type semiconductor substrate, wherein the two grooves are equal in transverse length and longitudinal depth;

step 2: depositing an ONO layer on the surface of the P-type semiconductor substrate and on the bottom surface and the side surface of the groove;

and step 3: removing the ONO layer in the region except the bottom surface and the side surface of the groove by photoetching by utilizing a graphical mask, and then depositing and etching the exposed surface of the P-type semiconductor substrate to form an oxide layer;

and 4, step 4: depositing and filling polycrystalline silicon on the whole surface of the device, and carrying out ion doping injection on the polycrystalline silicon;

and 5: chemically and mechanically polishing the polysilicon, and grinding the polysilicon into a plane; then, according to a graphical mask, etching the polycrystalline silicon to the surface of the oxidation layer by a downward dry method, forming a first storage tube grid in a region right opposite to the bottom surface of the groove on the left side, forming a second storage tube grid in a region right opposite to the bottom surface of the groove on the right side, forming a selection tube grid between the first storage tube grid and the second storage tube grid, forming a logic tube grid on the right side of the second storage tube grid, wherein the transverse lengths of the first storage tube grid and the second storage tube grid are equal;

step 6: depositing and filling silicon nitride oxide on the surface of the device, and then carrying out chemical mechanical polishing on the surface until the upper surface of the polycrystalline silicon with the structure obtained in the step 5 is reached;

and 7: etching the silicon nitride oxide, forming side walls on the left side edge of the first storage tube grid, the right side edge of the second storage tube grid and the left side edge and the right side edge of the logic tube grid respectively, and etching the silicon nitride oxide among the selection tube grid, the first storage tube grid and the second storage tube grid;

and 8: etching the middle part of the grid electrode of the selection tube by using a graphical mask plate to form a first grid electrode of the selection tube and a second grid electrode of the selection tube, and then respectively forming oxidation side walls on the right side edge of the first grid electrode of the selection tube and the left side edge of the second grid electrode of the selection tube;

and step 9: etching the oxide layer exposed on the surface of the substrate, and then doping a light drain electrode to form a PN junction;

step 10: and carrying out source and drain region ion heavy doping injection in the PN junction region to form a source and drain electrode.

And obtaining the 1.5T SONOS device according to the preparation method of the 1.5T SONOS device.

Has the advantages that: the invention provides a 1.5T SONOS device and a preparation method thereof, wherein an isolation effect is enhanced by depositing and filling silicon oxide nitride between a grid electrode of a storage tube and a grid electrode of a selection tube, and the risk of electric leakage between the grid electrodes of the storage tube and the selection tube is reduced; under the condition that the transverse length of a grid electrode of the storage tube and the thickness of silicon nitride in the ONO layer are not increased, a groove is formed on the surface of the substrate, the ONO layer is deposited, and the length of the ONO layer is increased, so that the device has good charge storage capacity, and the working performance of the device is improved.

Drawings

FIG. 1 is a diagram of a prior art 1.5T SONOS memory structure;

FIG. 2 is a schematic diagram of a 1.5T SONOS memory structure according to the present invention;

FIGS. 3-11 are flow charts of the method for fabricating a 1.5T SONOS memory according to the present invention.

Detailed Description

The invention is further explained below with reference to the drawings.

A preparation method of a 1.5T SONOS device comprises the following steps:

step 1: two grooves are machined on the surface of the P-type semiconductor substrate 201 at a lateral interval side by side, the two grooves have the same lateral length and the same longitudinal depth, as shown in fig. 3.

Step 2: an ONO layer 202 is deposited on the surface of the P-type semiconductor substrate 201 and on the bottom and side surfaces of the recess, as shown in fig. 4. Wherein the ONO layer 202 has a structure of silicon oxide-silicon nitride-silicon oxide from bottom to top.

And step 3: the ONO layer 202 is removed by photolithography in regions other than the bottom and side surfaces of the recess using a patterned mask, and then an oxide layer 203 is deposited and etched on the exposed surface of the P-type semiconductor substrate 201, as shown in fig. 5, in which there are two storage regions, a storage tube 1 and a storage tube 2.

And 4, step 4: depositing and filling polycrystalline silicon 204 on the whole surface of the device, and carrying out ion doping injection on the polycrystalline silicon 204; due to the uniform depth of deposition in the lateral direction, a structure as shown in fig. 6 is obtained. The polysilicon 204 is used for the selection tube gate, the storage tube gate and the logic tube gate which are formed subsequently, and the polysilicon only needs to be deposited once in the process step of the method.

And 5: chemically and mechanically polishing the polysilicon 204, and grinding the polysilicon 204 into a plane; then, according to the patterned mask, the polysilicon 204 is dry etched down to the surface of the oxide layer 203, a first memory gate 204-1-1 is formed in the right area of the bottom surface of the left groove, a second memory gate 204-1-2 is formed in the right area of the bottom surface of the right groove, a select gate 204-2 is formed between the first memory gate 204-1-1 and the second memory gate 204-1-2, and a logic gate 204-3 is formed on the right side of the second memory gate 204-1-2, wherein the first memory gate 204-1-2 and the second memory gate 204-1-2 have the same lateral length, as shown in fig. 7. The select tube gate 204-2 includes a first select tube gate 204-2-1 and a second select tube gate 204-2-2 formed subsequently.

In the step, the grid electrode of the selection tube and the grid electrode of the storage tube are formed by etching the same polycrystalline silicon layer, so that the top height of the polycrystalline silicon is ensured to be consistent, the step of depositing the polycrystalline silicon for the second time is reduced, and meanwhile, the length is increased because the deposited ONO is in the shape of a groove, so that the charge storage capacity is increased, and the working performance of the device is improved.

Step 6: a filling silicon nitride oxide 205-1 is deposited on the surface of the device, and then the surface is chemically and mechanically polished until the upper surface of the polysilicon 204 of the structure obtained in step 5, as shown in fig. 8.

In the step, 205-1 deposited and filled between the grid of the selection tube and the grid of the storage tube has the advantages of silicon oxide and silicon nitride, the isolation performance of the step is better than that of the step of silicon oxide and the step of silicon nitride, and even under the condition of the pressure difference of about 12V, the step of silicon nitride still can play a good role in isolating, so that the possibility of electric leakage between the grid of the selection tube and the grid of the storage tube is reduced.

And 7: etching silicon nitride oxide, forming side walls 205-2 on the left side of the first storage tube gate 204-1-1, the right side of the second storage tube gate 204-1-2, and the left and right sides of the logic tube gate 204-3, respectively, and not etching the silicon nitride oxide 205-1 between the select tube gate 204-2 and the first storage tube gate 204-1-1, and the second storage tube gate 204-1-2, as shown in fig. 9.

And 8: by using a patterned mask, a middle portion of the select-tube gate 204-2 is etched away to form a first select-tube gate 204-2-1 and a second select-tube gate 204-2-2, and then oxide spacers 206 are formed on a right side of the first select-tube gate 204-2-1 and a left side of the second select-tube gate 204-2-2, respectively, as shown in fig. 10.

And step 9: the oxide layer 203 exposed on the surface of the substrate 201 is etched away, and then the PN junction 207 is formed by performing light drain doping, as shown in fig. 11.

Step 10: and performing source and drain region ion heavily doped implantation in the PN junction 207 region to form a source and drain 208, as shown in fig. 2.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A preparation method of a 1.5T SONOS device is characterized by comprising the following steps:

step 1: processing two grooves which are transversely spaced and arranged side by side on the surface of a P-type semiconductor substrate (201), wherein the two grooves are equal in transverse length and longitudinal depth;

step 2: an ONO layer (202) is deposited and formed on the surface of the P-type semiconductor substrate (201) and the bottom surface and the side surface of the groove;

and step 3: removing the ONO layer (202) in the region except the bottom surface and the side surface of the groove by photoetching by using a graphical mask, and then depositing and etching the surface of the exposed P-type semiconductor substrate (201) to form an oxide layer (203);

and 4, step 4: depositing and filling polycrystalline silicon (204) on the whole surface of the device, and carrying out ion doping implantation on the polycrystalline silicon (204);

and 5: chemically mechanically polishing the polysilicon (204) by first grinding the polysilicon (204) to a flat surface; then, according to the patterned mask plate, the polysilicon (204) is etched down to the surface of the oxide layer (203) in a dry etching way, a first storage tube grid (204-1-1) is formed in the right opposite area of the bottom surface of the groove on the left side, a second storage tube grid (204-1-2) is formed in the right opposite area of the bottom surface of the groove on the right side, and a select transistor gate (204-2) is formed between the first memory transistor gate (204-1-1) and the second memory transistor gate (204-1-2), a logic tube grid (204-3) is formed at the right side of the second storage tube grid (204-1-2), the transverse lengths of the first storage tube grid (204-1-1) and the second storage tube grid (204-1-2) are equal;

step 6: depositing and filling silicon nitride oxide (205-1) on the surface of the device, and then carrying out chemical mechanical polishing on the surface until the upper surface of the polysilicon (204) of the structure obtained in the step 5;

and 7: etching the silicon nitride oxide, forming side walls (205-2) on the left side of the first storage tube grid (204-1-1), the right side of the second storage tube grid (204-1-2) and the left side and the right side of the logic tube grid (204-3), respectively, and not etching the silicon nitride oxide (205-1) between the selection tube grid (204-2) and the first storage tube grid (204-1-1) and the second storage tube grid (204-1-2);

and 8: etching the middle part of the selection tube grid (204-2) by using a graphical mask to form a first selection tube grid (204-2-1) and a second selection tube grid (204-2-2), and then respectively forming an oxidation side wall (206) on the right side of the first selection tube grid (204-2-1) and the left side of the second selection tube grid (204-2-2);

and step 9: firstly, etching the oxide layer (203) exposed on the surface of the substrate (201), and then doping a light drain electrode to form a PN junction (207);

step 10: and carrying out source and drain region ion heavily doped injection in the PN junction (207) region to form a source and drain electrode (208).

2. A1.5T SONOS device obtained by the preparation method of claim 1.