KR100622414B1 - Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and ic card - Google Patents

Abstract

10. A semiconductor memory device comprising memory cells, each memory cell comprising: a gate insulator formed on a semiconductor substrate, a gate electrode formed on the gate insulator, a channel forming region located below the gate electrode, and disposed at both sides of the channel forming region And a pair of source / drain regions having a conductivity type opposite to that of the channel forming region, and a charge holding portion made of a material for storing charge, and a charge storing portion from both the gate electrode and the semiconductor substrate. And a dissipation preventing dielectric, each of which has a function of preventing dissipation of stored charges, and a memory functional body located on both sides of the gate electrode, respectively, the distance between the sidewalls of the gate electrodes facing each other and the charge holding portion side. So that T2 is different from the distance T1 between the bottom of the charge holding portion and the substrate surface. It generated a semiconductor memory device.

Description

Semiconductor memory device, semiconductor device and manufacturing method thereof, portable electronic device, and IC card {SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THEM, PORTABLE ELECTRONIC EQUIPMENT, AND IC CARD}

1A to 1C are schematic cross-sectional views showing the structural appearance of a semiconductor memory device according to a first embodiment of the present invention;

2A to 2D are schematic cross-sectional views showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

3A to 3B are schematic cross-sectional views showing the structural appearance of a semiconductor memory device according to a third embodiment of the present invention;

4A to 4D are schematic cross-sectional views showing the structural appearance of a semiconductor memory device according to a fourth embodiment of the present invention;

5 is a schematic cross-sectional view showing the structural appearance of a semiconductor memory device according to the fifth embodiment of the present invention;

6A to 6B are schematic cross-sectional views showing the structural appearance of a semiconductor memory device according to the sixth embodiment of the present invention;

7A to 7D are schematic cross-sectional views showing the structural appearance of a semiconductor memory device according to the seventh embodiment of the present invention;

8A to 8C are schematic cross sectional views showing the manufacturing process of the semiconductor memory device according to the eighth embodiment of the present invention;

9D to 9E are schematic cross sectional views showing a subsequent manufacturing process of a semiconductor memory device according to the eighth embodiment of the present invention;

10A to 10I are schematic cross-sectional views showing the structural appearance of the charge storage region of the semiconductor memory device according to the ninth embodiment of the present invention;

11A to 11D are schematic sectional views showing the structure of a semiconductor memory device according to the tenth embodiment of the present invention;

12A to 12D are schematic sectional views showing the manufacturing process of the semiconductor memory device according to the eleventh embodiment of the present invention;

13 is a schematic sectional view showing a structure of a semiconductor memory device according to the eleventh embodiment of the present invention;

14A to 14C are schematic sectional views showing the manufacturing process of the semiconductor memory device according to the twelfth embodiment of the present invention;

15A to 15C are schematic sectional views showing the manufacturing process of the semiconductor memory device according to the thirteenth embodiment of the present invention;

16A to 16D are schematic sectional views showing the manufacturing process of the semiconductor memory device according to the fourteenth embodiment of the present invention;

17A to 17B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the fifteenth embodiment of the present invention;

18A to 18B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the fifteenth embodiment of the present invention;

19A to 19B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the fifteenth embodiment of the present invention;

20A to 20B are schematic sectional views showing the structural appearance of a semiconductor memory device according to a fifteenth embodiment of the present invention;

21A to 21B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the sixteenth embodiment of the present invention;

22A to 22B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the seventeenth embodiment of the present invention;

23A to 23B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the eighteenth embodiment of the present invention;

24A to 24B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the nineteenth embodiment of the present invention;

25A to 25B are schematic sectional views showing the structural appearance of a semiconductor memory device according to a twentieth embodiment of the present invention;

26A to 26B are schematic sectional views showing the structural appearance of a semiconductor memory device according to the twenty-first embodiment of the present invention;

27A to 27B are schematic sectional views showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention;

28A to 28B are horizontal sectional views showing separate charge accumulation regions according to the second embodiment of the present invention;

29A to 29B show a structure of a semiconductor memory device including a memory device of the present invention and peripheral circuits such as an MPU and a cache SRAM;

30A to 30B are schematic block diagrams showing an IC card of a twenty-second embodiment of the present invention;

31 is a schematic block diagram showing a portable electronic device according to a twenty-third embodiment of the present invention; And

32 is a schematic cross-sectional view showing the structural appearance of a conventional semiconductor memory device.

This application claims the priority of Japanese Patent Application No. 2003-142120 filed May 20, 2003 and Japanese Patent Application No. 2003-141031 filed May 19, 2003, the entire disclosure of which is incorporated by reference. .

The present invention relates to a semiconductor memory device, a semiconductor device and a method of manufacturing the same, a portable electronic device, and an IC card. More specifically, the semiconductor memory device can be suitably used for an electrically erasable and programmable semiconductor memory device and a method of manufacturing the same.

An example of an electrically erasable and programmable memory device is a flash memory. A structural cross-sectional view of a device of a general flash memory is shown in FIG. In the device, a floating gate 906 made of polysilicon is disposed on the semiconductor substrate 901 through the first oxide film 904, and a control gate 907 made of polysilicon is semiconductor through the second oxide film 905. It is disposed on the substrate 901 and has a structure in which a pair of source / drain diffusion regions 902 and 903 are disposed on the surface of the semiconductor substrate 901. The control gate 907 functions as a gate electrode of the field effect transistor (FET) in the flash memory. A first oxide film 904, a floating gate 906, and a second oxide film 905 are interposed between the control gate 907 and the semiconductor substrate 901. That is, a flash memory is a memory that performs a function of changing a threshold voltage of a FET in accordance with the amount of charge stored in the memory film by disposing a memory film (floating gate) in the gate oxide film portion of the FET (for example, See p55-58 of "Handbook of Flash Memory Technology" published August 15, 1993 by the Kabushiki kaisha Science Forum and edited by Fujio Masuoka.

The flash memory of the above structure has a problem of so-called "overerase". More specifically, the erase operation of the flash memory lowers the threshold voltage of the FET in the flash memory by extracting electrons stored in the floating gate or injecting holes into the floating gate. However, since the erase operation is excessively performed, no voltage is applied to the gate electrode of the FET, and the FET is turned ON under the influence of the charge stored in the floating gate located under the gate electrode (i.e., the control gate). Current flows through the / drain region. This phenomenon is due to the structural characteristics of the flash memory that the control gate, which is a gate electrode as a FET, and the floating gate, which is a memory film as a memory, are stacked vertically, so that the charge stored in the floating gate without applying any voltage to the control gate. Only by turning on the FET. This is due to leakage current from unselected memory cells. Thus, a poor readout occurs in which the current read from the selected memory cell is incorrectly read due to the leakage current.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device, a semiconductor device and a method of manufacturing the same, a portable electronic device, and an IC card, which have been over-erased and their read defects improved.

An embodiment of the present invention is a semiconductor memory device including memory cells, each memory cell,

A gate insulator formed on the semiconductor substrate;

A gate electrode formed on the gate insulator; A channel formation region under the gate electrode; A pair of source / drain regions disposed on both sides of the channel forming region and having a conductivity type opposite to that of the channel forming region; And

A charge holding part made of a material which functions to store electric charges, and a dissipation preventing dielectric which functions to prevent dissipation of stored charges by isolating charge storage parts from both the gate electrode and the semiconductor substrate, and Memory functions located on both sides of the gate electrode, and configured such that the distance T2 between the sidewalls of the gate electrodes facing each other and the charge holding portion side is different from the distance T1 between the bottom of the charge holding portion and the substrate surface; Provided is a semiconductor memory device.                         

According to the semiconductor memory device of the embodiment of the present invention, since the charge holding portions are respectively located on both sides of the gate electrode rather than on the gate insulator of the field effect transistor, the problem of over-erasing and reading failure thereof is eliminated.

In addition, since a dissipation preventing insulating film capable of suppressing dissipation of charge from the charge holding portion of the memory functional body exists, the charge holding time is improved.

The distance T2 is made different from the distance T1, for example, if the distance T1 is made shorter than the distance T2, the charge injected from the semiconductor substrate passes through the memory functional body to the gate electrode. On the contrary, if the distance T1 is made longer than the distance T2, the charge injected from the gate electrode passing through the memory functional body to the semiconductor substrate can be suppressed. Therefore, a semiconductor memory device having a high charge injection efficiency and a high write / erase speed can be obtained.

A semiconductor memory device according to an embodiment of the present invention includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a gate electrode formed on the gate insulator, a channel forming region disposed below the gate electrode, and a channel forming region. A pair of source / drain diffusion regions disposed on both sides and having a conductivity type opposite to that of the channel forming region, and a charge holding portion made of a material disposed on both sides of the gate electrode and having a function of storing charge; Mainly comprising memory functional bodies each including a dissipation preventing dielectric having a function of preventing dissipation of stored charges, wherein a distance T2 between the sidewall of the gate electrode and the charge holding portion opposite the sidewall is located on the semiconductor substrate side A semiconductor memory device having a different distance T1 between the bottom of the charge holding portion and the front surface of the semiconductor substrate. The.

As used herein, the "source / drain region" refers to a diffusion region that may function as either a source region or a drain region. These source / drain regions may sometimes be referred to individually as either "source regions" or "drain regions", but it should be understood that either region may be a source or a drain, depending on the configuration of the circuit.

The semiconductor memory device of one embodiment of the present invention basically uses a MOS circuit, and all circuits including the MOS circuit are preferably mounted on a single semiconductor substrate.

In the semiconductor memory device according to the semiconductor memory device of one embodiment of the present invention, the distance T2 may increase as it is measured further from the substrate.

In the above aspect, the charge holding portion is formed so that its upper portion is farther from the gate electrode than the lower portion thereof, so that unnecessary charges are injected into the upper portion of the charge holding portion, and dissipation of unnecessary charges is also suppressed. For example, electron injection from the gate electrode as occurring in the erase mode can be strongly suppressed. In addition, since the lower portion does not go as far as the upper portion, the charge to be retained is formed without unnecessary space from the channel forming region. Due to the above, it is possible to suppress the injection and dissipation of unnecessary charges without reducing the difference between the currents read in the write / erase mode.

In the semiconductor memory device, the distance T2 may be longer than the distance T1.

In this aspect, since the distance T1 is made shorter with respect to the distance T2, the electron injection from the gate electrode in the erase mode can be suppressed, and the semiconductor memory device in which the erase failure is suppressed can be provided. .

Further, in an embodiment of the semiconductor memory device, an oxynitride film may be formed between the charge holding unit and the gate electrode.

In the above aspect, since the electron injection from the gate electrode in the erase mode can be suppressed more remarkably, a semiconductor memory device in which erase failure is suppressed can be provided.

Alternatively, in one embodiment of the semiconductor memory device, a deposited insulating film may be formed between the charge holding unit and the gate electrode.

In the above aspect, a deposition insulator having good uniformity can be formed between the charge holding portion and the gate electrode in a thick film, and deterioration due to aperity, i.e., ruggedness appearing on the gate electrode, is obtained. The problem is also suppressed, and the electron injection from the gate electrode in the erase mode can be suppressed more remarkably, and a semiconductor memory device in which the erase failure is suppressed can be provided.

In an embodiment of the semiconductor memory device, a thermal insulator having a thickness of 1 nm to 10 nm may be disposed between the deposition insulator and the semiconductor substrate.

In the above aspect, a thermal insulator formed by substantially uniform heat treatment and having a thickness of 1 nm to 10 nm is disposed between the stacked insulator and the semiconductor substrate. Therefore, the shape of the interface between the thermal insulator and the semiconductor substrate is good, the decrease in mobility of the current flowing through the interface can be suppressed, a large driving current is obtained, and the read speed is further improved. May be provided. In addition, since the film thickness of the thermal insulator is 1 nm or more, the interface characteristics can be satisfactorily improved, and since the film thickness is 10 nm or less, the occurrence of deterioration due to the earthiness can be suppressed.

In an embodiment of the semiconductor memory device, the gate electrode may be made of a material having a composition different from that of the substrate, and the distance T2 may be different from the distance T1.

When the gate electrode is formed of a material having a composition different from that of the substrate, the distance T2 can be made such that the distance T1, that is, the gate electrode sidewall is significantly different from the thickness of the anti-dissipation insulating film formed on the semiconductor substrate, A semiconductor memory device having higher efficiency and a faster write / erase speed can be provided.

In one embodiment of the semiconductor memory device, the charge holding portion of the memory functional body is isolated from both the gate electrode made of silicon and the substrate by a dissipation preventing dielectric, and the impurity concentration of the region of the substrate facing the memory functional body is controlled by the memory function. It is different from the impurity concentration in the region of the gate electrode facing the sieve, and the distance T2 may be different from the distance T1.

Here, the expression "made of silicon" means more specifically "the main raw material is made of a material of silicon". Specifically, the main material is monocrystalline silicon, polysilicon or amorphous silicon, and may contain impurities.

In the above aspect, since the semiconductor substrate and the gate electrode can be formed of silicon which is commonly used as a material of the current semiconductor device, a semiconductor process having high affinity with a general semiconductor manufacturing process can be constructed, and a semiconductor having low manufacturing cost A memory device may be provided.

In addition, in an embodiment of the semiconductor memory device, the gate electrode may have an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more, and the substrate may have a lighter impurity concentration than the gate electrode. In the above aspect, the impurity concentration of the other is lighter and the film of the anti-dissipating dielectric becomes thinner for either the gate electrode made of silicon or the semiconductor substrate. In addition, since the higher impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more, the effect of impurity-enhanced oxidation is remarkable, whereby the difference in the film thickness on the corresponding region becomes remarkable. Thus, a semiconductor memory device with remarkably good charge injection efficiency and remarkably fast write / erase speed can be provided.

However, since the concentration of impurities that can be contained in silicon is limited, the maximum number of digits is 10 ²¹ cm ^-3 . In addition, since the impurity concentration of a general semiconductor substrate is 10 ¹⁵ cm ^-3 digits, it is preferable that it is at least 10 ¹⁵ cm ^-3 digits.

Alternatively, in an embodiment of the semiconductor memory device, the impurity concentration of the gate electrode of the semiconductor memory device may be 1 × 10 ²⁰ cm ⁻³ or more and the impurity concentration of the semiconductor substrate may be lighter than the impurity concentration of the gate electrode.

In this aspect, the impurity concentration of the gate electrode made of silicon is higher than the impurity concentration of the semiconductor substrate, and the insulating film is thickened on the sidewall of the gate electrode.

In addition, since the impurity concentration of the gate electrode is 1 × 10 ²⁰ cm ⁻³ or more, the effect of impurity strengthening oxidation is remarkable, and the film on the gate electrode becomes thick, and the difference in film thickness becomes apparent. Therefore, it is possible to provide a semiconductor memory device with a remarkably good charge injection efficiency and a remarkably fast write / erase speed.

However, since the impurity concentration that can be contained in silicon is limited, it is at most 10 ²¹ cm ^-3 digits. In addition, since the impurity concentration of a general semiconductor substrate is 10 ¹⁵ cm <^-3> , it is preferable that it is at least 10 ¹⁵ cm <^-3> digits.

Alternatively, in one embodiment of the semiconductor memory device, at least a portion of the gate insulator and at least a portion of the memory functional body may each be made of an oxide film, and the gate insulator may function from the sidewall of the gate electrode opposite the memory functional body. It may have an equivalent oxide thickness that is thinner than the equivalent oxide thickness of the path extending through the sieve to the surface of the substrate located below the memory functional body. Here, the "equivalent oxide film thickness" is obtained by multiplying the thickness of the insulating film by the ratio of the dielectric constant of the oxide film to the dielectric constant of the insulating film. If the insulating film is composed of several dielectric layers and one of the layers is not an oxide film, for example, a nitride film, the equivalent thickness of the nitride film is calculated to determine the oxide film equivalent thickness.

The structure is such that, when a voltage is applied between the gate electrode and the substrate under the gate electrode, the strength of the electric field in the path extending from the gate electrode to the substrate through the gate insulator is such that the memory from the sidewall of the gate electrode opposite the memory function It means less than the strength of the electric field of the path extending through the functional body to the surface of the substrate located below the memory functional body.

In the above aspect, since the equivalent oxide film thickness of the gate insulator is thinner than the equivalent oxide film thickness of the path extending from the sidewall of the gate electrode opposite the memory functional body to the semiconductor substrate through the memory functional material, for example, The threshold voltage when used as a gate insulator can be set low, and low voltage driving with a low read voltage can be realized. Accordingly, a semiconductor memory device having low power consumption can be provided.

In addition, in one embodiment of the semiconductor memory device, the charge holding portions respectively located on both sides of the gate electrode may be adopted to store the charge independently.

In the above aspect, the charges can be held independently of each other in the two charge holding sections, whereby tetravalent information can be stored per memory cell, and a large capacity semiconductor memory device can be provided.

In one embodiment of a semiconductor memory device, at least a portion of the gate insulator and at least a portion of the memory functional body may each be made of an oxide film, the gate insulator being memory through the memory functional body from the sidewall of the gate electrode opposite the memory functional body. It may have an equivalent oxide film thickness that is thicker than the equivalent oxide film thickness of the path extending to the surface of the substrate located below the functional body.

In this aspect, information can be recorded, for example, by applying potentials of 10 volts and 0 volts on the gate electrode and the source / drain diffusion regions, respectively, and -10 on the gate electrode and the source / drain diffusion regions, respectively. Information can be erased by applying a potential of volts and zero volts, and since the potentials of one source / drain diffusion region and the other source / drain diffusion region are the same, no drain current flows. In addition, the gate insulator is thick and the leakage current passing through the gate insulator is suppressed. Therefore, a semiconductor memory device having low power consumption is provided. In addition, since no hot carrier is generated and no charge is injected into the gate insulator, fluctuation in threshold voltage due to injection of charge into the gate insulator is suppressed, thereby providing a highly reliable semiconductor memory device. Can be.

In the semiconductor memory device, at least a portion of the source / drain region may be disposed under the gate electrode.

In one embodiment of the above aspect, since at least a portion of the source / drain regions may be disposed under the gate electrode, the semiconductor memory device has the same structure as a general field effect transistor, so that the manufacturing process of the It is possible to provide a semiconductor memory device with low manufacturing costs, which can be achieved by a general field effect transistor process having a track record.

In one embodiment of the semiconductor memory device, the top position of the charge holding portion may be lower than the top position of the gate electrode.

In this aspect, the charge holding portion may be disposed only near the channel. Thus, the electrons injected by the recording are confined in the vicinity of the channel, and are easily removed by erasing. Therefore, erasure is prevented. In addition, assuming that the number of injection electrons does not change by defining the charge holding unit, the density of electrons becomes high, electrons can be efficiently written / deleted, and a semiconductor memory device having a high write / erase speed can be formed.

In one embodiment of the semiconductor memory device, the uppermost position of the charge holding portion may be lower than the uppermost position of the first insulating film.

In this aspect, since the top position of the charge holding portion is lower than the top position of the first insulating film, the shortest distance between the gate electrode and the charge holding portion becomes long. Therefore, in the siliciding or wiring step, since a short circuit between the gate electrode and a region made of a material having a function of storing charge can be suppressed, a semiconductor memory device having a high yield percentage can be formed. Can be.

In one embodiment of the semiconductor memory device, the charge holding unit may be formed of a plurality of fine particles having a function of storing charge.

In this aspect, since the charge holding part can be limited to a finer area, the erasure can be prevented more effectively. In addition, since the charge holding portion is divided into fine particles, even when leakage occurs, the leakage area is composed of only the adjacent fine particles, and the retention characteristics are improved. In addition, for example, a region made of a material having a function of storing charge can be formed in a dot shape on the order of nanometers, so that the memory effect is remarkably improved due to the coulomb blockade effect. And a semiconductor memory device having high long-term reliability can be formed.

In one embodiment of the semiconductor memory device, the anti-dissipating dielectric is formed in the first insulating film that isolates the charge holding portion from the gate electrode and the charge holding portion from the semiconductor substrate, and the sidewall portions of the charge holding portion on the opposite side of the first insulating film. The sidewall insulator may be formed, and the charge holding unit may be interposed between the first insulating film and the sidewall insulator.

In this aspect, the electrons injected by recording are confined in the charge holding portion so that they can be easily removed by erasing, and the erasure can be prevented. In addition, the volume of the charge holding portion decreases without changing the injected electron amount, so that the amount of charge per unit volume can be increased, electrons can be efficiently written / erased, and a semiconductor memory device having a high write / erase speed can be provided. Can be.

Further, in one embodiment of the semiconductor memory device, the charge holding portion may be covered with the first insulating film and the second side wall insulator.

In the above aspect, since the charge holding part is covered with the second side wall insulator, the charge holding part and the contact can be prevented from being shorted in the contact forming step for the gate electrode. Therefore, since the design margin of the size of the contact portion can be further reduced, the semiconductor device can be further miniaturized. Therefore, a semiconductor memory device with reduced cost can be provided.

Alternatively, in one embodiment of the semiconductor memory device, the anti-dissipating dielectric of the memory function may be made of a silicon oxide film or a silicon oxynitride film, and the charge holding portion of the memory function may be made of a silicon nitride film.

On the other hand, since the silicon nitride film includes many levels of trapping charges, large hysteresis characteristics can be obtained. In addition, since the silicon nitride film has a long charge holding time and almost no problem of charge leakage due to the occurrence of leakage paths, desirable retention characteristics are obtained. In addition, since the material is a very commonly used material in the LSI process, the manufacturing cost can be kept low.

In one embodiment of the semiconductor memory device, the charge holding portion may be composed of a plurality of particles having a function of storing charge, a plurality of particles and a gate electrode, and a film of a semiconductor or a conductor positioned between the plurality of particles and the semiconductor substrate. have.

In the above aspect, since the influence of variation in the position and size of the fine particles on the threshold voltage of the field effect transistor can be suppressed by the intervening semiconductor or conductor, a semiconductor memory device with little misread can be provided.

Alternatively, in one embodiment of the semiconductor memory device, at least a portion of the charge holding portion of the memory functional body may be disposed over the source region or the drain region.

In the above aspect, the current value in the read operation of the semiconductor memory device may be remarkably high, and since the read speed of the device is remarkably fast, a semiconductor memory device having a high read speed can be provided.

Further, in one embodiment of the semiconductor memory device, the charge holding portion of the memory functional body may have a surface substantially parallel to the surface of the gate insulator.

In this aspect, the ease of formation of the inversion layer in the offset region can be efficiently controlled in accordance with the amount of charge held in the charge holding portion, and the memory effect can be enhanced. In addition, even when there is a deviation in the offset size, the variation in the memory effect can be kept relatively small, and the variation in the memory effect can be suppressed.

Further, in one embodiment of the semiconductor memory device, the charge holding portion of the memory functional body may include a portion extending substantially parallel to the side surface of the gate electrode.

In this aspect, since the charge injected into the charge holding portion in the rewriting operation increases, the rewriting speed is increased.

In addition, in an embodiment of the semiconductor memory device, the semiconductor memory device may include an insulating film that isolates the charge holding portion of the memory functional body from the substrate, and the leading edge film may be thinner than the gate insulator and may have a thickness of 0.8 nm or more.

In this aspect, the injection of charge into the charge holding portion may be facilitated, and the voltage of the write and erase operations may be lowered or the speed thereof may be increased. In addition, since the amount of charge induced in the channel forming region or the well region increases when charge is stored in the charge holding portion, the memory effect can be enhanced.

Moreover, since the thickness of the insulating film which isolate | separates a charge holding part and a semiconductor substrate is 0.8 nm or more, the fall of the retention characteristic is suppressed extremely.

Alternatively, the semiconductor memory device according to the aspect of the present invention includes an insulating film that isolates the charge holding portion of the memory functional body from the substrate, and the insulating film may be thicker than the gate insulator and may be 20 nm or less in thickness.

In the above aspect, since the thickness of the insulating film separating the charge holding portion and the semiconductor substrate is 20 nm or less than that of the gate insulator, the memory retention characteristics can be improved without deteriorating the short channel effect of the memory. .

In addition, since the thickness of the insulating film separating the charge holding portion and the semiconductor substrate is 20 nm or less, a decrease in the rewriting speed can be suppressed.

Embodiments of the present invention further comprise a semiconductor device of the present invention comprising a semiconductor memory cell and a semiconductor element, each semiconductor memory cell and semiconductor element comprising: a gate insulator formed on a semiconductor substrate; A gate electrode formed on the gate insulator; A channel formation region under the gate electrode; A pair of source / drain regions disposed on both sides of the channel forming region and having a conductivity type opposite to that of the channel forming region; And a memory functional member each located on both sides of the gate electrode and including a charge holding portion made of a material which stores charges, and a dissipation preventing dielectric which prevents the stored charges from dissipating. And a distance between the sidewalls of the gate electrodes facing each other and the side of the charge holding portion is different from a distance between the bottom of the first charge holding portion and the surface of the substrate, wherein the source / drain region of the memory cell is the gate of the memory cell. A portion of the source / drain region of the semiconductor element is disposed outside the region under the electrode, and is disposed below the gate electrode of the semiconductor element.

Therefore, a semiconductor device in which the source / drain diffusion region is not offset with respect to the end part of the gate electrode and a semiconductor memory element in which the source / drain diffusion region is offset with respect to the end portion of the gate electrode coexist on the same substrate, A memory functional body having a function of storing electric charges is disposed on sidewalls of the gate electrode of each of the semiconductor element and the semiconductor memory element. However, since the manufacturing process of both elements does not have a big difference, coexistence of the nonvolatile memory formed with the semiconductor memory element and the logic circuit formed with the semiconductor element can be realized very easily. In addition, since the thickness of the gate insulator is not limited, a semiconductor device capable of easily applying a state-of-the-art MOSFET manufacturing process can be provided.

In addition, in an embodiment of the semiconductor device of the present invention, the nonvolatile memory unit may include the semiconductor memory device.

In the above aspect, the nonvolatile memory portion is composed of a plurality of the semiconductor memory elements, and the logic element is composed of the semiconductor elements. Therefore, it is possible to realize a semiconductor device including a nonvolatile memory portion and a logic circuit portion which are easily mounted on the same substrate and coexist.

Further, the semiconductor device of one embodiment of the present invention may include a logic circuit portion driven by a supply voltage lower than the supply voltage supplied to the nonvolatile memory portion.

In this aspect, for example, since a high supply voltage can be supplied to the nonvolatile memory portion, the write / erase speed can be significantly increased. In addition, since the logic circuit portion can be supplied with a low supply voltage, a decrease in transistor characteristics due to breakage of the gate insulator or the like can be suppressed, and power consumption can be reduced. Therefore, it is possible to realize a semiconductor device including a highly reliable logic circuit portion easily mounted on the same substrate and a nonvolatile memory portion having a very high write / erase speed.

In addition, the semiconductor device of one embodiment of the present invention may further include a static random access memory (SRAM) in which a circuit is formed of the semiconductor device.

In this aspect, the logic circuit portion and the SRAM are composed of semiconductor elements, and the nonvolatile memory portion is composed of semiconductor memory elements. Therefore, a semiconductor device including a logic circuit portion, an SRAM, and a nonvolatile memory portion, which are easily mounted on the same substrate and coexist, can be realized. In addition, the SRAM may be mounted and coexist as a high speed operating memory or temporary storage memory, whereby performance may be further improved.

According to the present invention, the IC card of the present invention includes a semiconductor memory device or the semiconductor device.

Therefore, since the IC card can include a semiconductor device in which a nonvolatile memory, its peripheral circuit portion, a logic circuit portion, an SRAM portion, and the like are easily installed and coexist, and can be reduced in cost, an IC card with low cost can be provided. have.

In addition, the portable electronic device according to the embodiment of the present invention includes a semiconductor memory device or the semiconductor device.

Thus, for example, the cellular phone can include a semiconductor device which is easily equipped with a nonvolatile memory, its peripheral circuit portion, a logic circuit portion, an SRAM portion, etc., can coexist and can be reduced in cost, thereby providing a low-cost cellular phone. Can be.

In another aspect, the present invention includes forming a gate insulator on a semiconductor substrate, and forming a gate electrode on the gate insulator; Forming a first insulating film on the gate electrode and the semiconductor substrate; Partially removing the first insulating film so that the first insulating film remains on at least a sidewall of the gate electrode; Forming a second insulating film on the sidewalls of the substrate and the gate electrode such that the portion covering the sidewall of the gate electrode is thicker than the portion covering the sidewall of the substrate by any one of oxidation and oxynitride treatment; Forming a charge storage region on a sidewall of the gate electrode through the second insulating layer; And forming a source / drain region by implanting impurities into the substrate using the gate electrode, the first and second insulating layers on the sidewalls of the gate electrode, and the charge storage region as an implantation mask. It provides a method of manufacturing a semiconductor memory device comprising the step of.

Therefore, since the thickness of the insulating film portion of the semiconductor memory element in contact with the gate electrode can be made significantly different from the thickness of the portion in contact with the semiconductor substrate, the erase failure in the erase mode can be suppressed or the write / erase speed can be increased. More specifically, when the insulating film in the portion in contact with the semiconductor substrate is formed thinner than the insulating film in the portion in contact with the gate electrode, suppression of erase failure in the erase mode or charge injected from the semiconductor substrate passes through the insulating film. Since the exit to the gate electrode can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high writing / erasing speed can be provided. On the contrary, when the first insulating film in a portion in contact with the semiconductor substrate is thicker than the first insulating film in a portion in contact with the gate electrode, it is possible to suppress the charge injected from the gate electrode from passing through the first insulating film into the semiconductor substrate. Therefore, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided.

In addition, since the source / drain diffusion region of the semiconductor memory device may be formed to be offset to the gate electrode, and may be formed to overlap by the charge storage region, the memory effect is good, and the source / drain diffusion region may be charged. The current value in the read operation of the semiconductor memory device is significantly improved than in the case where it is not overlapped by the storage area. Therefore, since the read speed is remarkably improved, a semiconductor memory device having a high read speed is provided.

In another aspect, the present invention provides a method of forming a gate insulator comprising: forming a gate insulator on a semiconductor substrate and forming a gate electrode on the gate insulator made of a material of a different composition than the substrate; Forming an insulating film on the sidewall of the gate electrode and the substrate using heat treatment such that the thickness of the insulating film portion covering the substrate is different from the thickness of the insulating film portion covering the gate electrode sidewall; Forming a charge storage region on a sidewall of the gate electrode through the insulating layer; And forming a source / drain region by implanting impurities into the substrate using the gate electrode, the insulating film on the sidewall of the gate electrode, and the charge storage region as an injection mask. Provide more ways.

Therefore, since the semiconductor substrate and the gate electrode of the semiconductor memory element are formed using materials having different compositions, the thickness of the insulating film portion in contact with the gate electrode may be made different from the thickness of the insulating film portion in contact with the semiconductor substrate. Erase defects in the erase mode can be suppressed, or the recording / erase speed can be increased.

In addition, since the step of forming the insulating film of the first semiconductor memory element so that the film thickness of the portion in contact with the gate electrode and the portion in contact with the semiconductor substrate is different, it can be performed only by the usual insulating film forming step without using an etching step, A semiconductor memory device can be provided that does not require any complicated steps and is low in manufacturing cost.

In addition, since the source / drain diffusion region of the semiconductor memory device may be formed to be offset to the gate electrode and overlapped by the charge storage region, the memory effect is good, and the source / drain diffusion region is the charge storage region. The current value in the read operation of the semiconductor memory device can be improved more remarkably than in the case of not overlapping with each other. Therefore, since the read speed can be remarkably improved, a semiconductor memory device having a high read speed is provided.

In another aspect, the invention provides a method for forming a semiconductor insulator comprising: forming a gate insulator on a semiconductor substrate made of silicon; Forming a gate electrode made of silicon having an impurity concentration greater than that of a region located near the surface of the semiconductor substrate and having an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or more; Forming an insulating film on the sidewalls of the substrate and the gate electrode using heat treatment such that the thickness of the insulating film portion covering the substrate is different from the thickness of the portion covering the gate electrode sidewalls; Forming a charge storage region on a sidewall of the gate electrode through the insulating layer; And forming a source / drain region by implanting impurities into the substrate using the gate electrode, the insulating film on the sidewall of the gate electrode, and the charge storage region as an injection mask. To provide more.

Therefore, since the impurity concentration of the gate electrode of the semiconductor memory element is 5 × 10 ¹⁹ cm ^-3 or more, the effect of impurity strengthening oxidation is remarkable. In addition, since a region having an impurity concentration lighter than that of the gate electrode is formed in the semiconductor substrate, and an insulating film is formed on the semiconductor substrate and the gate electrode by heat treatment, the thickness of the portion of the first insulating layer in contact with the gate electrode is in contact with the semiconductor substrate. Since the thickness of the insulating film portion can be made largely different, a semiconductor memory device having low manufacturing cost can be provided without requiring any complicated steps such as etching.

In addition, when the first insulating film in the portion in contact with the semiconductor substrate of the semiconductor memory element is formed thinner than the first insulating film in the portion in contact with the gate electrode, the charge injected from the semiconductor substrate passes through the first insulating film and exits to the gate electrode. Since it can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided.

In another aspect, the present invention provides a method of forming a semiconductor insulator comprising: forming a gate insulator on a semiconductor substrate made of silicon and having an impurity region in the vicinity of a surface having an impurity concentration of at least 5 x 10 ¹⁹ cm ^-3 ; Forming a gate electrode made of silicon, the impurity concentration being lighter than the impurity region near the surface of the substrate, and having a impurity concentration of 1 × 10 ²⁰ cm ^-3 or less; Forming an insulating film on the sidewalls of the substrate and the gate electrode using heat treatment such that the thickness of the insulating film portion covering the substrate is different from the thickness of the portion covering the gate electrode sidewalls; Forming a charge storage region on the sidewall of the gate electrode through the insulating layer; And forming a source / drain region by implanting impurities into the substrate using the gate electrode, the insulating film on the sidewall of the gate electrode, and the charge storage region as an injection mask. To provide more.

Therefore, since the impurity concentration of the gate electrode of the semiconductor memory element is 1 × 10 ²⁰ cm ^-3 or less and lower than that of the semiconductor substrate, a condition in which the effect of impurity strengthening oxidation is not exhibited can be set for the gate electrode, and the impurity of the semiconductor substrate When the concentration is higher than the impurity concentration of the gate electrode and is 5 × 10 ¹⁹ cm ⁻³ or more, the effect of impurity strengthening oxidation starts to appear clearly on the semiconductor substrate. Therefore, when the insulating film is formed on the semiconductor substrate and the gate electrode by heat treatment, the thickness of the first insulating film portion in contact with the gate electrode can be made significantly different from the thickness of the non-insulating film portion in contact with the semiconductor substrate. It is possible to provide a semiconductor memory device which requires no manufacturing cost and which is better in manufacturing cost. Further, since the thickness of the first insulating film portion in contact with the gate electrode is significantly different from the thickness of the first insulating film portion in contact with the semiconductor substrate, a semiconductor memory device having a remarkably fast write / erase speed can be provided.

In addition, since the first insulating film of the semiconductor memory element is thicker in the contact with the semiconductor substrate than in the contact with the gate electrode, the charge injected from the gate electrode is prevented from passing through the first insulating film and exiting the semiconductor substrate. In addition, a semiconductor memory device having good charge injection efficiency and a high writing / erasing speed can be provided.

Further, when the thickness of the first insulating film in the portion in contact with the semiconductor substrate of the semiconductor memory element is made thinner than the thickness of the first insulating film in the portion in contact with the gate electrode of the semiconductor memory element, the charge injected from the semiconductor substrate is reduced. Since it can be suppressed to pass through the single insulating film to the gate electrode, a semiconductor memory device having good charge injection efficiency and high writing / erasing speed can be provided.

A semiconductor memory device of a first embodiment of the present invention, comprising: a semiconductor substrate; A pair of source / drain regions formed on said substrate and isolated by channel forming regions; A gate insulator formed on the channel formation region; A gate electrode formed on the gate insulator; And a memory functional body located at both sides of the gate electrode and including a charge holding portion and a dissipation preventing dielectric, wherein the charge holding portion is separated from the substrate by a first distance T1 and is not equal to the first distance T1. A semiconductor memory device including memory cells spaced apart from the gate electrode by a second distance T2 is provided.

In the semiconductor memory device, the second distance T2 may increase as the distance from the substrate is measured.

In addition, the second distance T2 may be much longer than the first distance T1.

In the first embodiment, the semiconductor memory device and the gate electrode may be formed of a material having a different composition from that of the substrate.

Further, the impurity concentration of the gate electrode is 1 × 10 ²⁰ cm ⁻³ or more, and the impurity concentration of the substrate is lighter than that of the gate electrode.

In the semiconductor memory device, the anti-dissipation dielectric may include a silicon oxide film or a silicon oxynitride film, and the charge holding part includes a silicon nitride film.

In another aspect of the present invention, a gate electrode formed on a semiconductor substrate through a gate insulator and a pair of source / drain diffusion regions formed on a surface of a semiconductor substrate in a range corresponding to both sides of the gate electrode, Concave portions are formed between both sides of the gate electrode and the surface of the semiconductor substrate so as to gradually widen laterally, and the dissipation prevention function having a function of preventing dissipation of stored charges and a charge holding portion made of a material having a function of storing charges There is provided a semiconductor memory device including field effect transistors each having a memory functional body made of a dielectric formed on both sides of a gate electrode such that the recess is buried.

In the semiconductor memory device, the surface of the semiconductor substrate is a flat portion facing the bottom surface of the gate electrode through a gate insulator, an inclined portion adjacent to both sides of the flat portion relative to the gate longitudinal direction to form part of the concave portion, and the It may have a bottom face part adjacent to the outer side of an inclination part, respectively.

Further, in an embodiment of the semiconductor memory device, a space may be provided between the bottom surface of the gate electrode and the source / drain diffusion region in the gate longitudinal direction.

In the semiconductor memory device, the side of the gate electrode may have a flat portion that is generally perpendicular to the surface of the gate insulator, and an inclined portion adjacent to the lower portion of the flat portion to form a portion of the concave portion. A first dielectric covering the bottom surface and the inclined portion of the surface of the semiconductor substrate as well as the inclined portion and the flat portion of the side of the gate electrode with a substantially uniform film thickness so that the charge holding portion and the semiconductor substrate as well as the gate electrode are respectively isolated from each other. do.

Further, in the semiconductor memory device, at least part of the charge holding part may overlap part of the source / drain diffusion region.

In addition, the charge holding portion may have a portion generally parallel to the gate insulator.

In the semiconductor memory device, the side of the gate electrode may have a flat portion that is generally perpendicular to the surface of the gate insulator and a slanted portion adjacent to the lower side of the flat portion to form a portion of the concave portion, and the charge holding portion is formed on the side of the gate electrode. A portion extending generally parallel to the flat portion.

In addition, the thickness of the anti-dissipating dielectric portion separating the charge holding portion and the semiconductor substrate from each other may be thinner than the film thickness of the gate insulator and may be 0.8 nm or more.

In addition, the thickness of the anti-dissipating dielectric portion that isolates the charge holding portion and the semiconductor substrate from each other may be thicker than 20 nm or less than the thickness of the gate insulator.

In one embodiment of the semiconductor memory device, at least a portion of the source / drain diffusion region may be disposed on the inclined portion of the surface of the semiconductor substrate.

Also, inside the source / drain diffusion region, a counter region that can be doped more heavily than the channel formation region located directly below the bottom surface of the gate electrode is a source / drain diffusion region. It is formed of the opposite conductivity type

Further, the source / drain diffusion region may each have an extension portion on one side where the channel formation region exists, and the junction depth of the enlarged portion may be shallower than the junction depth of portions other than the extension portion.

In an embodiment of the semiconductor memory device, the impurity concentration of the extension may be lighter than that of the source / drain diffusion region other than the extension.

In the semiconductor memory device, the charge holding portion of the memory functional body may be accommodated in the recess.

In another embodiment of the present invention, there is provided a memory region having a semiconductor memory element and a logic circuit region having a semiconductor switching element, wherein both the memory region and the logic circuit region are provided on a semiconductor substrate, The semiconductor switching element is operated by a field effect transistor having a pair of source / drain diffusion regions and gate electrodes respectively formed on portions of the surface of the semiconductor substrate corresponding to both sides of the gate electrode, and any of the semiconductor memory element and the semiconductor switching element. On one side, concave portions are formed so as to gradually widen on both sides of the cross section, and memory functional bodies each composed of a charge holding portion made of a material having a function of storing charge and a dissipation preventing dielectric having a function of preventing the dissipation of stored charges are formed. Crab the recess to be buried Formed on both sides of the bit electrode, and the semiconductor memory device is moved from one source / drain diffusion region to the other source / drain diffusion region based on the level of charge held in the charge holding portion when a voltage is applied to the gate electrode. A semiconductor device is provided which is capable of changing the amount of current flowing, and wherein the semiconductor switching element is configured to perform a switching operation irrespective of the level of charge held in the charge holding portion.

In another aspect of the present invention, an IC card to which the semiconductor memory device as described above is mounted is provided.

Also provided is a portable electronic device equipped with the semiconductor memory device as described above.

In still another aspect of the present invention, there is provided a semiconductor memory device comprising field effect transistors, comprising: forming a gate electrode on a surface of a semiconductor substrate through a gate insulator; Forming a bird's beak dielectric film having a laterally wider cross section between both sides of the gate electrode and the surface of the semiconductor substrate; Removing the beak dielectric film so as to form a recess in which the cross-section is gradually widened in a position where the beak dielectric film is removed; Forming a memory functional body on both sides of the gate electrode such that the recess is filled with a charge holding part made of a material having a function of storing charge and a dissipation preventing dielectric having a function of preventing the dissipation of stored charge; Fabricating a semiconductor memory device comprising using the gate electrode and the memory functional body as a mask to implant impurities into surface portions of a semiconductor substrate corresponding to both sides of the mask to form a pair of source / drain diffusion regions A method is provided.

In the above method of manufacturing a semiconductor memory device, the forming of the memory functional body comprises forming at least a portion of the anti-dissipating dielectric material with a substantially uniform film thickness along the exposed surface of the semiconductor substrate and the gate electrode between the recessed portions. Forming a first insulating film; Forming silicon nitride as a material of the charge holding portion on the exposed surface of the first insulating film so that the recess is buried; Etching the silicon nitride and the first insulating film on both sides of the gate electrode such that the memory function remains on both sides of the gate electrode, respectively.

Further, in the etching of the silicon nitride and the first dielectric film, the silicon nitride portions other than the recesses may be removed so that the silicon nitride portions existing in the recesses remain.

In another aspect of the present invention, semiconductor memory elements each composed of field effect transistors are formed in a memory region set on a semiconductor substrate, and semiconductor switching elements each composed of field effect transistors are formed in a logic circuit region set on a semiconductor substrate, Forming a gate electrode on a portion of a surface of the semiconductor substrate corresponding to the memory region and the logic circuit region through a gate insulator, respectively; In both the memory region and the logic circuit region, there is formed a beak dielectric film having a wider cross section laterally between the semiconductor substrate surface and both sides of the gate electrode, respectively, and is laterally cross section at the place where the beak dielectric film is removed. Removing the beak dielectric film to form this gradually widening recess; Forming a first dope region in the logic circuit which forms a part of a source / drain diffusion region by introducing impurities into the logic circuit using the gate electrode as a mask so that impurities are not introduced into the memory region. ; In both the memory region and the logic circuit region, a charge holding portion made of a material having a function of storing charges and a dissipation preventing dielectric having a function of preventing dissipation of stored charges on both sides of the gate electrode such that the recess is buried. Forming memory functional bodies each consisting of; A second impurity having the same conductivity type as that of the above step into the memory region and the logic circuit region by using the gate electrode and the memory functional body as a mask to form at least a portion of the source / drain diffusion region A semiconductor device manufacturing method comprising forming a dope region is provided.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail by the embodiments shown in the drawings. In addition, the present invention is not limited by the above embodiments.

(First embodiment)

As shown in FIG. 1A, the semiconductor memory device of the present embodiment includes a gate electrode 3 formed on the semiconductor substrate 1 through a gate insulator 2, and a channel forming region disposed under the gate electrode 3. 19), a pair of source / drain diffusion regions 13 disposed on both sides of the channel formation region 19 and having a conductivity type opposite to that of the channel formation region 19, and the gate electrode 3, respectively. It mainly includes a memory function 30 formed on both sides and each having a function of storing charge, each of the memory function 30 is a charge holding portion 31 capable of holding charge and dissipation of charge A dissipation preventing dielectric 32, wherein the charge holding portion 31 is isolated from the gate electrode 3 and the semiconductor substrate 1 by the dissipation preventing dielectric 32, and the semiconductor The substrate 1 and the gate electrode 3 have different compositions And the distance T2 between the charge holding unit 31 and the gate electrode 3 is different from the distance T1 between the charge holding unit 31 and the semiconductor substrate 1. do. Here, when the distance T2 between the gate electrode 3 and the charge holding portion 31 is not constant, the distance of the nearest contact portion of the charge holding portion 31 is set to the distance T2.

In addition, one aspect of the present invention corresponds to a case where the gate electrode 3 and the semiconductor substrate 1 are made of silicon and have different impurity concentrations. In such a case, by taking advantage of the fact that the film formation rate is influenced by the silicon impurity concentration of the oxide film to be formed on the silicon (called "impurity enhanced oxidation"), no special step such as etching is required, and the distance The film thickness which makes T1 and distance T2 different can be formed easily.

Here, the names of the memory functional bodies and their components are defined as follows.

As shown in Fig. 1A, " memory functional body 30 " represents regions each formed laterally of the gate electrode 3 with a function of storing charge. In addition, each memory functional element 30 is composed of a charge holding portion 31 which is a portion capable of holding charge and a dissipation preventing dielectric 32 which is a portion which suppresses dissipation of charge.

In addition, reference numeral 8 of FIG. 1A denotes a gate stack including the gate insulator 2 and the gate electrode 3. Reference numeral 20 denotes an offset area. Reference numeral TG denotes the thickness of the gate insulator 2.

In addition, as shown in FIG. 1B, one aspect of each memory functional body 30 corresponds to a case in which the dissipation radiator insulator 32 is divided into a first insulator 32a and a second insulator 32b. Here, for convenience, a region of the memory functional body 30 except for the first insulator 32a, that is, a region composed of the charge holding part 31 and the second insulator 32b will be referred to as a "charge storage region 33". will be. However, the charge storage region 33 may be composed of only the charge holding unit 31 as described below.

As shown in FIG. 1C, each memory functional body 30 does not include the second insulator 32b but includes the first insulator 32a and the charge holding part 31. In this case, the charge storage region 33 is composed of only the charge holding portion 31.

As shown in the figure, since the charge storage region is not formed in the gate insulator portion of the field effect transistor as described in the prior art, but is formed laterally of the gate electrode, the problem of over-erasing included in the prior art is substantially Removed.

In addition, the first insulator 32a does not require, for example, an etching step specifically for changing the film thickness, and can form a different film thickness by a very simple step.

In addition, due to the variable resistance effect of the memory functional body, the semiconductor memory device can function as a memory cell having the functions of the selection transistor and the memory transistor.

In addition, the semiconductor substrate and the gate electrode are preferably formed of a material made of silicon. In this case, since the semiconductor substrate and the gate electrode are made of silicon, which is often used as a material of a semiconductor device at present, a semiconductor process having a high affinity with conventional semiconductor manufacturing processes can be constructed, and thus a semiconductor memory having a low manufacturing cost An apparatus may be provided.

Further, in the embodiment of the semiconductor memory device of the present invention, when one device stores two or more bits of information, it may function as a memory device for storing four or more pieces of information.

In addition, the semiconductor memory device shown in FIG. 1 has a shape in which the distance T2 is widened so as to be far from the semiconductor substrate. Therefore, since the upper portion of the charge holding portion is formed to be farther from the gate electrode than the lower portion thereof, it is possible to suppress that unnecessary charge is injected into the upper portion of the charge holding portion. For example, injection of electrons from the gate electrode, which may occur in the erase mode, can be greatly suppressed. Further, since the lower portion is not separated by the upper portion, the charge to be retained is formed so as not to be unnecessarily separated from the channel forming region, so that the effect of the amount of the retained charge on the amount of driving current can be sufficiently maintained. This makes it possible to suppress unnecessary charge injection and dissipation without reducing the difference between the read currents in the write / erase mode. On the other hand, although the state in which the distance differs is explicitly shown in FIG. 1 in order to demonstrate the distance T2 in detail, also in another embodiment, the same aspect can be obtained without special description, and the effect accordingly is the same. Of course it can be obtained.

In addition, the semiconductor memory device of the embodiment of the present invention may be configured as follows.

The semiconductor memory element functions as a semiconductor memory element that stores tetravalent or higher information such that bivalent or higher information is stored in one memory functional body. In addition, due to the variable resistance effect by the memory functional body, the semiconductor memory element can function as a memory cell having both the function of the selection transistor and the memory transistor. However, the semiconductor memory element does not always need to store and function tetravalent or more information, for example, may also function by storing bivalent information.

The semiconductor memory device of the present invention is preferably formed on a semiconductor substrate or a well region of the same conductivity type as the channel formation region formed in the semiconductor substrate.

The semiconductor substrate is not particularly limited as long as it is used in a semiconductor device. For example, a semiconductor substrate made of an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe or GaN may be mentioned. In addition, various substrates such as a silicon on insulator (SOI) substrate or a multi-layer SOI substrate, or a glass or plastic substrate having a semiconductor layer on the surface may be used. Among them, a silicon substrate or an SOI substrate having a silicon layer formed on its surface is preferable. The semiconductor substrate or the semiconductor layer may be any of a single crystal (for example, a single crystal due to epitaxial growth), a polycrystalline and an amorphous substrate, although there are some differences in the amount of current flowing therein. In the case of using an SOI substrate, since the capacity of the source / drain diffusion region and the semiconductor substrate can be minimized, a semiconductor device capable of high speed operation can be provided.

It is preferable that a device isolation region is formed on the semiconductor substrate or the semiconductor layer. In addition, a semiconductor device may be formed in a single layer or a multilayer structure by combining a semiconductor substrate or a layer with elements such as transistors, capacitors, resistors, circuits formed of elements, other semiconductor devices, and interlayer insulating films. In addition, the device isolation region may be formed of various device isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have either a conductive type of P type or N type, and at least one well region of P type or N type is preferably formed in the semiconductor substrate. Impurity concentrations of the semiconductor substrate and the well region may be within a range known in the art. However, when the SOI substrate is used as a semiconductor substrate, a well region may be formed in the surface semiconductor layer, and a body region may be maintained under the channel formation region. In this way, the well region and the body region formed in the semiconductor substrate and the surface semiconductor layer have conductivity types opposite to those of the source / drain diffusion regions, and are adjusted to appropriate impurity concentrations. More specifically, the current leaking from one source / drain diffusion region to the other source / drain diffusion region can be reduced by forming a well region and a body region. Therefore, the substrate floating effect which becomes a problem when using an SOI substrate can also be reduced.

However, in order to form the insulating film for the gate electrode and the insulating film on the semiconductor substrate to have a different thickness, it is preferable to set the impurity concentration of the well region in the insulating film forming region when the insulating film is formed to be different from the impurity concentration of the gate electrode. . When setting impurity concentration light, it is 1 * 10 <^20> cm <^-3> or less, and when setting it to dark, it is preferable to set it as 5 * 10 <^19> cm <^-3> or more. In this case, the insulating film for the gate electrode and the insulating film on the semiconductor substrate can be effectively formed to have different thicknesses.

In this regard, in the case where an impurity region is formed near the front surface of the substrate and used for adjusting the threshold voltage by channel injection, for example, the concentration of the impurity region may satisfy the above condition.

The gate insulator or the gate film is not particularly limited as long as it is generally used for semiconductor devices. For example, a single layer film or a laminated film made of a high dielectric film such as an insulating film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film can be used. Among them, a silicon oxide film is preferable. The gate insulator is suitably formed to a thickness of, for example, about 1 to 20 nm, preferably about 1 to 6 nm. The gate insulator may be formed directly below the gate electrode, or may be formed larger (widely) than the gate electrode. Since a wide insulating film depending on the structure and the process can also serve as an insulating film under the charge storage region, the manufacturing process of the semiconductor memory device can be simplified.

The gate electrode or the electrode is formed on the gate insulator in a shape generally used in a semiconductor device or in a shape having a recess at a low end. In addition, the "single gate electrode" means the gate electrode which is integrally formed without being isolated by a single | mono layer or a multilayer conductive film. In addition, the gate electrode may have a sidewall insulating film on the sidewall. Further, the gate electrode is formed on the gate insulator. In addition, the gate electrode is a conductive film generally used in semiconductor devices, for example, a metal such as polysilicon, copper or aluminum, a high melting point metal such as tungsten, titanium, or tantalum, a silicide having a high melting point metal, or the like. It is formed using a material that is a single layer film or a laminated film made. In particular, the material of the gate electrode may be selected from a material different from that of the semiconductor substrate. Generally, silicon substrates are used for semiconductor substrates. Therefore, in this case, the gate electrode material is preferably a single layer film or a laminated film made of a silicide having a metal such as copper or aluminum, a high melting point metal such as tungsten, titanium, or tantalum, and a high melting point metal. In this case, the insulating film for the gate electrode and the insulating film on the semiconductor substrate may be formed to have significantly different thicknesses.

The gate electrode is suitably formed to have a thickness of, for example, about 50 to 400 nm. In addition, a channel formation region is formed under the gate electrode. The channel forming region is preferably formed below the region including the outer side of the gate end in the gate length direction as well as the gate electrode. When there is a portion of the channel formation region not covered with the gate electrode in this manner, it is preferable that the channel formation region is covered with the gate insulator or the charge storage region described later.

It is also important that the gate electrode differs from the semiconductor substrate in the formation rate during the formation of the first insulator 32a. More specifically, when the process of forming the insulating film for a desired time is performed, the gate is formed so that the thickness T1 of the insulating film formed on the semiconductor substrate is different from the thickness T2 of the insulating film formed on the sidewall portion of the gate electrode. The electrode material and the semiconductor substrate material are determined in turn. Therefore, since the film thickness can be made to be self-aligned by simple steps, a semiconductor memory device having low manufacturing cost without requiring complicated steps can be provided.

In addition, the insulator 32a may have a smaller thickness T1 of the portion in contact with the semiconductor substrate than the thickness T2 of the portion in contact with the gate electrode 3. Therefore, since the charge injected from the semiconductor substrate can be prevented from passing through the insulator and exiting to the gate electrode, a semiconductor memory device having good charge injection efficiency and high writing / erasing speed can be provided.

In addition, in the first embodiment of the present invention, the insulators 32a and 32b may have a thicker thickness T1 of the portion in contact with the semiconductor substrate than the thickness T2 of the portion in contact with the gate electrode 3. have. Since the charge injected from the gate electrode can be prevented from passing through the insulator and exiting the semiconductor substrate, a semiconductor memory having good charge injection efficiency and high writing / erasing speed can be provided.

Each memory functional body comprises at least a film or region having a function of holding a charge, storing or holding a charge, trapping a charge, or maintaining a charge polarization state. As a material which exhibits such a function, silicon nitride; silicon; Silicate glass containing impurities such as phosphorus or boron; Silicon carbide; Alumina; High dielectric materials such as hafnium oxide, zirconium oxide, or tantalum oxide; Zinc oxide, ferroelectric; Metal and the like. The memory functional body may include, for example, an insulator film including a silicon nitride film; An insulator film including a conductive film or a semiconductor layer therein; An insulator film comprising at least one conductor or semiconductor dot; The internal charge may be formed in a single layer or a laminated structure made of an insulating film including a ferroelectric film in which polarization is maintained by polarization by an electric field. Among them, since the silicon nitride film has a large number of levels trapping charges, a large hysteresis characteristic can be obtained. In addition, since the charge holding time is long and free from charge leakage due to the occurrence of leakage paths, the holding characteristics are good. Moreover, since it is a material generally used in an LSI process, it is preferable.

If an insulating film containing an insulating film having a charge holding function such as a silicon nitride film therein as a memory functional body is used, the reliability of storage holding can be improved. This is because the silicon nitride film is an insulator, so that even when a portion of the charge leaks, the charge of the entire silicon nitride film is not immediately lost. Further, when a plurality of semiconductor memory elements are arranged, information stored in each memory functional bodies as in the case of a memory functional body made of a conductor, even when the distance between the semiconductor memory elements is shortened or an adjacent memory functional body is in contact with each other. Do not lose items. In addition, contact plugs can be disposed closer to the memory function, and sometimes can be arranged to overlap the memory function, thereby facilitating microfabrication of the semiconductor memory device.

In addition, in order to improve the reliability of storage holding, an insulating "film" having a charge holding function is not always necessary, and an insulator having a charge holding function is preferably present discretely in the insulating film. Specifically, it is preferable to be dispersed in a dot shape in a material that is difficult to hold electric charge, for example, silicon oxide.

In addition, a conductor or a semiconductor may be used as the material of the charge storage region. Therefore, since the injection amount of charge into the conductor or the semiconductor can be freely controlled, there is an advantage that a multivalued semiconductor memory device can be easily constructed.

In addition, when an insulator including one or more conductors or semiconductor dots is used as the material of the charge storage region, the charge can be easily written / erased by direct tunneling, thereby reducing the power consumption. Bring.

As the material of the charge storage region, a ferroelectric film such as PZT or PZLT whose polarization direction is changed by an electric field may be used. In this case, electric charge is substantially generated on the entire surface of the ferroelectric film due to polarization, and such a state is maintained. Thus, the same hysteresis characteristics as those of a film having a memory function and supplying charges from the outside for trapping charges can be obtained. In addition, since hysteresis characteristics can be obtained only by maintaining charges and polarizing charges in the film without requiring charge injection from the outside of the ferroelectric film, there is an advantage that information can be recorded / erased at high speed.

In addition, each memory functional body preferably further includes a film having a function of making it difficult to escape the charge or a region making it difficult to escape the charge.

A silicon oxide film etc. are mentioned as a film | membrane which exhibits the function which makes it difficult to escape an electric charge.

The charge holding part included in the memory functional body is formed on both sides of the gate electrode directly or through an insulating film, and is disposed directly on the semiconductor substrate (well region, body region, or source / drain region or diffusion region) through the gate insulator or insulating layer. have.

The charge holding portions on both sides of the gate electrode are preferably formed so as to cover all or part of the sidewall of the gate electrode either directly or through an insulating film. As an application example, when the gate electrode has a recessed portion at its lower end, it may be formed so as to completely or partially fill the recessed portion directly or through an insulating film.

The gate electrode is preferably formed only on the sidewall of the memory function or does not cover the top of the memory function. This arrangement facilitates miniaturization of the semiconductor memory device because the contact plug can be located close to the gate electrode. In addition, the semiconductor memory device having such a simple arrangement is easy to manufacture and can improve the yield.

In the case where a conductive film is used as each charge holding portion, it is preferable that the charge holding portion is disposed through the insulating film so as not to directly contact the semiconductor substrate (well region, body region, source / drain region or diffusion region) or the gate electrode. Examples of the charge holding unit include a laminated structure consisting of a conductive film and an insulating film, a structure in which the conductive film is dispersed in a dot shape or the like on the insulating film, or a structure in which the conductive film is disposed on a part of the sidewall insulating film formed on the sidewall of the gate. Can be.

The source / drain diffusion region is a diffusion region having a conductivity type opposite to that of the semiconductor substrate or the well region, and is disposed on the opposite side of the charge storage region with respect to the gate electrode. It is preferable that the impurity concentration rapidly increases in the junction between each source / drain diffusion region and the semiconductor substrate or well region. This is because hot electrons and passion holes are efficiently generated at low voltage, and high speed operation is realized by lower voltage. The junction depth of each source / drain diffusion region is not particularly limited, but may be appropriately adjusted according to the performance of the semiconductor memory device to be obtained and the like. By the way, when using an SOI substrate as a semiconductor substrate, each source / drain diffusion region may have a junction depth that is smaller than the thickness of the surface semiconductor layer of the SOI substrate, but the junction depth substantially equal to the thickness of the surface semiconductor layer. It is desirable to have.

The source / drain regions may be disposed to overlap the gate electrode terminal, may be disposed to coincide with the gate electrode terminal, or may be disposed to be offset with respect to the gate electrode terminal. In particular, in the case of the offset arrangement, when the voltage is applied to the gate electrode, the ease of inversion of the offset region under the charge holding portion varies greatly depending on the amount of charge stored in the memory functional body. Therefore, it is desirable for the memory effect to increase and the short channel effect to decrease. However, if the source / drain regions are excessively offset, the driving current between the source and the drain becomes considerably small. Therefore, it is preferable that the magnitude of the offset, i.e., the distance from one of the gate electrode ends to the closer of the source / drain regions in the gate longitudinal direction is shorter than the thickness of the charge holding portion in the gate longitudinal direction. In particular, it is important that at least a portion of the charge holding portion of the memory functional body overlap with the source / drain region which is the diffusion region. The essence of the semiconductor memory device constituting the semiconductor memory device of this embodiment of the present invention is stored by an electric field across the memory function based on the voltage difference between the gate electrode and the source / drain region existing only in the sidewall portion of the memory function. This is because it rewrites.

Each source / drain region may partially extend at a position above the front surface of the channel formation region, that is, the bottom surface of the gate insulator. In such a case, it is appropriate that a conductive film integrated with the source / drain regions is laminated on the source / drain regions formed in the semiconductor substrate. Examples of the material of the conductive film include semiconductors such as polysilicon or amorphous silicon, silicides, or the metals or high melting point metals described above. Among them, polysilicon is preferable. The reason is that since polysilicon has an impurity diffusion rate much higher than that of the semiconductor substrate, it is easy to shallowen the junction depth of the source / drain regions of the semiconductor substrate, and the short channel effect is easily suppressed. In this case, however, it is desirable to position at least a portion of the memory functional element between a portion of the source / drain region and the gate electrode.

The semiconductor memory device of the present invention is a conventional semiconductor process, for example,

It can be formed by a method similar to the method of forming the sidewall spacer of a single layer or a laminated structure on the sidewall of the gate electrode. Specifically, after the gate electrode or the electrode is formed, a single layer film including a charge holding portion, or a stack including a charge holding portion such as a charge holding portion / insulating film, an insulating film / charge holding portion, or an insulating film / charge holding portion / insulating film A method of forming a film and etching back under suitable conditions such that the film remains in the shape of sidewall spacers can be mentioned. Further, a method of forming an insulating film or a charge holding part, etching back under appropriate conditions so as to remain in the shape of the sidewall spacers, and forming an insulating film or a charge holding part and etching back similarly so as to remain in the shape of the sidewall spacers may be mentioned. In addition, a method of applying or depositing an insulating film in which particle charge holding materials are dispersed on a semiconductor substrate including a gate electrode and etching back under appropriate conditions so as to remain in the form of sidewall spacers may be used. In addition, after the gate electrode is formed, a method of forming the single layer film or the laminated film and patterning using a mask is also possible. Another specific method is to form a film including a charge holding portion or a film including a charge holding portion / insulating film, an insulating film / charge holding portion, or an insulating film / charge holding portion / insulating film before forming the gate electrode or the electrode. There is a method of forming an opening in a region of the film to be a channel forming region, forming a gate electrode material film in the entire area of the structure thus formed, and patterning the gate electrode material film in a shape including the opening and larger than the opening. In the case of constituting a memory cell array by arranging the semiconductor memory elements of the present invention, the best form of a semiconductor memory device is, for example, (1) the gate electrodes of a plurality of semiconductor memory elements are integrated to provide a function of a word line. Have (2) Memory functional bodies are formed on both sides of the word line. (3) It is the insulator, especially the silicon nitride film, that holds the charge in the memory functional body. (4) The memory functional body is made of an ONO (Oxide Nitride Oxide) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulator. (5) The silicon nitride film in the memory functional body is divided into a word line and a channel forming region by a silicon oxide film. (6) The silicon nitride film in the memory functional body overlaps with the diffusion layer. (7) The thickness of the silicon nitride film having a surface substantially parallel to the surface of the gate insulator and the insulating layer separating the channel forming region or the semiconductor layer is different from the thickness of the gate insulating layer. (8) The write and erase operations of one semiconductor memory element are performed by a single word line. (9) There is no electrode (word line) having a function of assisting the write and erase operations on the memory functional body. (10) It satisfies the requirement that a region where the impurity concentration of the conductivity type opposite to the conductivity type of the diffusion region exists in a portion directly below the memory functional body in contact with the diffusion region.

It is best to meet all of the above requirements, but of course it is not necessary to meet all of the above requirements.

Particularly preferred combinations exist when two or more of the above requirements are met. Examples of such combinations include (3) holding charge in the memory functional body is an insulator, in particular a silicon nitride film, and (9) an electrode having a function of assisting write and erase operations on the memory functional body (word line ) Is not present, and (6) an insulating film (silicon nitride film) in the memory functional body overlaps with the diffusion layer. In the case where an electric charge is maintained in the memory functional body and an electrode having a function of assisting the write and erase operations does not exist on the memory functional body, an insulating film (silicon nitride film) in the memory functional body overlaps with the diffusion layer. It has been found that only if the write operator is performed preferably. That is, when the requirements (3) and (9) are satisfied, it is particularly preferable to satisfy the requirement (6). On the other hand, when the electric charge is held in the memory functional body or the electrode having a function of assisting the write and erase operations is present on the memory functional body, the insulating film in the memory functional body does not overlap with the diffusion layer. The recording operation could also be performed at. However, when retaining charge in the memory functional body is not an conductor but an insulator, or when there is no electrode on the memory functional body having a function of assisting the write and erase operations, the following great advantages can be obtained. . Since the contact plug can be located closer to the memory function or the plurality of memory functions interfere due to the shortening of the distance between the semiconductor memory elements, the stored information can be retained, so that the microfabrication of the semiconductor memory device This becomes easy. In addition, since the device structure is simple, the number of process steps is reduced, the yield is improved, and the transistor and the semiconductor memory device constituting the logic circuit or the analog circuit can easily coexist. It has also been confirmed that write and erase operations are performed at a voltage lower than 5V. As mentioned above, it is especially preferable to satisfy requirements (3), (9), and (6).

The semiconductor memory device in combination with the semiconductor memory device or the logic element of the present invention can be applied to a battery-powered portable electronic device, especially a portable information terminal. Examples of portable electronic devices include portable information terminals, mobile phones, and game machines.

Hereinafter, various embodiments of the present invention will be described in detail. Of course, the present invention is not limited to the following examples.

In the following embodiments, a case of using an N-channel element as a memory will be described, but a P-channel element can also be used as a memory. In this case, all of the conductivity types of the impurities may be reversed.

In addition, in description of drawing of this invention, the same code | symbol is attached | subjected to the part using the same material and substance, and the part does not necessarily show the same shape.

In addition, it should be noted that the drawings of the present invention are schematic, and that the relationship between the thickness and the planar dimension, the ratio of the thickness and size of each layer or each part, etc. is different from the actual one. Therefore, the actual thickness or size should be determined in consideration of the following description. In addition, of course, drawings may include portions having different dimensional relationships or ratios from one another.

Second Embodiment

A second embodiment of the present invention will be described with reference to Figs. 2A to 2D. As shown in Fig. 2D, in the memory device constituting the semiconductor memory device of the present embodiment, the gate electrode 3 is formed on the semiconductor substrate 1 via the gate insulator 2, and at least two kinds of film thicknesses. First insulators 32a each having a sidewall of a gate stack 8 formed of a gate insulator 2 and a gate electrode 3 and formed on a semiconductor substrate 1, wherein Sidewall-shaped charge storage regions 33 are formed on both sides of the gate electrode 3 through the first insulators 32a each having a film thickness. In addition, a pair of source / drain diffusion regions 13 are formed below the charge storage region 33.

The first insulator 32a each having at least two kinds of film thicknesses does not require a special step, for example, an etching step for processing two or more kinds of film thicknesses, and a very simple step to at least two kinds of film thicknesses. Can be formed.

In addition, the source / drain diffusion region 13 is offset with respect to the end of the gate electrode 3. That is, on the entire surface of the semiconductor substrate 1, the source / drain diffusion region 13 is not under the gate electrode 3, and each of them is separated from the gate electrode 3 by a width corresponding to the offset region 20. have. That is, the channel formation region 19 between the source / drain diffusion regions 13 is disposed below the charge storage region 33 on the entire surface of the semiconductor substrate 1 by the width of the offset region 20. Therefore, the injection of electrons into the charge storage region 33 and the injection of holes can be efficiently performed to form a memory device having a high writing and erasing speed.

In addition, since the source / drain diffusion region 13 is offset from the gate electrode 3 of the memory element, the offset region 20 under the charge holding region 33 when a voltage is applied to the gate electrode 3 is applied. Since the ease of inversion of the portion can be greatly changed depending on the amount of charge stored in the charge storage region 33, the memory effect can be increased. In addition, the short-channel effect can be strongly prevented and the gate length can be further shortened as compared with the MOSFET of the conventional structure. In addition, since the memory element is suitable for suppressing the short channel effect due to its structure, a gate insulator thicker than a logic transistor can be used and its reliability can be improved.

In addition, the charge storage region 33 of the memory transistor is formed independently of the gate insulator 2. Therefore, the memory function of the charge storage region 33 and the transistor operation function of the gate insulator 2 are separated from each other. In addition, the charge storage region 33 can be formed by selecting a material suitable for the memory function.

The memory device may be formed through the same steps as conventional logic transistors.

Hereinafter, a manufacturing process is demonstrated in order according to FIG. 2A-FIG. 2D.

As shown in FIG. 2A, a semiconductor substrate having a MOS (metal-oxide film-semiconductor) structure and a gate insulator and gate electrode 3, that is, a gate stack 8 having a MOS formation process, having a P-type conductivity type It forms on (1).

Representative MOS forming processes are as follows.

First, an element isolation region is formed by a known method on a semiconductor substrate 1 made of silicon and having a P-type semiconductor region. The device isolation region can prevent the leakage current from flowing through the substrate between adjacent devices. However, in devices in which the source / drain diffusion regions are shared between adjacent devices, it is not necessary to form such device isolation regions. The "known method of forming an isolation region" can be a known method using a LOCOS oxide film, a known method using a trenched isolation region, or any known method that can achieve the purpose of device isolation. have. The device isolation region is not particularly shown.

Next, although not particularly shown, an impurity diffusion region is formed in the vicinity of the entire surface of the exposed portion of the semiconductor substrate 1. The impurity diffusion region serves to adjust the threshold voltage and increase the concentration of impurities in the channel formation region. In addition, as an important reason, in order to change the film thickness of the insulating film for the gate electrode and the insulating film formed on the semiconductor substrate, the impurity concentration of the surface of the semiconductor substrate in the insulating film forming region in the case of forming the insulating film is determined by the gate electrode 3. Different from impurity concentration in When setting impurity concentration light, it is 1 * 10 <^20> cm <^-3> or less, and when setting it to dark, it is preferable to set it as 5 * 10 <^19> cm <^-3> or more. In that case, the insulating film on the gate electrode 3 and the insulating film on the semiconductor substrate 1 can be effectively formed to have different thicknesses.

Next, an insulating film is formed over the entire exposed surface of the semiconductor region. Since the insulating film can suppress leakage, a high dielectric film such as an oxide film, a nitride film, a composite film made of an oxide film and a nitride film, a hafnium oxide film or a zirconium oxide film, and a composite film made of a high dielectric film and an oxide film can also be used. In addition, since the insulating film serves as a gate insulator of the MOSFET, it is preferable to form a film capable of exhibiting excellent performance as the gate insulator by using steps including N ₂ O oxidation, NO oxidation, and post-oxidation nitriding treatment. The term "film that exhibits excellent performance as a gate insulator" can suppress all factors that impede the progress of MOSFET microfabrication and performance improvement. For example, the short channel effect of the MOSFET and the gate insulator are unnecessary. It refers to an insulating film capable of suppressing diffusion of gate electrode impurities into the channel formation region of the MOSFET while suppressing leakage current which is a flowing current and depletion of impurities of the gate electrode.

As a representative example of the film and its thickness, in an oxide film such as a thermal oxide film, an N ₂ O oxide film or an NO oxide film, the film thickness is suitably in the range of 1 to 6 nm.

Next, polysilicon doped with impurities is formed on the gate insulator. Impurities are added to increase the electrical conductivity so that polysilicon acts as a gate electrode, and importantly, to add the effect of so-called "impurity-enhanced oxidation", which is an increase in the oxidation rate of silicon based on doping with impurities. . More specifically, the first insulator 32a formed on the semiconductor substrate 1 and the gate electrode 3 (by using the difference between the effects of the impurity strengthening oxides of the semiconductor substrate 1 and the gate electrode 3) ( 2b) to give a thickness difference. Therefore, it is necessary to give the polysilicon an impurity concentration different from that of the semiconductor substrate 1. Here, the impurity concentration of the gate electrode 3 may be higher than the impurity concentration of the semiconductor substrate 1. Preferably, the impurity concentration of the semiconductor substrate 1 is 1 × 10 ²⁰ cm ⁻³ or less, the impurity concentration of the gate electrode 3 is 5 × 10 ¹⁹ cm ⁻³ or more, and the impurity concentration of the gate electrode 3. It is desirable to make the condition higher than the impurity concentration of the semiconductor substrate 1. Therefore, since the impurity concentration of the gate electrode 3 is 5 × 10 ¹⁹ cm ⁻³ or more, the effect of impurity strengthening oxidation starts to appear remarkably. In addition, since the impurity concentration in the channel formation region is 1 × 10 ²⁰ cm ⁻³ or less, the effect of impurity strengthening oxidation does not appear under some conditions of oxidation time. Further, since the impurity concentration of the gate electrode 3 is higher than the impurity concentration of the semiconductor substrate 1, the thickness T2 of the insulating film portion in contact with the gate electrode and the insulating film portion in contact with the semiconductor substrate 1 The thickness T1 can be made differently self-aligning, and T2 can be made thicker than T1. Therefore, since the charge injected from the semiconductor substrate 1 can be prevented from passing through the insulating film and exiting to the gate electrode, a semiconductor memory device having high charge injection efficiency and high writing / erasing speed can be provided at low cost without complicated steps. can do.

Here, the thickness of the polysilicon film is preferably about 50 to 400 nm.

Further, here, only doped polysilicon is used as the material of the gate electrode 3, but a film made of undoped polysilicon on the doped polysilicon, a film made of metal such as Al, Ti, or W, or the like It is also possible to apply a film made of a compound of metal and silicon. An undoped polysilicon may be laminated on the doped polysilicon.

Next, in order to etch the gate electrode material and the gate insulator to form the structure shown in FIG. 2A, a desired photoresist pattern is formed on the gate electrode material by a photolithography step, and the gate is formed using the photoresist pattern as a mask. Etch is performed. That is, the gate insulator 2 and the gate electrode 3 are formed, and the gate stack 8 which consists of these is formed. Although not shown, the gate insulator does not need to be etched in this case. In the case where the gate insulator is used as the injection protection film during the implantation of the impurity in the next step without etching, the step of forming the injection protection film can be omitted.

In addition, the material of the gate insulator 2 and the gate electrode 3 may be a material used for the logic process according to the scale rule of the time as mentioned above, and this invention is not limited to the said material.

In addition, the gate stack 8 may be formed by the following method. The same gate insulator is formed on the entire exposed surface of the semiconductor substrate 1 having the P-type semiconductor region. Subsequently, the same gate electrode material as above is formed on the gate insulator. Subsequently, a mask insulating film such as an oxide film, a nitride film, or an oxynitride film is formed on the gate electrode material. Next, the same photoresist pattern is formed on the mask insulating film, and the mask insulating film is etched. Next, the photoresist pattern is removed, and the gate electrode material is etched using the mask insulating film as an etching mask. The exposed portions of the mask insulating film and the gate insulator are then etched to form the structure shown in FIG. 3A. In the case where the gate stack 8 is formed in this manner, the selection ratio at the time of etching, that is, the selection ratio between the gate electrode material and the gate insulator material can be set large, and the substrate 1 is not etched. Etching of the gate insulator made of a thin film can be realized. Although not shown, in this case the gate insulator does not need to be etched for the same reason.

Next, as shown in FIG. 2B, a film of the first insulator 32a is formed on the exposed surface of the gate stack 8 and the semiconductor substrate 1.

Here, the thickness T1 of the portion formed on the semiconductor substrate 1 is different from the thickness T2 of the portion formed on the gate electrode 3 by using a heat treatment step by a furnace as a film forming method. The first insulator 32a may be formed and the thickness T1 may be thinner than the thickness T2 under the impurity concentration condition.

These facts take advantage of the effect of varying the formation rate of the insulating film thickness using the heat treatment step by the impurity, and do not require any special step such as etching and can make a difference in the film thickness by a simple step. Therefore, the present invention can be carried out without increasing the manufacturing cost.

Also, since the first insulator 32a can suppress leakage, it may be made of a high dielectric insulating film such as an oxide film, a nitride film, a composite film made of an oxide film and a nitride film, or a hafnium oxide film or a zirconium oxide film. In addition, since the first insulator 32a is an insulating film through which electrons pass, a film having high withstand voltage, low leakage current, and high reliability is preferable. For example, like the material of the gate insulator 2, the first insulator 32a is made of an oxide film such as a thermal oxide film, an N ₂ O oxide film, or an NO oxide film. In the case of an oxide film, it is good that it is about 1-20 nm. In addition, when the thickness T1 of the portion for injecting / erasing the charge, that is, the portion in contact with the semiconductor substrate 1 is made so thin that the tunnel current flows through the insulating film, the voltage required for injecting / erasing the charge can be lowered. Therefore, power consumption can be lowered. Typical thickness in such cases is preferably about 1-6 nm. Here, due to the formation of the first insulator 32a, since each memory functional body includes an insulating film without directly contacting the semiconductor substrate 1 and the gate electrode 3, leakage of the sustain electrons is suppressed by the insulating film. can do. As a result, a memory element having good charge holding characteristics and high long-term reliability is formed.

Next, polysilicon, which is a material forming the charge storage region 33, is deposited substantially uniformly. Here, the material of the charge storage region 33 may be a material capable of holding or inducing a charge, for example, a material such as a nitride film or an oxynitride film capable of holding electrons and holes, or an oxide film having a charge trap; Materials such as PZT and PLZT, which can induce charge on the surface of the charge storage region by a phenomenon such as polarization; Alternatively, the material may be a material having a substrate capable of holding charge such as floating polysilicon or silicon dots in the oxide film.

The film thickness of the material forming the charge storage region 33 may be, for example, about 2 to 100 nm when a nitride film or polysilicon is used. The film thickness is an important parameter for forming the source / drain diffusion region 13 offset with respect to the gate electrode. Therefore, the size of the offset may be taken into consideration and the film thickness of the first insulator 32a may also be adjusted within the above range.

Next, as shown in FIG. 2C, the material forming the charge storage region 33 is anisotropically etched to form the charge storage region 33 on the sidewall of the gate stack 8. Etching may selectively etch the material forming the charge storage region 33, or may be performed under conditions in which the etching selectivity with respect to the first insulator 32a is large. At this time, the top of each charge storage region 33 may be the same height or lower than the top of the gate electrode (3).

By etching the first insulator 32a in a subsequent step, the gate electrode 3 and the charge storage region 33 may be shorted. However, the etching is performed in advance to extend the charge storage region 33 and short-circuit. Can be suppressed. The term "short circuit" also includes a short circuit in the silicide step and the contact step of the gate electrode 3.

In addition, when anisotropic etching is performed so that the uppermost portion of the charge storage region 33 is lower than the uppermost portion of the gate electrode 3, the charge storage region 33 may be disposed only in the vicinity of the channel. Anisotropic etching may be further performed to make the charge storage region 33 smaller. As a result, electrons injected by recording are limited in the vicinity of the channel, so that electrons can be easily removed by erasing. Therefore, erasure is prevented. In addition, assuming that the number of injection electrons does not change due to the limitation of each charge holding unit, the electron density of the charge holding unit is increased, so that the writing / erasing of electrons is performed efficiently, thereby forming a semiconductor memory device having a high writing / erasing speed. . However, in the case where the arrangement prevents sufficient offset magnitude between the gate electrode and the source / drain diffusion region, the step of forming the sidewall spacers must be further performed.

In this regard, in the case where a material having electrical conductivity such as a conductor or a semiconductor as a material of the charge storage region 33, and polysilicon is used as a typical example, the left and right charge storage regions 33 are formed after the charge storage region 33 is formed. It is necessary to insulate electrically. Therefore, as shown in Fig. 28A, part of the charge storage region 33 (removal region) is etched and removed. As the removal method, the photoresist is patterned by a known photolithography step so as to cover a portion of the region 33 other than the removal region 21 of the charge storage region 33. Then, anisotropic etching is performed to remove the removed region, which is the exposed portion of the charge storage region 33. The etching need not always be anisotropic etching, and wet etching may be performed as long as it can selectively etch the charge storage region 33 and can be performed under conditions that increase the etching selectivity with respect to the first insulator 32a. have. However, in the removal region 21, the removal region 21 is preferably positioned above the device isolation region to prevent damage to the device due to etching.

Next, as shown in FIG. 2D, by anisotropically etching the first insulator 32a, only the exposed portion thereof is selectively etched to finish the first insulator 32a. Etching may selectively etch the first insulator 32a to increase the etching selectivity of the material of the gate electrode 3 and the material of the semiconductor substrate 1 with respect to the material forming the charge storage region 33. It may also be carried out under conditions.

In this process, a part of the first insulator 32a which is not covered with the charge storage region 33, that is, the portion corresponding to the portion of the removal region 21 of the charge storage region 33 in the step (semiconductor substrate) (1) contact part is removed by etching. On the other hand, some (parts in contact with the gate sidewalls) remain in the state shown in Fig. 28B. Here, a part of the first insulator 32a remains in the state of FIG. 28B and covers the outer circumference of the gate electrode 3, so that a short circuit between the source / drain contact and the gate electrode 3 can be suppressed. Therefore, the micromachining becomes easy, and the high integration of the memory is realized.

In addition, the forming of the charge storage region 33 and the forming of the first insulator 32a may be performed by a single step. More specifically, all of the materials forming the first insulator 32a and the charge storage region 33 can be selectively etched, and etching choices regarding the material of the gate electrode 3 and the material of the semiconductor substrate 1 can be made. By performing anisotropic etching using a condition in which the ratio becomes large, what was normally required for two steps can be performed by a single step, thereby reducing the number of steps. However, even in this case, when a material containing an electrically conductive material such as a conductor or a semiconductor is used as the material of the charge storage region 33, it is necessary to electrically insulate the left and right charge storage regions 33. Therefore, as shown in Fig. 28B, part of the charge storage region 33 (removal region) is removed by etching. The removal method may be the same as above.

Next, source / drain impurity implantation is performed using a source / drain implantation region consisting of the gate electrode 3, the first insulator 32a, and the charge storage region 33 as a mask, and a known heat treatment is performed. Source / drain diffusion regions 13 are formed. If an implantation protective film (not shown) is formed in advance in the exposed portion of the semiconductor substrate 1 during ion implantation, the surface of the semiconductor substrate can be prevented from being roughened due to ion implantation, and unnecessary deep implantation can be suppressed.

According to the present semiconductor memory device, the first insulator 32a is different from the portion where the film thickness T1 of the portion formed on the semiconductor substrate 1 is in contact with the gate electrode 3, and T1 becomes thinner than T2. Is formed. In addition, these utilize the effect that the formation rate of the insulating film thickness using the heat treatment step is changed by impurities, and the film thickness can be changed by a simple step without requiring a special step such as etching. Therefore, the present invention can be carried out without increasing the manufacturing cost.

In addition, according to the semiconductor memory device, it is possible to realize storage of 2 bits per transistor. Here, the principle of the write / erase and read methods for realizing 2 bits of storage per transistor will be described below. Here, the case where the memory element is an N-channel type will be described. In the case where the memory element is a P-channel type, the sign of the voltage can be reversed and applied similarly. In addition, a ground potential can be given to a node (source / drain, gate, and substrate) to which the applied contact voltage is not specifically specified.

In the case of writing information in the memory device, a positive voltage is applied to the gate and a positive voltage almost equal to or greater than the gate voltage is applied to the drain. At this time, the electric charges (electrons) supplied from the source are accelerated near the drain end to become hot electrons, and are mainly concentrated in the charge storage region on the drain side. At this time, electrons are not injected into the charge storage region existing on the source side. In this way, information can be recorded in the charge storage region on the specific side. Also, by changing the drain to the source, two bits of writing can be easily performed.

In order to erase the information recorded in the memory device, passionate implantation is used. A positive voltage may be applied to the diffusion layer region (source / drain) on the side of the charge storage region to be erased, and a negative voltage may be applied to the gate. At this time, holes are generated by inter-band tunneling at the PN junction between the semiconductor substrate and the diffusion layer region to which the positive voltage is applied. Holes are attracted toward the gate having a negative potential and injected into the charge storage region to be erased. In this way, the information on the specific side can be erased. However, in order to erase the information recorded in the charge storage region on the opposite side, a positive voltage may be applied to the charge storage region on the opposite side.

Next, in order to read the information recorded in the memory element, the diffusion region on the side of the charge storage region to be read is set as the source, and the diffusion region on the opposite side is set as the drain. In other words, a positive voltage may be applied to the gate, and a positive voltage equal to or greater than the gate voltage may be applied to the drain (set as a source in the proxy). However, at this time, it is necessary to make the voltage small enough so that information is not recorded. The drain current changes based on the amount of charge stored in the charge storage region, and the stored information can be detected. By the way, in order to read the information recorded in the charge storage area on the opposite side, the source and the drain may be interchanged.

The writing / erasing and reading method is an example of using a nitride film for each charge storage region, and other methods can be used. Also, for any other material, the above method or other recording / erasing method can be used. For this reason, according to the semiconductor memory device, since storage of two bits per transistor can be realized, the area occupied by the memory element per bit can be reduced, and a large capacity nonvolatile memory can be formed.

Further, according to the present memory device, the charge storage region is disposed below the gate electrode and is disposed on both sides of the gate electrode. Therefore, it is not necessary to function the gate insulator as the charge storage region, and since the gate insulator can be separated from the charge storage region and used simply as a gate insulator, a design conforming to the scaling rules of the LSI can be achieved. Therefore, there is no need to insert a floating gate between the channel and the control gate as in a flash memory, and there is no need to use an ONO film having a memory function as the gate insulator, and a gate insulator according to microfabrication can be used. At the same time, the influence of the electric field of the gate electrode on the channel is increased, and a semiconductor memory device having a memory function that is not affected by the short channel effect can be realized. Therefore, the degree of integration can be improved by micromachining and an inexpensive semiconductor device can be provided.

In addition, when charge is held in the charge storage region, the drain current value changes because part of the channel forming region is strongly influenced by the charge. Thus, a semiconductor memory device that distinguishes the presence or absence of electric charges is formed.

In addition, since each charge storage region is in contact with the semiconductor substrate and the gate electrode through the insulating film, leakage of sustaining charge can be suppressed by the insulating film. Thus, a semiconductor memory device having good charge holding characteristics and high reliability for a long time is formed.

Further, according to the method of forming a semiconductor memory device, etching, or etching and oxidizing the first insulator 32a having a thinner film thickness T1 on the semiconductor substrate as compared with the film thickness T2 at the sidewall portion of the gate electrode. It can be formed by a simple step without using any complicated steps such as.

(Third Embodiment)

A third embodiment of the present invention will be described with reference to FIGS. 3A and 3B. This embodiment uses a step different from that of the second embodiment with respect to a method of forming the first insulator 32a having a different film thickness. Therefore, in other steps, the semiconductor memory device can be formed using the steps described in the second embodiment. The third embodiment will be described in detail with respect to the differences from the second embodiment.

First, as shown in FIG. 3A, the gate electrode 3, that is, the gate stack 8, is formed on the semiconductor substrate 1 through the gate insulator 2. Thereafter, an initial insulating film 34 having a substantially uniform thickness is formed so as to cover the surface of the semiconductor substrate 1 and the gate stack 8. The method of forming each component is as follows.

The method of forming the gate electrode 3, that is, the gate stack 8 on the semiconductor substrate 1 through the gate insulator 2 may be the same formation method as in FIG. 2A of the second embodiment. However, in the present embodiment, even if no impurity is contained in the gate electrode 3, the same effect as in the case where it is contained can be obtained, so that the method becomes simpler.

The method of forming the initial insulating film 34 on the exposed surfaces of the semiconductor substrate 1 and the gate stack 8 may be an oxide film forming method using a conventional thermal oxidation method. Here, when the so-called oxynitride film in which the oxide film is doped with nitrogen is used as the insulating film 34, the effect of suppressing leakage in the film is improved. In addition, due to the use of the heat treatment, the interface characteristics with the semiconductor substrate are improved as compared with the film using the CVD (chemical vapor deposition) method or the like. Therefore, the driving current becomes larger.

Alternatively, a substantially uniform oxide film or nitride film may be formed using the CVD method. In this connection, the initial insulating film 34 finally becomes an insulating film of the thickness in the first insulating film formed on each sidewall portion of the gate electrode 3, and it is necessary to suppress leakage of stored charge. Therefore, when the same formation method as that of the gate insulator in the second embodiment is used, the leakage suppression effect is improved. Here, for example, when the N ₂ O film is formed as the initial insulating film 34, the film thickness is preferably substantially uniform within the range of 1 to 20 nm. The film thickness of other materials may be adjusted so that the equivalent oxide film thickness is about 1 to 20 nm.

Next, as shown in FIG. 3B, a film that becomes the first insulator 32a on the exposed surfaces of the semiconductor substrate 1 and the gate stack 8, that is, the film at each sidewall portion of the gate electrode 3. An insulating film in which the film thickness T1 on the semiconductor substrate 1 is formed thinner than the thickness T2 is formed. The insulating film is formed as follows.

The initial insulating film 34 is etched using the anisotropic etching method, so that the film thickness at the sidewall portion of the gate stack 8 becomes substantially equal to or thinner than the thickness of the initial insulating film 34, and is formed on the semiconductor substrate 1. The initial insulating film is processed so that the film thickness becomes thinner or completely removed than the thickness of the initial insulating film 34. Therefore, the first insulating film 32a is formed in which the film thickness T1 on the semiconductor substrate 1 is thinner than the film thickness T2 at the sidewall portion of the gate electrode 3. In this regard, the step of forming the insulating film again may be added thereto. Therefore, the semiconductor substrate 1 can reduce damage caused by the etching and can form the first insulator 32a which can reduce leakage. In that case, the additional step of forming the insulating film may be performed using the same method as the method of forming the gate insulator described in the second embodiment.

As described above, the structure shown in FIG. 3B was formed. The structure is identical in appearance to that of Fig. 2B of the second embodiment, and subsequent steps can also be formed by using the steps shown in the second embodiment as in the second embodiment. .

Due to the semiconductor memory device or the manufacturing method thereof, the same advantages as in the second embodiment can be obtained. However, other advantages are obtained in the method of forming the first insulating film. More specifically, according to the third embodiment, it is not necessary to contain any impurities in the gate electrode in advance, and it is a simpler step in that respect. In addition, a double-gate CMOS step that is frequently used in a conventional CMOS forming process, that is, a step of implanting impurities into the gate electrode at the same time as the impurity implantation step for forming the source / drain diffusion region, can be used. Since the forming step can be applied, a highly reliable semiconductor memory device is formed. In addition, a semiconductor memory device in which coexistence with a CMOS device is easy is formed.

(Example 4)

A fourth embodiment of the present invention will be described with reference to Figs. 4A to 4D. The present embodiment has a novel structure that can obtain a new advantage in solving the problems caused by the asperities with respect to the structure and the formation method of the insulating film formed in the sidewall portion of the gate electrode of the semiconductor memory device described in each of the above embodiments, and The formation method is demonstrated. FIG. 4A shows a semiconductor memory element formed by the formation method described in the second embodiment and in which the first insulator 32a is formed by heat treatment. 4B shows an enlarged schematic diagram of the area indicated by the dotted circle in FIG. 4A. It is seen from FIG. 4B that the aperture 40 is formed on the side surface of the gate electrode 3. &Quot; Asperity " occurs on the polysilicon surface as shown in FIG. 4B, for example, when the gate electrode 3 is made of polysilicon and the anti-dissipative dielectric or first insulator is formed by a thermal oxidation step. . More specifically, "aperity" refers to poly because of variations in the ease of oxidation on the surface of polysilicon and deviations that occur due to reasons such as a hardening of the particulate boundaries of polysilicon during thermal oxidation of polysilicon. It is considered ruggedness that appears on the silico surface.

In FIG. 4A, the asperity is not omitted. Although the aperity is not shown in the drawings other than FIG. 4, this does not indicate that the aperity is not formed, and omits the as shown in FIG. 4A. In the case where the appearance appears due to the above reason, it should be considered that the appearance is formed whether or not shown.

In the case where the appearance appears due to the formation method of the second embodiment, the injection of charge from the gate electrode 3 into the charge holding portion 31 becomes easier than when the appearance does not appear. Therefore, erasing failure is likely to occur in the erasing mode of the semiconductor memory device. More specifically, the situation in which the potential is applied in the erase mode applies a negative potential to the gate electrode 3 and a positive potential to the source / drain diffusion region 13 so that the electrons held in the charge holding part 31 are maintained. Is discharged to the source / drain diffusion region 13 side, the electrons are discharged from the charge holding portion 31 and at the same time, leakage of electrons injected from the gate electrode 3 into the charge holding portion 31 is likely to occur. Lose. Therefore, the erasing efficiency deteriorates and the erasing failure tends to occur.

On the other hand, if the structure as shown in Fig. 4C or 4D is formed, the above problem of erasing of the defective erase easily can be solved. Hereinafter, the structure will be described in detail.

In the structure of FIG. 4C, a deposition insulator 41 is formed on each side of the gate electrode 3, and a third insulator 42 is formed on the surface of the semiconductor substrate 1 outside the deposition insulator 41. The charge holding part 31 and the second insulator 32b are formed on the surfaces of the optimum insulator 41 and the third insulator 42. Therefore, the insulator in the portion in contact with the gate electrode 3 is a deposition insulator 41 based on CVD and an insulator formation method using heat treatment, unlike the first insulator 32a shown in Fig. 4B. Therefore, the insulator 41 of FIG. 4C is free from the arising resulting from the formation of the insulator by the heat treatment shown in FIG. 4B. Therefore, leakage caused by the earthiness can be suppressed, and erase failure can be suppressed. However, since the third insulator 42 is formed by heat treatment, some aperity appears, but it is possible to suppress the occurrence of a much more than the case shown in Fig. 4B. Therefore, erasure failure can be suppressed.

The structure of FIG. 4D includes, on each side of the gate electrode 3, the insulator 41 formed in FIG. 4C, but between the insulator 41 and the gate electrode 3 and between the insulator 41 and the semiconductor substrate. It differs especially from the structure of FIG. 4C in that it is the thermal insulator 43 in which the insulator based on heat processing is formed between (1). Here, the structure of FIG. 4D is that the thermal insulator 43 suppresses the reduction of the driving current due to the phenomenon that the mobility of the channel is degraded due to the deterioration of the interface property between the semiconductor substrate 1 and the deposition insulator 41. It is more advantageous than the structure of Fig. 4c. In order to reduce the influence of the earthiness, the film thickness of the thermal insulator 43 must be made thin. In the case of forming a thermal oxide film as the thermal insulator 43, the thickness thereof is preferably about 1 nm to 20 nm, particularly preferably about 10 nm. Therefore, since the shape of the interface between the thermal insulator 43 and the semiconductor substrate 1 is good and the mobility deterioration of the current flowing through the interface can be suppressed, a larger driving current is obtained and the reading speed is further improved. A semiconductor memory device may be provided. In particular, since the thickness of the thermal oxide film is 1 nm or more, the interface characteristics can be sufficiently improved, and if it is 10 nm or less, the occurrence of deterioration due to the earthiness can be suppressed.

Next, a method of forming the structure of FIG. 4C will be described. Part of the process uses the same manufacturing method as part of the manufacturing method described in the second embodiment.

First, using the same method as the second embodiment, a gate stack 8 composed of a gate insulator 2 and a gate electrode 3 is formed on the semiconductor substrate 1 as shown in FIG. 2A.

Subsequently, the insulating film is formed to be substantially uniform using the CVD method. The thickness of the insulating film may be substantially the same as that of the first insulator 32a of the second embodiment in terms of oxide film. In addition, anisotropic etching is performed until the semiconductor substrate 1 is exposed to form the deposition insulator 41 on the gate sidewall. As the material of the insulating film, an insulating film such as an oxide film or an oxynitride film generally used for the sidewall of the gate electrode 3 can be used.

Next, a thermal oxide film is formed to form the third insulator 42. At this time, since the deposition insulator 41 is already formed on the side of the gate electrode 3, the thermal oxide film is not formed as thick on the gate side as the exposed surface of the semiconductor substrate. Therefore, in the figure, the thermal oxide film is shown as being formed on the semiconductor substrate 1 portion outside the deposition insulator 41, but is omitted on the gate side surface. In addition, since the thermal oxidation step is used as the step of forming the insulator, the gate electrode 3 is thermally oxidized as the thickness of the insulating film on the side of the gate increases. However, since the thickness of thermal oxidation is much thinner than the thickness of the first insulator 32a of the second embodiment, the formation of the aurity is significantly suppressed. Here, the film thickness of the third insulator 42 may be substantially the same as the film thickness of the first insulator 32a, and the formation method may be any of CVD or heat treatment. In this regard, when the insulating film is formed by heat treatment, since the interface characteristics between the semiconductor substrate 1 and the insulating film are good, the mobility is improved and the driving current is increased.

Next, the method of forming the structure of FIG. 4D is the same as the method of forming the structure of FIG. 4C, except that the thermal insulator 43 is formed before the deposition insulator 41 is formed. Therefore, the thermal insulator 43 may be based on oxidation or oxynitride (oxynitride film) using heat treatment, and in particular, the oxynitride treatment using N ₂ O gas or NO gas is preferable because leakage can also be suppressed. The film thickness of the thermal insulator 43 is preferably about 1 to 20 nm in terms of oxide film, and particularly preferably about 10 nm. Therefore, since the shape of the interface between the thermal insulator 43 and the semiconductor substrate 1 is good, and the mobility deterioration of the current flowing through the interface can be suppressed, a larger driving current is obtained and the reading speed is further improved. A semiconductor memory device may be provided. In particular, since the thickness of the thermal oxide film is 1 nm or more, the occurrence of deterioration due to the earthiness can be suppressed when the thickness is 10 nm or less.

In addition to the above structure and method, a method of suppressing erasure failure by suppressing leakage due to aperity is as follows. The first insulator 32a in the second embodiment is formed of a thermal oxide film using N ₂ O gas or NO gas as the oxidizing gas. Therefore, a nitride film, which is an oxide film containing nitrogen, is formed to suppress the leakage current of the insulating film.

(Example 5)

A fifth embodiment of the present invention will be described with reference to FIG. This embodiment uses substantially the same steps as the second embodiment. In particular, there are two differences. First, in the step of forming the charge storage region 33, each charge storage region can be made higher than in the second embodiment. Second, in order to form the L-shaped first insulator 32a in the etching of the first insulator 32a, the first insulator 32a is exposed until the semiconductor substrate 1 or the gate electrode 3 is exposed. The etching step has been eliminated. In view of the above, by performing the steps described in the second embodiment, the structure shown in FIG. 5 is formed.

As shown in FIG. 5, the uppermost position of each charge storage region 33 may be made the same as or lower than the uppermost position of the first insulator 32a.

In addition, the forming of the first insulator 32a may be the method shown in the third or fourth embodiment. In that case, of course, the advantage described in the said Example can be acquired.

In addition, the first insulator 32a is etched by a subsequent contact step for the gate electrode 3 and the source / drain diffusion region to be connected to the wiring. Here, in order to easily etch the first insulator 32a, a material having the same composition as that used as the interlayer insulating film may be used. For example, since an oxide film is often used as the interlayer insulating film, an oxide film may be used as the material of the first insulator 32a. The contact etching may be performed under conditions in which the oxide film is etched and the selectivity of the oxide film to the silicon of the substrate and the polysilicon of the gate electrode 3 is high. Further, even when the first insulating film is made of, for example, a silicon nitride film, the semiconductor substrate 1, which functions as an etching stopper in the contact etching step and is formed of the source / drain diffusion region 13, is irrelevantly etched. By being avoided, a short circuit between the source / drain diffusion region 13 and the semiconductor substrate 1 is effectively prevented.

In addition, since the first insulator 32a can be used as an implantation protection film during impurity implantation of the source / drain diffusion region 13, it is unnecessary to form the implantation protection film.

In addition, even when the contact with the source / drain diffusion region 13 is partially disposed on the gate electrode 3 due to misregistration, the source / drain region may differ due to the difference in the film thickness of the first insulator 32a. Insulation between 13 and the gate electrode 3 can be maintained. More specifically, the insulating film on the gate electrode 3 is formed thicker than the insulating film on the source / drain diffusion region 13. Therefore, although contact holes are formed on the source / drain diffusion region 13 but not formed on the gate electrode 3, insulation can be maintained. Therefore, the tolerance at the time of design can be made small, and micromachining and high integration are attained.

(Example 6)

A sixth embodiment of the present invention will be described with reference to FIGS. 6A and 6B. The structure shown in Fig. 6A of this embodiment can be formed using substantially the same steps as in the second embodiment. Also, the structure shown in Fig. 6B can be formed using substantially the same steps as in the second embodiment.

In particular, the differences are as follows. The thickness TG of the gate oxide film 2 is the thickness T1 of the portion of the first insulator 32a in contact with the semiconductor substrate 1 and the thickness T2 of the portion of the first insulator 32a in contact with the gate electrode 3. It is made thicker in terms of equivalent oxide film thickness than the sum of. In addition, impurity implantation of the source / drain diffusion region 13 is performed after the formation of the gate electrode 3.

By the above steps, the semiconductor memory device of this embodiment can be driven by the following tunneling operation method.

In addition, the forming of the first insulator 32a may be the method shown in the third or fourth embodiment. In that case, of course, the advantage described in the said Example can be acquired.

However, if the method of forming the first insulator 32a described in the second embodiment is used in this step, for the same reason as described in the second embodiment, the first insulator 32a shown in Fig. 6A, or Fig. The first insulator 32a shown in 6b does not require any special steps such as etching and can make a difference in film thickness by a simple step. Therefore, since the semiconductor memory device can be manufactured in a relatively small number of manufacturing steps, a lower cost semiconductor memory device can be provided.

In addition, the film thickness T1 of the portion of the first insulator 32a in contact with the semiconductor substrate 1 and the film thickness T2 of the portion of the first insulator 32a in contact with the gate electrode 3 may be different. This may be thicker. Here, the driving method in the case where the thickness T1 is thinner than the thickness T2 will be described, but in the opposite case, it is applied to the gate electrode 3 and the source / drain diffusion region 13 to inject / remove the charge from the thinner side. The condition of the voltage can also be reversed. By doing so, the following advantages are shown. When the thickness of the insulating film in the portion in contact with the semiconductor substrate 1 is made thinner than the thickness of the insulating film in the portion in contact with the gate electrode 3, the charge injected from the semiconductor substrate 1 may cause the first insulator 32a to become thin. Since passing through the gate electrode 3 can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided. On the contrary, when the thickness of the insulating film in the portion in contact with the semiconductor substrate 1 is made thicker than the thickness of the insulating film in the portion in contact with the gate electrode 3, the charge injected from the gate electrode 3 is the first insulator 32a. Since it can be suppressed to pass through the semiconductor substrate to the semiconductor substrate, a semiconductor device having a good charge injection efficiency and a high writing / erasing speed can be provided.

In addition, since the source / drain diffusion region 13 may be partially disposed under the gate electrode 3, the step of forming the offset region is not necessary and a semiconductor memory device may be provided. In addition, since the structure is the same as that of a conventional field effect transistor, it is possible to use a conventional field effect transistor process that has been accomplished so far, and a semiconductor memory device having a low manufacturing cost can be provided. In addition, when the source / drain diffusion region 13 is formed to be offset from the gate electrode 3, the same advantages as described in the second embodiment can be obtained.

The semiconductor memory device having the above structure uses a write / erase condition different from those described in the first to fifth embodiments. That is, tunneling in which writing / erasing is performed so that electric charge tunnels through a thin portion of the first insulating film 32a in contact with the semiconductor substrate 1 by the potential difference between the source / drain diffusion region 13 and the gate electrode 3. Drive method is used. An example of the writing / erasing / reading method of the semiconductor memory element having the above structure will be described below.

First, the recording operation will be described. A potential of 10 volts and 0 volts is applied to the gate electrode 3 and the source / drain diffusion region 13, respectively. The potential of the gate electrode 3 relative to the source / drain diffusion region 13 is then raised to 10 volts. The potential of the charge storage region 33 increases to the level required for tunnel current generation due to capacitive coupling with the gate electrode 3. More specifically, for example, when the potential of the gate electrode 3 is raised to 0 to 10 volts at the rise time of about 1 to 2 nanoseconds, the potential of the charge storage region 33 becomes " overshoot. Is temporarily raised to about 15 volts. As a result, the electrons of the source / drain diffusion region 13 tunnel through the thin portions of the first insulator 32a in contact with the semiconductor substrate 1, respectively, and the charge storage region 33 located on both sides of the gate electrode 3. Inject into). Even after the electrons are injected into the charge storage region 33, even if the potential of the gate electrode 3 is lowered below 10 volts, each of the charge storage regions 33 is surrounded by an insulating film. Is maintained at 33.

According to the above recording method, since the potentials of one source / drain diffusion region 13 and the other source / drain diffusion region 13 are the same, no drain current flows. Thus, a semiconductor memory device having low power consumption is provided. In addition, since no hot carrier is generated and no charge is injected into the gate insulator 2, variations in the threshold voltage generated by the injection of charge into the gate insulator 2 can be suppressed, and highly reliable semiconductor memory cells. Is provided

Among the plurality of memory cells, a potential of 10 volts is selectively applied to the gate electrode 3 of any particular memory cell, and a potential of 0 volts is applied to the gate electrode 3 of the unselected memory cells. Then, electrons may be stored only in the charge storage region 33 of the selected memory cell.

Next, the read operation will be described. 5 volts, 0 volts, and 1 to the gate electrode, one source / drain diffusion region 13 (assuming a source region for convenience), and the other source / drain diffusion region 13 (assuming a drain region for convenience). Apply the potential of the bolts respectively. In this embodiment, since the threshold voltage of the semiconductor memory element is set to a value lower than 5 volts (for example, 1 volt), a conduction channel is formed between the source region and the drain region. As a result, electrons move from the source region into the drain region, and a drain current of a predetermined size is obtained.

In the present embodiment, since the charge storage region 33 is located outside the channel formation region 19, the threshold voltage and charge storage region of the semiconductor memory element when the charge storage region 33 does not store electrons ( 33) The threshold voltage when storing these electrons is substantially the same. Therefore, in both cases, since the same conduction channel is formed between the source region and the drain region, and electrons move from the source region into the drain region, a drain current is obtained. However, when the charge storage region 33 stores electrons, the presence of the storage electrons increases the diffusion layer resistance (parasitic resistance) of the source / drain diffusion region 13. As a result, the drain current when the charge storage region 33 stores electrons is lower than the drain current when the charge storage region 33 does not store electrons.

As described above, in the sidewall storage type nonvolatile memory cell according to the present invention, one bit of information is not stored according to the magnitude of the threshold voltage of the semiconductor memory device. In the present invention, one bit of information is stored according to the magnitude of the parasitic resistance of the source / drain diffusion region 13 located directly below each memory functional body. When the charge storage region stores a large number of electrons, the electrons of the source / drain diffusion region 13 decrease near the charge storage region 33 under the influence of the electric field formed by the electrons, and increase the resistance of the region. Is considered. Since the magnitude of the drain current changes depending on the magnitude of the parasitic resistance of the source / drain diffusion region, data can be identified by the magnitude of the drain current.

In order to perform data readout practically, the drain current in the state in which data is written needs to have a magnitude of 80% or less of the drain current in the state in which data is not written. In addition, in order to perform data reading without any error, it is preferable that the drain current in the state where data is recorded has a magnitude of 70% or less of the drain current in the state where data is not recorded.

In order to increase the change of the drain current in accordance with the accumulation / accumulation of charge in the charge storage region 33, for example, the first insulator 32a which increases the width of the charge storage region 33 and contacts the semiconductor substrate 1. It is recommended to make the film thickness (T1) of the () part thin.

Next, the erase operation will be described. A potential of -10 volts and 0 volts is applied to the gate electrode 3 and the source / drain diffusion region 13, respectively. Then, the potential of the charge storage region 33 is lowered to a sufficiently low level due to the capacitive coupling with the gate electrode 3. As a result, electrons stored in the charge storage region 33 move (discharge) from the charge storage region 33 into the source / drain diffusion region 13.

According to the erasing method, since the potentials of one source / drain diffusion region 13 and the other source / drain diffusion region 13 are the same, no drain current flows. Therefore, a semiconductor memory device having low power consumption is provided. In addition, since no hot carrier is generated and no charge is injected into the gate insulator 2, variations in the threshold voltage caused by the injection of a contact into the gate electrode film 2 can be suppressed, and a highly reliable semiconductor memory. An element is provided.

As described above, according to the semiconductor memory device of the present embodiment, a semiconductor memory device having low power consumption and high reliability is provided. Since the semiconductor memory device can be manufactured by fewer manufacturing steps than in the case of forming the semiconductor memory device using an etching process or the like, a low cost semiconductor memory device can be provided.

(Example 7)

A seventy-eighth embodiment of the present invention will be described with reference to Figs. 7A to 7D. Each structure shown in Figs. 7A to 7D of this embodiment can be formed using substantially the same steps as the second embodiment, and has the same effect. In addition, the structures shown in Figs. 7A to 7D can be formed using substantially the same steps as those shown in Figs. 6A to 6B of the sixth embodiment, respectively, and have the same effect.

In addition, the forming of the first insulator 32a may be the method shown in the third or fourth embodiment. In that case, of course, the effect described in the said Example can be acquired.

In particular, the difference is that after the impurity ion implantation for forming the source / drain diffusion region 13, the charge storage region 33 is further etched to further limit the range on which the charge can be retained on the semiconductor substrate side.

That is, the charge storage region 13 is further etched to make the charge storage region 33 very small as shown in FIG. More preferably, in FIG. 7A or 7B, since the charge storage region 33 may be above the offset region 20, the charge storage region (depending on the lateral diffusion width of the source / drain diffusion region 13) The size of the structure can be reduced by etching 33) laterally.

As mentioned above, since the electrons injected by recording are limited in the vicinity of the channel, it is easy to remove the electrons by erasing, and the erasure can be prevented. In addition, since the volume of each charge storage region capable of holding charge without changing the amount of injected charge is reduced, the amount of charge per unit volume can be increased, so that electrons can be efficiently recorded / erased and recorded / A semiconductor memory device having a high erase speed is formed.

(Example 8)

29A shows a plan view of a memory unit 200 which is an embodiment of a semiconductor device of the present invention.

In the memory unit 200, a memory cell array 201 including a semiconductor memory element and a peripheral circuit 202 including a semiconductor switching element are disposed on the same semiconductor substrate 1. The memory cell array 201 allows semiconductor memory devices, which will be described later, to be arranged in the shape of an array. Peripheral circuits 202 include decoders 203 and 206, write / erase circuits 209, readout circuits 208, analog circuits 206, control circuits 205, various I / O circuits 204, and the like. It is formed of peripheral circuits each of which can be composed of conventional MOSFETs (field effect transistors).

In addition, as shown in FIG. 29B, in order to be able to configure the memory device 300 of an information processing system such as a personal computer or a mobile phone as a single chip, in addition to the memory unit 200, an MPU (micro processing unit) 301, a cache SRAM (static RAM) 302, a logic circuit 303, an analog circuit (not shown), and the like, must be disposed on the same semiconductor substrate 1.

Until now, in order to coexist with the memory cell array 201, the peripheral circuit 202, etc., the manufacturing cost has greatly increased compared with the case of forming a standard CMOS. In this regard, as can be seen from the following description, an increase in manufacturing cost can be suppressed by the present invention.

As can be seen from the procedure of the step described in the second embodiment, the procedure of the step of forming the semiconductor memory device of the present invention has a high affinity with a known general MOSFET forming process. As can be seen from Fig. 2, the configuration of the memory element is close to a known general MOSFET. In order to change the said general MOSFET into a memory element, it is sufficient, for example, to use the side wall spacer of a general MOSFET as a memory functional body, and not to form an LDD area | region. Even when the sidewall spacers of the general MOSFETs constituting the memory peripheral circuit section, the logic circuit section, the SRAM section, etc., have the function of a memory functional body, as long as the MOSFET operates within a voltage range in which the sidewall spacer width is appropriate and rewriting operation does not occur, Transistor performance is not degraded. Thus, typical MOSFETs and memory devices may use common sidewall spacers. In addition, coexistence of a general MOSFET and a memory element constituting the memory peripheral circuit portion, the logic circuit portion, the SRAM portion, and the like can be achieved by further forming an LDD structure only in the memory peripheral circuit portion, the logic circuit portion, and the SRAM portion. In order to form the LDD structure, impurity implantation for forming the LDD region may be performed after the formation of the gate electrode and before the deposition of the material constituting the charge storage region. Therefore, in the case of performing impurity implantation for LDD formation, only the memory region is masked with photoresist to easily coexist memory elements with MOSFETs of ordinary structures constituting the memory peripheral circuit portion, logic circuit portion, SRAM portion, and the like. Can be. In addition, when the SRAM is composed of a memory element and a MOSFET having a conventional structure constituting the memory peripheral circuit portion, the logic hero portion, and the SRAM portion, the semiconductor memory device, the logic circuit, and the SRAM can easily coexist.

On the other hand, when the voltage to be applied to the memory element is higher than the allowable voltage in the logic circuit section, SRAM section, or the like, the high withstand voltage well formation mask and the high withstand voltage gate insulator formation mask may be added only to the standard MOSFET formation mask. Conventionally, the process for coexisting EEPROM (electrically erasable and programmable ROM) and logic circuitry on a single chip is significantly different from standard MOSFET processes, and the number of required masks and the number of process steps have increased significantly. Therefore, the number of masks and the number of process steps can be greatly reduced as compared with the prior art in which EEPROMs, circuits such as memory peripheral circuits, logic circuits, and SRAM sections exist. Therefore, the cost of a chip in which a general MOSFET such as a memory peripheral circuit portion, a logic circuit portion, and an SRAM portion and a semiconductor memory device coexist can be reduced. In addition, since a high supply voltage can be supplied to the memory element, the write / erase speed is remarkably improved. In addition, since a low supply voltage is supplied to the logic circuit section, the SRAM section, and the like, deterioration of transistor characteristics due to damage of the gate insulator or the like can be suppressed, and power consumption can be further reduced. Therefore, a semiconductor device having a highly reliable logic circuit portion that can easily coexist on the same substrate and a memory element having a very high write / erase speed can be realized.

An eighth embodiment of the present invention will be described in detail with reference to Figs. 8A to 9E.

In the present embodiment, it is shown that the general MOSFET and the semiconductor memory device in the peripheral circuit and the like can be easily formed on the same substrate at the same time without requiring any complicated process. More specifically, by adding a photolithography process to the step of forming the semiconductor memory device described in the second embodiment, a region in which an LDD diffusion region is formed and a region in which it is not formed are separated, so that a general MOSFET and a semiconductor memory element are the same. Indicates that it can be produced automatically on the substrate.

Hereinafter, the manufacturing steps will be described in order together with the drawings.

The left and right sides of each figure represent a separate device, the left side showing a general MOSFET of the peripheral circuit region 4 and the right side showing a memory element of the memory region 5.

The process before forming the LDD region may use the same steps as in the second embodiment. That is, as shown in FIG. 8A, the structure shown in FIG. 2A is formed in each peripheral region 4 and memory region 5, respectively.

Next, as shown in FIG. 8B, the LDD region 6 is formed only in the peripheral circuit region 4. At this time, the photoresist 7 is formed in the memory region 5, but not in the LDD region. Here, without forming the LDD region 6 in the memory region 5, the LDD region was successfully formed in the peripheral circuit region 4 which forms a general transistor having a normal structure. The photoresist may be an insulating film such as, for example, a nitride film, which serves to prevent the injection and can be selectively removed. This step is only a special step different from that of the second embodiment, after which the same steps as the second embodiment are used.

Next, as shown in FIG. 8C, the first insulator 32a is formed using the same steps as in FIG. 2B of the second embodiment.

In addition, as shown in FIG. 9D, the charge storage region 33 is formed using the same steps as in FIG. 2C of the second embodiment.

In addition, as shown in Fig. 9E, the source / drain diffusion region is formed using the same steps as in Fig. 2D of the second embodiment.

Due to the foregoing, any complicated process can be performed by adding the photolithography step to the step of forming the semiconductor memory device described in the second embodiment, and separating the region where the LDD diffusion region 6 is formed from the region not formed. It was possible to automatically manufacture common MOSFETs and semiconductor memory devices on the same substrate without the need.

27A to 27D, the manufacturing steps of the semiconductor device of this embodiment different from the semiconductor device will be described in detail as follows. The semiconductor device of this manufacturing process is shown by way of example in Figs. 11A to 11D.

In this embodiment, it is shown that individual devices of semiconductor switching elements such as logic circuits and semiconductor reservoirs can all be simply formed simultaneously on the same substrate without any complicated process. More specifically, by adding a photolithography step to the formation process of forming a semiconductor storage device according to the eleventh embodiment, a semiconductor switching element and a semiconductor reservoir are simultaneously manufactured on one substrate, where one LDD diffusion region is formed. And other areas that do not.

Hereinafter, the manufacturing process will be described with reference to FIGS. 27A to 27D. 27A to 27D, the left side corresponds to the semiconductor switching element of the logic circuit region 4 and the right side corresponds to the semiconductor reservoir of the memory region 5.

The same steps as in the eleventh embodiment may be used up to the step of forming the first dielectric film 9. That is, as shown in FIG. 27A, the structure described in FIG. 12C is formed for both the logic circuit region 4 and the memory region 5.

Next, as shown in FIG. 27B, the photoresist 7 serving as an implantation mask is covered in the memory region 5, and impurities are implanted to form an LDD region only in the logic circuit region 4. In this case, the photoresist 7 is formed in the memory region 5, and the LDD region is not formed. In this step, since the LDD region can be reliably formed to extend below the gate electrode and overlap together, it is preferable to perform impurity implantation at an implantation angle larger than the implantation angle with respect to the extended portion described in Fig. 14A. Also, by this step, the LDD region is formed in the logic circuit portion 4 where the general semiconductor switching element is to be formed, and the LDD region 6 is not formed in the memory region 5. This photoresist is intended to prevent implantation and can be selectively removed and be a dielectric film such as silicon nitride. This step is only a special step different from the eleventh embodiment, and subsequent steps may be the same as the eleventh embodiment.

That is, as shown in Fig. 27C, silicon nitride 17 is formed using the same steps as shown in Fig. 12D of the eleventh embodiment. Alternatively, the formation in this step may be made before the implantation step for forming the LDD region or in the sidewall formation step after performing the separation step.

Further, as shown in Fig. 27D, the memory functional body 11 is formed using the same steps as shown in Fig. 13 of the eleventh embodiment. Further, the source / drain diffusion region 13 is formed using the same step.

As a result of this step, a photolithography step is added to the step for formation of the semiconductor storage device according to the eleventh embodiment, so that the area is different from the area 4 in which the LDD diffusion region is formed and the other area 5 in the other case. Divided. Thus, the semiconductor switching element and the semiconductor reservoir can be manufactured simultaneously on the same substrate simply without requiring any complicated process.

When charge is maintained in the memory functional body, the channel formation region portion is strongly influenced by the charge, and the drain current value changes. Therefore, a semiconductor reservoir for distinguishing the presence or absence of electric charge is formed in accordance with the change of the drain current value.

By disposing the gate stack 8 and the memory functional element 11 separately from each other, the semiconductor switching device on one chip does not include any many process changes or man-hour increases compared to standard MOSFET processes. And the semiconductor reservoir can be mounted in combination.

Semiconductor switching elements in which the gate electrode terminal and the source / drain regions are offset and the semiconductor switching elements of the logic circuit region in which the gate electrode terminal and the source / drain regions are not offset are placed on the same substrate by a self-aligned process. By forming the semiconductor switching element and the logic circuit region having a large memory effect, the semiconductor switching element having a high current driving power can be mounted in a complex manner without any complicated process.

Further, according to the present semiconductor reservoir, since 2-bit storage per transistor can be realized, the semiconductor reservoir occupied area per bit can be reduced to form a large capacity semiconductor reservoir.

(Example 9)

A ninth embodiment of the present invention will be described with reference to Figs. 10A to 10I.

This embodiment shows the configuration of each charge storage region 33 in all the above embodiments. In addition to the effect of the said Example, it has the following effects.

In the charge storage region illustrated in FIG. 10A, one layer of silicon dots is included in the second insulator 32b.

As the fabrication method, the silicon dot 10 is formed after the formation of the first insulator 32a, the deposition insulating film is formed, and the residue removal step is carried out through an etching-back step. To prepare. The detail of each step is demonstrated below.

The method of forming the silicon dot 10 is as follows. By using CVD, disilane is used as a raw material gas, and the silicon dots 10 are grown for 2 minutes under a pressure of 1 Torr and a substrate temperature of 700 ° C. Each silicon dope is about 5 nm in size. In this regard, the size of each silicon dot at this time is preferably about 1 to 15 nm, which is a size for expressing quantum effects such as coulomb shielding. Here, the silicon dots 10 can be formed by optimizing the size, density, etc. by appropriately changing and adjusting respective conditions such as source gas, pressure, substrate temperature, growth time, and the like in CVD.

In addition, considering that the dot diameter becomes small due to the oxidation of the next step, the silicon dot 10 can be formed to a suitable large size in advance, so that the silicon dot 10 having an optimal shape can be formed.

In addition, although not shown, it is preferable to oxidize the surface of the formed silicon dot 10. The step of oxidation may be thermal oxidation. In this case, since the rate of oxidation is delayed as the size of each silicon dot decreases, the variation in the size of the silicon dot 10 is suppressed. In addition, since the oxide film on the surface of the silicon dot acts as an insulating film through which electrons pass, it may be a film having high withstand voltage, low leakage current, and high reliability. For example, the oxide film may be an N ₂ O oxide film or an NO oxide film. In the case of the oxide film, the thickness of the film in its final shape is preferably about 1 to 20 nm in thickness of the equivalent oxide film including the first insulator 32a. More specifically, when the size of each silicon dot is 1 to 15 nm, the film thickness is preferably about 1 to 10 nm. In this way, when the silicon dot 10 is oxidized to a smaller size, it is needless to say that the silicon dot 10 needs to be formed to some extent in advance in consideration of the reduction ratio of the size during the formation of each silicon dot. In addition, when the insulating film is formed thin enough to flow through the tunnel current, and the charge is maintained by the Coulomb shielding effect based on the double tunnel junction, the voltage required for injecting / erasing the charge can be lowered, thereby reducing power consumption. Can be reduced. Typical oxide film thickness in that case may be about 1 to 3 nm. In addition, as shown in the figure, the silicon dots 10 may be deposited unevenly without having a uniform height.

Next, as a method of forming a deposition insulating layer using the CVD method, a film having a good step coverage using high temperature oxide (HTO) or low-pressure chemical vapor deposition (LPCVD) may be used. In the case of using an HTO film, the thickness may be about 20 to 100 nm. In addition, the deposition insulating film 15 is etched back in the shape of sidewall spacers in a later step, and functions as an injection mask in the case of impurity implantation forming a source / drain diffusion region. That is, it becomes an important factor for defining the shape of each source / drain diffusion region, in particular, the offset width with respect to the gate electrode end. therefore,

An optimum offset width can be obtained so as to appropriately adjust and change the thickness of the deposition insulating film so as to form each source / drain diffusion region in an optimal shape.

Next, by anisotropically etching the deposition insulating film and the silicon dot 10, a charge storage region in the shape of sidewall spacers and including the silicon dot 10 is formed on the sidewall of the gate stack 8. At this time, by selecting another material as the material of the first insulator 32a and the optimum insulating film, the selectivity between these films can be improved, and the step can be easily performed efficiently. For example, a nitride film can be used as the material of the first insulator 32a and an oxide film can be used as the material of the deposition insulating film.

However, since a silicon substrate is generally used as the semiconductor substrate 1 and silicon is used as the material of the dot in that case, the silicon dots cannot be etched and etching residues are generated. In this case, after the anisotropic etching, the silicon residue may be removed to anisotropically etch the remaining insulating film by wet etching with hydrofluoric acid or the like. In addition, when the residue remains, oxidation may be carried out so that the surface or the whole of the residue is oxidized, and the residue may be removed by wet etching with hydrofluoric acid or the like.

By employing a structure in which charges can be held by silicon dots in this manner, even when leakage of an insulating film deteriorating the memory retention characteristics occurs, all of the held charges are not leaked to the silicon dots near the leakage portion of the insulating film. Only the held charges leak. Therefore, a semiconductor memory device having good retention characteristics is provided.

In addition, due to the oxidation of the surface of the silicon dot, the variation in the size of the silicon dot can be suppressed, and a semiconductor memory device having less variation in electrical characteristics is provided.

Next, the charge storage region illustrated in FIG. 10B has a structure in which two layers of silicon dots 10 are included in the second insulator 32b. In the manufacturing method, after the formation of the first insulator 32a, the silicon dots 10 are formed by the method shown in FIG. 10A to oxidize the surface of the silicon dots 10. Thereafter, the silicon dot 10 is further formed by the same method. Subsequently, a deposition insulating film is formed, and a residue removal step is performed through an etching back step. Then, the structure shown is manufactured. Each step may be the method described with reference to FIG. 10A.

With the above structure, since the silicon dots 10 constitute multiple dots or more in the vertical direction, the memory holding performance is greatly improved as compared with the case of dots of a single layer. Further, since the number of silicon dots 10 of the memory functional film is increased than in the case of a single layer dot, the number of sustaining charges is increased. Therefore, since the difference between the threshold voltage at the time of writing and erasing and the difference between the driving current increases, a semiconductor memory device having a large voltage margin and improved reliability can be formed.

Next, the charge storage region illustrated in FIG. 10C has a structure in which three layers of silicon dots 10 are included in the second insulator 32b. As the manufacturing method, after the formation of the first insulator 32a, the silicon dots 10 are formed by the method shown in Fig. 10A to oxidize the surface of the silicon dots 10. Thereafter, the silicon dot 10 is further formed. Subsequently, a deposition insulating film is formed and the residue is removed by an etching back step. Then, the structure shown is manufactured. Each step may be the method described with reference to FIG. 10A.

With the above structure, since the silicon dot 10 constitutes three or more triple dots in the vertical direction, the memory holding performance is greatly improved as compared with the case of a single layer or two layers of dots. Further, since the number of silicon dots 10 of the memory functional film is increased than in the case of a single layer or two layers of dots, the number of sustaining charges is increased. Therefore, since the difference between the threshold voltage and the drive current during writing and erasing increases, a semiconductor memory device having a large voltage margin and improved reliability can be formed.

FIG. 10D shows the charge storage region in the case where the silicon dots 10 are stacked up to the film thickness in which the memory functional film is sufficiently filled. As the manufacturing method, the formation and oxidation steps of the silicon dots 10 may be appropriately repeated several times with respect to the method of FIGS. 10A to 10C. The memory holding performance is greatly improved as compared with the case of single layer, two layer, or three layer dots. Further, since the number of silicon dots 10 of the memory functional film is increased than in the case of a single layer, two layers, or three layers of dots, the number of sustaining charges increases. Therefore, since the difference between the threshold voltage and the drive current during writing and erasing increases, a nonvolatile memory having a large voltage margin and improved reliability can be formed.

FIG. 10E shows a structure in which the deposition insulating film 15 is included in the second insulator 32b in the shape of a very small sidewall near the charge injection portion. As the manufacturing method, after the formation of the first insulator 32a, polysilicon is deposited and etched back by a method having good step coverage such as LPCVD, whereby charge is injected at the corners of the charge storage region as shown in the figure. A deposition insulating film is formed only in the portion. Thereafter, a deposition insulating film is formed and an etching back step is performed. Then, the structure shown is manufactured.

With the above structure, since the electrons injected by recording are limited in the vicinity of the channel, the electrons can be easily removed by erasing and the erasure can be prevented. In addition, since the volume of the charge holding portion that can maintain the charge without changing the amount of the injected charge is reduced, the amount of charge per unit volume can be increased, so that the charge can be efficiently recorded / erased, and the recording / erasing speed is high. A semiconductor memory device is provided. This effect is the same as in the fifth embodiment. However, according to the above structure, since the second insulator 32b further covers the deposition insulating film 15, the contact between the gate electrode and the source / drain diffusion region is prevented from shorting the deposition insulating film 15 and the contact. can do. Here, the interlayer insulating film and the sidewall insulator are made of different materials, for example, an oxide film and a nitride film, respectively. Therefore, since the design contact margin is small, the apparatus is miniaturized. Thus, a low cost semiconductor memory device is provided.

FIG. 10F shows a structure in which the deposition insulating film 15 is included in a narrow sidewall shape near the charge injection portion of the second insulator 32b. The formation method may be the same as that shown in Fig. 10E, or may be formed by adjusting the deposition film thickness and the etching amount of polysilicon. The effect is also the same as in FIG. 10E.

10G shows a structure in which the charge storage region is composed of the second insulator 32b and the L-shaped deposition insulating film 15. As the formation method, after the formation of the first insulator 32a, polysilicon is deposited by a method having good step coverage such as LPCVD, and then a deposition insulating film is formed. After that, the polysilicon and the deposition insulating film are etched. Thus, the structure shown is manufactured. By the above structure, the same effects as in Fig. 10E can be obtained.

In addition, as shown in FIG. 10I, in the semiconductor memory device having the charge storage region having the structure shown in FIG. 10G, the first insulator 32a is made of a silicon oxide film or a silicon oxynitride film, and the deposition insulating film 15 is formed. Is changed to a silicon nitride film, a better semiconductor memory device is obtained by the following points.

Since there are many levels trapping charges, large hysteresis characteristics can be obtained. In addition, since the charge holding time is long and the problem of charge leakage due to the occurrence of leakage paths does not occur, the retention characteristics are good. In addition, since the material is very commonly used in the LSI process, the manufacturing cost is low.

The method for forming each film may follow the forming method described in the second embodiment or the present embodiment. However, the silicon nitride film is preferably deposited by a method having good step coverage such as LPCVD.

10H illustrates a structure in which the charge storage region is formed of the second insulator 32b, the L-shaped deposition insulating film 15, and the silicon dot 10. As the forming method, after the first insulator 32a is formed, polysilicon is deposited by a method having good step coverage such as LPCVD, the surface is oxidized, silicon dots are formed, and then a deposition insulating film is formed. do. The structure may be formed using the steps of FIGS. 10A and 10H. With the above structure, the semiconductor or the conductor film is present between the semiconductor substrate and the plurality of fine particles, whereby the influence of the position and size of the fine particles on the threshold voltage of the field effect transistor can be suppressed. Therefore, a semiconductor memory device in which misreading is suppressed can be provided.

In addition, the following steps may be used. After the first insulator 32a is formed, polysilicon is deposited by a method having good step coverage such as LPCVD, and the surface thereof is oxidized. Thereafter, the process is carried out under the same conditions as those in which polysilicon is deposited.

Due to the difference in the roughness of the underlying oxide film in the first polysilicon deposition step and the step at this time, silicon dots are formed in this step. In the case of performing such silicon dot formation, if the silicon dot is too small, the coulombic shielding effect is so strong that injection of charge becomes difficult, and if the silicon dot is too large, a thin film is obtained. Therefore, the optimum thickness of the polysilicon film is about 1 to 20 nm. As a typical example, a 5 nm polysilicon film and a silicon dot can be formed by low pressure chemical vapor deposition (LPCVD) in a SiH ₄ atmosphere at 620 ° C., such as the polysilicon film.

The charge storage regions shown in FIGS. 10E-10H are circumventive parts (removal regions 21) as shown in FIGS. 28A and 28B to prevent short circuits between left and right charge storage regions. Need to be removed.

In addition, in the polysilicon of the charge storage region shown in Figs. 10E to 10H, any substrate other than polysilicon obtains the same effect as long as it has a function of retaining charge. For example, a silicon nitride film, a conductor, or a ferroelectric such as PZT or PLZT may be used.

(Example 10)

A semiconductor storage device of a tenth embodiment of the present invention will be described with reference to FIGS. 11A through 11D.

The semiconductor storage device of the present embodiment, as shown in FIG. 11A, has a FET having a gate electrode 3 formed on the semiconductor substrate 1 through the gate insulator 2, and on both sides of the gate electrode 3. And a pair of source / drain diffusion regions 13, 13 formed on the corresponding semiconductor substrate surface. The region between the pair of source / drain diffusion regions 13 and 13 corresponds to the channel forming region 19. The gate insulator 2 and the gate electrode 3 form a gate stack 8.

Between the both sides of the gate electrode 3 and the surface of the semiconductor substrate, recesses 50 and 50 whose cross sections gradually widen laterally are formed, respectively. The side surface of the gate electrode 3 has a flat portion 3a substantially perpendicular to the surface of the gate insulator 2, and an inclined portion 3b adjacent to the lower side of the flat portion to form part of the concave portion 50. Have

The semiconductor substrate surface has a flat portion 1a facing the bottom surface of the gate electrode 3 through the gate insulator 2 and on both sides of the flat portion with respect to the gate longitudinal direction to form a part of the recess 50. Each of the inclined portions 1b and 1b adjacent to each other and the bottom surface portions 1c and 1c adjacent to the outer sides of the inclined portions 1b and 1b, respectively.

Memory functional bodies 11 and 11 are formed on both sides of the gate electrode 3 so that the recesses 50 and 50 are embedded. The memory functional element 11 is composed of a charge holding portion 31 made of a material having a function of storing charge and a dissipation preventing dielectric (generally indicated by reference numeral 32 for convenience) having a function of preventing the dissipation of stored charge. .

In this example, the anti-dissipating dielectric 32 is inclined portion 1b of the surface of the semiconductor substrate so that the charge holding portion 31 and the gate electrode 3 as well as the charge holding portion 31 and the semiconductor substrate 1 are respectively isolated from each other. ) And the bottom surface portion 1c, as well as the inclined portion and the flat portion 3a of the side surface of the gate electrode, and the first dielectric material 32a having a substantially uniform film thickness.

A space (offset region) 20 is formed between the source / drain diffusion region 13 in the gate longitudinal direction and the bottom surface of the gate electrode 3. Each space 20 is covered with a memory functional body 11.

That is, in the present semiconductor storage device made of FET, a swelling portion is formed on the surface of the semiconductor substrate 1, and the lower portion of the side surface of the gate electrode 3 is tapered in the reverse direction. The channel forming region 19 is formed under the gate electrode, and a pair of source / drain diffusion regions 13 and 13 having opposite conductivity types of the channel forming region are formed on both sides of the channel forming region 19. . On the sidewall of the gate electrode 3, a memory functional element 11 each comprising a charge holding part 31 formed of silicon nitride having a function of storing charge and a dissipation preventing dielectric 32 having a function of preventing the dissipation of stored charges. , 11) is formed.

Since the offset regions 20 are each covered with the memory functional bodies 11, the source / drain diffusion regions 13 from one source / drain diffusion region 13 to the other by the voltage applied to the gate electrode 3. The amount of current flowing into N) may vary depending on the amount of charge held by the memory functional bodies 11 and 11.

As shown in the figure, since the charge holding portion is formed on both sides of the gate electrode, not the FET portion that functions as a gate insulator as shown in the prior art, the problem of over-erasing in the prior art can be solved. have.

In addition, the source / drain diffusion regions 13 and 13 are disposed at the bottom portions 1c and 1c of the semiconductor substrate surface, and the gate stack 8 is located at the flat portion 1a of the semiconductor substrate surface. They are separated from each other via the inclined portion 1b. Therefore, since the substantial offset width becomes larger than the design (lateral) offset width, the device can be miniaturized while maintaining a sufficient offset width. In addition, the distance between the pair of source / drain diffusion regions 13 and 13 is substantially larger than that of the basic design for structural reasons, so that deterioration of transistor operation such as punch-through and short channel effects due to miniaturization is suppressed. do. Therefore, a semiconductor storage device suitable for miniaturization and in which manufacturing cost can be suppressed can be provided.

The source / drain diffusion region 13 is formed so as not to extend on the inclined portion 1b of the semiconductor substrate surface as shown in the figure, but is not limited thereto. That is, the source / drain diffusion region 13 is formed at the bottom surface of the gate electrode 3 that forms the gate stack 8 on the semiconductor substrate surface when the source / drain diffusion region 13 is formed to extend on the inclined portion. It should be formed to be more offset. In addition, by doing so, the efficiency of injecting hot electrons generated during writing into the memory functional body can be improved. Further, according to such a configuration, since the offset region 2 can be formed so as to cover the gate electrode, the short channel effect can be suppressed, thereby achieving miniaturization. In addition, in the injection or release of electrons by the voltage of the gate electrode 3, since the gate electrode 3 is located above the offset region 20, the injection or release of electrons can be made more effective. Therefore, the recording speed can be improved.

Further, for structural reasons, since the voltage of the gate electrode 3 effectively affects the vicinity of the channel of the memory functional bodies 11 and 11, charge is more easily injected and erased. Thus, a semiconductor storage device in which write / erase or read errors are suppressed and high reliability can be provided. In addition, since the voltage of the gate electrode 3 effectively affects the offset portion of the channel, the misread can be suppressed because the driving current in the erase operation is large, and a semiconductor storage device having a high read speed can be provided.

In addition, the semiconductor storage device can function as a memory cell having the functions of both the selection transistor and the memory transistor due to the variable resistance effect by the memory functional body 11.

The semiconductor substrate 1 and the gate electrode 3 are preferably formed of a material made of silicon. In this case, since the semiconductor substrate 1 and the gate electrode 3 are formed of silicon generally used as a material of a semiconductor device in recent years, the semiconductor process which is highly compatible with the conventional semiconductor manufacturing process can be rescued. Thus, a semiconductor storage device having a low manufacturing cost can be provided.

Further, in the embodiment of the semiconductor storage device of the present invention, two or more bits of information are stored in one element, so that the semiconductor storage device can be made to function as a memory element storing four or more pieces of information.

In addition, the semiconductor storage device of the present invention may have the following configuration.

Hereinafter, the names of the memory functional bodies and their respective parts are defined as follows.

As shown in Figs. 11A to 11C, the memory functional body 11 is made of a material having a function of storing electric charges, and is formed of a charge holding part 31 formed next to the gate electrode 3, and of the stored electrons. It is assumed that the anti-dissipation dielectric 32 has a function of preventing dissipation. In this case, the anti-dissipating dielectric 32 may have the first dielectric 32a and the second dielectric 32b (FIGS. 11B and 11C), or may have only the first dielectric without the second dielectric (FIG. 11). 11a).

The first dielectric 32a is formed so that the charge holding portion 31 is isolated from the gate electrode 3 and the semiconductor substrate 1, and the second dielectric 32b is a sidewall spacer outside the charge holding portion 31. Both the first dielectric 32a and the second dielectric 32b have a function of preventing the dissipation of stored charges. As a result, the charge holding characteristic is improved.

11A to 11D, the source / drain diffusion region 13 is spaced apart from the gate electrode 3 in the channel direction on the surface of the semiconductor substrate 1. More specifically, the gate stack 8 consisting of the gate electrode 3 and the gate insulator 2 and the source / drain diffusion region 13 are separated from each other at the surface portion of the semiconductor substrate. That is, on the surface of the semiconductor substrate 1, the source / drain diffusion region 13 does not exist directly below the bottom surface of the gate electrode 3 (via the gate insulator 2), but the offset region 20 does not exist. It is separated by a range of widths. That is, the channel formation region 19 between the source region and the drain region is disposed under the memory functional body 11 over the width of the offset region 20 on the surface of the semiconductor substrate 1. As a result, not only the injection of holes into the memory functional body but also the injection of electrons can be efficiently performed, so that a semiconductor storage device having a high writing and erasing speed can be formed.

Therefore, in the semiconductor storage device, since the source / drain diffusion region 13 is offset from the gate electrode 3, the inversion of the offset region under the memory functional body 11 due to the voltage applied to the gate electrode 3 is reversed. The degree of invertibility can be greatly changed by the amount of charge stored in the memory functional body 11, thereby increasing the memory effect. In addition, compared with the MOSFET of the conventional structure, the short channel effect can be suppressed, so that the gate length can be reduced. Therefore, due to the structural suitability for suppressing the short channel effect, it is possible to use a gate insulator having a thicker film thickness than a logic transistor without an offset arrangement, thereby increasing the reliability.

In addition, the memory function 11 of the semiconductor storage device is formed independently of the gate insulator 2. Therefore, the memory function acting by the memory functional element 11 and the transistor operation function acting by the gate insulator 2 are separated from each other. Also, for the same reason, a material suitable for the memory function can be selected to form the memory function body 11.

In this case, as shown in FIG. 11C, the charge holding part 31 of the memory functional body 11 is formed to be bent along the outer shape of the gate electrode 3 or the semiconductor substrate 1. Although the charge holding part 31 is shown as a curve in this figure, in some drawings after this figure, the bending part is abbreviate | omitted for the sake of simplicity. Therefore, it is necessary to properly interpret the appearance in consideration of each embodiment.

In addition, as illustrated in FIG. 11D, the extension portions 6 and 6 having the same conductivity type as the source / drain diffusion regions and the shallower junction depths than the high source / drain diffusion regions have a pair of source / drain diffusion regions 13, 13), that is, in the offset region. Formation of a source / drain region comprising an extension 6 (generally denoted with reference 18) causes source / drain diffusion including the extension to extend over the inclined portion 1b while the short channel effect is suppressed. The region 18 can be formed. Therefore, the effect of injecting hot electrons into the memory functional body is improved, and recording is effectively performed. In addition, since the upper portion of the offset region can be formed to cover the gate electrode 3, the short channel effect can be suppressed, so that miniaturization can be achieved. In addition, since the gate electrode 3 is located above the offset region, the writing speed can be improved because the injection and release of charge can be made more efficiently with the voltage of the gate electrode 3. In such a case, if the extension 6 is lighter doped than the other portion (source / drain diffusion region) 13 of the source / drain diffusion region 18, the short channel effect can be largely suppressed, and conversely, If the portion 6 is heavily doped, the hot carrier generation efficiency can be further improved.

Also, inside the source / drain diffusion region 18 including the extension 6, the counter region 22 doped more heavily than the channel formation region located directly below the bottom surface of the gate electrode is the source / drain diffusion region. Since it is formed in the opposite conductivity type and the generation efficiency of hot electrons can be further improved, the recording efficiency can be greatly improved.

Further, even when such a counter area is formed in the source / drain diffusion areas 13 and 13, that is, in the diffusion area of the semiconductor storage device shown in Figs. 11A to 11C, the recording efficiency is equally improved.

In addition, the present semiconductor storage device may be implemented in the following modes.

The semiconductor reservoir forming the memory of the semiconductor storage device of the present invention is mainly formed under a gate insulator, a gate electrode formed on the gate insulator, a memory functional body formed on both sides of the gate electrode of the semiconductor reservoir, and formed under the gate electrode. And a source / drain diffusion region formed at both sides of the channel forming region and having a conductivity type opposite to that of the channel forming region.

Since the semiconductor storage device stores two or more pieces of information in one memory functional body, it functions as a semiconductor reservoir for storing four or more pieces of information. The semiconductor reservoir also functions as a memory cell having the functions of the selection transistor and the memory transistor simultaneously by the variable resistance effect function of the memory functional body. However, the semiconductor reservoir need not be made to store more than four kinds of information, but can also be made to store two kinds of information.

The semiconductor reservoir constituting the semiconductor device of the present invention is formed on the semiconductor substrate or in the well region having the same conductivity type as the channel formation region of the semiconductor substrate.

The semiconductor substrate is not particularly limited as long as it is suitable for a semiconductor device, a substrate made of an element semiconductor containing silicon and germanium, a compound semiconductor including SiGe, GaAs, InGaAs, ZnSe, and GaN, a silicon on insulator (SOI) substrate, and Various substrates may be used, such as a substrate made of a multilayer SOI substrate and a substrate having a semiconductor layer on a glass or plastic substrate. Among these, a silicon substrate or an SOI substrate having a silicon surface layer is preferable. The semiconductor substrate or the semiconductor layer may be any of single crystals (for example, single crystals obtained by epitaxial growth), polycrystals, or amorphous, although the amount of current flowing through the inside is slightly different.

In the semiconductor substrate or the semiconductor layer, an element isolation region is preferably formed, and it is more preferable to form a single layer or multilayer structure by combining transistors, capacitors and resistors, circuits in which they are combined, semiconductor devices, and interlayer insulating films or films. Do. The device isolation region may be formed by any of a variety of device isolation films including a local oxidation of silicon (LOCOS) film, a trench oxide film, and a shallow trench isolation (STI). The semiconductor substrate may have either a conductive type of a P type or an N type conductive type, and at least one well region of the first conductive type (P type or N type) is preferably formed in the semiconductor substrate. Impurity concentrations of the semiconductor substrate and the well region may be within a range known in the prior art. When the SOI substrate is used as a semiconductor substrate, a well region may be formed in the surface semiconductor layer, and a body region may be provided below the channel formation region.

Examples of the gate insulator are not particularly limited, and an insulating film including a silicon oxide film and a silicon nitride film, and a high dielectric film including an aluminum oxide film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film may be used in a semiconductor device in the form of a single layer film or a multilayer film. Includes commonly used ones. Among these, a silicon oxide film is preferable. Appropriate thickness of a gate insulator is about 1-20 nm, for example, 1-6 nm in thickness of an equivalent insulator. The gate insulator may be formed just below the right side of the gate electrode, or may be formed wider than the gate electrode.

The gate electrode or electrodes are formed on the gate insulator in a shape generally used in a semiconductor device or in a shape having a recess at a lower end thereof. Here, the "single gate electrode" is defined as a gate electrode made of a single layer or multilayer conductive film and is formed of a single inseparable. The gate electrode may have sidewall insulating films on each side. The gate electrode is not particularly limited as long as it is generally used in a semiconductor device, and may be polysilicon; Metals including copper and aluminum, high melting point metals including tungsten, titanium, and tantalum; And conductive films in which silicides of high melting point metals are in the form of a single layer or a multilayer. The gate electrode is suitably formed, for example, with a film thickness of about 50 to 400 nm. The channel forming region is formed under the gate electrode.

The memory functional body has a film or region having at least a function of holding a charge, a function of storing and holding a charge, a trapping charge, or a function of keeping the charge polarized. Examples of the material having these functions include silicate glass containing impurities such as silicon nitride, silicon, phosphorus or boron; Silicon carbide, alumina; High dielectric materials such as hafnium oxide, zirconium oxide, or tantalum oxide; Tantalum oxide; Zinc oxide, and metals. The memory functional body may include, for example, an insulating film including a silicon nitride film; An insulating film having a conductive film or a semiconductor layer bonded therein; It may be formed in a single layer or a multilayer structure of an insulating film containing one or more conductor dots or semiconductor dots. Among them, the presence of a large number of levels for trapping charges allows a large hysteresis characteristic to be obtained, a long charge holding time and a low retention of electric charges due to the occurrence of leakage paths. Since it is a material used, silicon nitride is preferable.

The use of an insulating film having an insulating film having a charge holding function, such as a silicon nitride film inside, can increase the reliability of memory retention. Since the silicon nitride film is an insulator, even if part of the charge leaks, the charge of the entire silicon nitride film is not immediately lost. Furthermore, in the case where a plurality of storage devices are arranged, even when the distance between the storage devices is short and adjacent memory functional bodies come into contact with each other, unlike the case where the memory functional bodies are made of conductors, information stored in each memory functional body is not lost. . Further, the contact plug can be arranged closer to the memory functional body, and in some cases, the contact plug can be arranged so as to overlap the memory functional body to facilitate the miniaturization of the storage device. In order to further increase the reliability regarding memory retention, the insulator having the function of holding charge does not have to be in the shape of a film, and it is preferable that the insulator having the function of holding charge is present in such a manner that it is dispersed in the insulating film. In more detail, it is preferable that the insulator is disperse | distributed in dot shape on the material which is hard to hold | maintain electric charge like silicon oxide.

In addition, the use of an insulator film containing a conductive film or a semiconductor layer inside as a memory functional body can freely control the amount of charge injected into the conductor or the semiconductor, thereby making it possible to easily obtain a multi-level cell.

In addition, when an insulating film containing at least one conductor or semiconductor dot is used as the memory functional body, since writing and erasing by direct tunneling of charge can be easily performed, there is an effect that power consumption can be reduced.

As the memory functional body, ferroelectric films such as lead zirconate titanate (PZT) and lead lanthanum zirconate titanate (PLZT) whose polarization direction changes with an electric field can be used. In this case, electric charges are substantially generated by the polarization on the surface of the ferroelectric film and maintained in that state. Therefore, charge is supplied from the outside of the film having a memory function, so that the same hysteresis characteristics as the film trapping the charge can be obtained. In addition, since there is no need to inject charges from the outside of the film, the hysteresis characteristics can be obtained only by polarization of the charge of the film, and thus the writing and erasing speed is increased.

The memory functional body preferably further includes a region which blocks the leakage of charge or a film having a function of blocking the leakage of charge. Silicon oxide is a material that functions to block leakage of charge.

The charge holding part included in the memory functional body is formed directly on both sides of the gate electrode or through an insulating film, and directly on a semiconductor substrate (well region, body region, or source / drain region or diffusion layer region) or a gate insulator or insulating layer. Is placed through. The charge holding portions on both sides of the gate electrode are preferably formed so as to cover the whole or part of the sidewall of the gate electrode directly or through an insulating film. When the gate electrode has a recess on the lower edge side, the charge holding portion may be formed so as to fill the entire recess or a portion of the recess directly or through an insulating film.

The gate electrode is preferably formed only on the sidewalls of the memory function or not to cover the top of the memory function. In such an arrangement, the contact plug can be disposed closer to the gate electrode, which facilitates the miniaturization of the semiconductor storage element. In addition, the semiconductor reservoir having such a simple arrangement is easily manufactured, so that the yield is increased.

When the conductive film is used as the charge holding portion, the charge holding portion is disposed together with the insert of the insulating film so that the charge holding film does not directly contact the semiconductor substrate (well region, body region, or source / drain diffusion region or diffusion side region) or the gate electrode. It is preferable. This is achieved by, for example, a multilayer structure composed of a conductive film and an insulating film, a structure in which a dot-shaped conductive film is dispersed in an insulating film, and a structure in which the conductive film is dispersed in a sidewall insulating film portion formed on the sidewall of the gate.

The source / drain diffusion region is a diffusion region having a conductivity type opposite to that of the semiconductor substrate or well region, and is disposed on the side of the memory functional body opposite from the gate electrode. It is preferable that the impurity concentration rapidly increase in the portion where the source / drain diffusion region is bonded to the semiconductor substrate or the well region. This is because rapidly increasing impurity concentrations efficiently generate hot electrons and passion holes at low voltages, thereby enabling high-speed operation at lower voltages. Since the junction depth of the source / drain diffusion region is not particularly limited, it can be adjusted as necessary according to the performance of the manufactured memory device. Although the junction depth is preferably about the same as the thickness of the surface semiconductor layer, when the SOI substrate is used as the semiconductor substrate, the junction depth of the source / drain diffusion region may be thinner than the thickness of the surface semiconductor layer.

The source / drain diffusion region may be arranged to overlap the edge of the gate electrode, meet the edge of the gate electrode, or offset from the edge of the gate electrode. In particular, it is preferable that the source / drain diffusion region be offset with respect to the edge of the gate electrode. This is because, in this case, when a voltage is applied to the gate electrode, the ease of inversion of the offset region under the charge holding portion is greatly changed by the amount of charge stored in the memory functional body, so that the memory effect increases and the short channel effect decreases. . However, too much offset reduces the drive current between the source and drain. Therefore, it is preferable that the offset amount, that is, the distance from one edge of the gate electrode to the source or drain region near the gate length direction is shorter than the thickness of the charge holding portion in the gate length direction. Of particular importance is that at least a portion of the charge holding portion of the memory functional body overlaps the source / drain diffusion region serving as the diffusion layer region. this is

This is because the nature of the semiconductor reservoir constituting the semiconductor device of the present invention is to rewrite the memory into an electric field across the memory function due to the voltage difference between the gate electrode and the source / drain diffusion region existing only in the sidewall portion of the memory function. to be.

A portion of the source / drain diffusion region may extend to a position above the surface of the channel formation region, that is, the bottom surface of the gate insulator.

In such a case, it is appropriate that the conductive film is integrally disposed with the source / drain diffusion region in the source / drain diffusion region formed in the semiconductor substrate. Examples of the conductive film include a semiconductor such as polysilylcone, amorphous silicon, silicide, and the metal and the high melting point metal. Among these, polysilicon is preferable. Since polysilicon has a much faster impurity diffusion rate than a semiconductor substrate, it is easy to shallowen the junction depth of the source / drain diffusion region of the semiconductor substrate and to control the short channel effect. In this case, the source / drain diffusion region is preferably disposed such that at least a portion of the charge holding film is interposed between a portion of the source / drain diffusion region and the gate electrode.

The semiconductor reservoir of the present invention can be formed by a conventional semiconductor process according to the same method as the method of forming sidewall spacers of a single layer or stacked structure on the sidewalls of a word line or a gate electrode. Specifically, forming a gate electrode or a word line, forming a single layer film or a multilayer film including a charge holding portion such as a charge holding portion, a charge holding portion / insulating film, an insulating film / charge holding portion, an insulating film / charge holding portion / insulating film, or the like And leaving the film or films in sidewall spacer shape by etching back under appropriate conditions; Forming an insulating film or charge holding portion, leaving the film in the form of sidewall spacers by etching back under suitable conditions, and further forming a charge holding portion or insulating film and leaving the film in the form of side wall spacers by etching back under suitable conditions; How to; Coating or depositing the insulating film material in which the particulate charge holding material is dispersed, onto the semiconductor wafer including the gate electrode, and leaving the insulating film material in the form of sidewall spacers by etching back under suitable conditions; Forming a gate electrode; And a method including forming a single layer film or a multilayer film, and performing patterning using a mask. Also, before forming the gate electrode or the electrode, forming the charge holding portion, the charge holding portion / insulating film, the insulating film / charge holding portion, or the insulating film / charge collecting / insulating film. Forming an opening through a film or films in an area to be a channel forming region, forming a gate electrode material film over the entire upper surface of the wafer, and forming the gate electrode material film larger than the opening and surrounding the opening. And a method comprising patterning.

When the memory cell is constructed by disposing the semiconductor reservoir of the present invention, the requirements for satisfying the best mode of the semiconductor reservoir are as follows.

(Iii) An integrated body of gate electrodes of a plurality of semiconductor reservoirs has a function of word lines.

(Ii) Memory functional bodies are formed on both sides of each word line.

(Iii) The material that holds the charge in the memory functional body is an insulator, in particular silicon nitride.

(Iii) The memory functional body is composed of an oxide Nitride Oxide (ONO) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulator.

(Iii) The silicon nitride film of each memory functional body is separated from the word line and the channel forming region by the silicon oxide film.

(Iii) The silicon nitride film of each memory functional body overlaps with the corresponding diffusion region.

(Iii) The thickness of the insulating film that separates the silicon insulating film having a surface substantially parallel to the surface of the gate electrode from the channel forming region or the semiconductor layer is different from the thickness of the gate insulator.

(Iii) Writing and erasing operations of one semiconductor reservoir are performed by a single word line.

(Iii) On each memory functional body, there is no electrode (word line) having a function of assisting write and erase operations.

(Iii) The portion in contact with the diffusion region on the lower right side of each memory functional body has a region where the impurity concentration of the conductivity type opposite to that of the diffusion region is high.

The best mode is a mode that satisfies all of these conditions, but does not need to satisfy all the conditions.

If some of the conditions are met, there is the most preferred combination of conditions. For example, (i) the material that holds the charge in the memory functional body is an insulator, in particular silicon nitride, and (i) there is no electrode (word line) having a function of assisting write and erase operations on each memory functional body. And (iii) the most preferred combination is that the silicon nitride film of each memory functional body overlaps with the corresponding diffusion region. According to the inventor's research, if the insulator has no electrodes having a function of retaining charge in the memory functional bodies and assisting write and erase operations on each memory functional body, the insulator (silicon nitride film) of each memory functional body corresponds to the diffusion region. Only if it overlaps with is long and the operation is performed. That is, it is especially preferable to satisfy the conditions (iv) if the conditions (iv) and (iv) are satisfied. On the other hand, in the case where an electrode having a function in which a conductor holds charge in a memory functional body or assists writing and erasing operations in each memory functional body, even when the insulator of each memory functional body does not overlap with the corresponding diffusion region, The write operation is performed. However, in the case where the insulator has no electrode in each memory function having a function of keeping charge in the memory function or assisting writing and erasing, the following great advantages are obtained. That is, the contact plug can be placed close to the memory functional body. Alternatively, even when the semiconductor reservoir is located close to each other, the plurality of memory functional bodies do not interfere with each other, and the stored information can be maintained. Therefore, miniaturization of the semiconductor reservoir becomes easy. In addition, because the device structure is simple, the number of manufacturing process steps is reduced, and the yield is improved. In addition, the combination of the logic circuit and the transistor constituting the analog circuit can be facilitated. In addition, we have confirmed that the write and erase operations can be performed even at a voltage lower than 5V. This is why it is particularly preferable to satisfy the conditions (iii), (iii) and (iii).

The semiconductor device of the present invention, in which the semiconductor reservoir is combined with a logic element, can be applied to a battery-powered portable electronic device, particularly a mobile information terminal. Examples of portable electronic devices include mobile phones and game machines in addition to mobile information terminals.

The tenth embodiment describes an N-channel device. However, if the conductivity type of the impurity is opposite, it may be a P-channel device.

In addition, in the drawings, the same reference numerals are given to portions where the same materials and materials are used and the same shapes need not be indicated.

In addition, the drawings are schematic and differ from the actual ones in terms of the dimensional relationship between the thickness and the plane, the ratio of the thickness and size between the layer and the part, and the like. Therefore, specific dimensions of thickness and size should be determined in consideration of the following description. Also, of course, the drawings include parts having different dimensional relations and ratios.

Incidentally, the thicknesses and dimensions of the layers and portions described in the present invention are the dimensions of the final shape in which the formation of the semiconductor device is completed unless otherwise described. Therefore, the size of the final shape may change somewhat depending on the thermal history of the subsequent process or the like as compared with the dimension immediately after the formation of the film and the impurity region or the like.

(Eleventh embodiment)

12A to 12D, a semiconductor storage device according to an eleventh embodiment of the present invention will be described.

Hereinafter, manufacturing processes are demonstrated in order along FIGS. 12A-12D.

As shown in FIG. 12A, the gate insulator 2 and the gate electrode 3, that is, the gate stack 8 having the MOS structure and undergoing a metal-oxide-semiconductor (MOS) forming process have a P conductivity type. It is formed on the silicon substrate 1.

A typical MOS formation process is as follows.

First, if necessary, the device isolation region is made of silicon and formed on the semiconductor substrate 1 having a P-type semiconductor region by a known method. The device isolation region may prevent the leakage current from flowing through the substrate between devices adjacent to each other. However, even when elements adjacent to each other are commonly coupled with the source / drain diffusion region 13, it is not necessary to form such an element isolation region. Formation of the device isolation region may prevent leakage current from flowing between neighboring devices through the substrate. Such device isolation area

It does not need to be formed for neighboring devices between shared source / drain diffusions. The known device isolation region forming method may be any known method using a LOCOS oxide, a known method using a trench isolation region, or any other known method that can achieve the purpose of isolating elements from each other. In the present embodiment, when no device isolation region is formed, the device isolation region is not shown in the figure.

Next, although not shown in detail, an impurity diffusion region is formed on the exposed surface of the semiconductor substrate and its circumference. This impurity diffusion region is for controlling the threshold voltage and increasing the impurity concentration in the channel formation region. In order to obtain an appropriate threshold voltage, an appropriate impurity diffusion region may be formed by a known method.

Next, a dielectric film is formed over the entire exposed surface of the semiconductor region. This dielectric film, which can only suppress leakage, may be formed of an oxide film, a nitride film, a composite film of an oxide film and a nitride film, a high dielectric film such as a hafnium oxide film or a zirconium oxide film, or a composite film of a high dielectric film and an oxide film. In addition, since the film forms a gate insulator of the MOSFET, it is preferable to form a film having excellent performance as the gate insulator by using a process including N ₂ O oxidation, NO oxidation, post-oxidation nitriding and other steps. A film having excellent performance as a gate insulator can suppress all factors that hinder the progress of miniaturization and performance improvement of the MOSFET. For example, the MOSFET short channel effect can be suppressed and unnecessary flow through the gate insulator It means an insulating film which can suppress the leakage current which is a current and can suppress the diffusion of the impurity of the gate electrode into the channel formation region of a MOSFET while suppressing the depletion of the impurity of the gate electrode. Generally, the film is an oxide film such as a thermal oxide film, an N ₂ O oxide film, or an NO oxide film, and the film thickness is suitably in the range of 1 to 6 nm.

Next, a gate electrode material is formed on the dielectric film. As the gate electrode material, any material can be used as long as it can exert a performance with a MOSFET such as polysilicon, doped polysilicon or other semiconductors, Al, Ti, W, or a thin metal, a compound of these metals and silicon. For example, when a polysilicon film is formed, it is preferable that the thickness of a polysilicon film is 50 nm-400 nm.

Next, a predetermined photoresist pattern is formed on the gate electrode material by a photolithography process, and using the obtained photoresist pattern as a mask, gate etching is performed so that the gate electrode material and the gate insulator are etched. To form. A gate stack 8 consisting of the gate insulator 2 and the gate electrode 3 is formed. Although not shown, in this process, the gate insulator may not be etched. If the gate insulator is not etched and used as the implantation protection film in a subsequent impurity implantation step, the step of forming the implantation protection film can be simplified.

The material of the gate insulator 2 and the gate electrode 3 may be used for a logic process which follows the scaling law of recent years, and is not limited to the above.

In addition, the gate stack 8 may be formed by the following process. The gate insulator constructed as described above is formed as a whole on the exposed surface of the semiconductor substrate 1 having the P-type semiconductor region. A gate electrode material constructed as described above is then formed on the gate insulator. Subsequently, a mask dielectric film of oxide, nitride, oxynitride or the like is formed on the gate electrode material. Subsequently, after forming the photoresist pattern constructed as described above on the mask dielectric film, the mask dielectric film is etched. Subsequently, the photoresist pattern is removed, and the gate electrode material is etched using the mask dielectric film as an etching mask. Subsequently, the exposed portion of the gate insulator and the mask dielectric film are etched to form the structure of FIG. 12A. In the case of forming the gate stack in this manner, the selectivity of etching, that is, the selectivity of the gate electrode material to the gate insulator material is increased, so that the thin film gate insulator can be etched without etching the substrate. In this case, although not shown, the gate insulator need not be etched for the same reason as above.

Next, as shown in Fig. 12B, thermal oxidation is performed so that the beak dielectric film 18 having the portions 18a and 18a made of silicon oxide and gradually widening in cross section laterally has a semiconductor substrate 1 surface. And between both sides of the gate electrode 3, respectively. Such a beak (parts 18a and 18a in which the cross-section is gradually widened) may be formed so that the oxide film penetrates into the interface between the gate electrode 3 and the semiconductor substrate 1. By the way, when a thick oxide film needs to be formed, a bird's beak can be formed even when oxidation is performed by weak oxidation under the following conditions. That is, under conditions where the reactant (oxygen oxide) is well dispersed in the interface between the gate electrode and the semiconductor substrate, that is, a higher pressure or higher temperature, or a pressure of the reactant is partially lower than in normal oxidizing conditions. In addition to being low, oxidation can occur at higher pressures or higher temperatures. Although an oxide film was used as the beak dielectric film 18, a nitride film can also be used and a mixed film of nitride and oxide can be substituted. By this step, a swelling portion can be formed on the surface of the semiconductor substrate 1, and lower portions of both sides of the gate electrode 3 can be formed to be tapered in the reverse direction.

Next, as shown in FIG. 12C, the beak dielectric film 18 is removed to remove the beak dielectric film 18, that is, between both sides of the gate electrode 3 and the surface of the semiconductor substrate 1. In the place of the recesses, recesses 50 and 50 whose cross sections gradually widen are formed. Subsequently, the first dielectric film 9 made of oxide is formed substantially uniformly along the exposed surface of the gate stack 8 and the semiconductor substrate 1 in which the recesses 50 and 50 are formed. This first dielectric film 9 forms a part of the anti-dissipating dielectric (described later). Since the first dielectric film 9 in the case where an oxide is used is a dielectric film through which electrons pass, it is preferable that the first dielectric film 9 is a film having high withstand voltage, low leakage current and high reliability. For example, an oxide film such as a thermal oxide film, an N ₂ O oxide film, or an MO oxide film is used as the material of the gate insulator 2. In addition, when the dielectric film is formed so thin that the tunneling current flows, the voltage required for injecting or erasing the charge can be lowered, thereby reducing power consumption. In this case, the general film thickness is preferably 3 nm to 8 nm.

In this step, after the beak dielectric film is formed once, the dielectric film is removed and a thinner dielectric film is formed again. However, a process other than this process may be adopted as shown below. That is, in the gate electrode forming process shown in FIG. 12A, an etching process is performed such that lower portions of both side surfaces of the gate electrode are tapered in the reverse direction. In this step, etching is performed to the vicinity of the gate oxide surface under the condition that deposits are provided on both sides of the gate electrode. This deposit becomes thicker from top to top. Next, etching is performed to completely remove the oxide in a process in which the lower portions of both sides of the gate electrode, which are thin or not provided with the deposits, are etched simultaneously. As a result, a structure is formed in which the concave portions are provided on the lower sides of both sides of the gate electrode. Then, as described in FIG. 12B, a common oxide is formed under the condition that a thinner coral film is formed, thereby forming a beak oxide made of an oxide. As a result, the same structure as shown in Fig. 12C, or the semiconductor substrate is flat and the same structure as shown in Fig. 12C can be formed only at the gate electrode. Even if the semiconductor substrate is flat, the same steps as in the case where the semiconductor substrate is not flat can be used for later steps. When the semiconductor substrate is flat, the processing effect that can be produced together with the semiconductor substrate that is not flat cannot be generated as compared with the case where the semiconductor substrate is not flat, but the processing effect that the driving current increases can occur.

Next, as shown in FIG. 12D, the silicon nitride 17 is substantially uniformly optimized as the material of the charge holding portion so that the recess 50 is embedded. The film thickness of the semiconductor storage device of silicon nitride 17 is, for example, 2 nm to 100 nm. The film thickness, which is an important variable for the source / drain diffusion region formed by the offset from the gate electrode 3, can be controlled within the film thickness range in consideration of the offset amount. Silicon nitride is used here, but instead of silicon nitride, a material capable of holding or inducing a charge, such as an oxynitride or oxide having a charge trap, capable of holding a material having charge such as electrons and holes, Alternatively, a material such as a ferroelectric material capable of inducing charges on the surface of the memory function by polarization or other phenomena, or a material having a structure in which an oxide film contains a floating material such as polysilicon or silicon dots capable of retaining charge can be used. It may be.

In this case, by the formation of the first dielectric film 9, the silicon nitride 17 having a function of storing charges contacts the semiconductor substrate and the gate electrode through the dielectric film, so that the leakage of the retained charge is caused by the dielectric film. Can be suppressed. Therefore, a semiconductor storage device having good charge holding characteristics and high long-term reliability can be realized.

Next, as shown in FIG. 13, the silicon nitride 17 is etched and the first dielectric film 9 is etched to form a memory functional body composed of the first dielectric 32a and the charge holding part 31, respectively. 11 and 11 are formed as sidewalls on both sides of the gate stack 8. The first dielectric 32a is formed of part of the first dielectric film 9, and the charge holding part 31 is made of part of silicon nitride.

In addition, using the gate electrode 3 and the memory functional bodies 11 and 11 as a mask, after performing impurity implantation to form the conventional source / drain diffusion region 13, a desired heat treatment is performed, thereby Drain diffusion region 13 is formed. In this case, before the formation of the memory functional body 11 or after the formation of the memory functional body 11, the source / drain diffusion region 13 may be formed, and in either case, substantially the same effect occurs. However, if the source / drain diffusion region 13 is formed before the formation of the memory functional body 11, it is not necessary to form the injection protection film, and the process can be simplified. Here, the case where the source / drain diffusion region 13 is formed after the formation of the memory functional body 11 has been described.

Now, the process of forming the memory functional body will be described in detail.

First, the silicon nitride 17 is anisotropically etched so that the silicon nitride film 17 remains as a sidewall on the sidewall of the gate stack 8 through the first dielectric film 9. In this case, it is preferable to perform etching under the condition that the first dielectric film 9 can be selectively etched and the etching selectivity with respect to the first dielectric film 9 made of oxide is large.

Next, the first dielectric film 9 is anisotropically etched to form a first dielectric 32a made of a part of the first dielectric film 9 on the sidewall of the gate stack 8. In this case, it is preferable that the first dielectric film 9 is selectively etched and performed by etching under conditions in which the etching selectivity for the silicon nitride 17, the gate electrode 3, and the semiconductor substrate 1 is large.

In this way, on both sides of the gate stack 8, the memory functional bodies 11 and 11 are formed as sidewalls so that the recesses 50 are embedded.

Next, the source / drain diffusion region 13 is formed. That is, by using the gate electrode 3 and the memory functional bodies 11 and 11 as masks, impurities having opposite conductivity types of the channel formation region are implanted, and heat treatment for conventional activation is performed. As a result, source / drain diffusion regions 13 and 13 having a specific junction depth are formed in a self-aligning manner. In this case, since the impurity implantation into the semiconductor substrate 1 is performed without passing through the coating film, the implantation energy is controlled so that the impurity is shallowly injected by the range of the film thickness of the coating film, and the junction is formed to a specific depth.

Now, through this step, the memory functional body is formed. The semiconductor storage device using these memory functional bodies has the following operational effects.

When charge is held in the charge holding part 31 of the memory functional body 11, part of the channel formation region is strongly influenced by the charge, and the drain current value changes. Thus, a semiconductor storage device is formed which distinguishes the presence or absence of electric charges according to the change of the drain current value.

In addition, since the gate insulator 2 and the memory functional body 11 are arranged to be separated from each other, scaling of another form is achieved. Therefore, a semiconductor storage device having a good memory effect by suppressing a short channel effect can be provided.

In addition, since the silicon nitride 17 of the memory functional body is in contact with the semiconductor substrate 1 and the gate electrode 3 through the dielectric film, leakage of sustaining charge can be suppressed by the dielectric film. As a result, a semiconductor storage device having good charge holding characteristics and high reliability for a long time is formed.

In addition, when a conductor or a semiconductor is used as a memory functional body, a positive voltage is applied to the gate electrode, polarization occurs in the memory functional body, and electrons are induced in the vicinity of the gate sidewall so that electrons decrease in the vicinity of the channel formation region. do. As a result, the injection of electrons from the substrate or the source / drain diffusion region can be accelerated, so that a semiconductor storage device having a high writing speed and high reliability can be formed.

(Twelfth embodiment)

A semiconductor storage device of a twelfth embodiment of the present invention will be described in detail with reference to FIGS. 14A to 14C.

As shown in Fig. 14C, the semiconductor reservoir of this embodiment is substantially the same as the structure of the semiconductor reservoir of the eleventh embodiment. However, this embodiment is characterized in that the extension 6 and / or the counter area 22 as shown in FIG. 11D are provided. By this embodiment, the structure can be formed in a self-aligning manner without increasing any special mask. In addition, the extension portion 6 having a smaller junction depth than the source / drain diffusion region 13 has the same conductivity type as the source / drain diffusion region, so that the pair of source / drain diffusion regions 13 and 13, that is, the offset region And a source / drain diffusion region 18 including a small extension portion. As a result, since the source / drain diffusion region 18 including the extension portion adjacent to the inclined portion can be formed with the short channel effect suppressed, the injection efficiency of the heat transfer into the memory functional body is increased, so that the recording is efficient. It can be performed as. In addition, since the upper portion of the offset region can be formed covering the gate electrode 3, the short channel effect can be suppressed and miniaturization can be achieved. Further, since the gate electrode is disposed above the offset region, the injection and release of the charge by the voltage of the gate electrode 3 can be performed more efficiently, so that the writing speed can be shaped. In this case, if the impurity concentration of the extension portion 6 is made lighter than other portions of the source / drain diffusion region 18, the short channel effect can be further suppressed. On the contrary, if the same impurity concentration is thickened, hot carriers are generated. The efficiency can be increased.

In addition, a counter region 22 having a conductivity type opposite to that of the source / drain diffusion region and having an impurity concentration higher than that of the channel formation region is formed inside the source / drain diffusion region 18 including the extension portion. It can be increased further and can be increased long and efficiency greatly.

Even when these counter areas 22 are formed inside the source / drain diffusion area 13, i.e., the offset areas, the recording efficiency is similarly improved.

Further, since the extension portion 6 has a shallower junction depth than the portion other than the source / drain diffusion region 18 compared to the portion where the junction depth is deeper, the lateral fluctuation can also be suppressed. Therefore, since the fluctuation in the width in the transverse direction (channel direction) of the offset region can be suppressed low, a highly reliable semiconductor storage device can be formed. However, the source / drain diffusion region may be formed so as to overlap on the inclined portion only by impurity implantation forming a normal source / drain diffusion region. However, in this case, compared with the case where the extension part is formed, the effect of reducing fluctuations in the width in the transverse direction (channel direction) does not occur, but the operation effect in which the process is simplified is produced.

As the manufacturing method for this semiconductor storage device, the manufacturing method of Figs. 12A to 12D described in the eleventh embodiment may be basically used. However, as a characteristic step of this embodiment, the step of forming an extension and / or a counter area is added. 14A to 14C show the case where only the extension part is formed, the following description includes the case where the counter area is also formed.

That is, as shown in Fig. 14A, the structure shown in Fig. 12C is formed first, and then the extension 6 is formed so that the same conductivity type as the source / drain diffusion region is obtained, which is the source / drain diffusion. This is accomplished by performing impurity implantation with a implantation energy lower than the region. However, the heat treatment for activation of the impurity does not yet have to be done at this stage, and may be performed simultaneously with the subsequent formation of the source / drain diffusion region.

In this process, the extension 6 having a lower implantation energy than the other portion 13 of the source / drain diffusion region 18 (see Fig. 14C) may have a shallower junction depth. As a result, since the lateral fluctuations included in the formation of the diffusion region of the extension portion 6 can be suppressed to be smaller than the lateral fluctuations included in the formation of the portion 13 with a deeper junction depth, the variation of the offset region is also reduced. It can be suppressed small. Therefore, in particular, since the fluctuation of the injection amount of charge into the memory functional body can be suppressed, the fluctuation of the device element characteristics can be suppressed, and a highly reliable semiconductor storage device can be formed.

In this step, a counter region can be formed by further performing impurity implantation forming the counter region so that the opposite conductivity type of the source / drain diffusion region can be obtained. As in the formation of the extension, heat treatment may be performed in a subsequent process. Furthermore, as shown in Fig. 11D, the counter area required to be formed inside the extension area is

It can be easily formed on the inside by performing the injection at a larger injection angle than the extension.

In the case where only the counter region is formed without forming the extension, a structure in which the source / drain diffusion region and the counter region are in contact with each other is formed.

Next, as shown in Fig. 14B, silicon nitride 17 is formed as a material of the charge holding portion so that the recess 50 is embedded. The method of forming the silicon nitride 17 may be the process described in the description of Fig. 12D of the eleventh embodiment.

Next, as shown in FIG. 14C, memory functional bodies 11 each formed of a charge holding part 31 and a first dielectric 32 a are formed on both sides of the gate stack 8. The method for forming the memory functional body 11 may be the process described in the description of Fig. 13 of the eleventh embodiment.

Thus, a semiconductor storage device in which a counter region and / or an extension is formed is formed.

(Thirteenth Embodiment)

A semiconductor storage device of a thirteenth embodiment of the present invention will be described in detail with reference to FIGS. 15A to 15C.

The semiconductor reservoir of this embodiment is substantially the same as the structure of the semiconductor reservoir of the eleventh embodiment, as shown in Fig. 15C. However, in the present embodiment, the charge holding portions 31 are formed so as to be respectively accommodated in the concave portions 50, so that the top position of each charge holding portion 31 is lower than the top position of the gate electrode 3. It is characterized by. As a result, compared with the semiconductor reservoir described in the eleventh embodiment, the charge holding portion can be formed so as to be limited to the vicinity of the place where the hot carrier occurs, so that the electrons injected by the write operation can be erased more easily. As a result, erasure failure is not generated further and reliability is formed. In addition, while the injected charge amount is invariably maintained, the volume of the charge holding portion of the memory functional body holding the charge decreases, so that the amount of charge per unit volume can be increased. Therefore, an electronic recording / erasing can be made efficiently, and a semiconductor storage device having a high recording / erasing speed is provided.

Further, in this structure, the charge holding portion 31 made of silicon nitride having a function of retaining charge with the memory functional element 11 is composed of the anti-dissipating dielectric 32, the first dielectric 32a and the second dielectric 32b. It is interposed between)). Therefore, dissipation of the retained charge can be suppressed, and a semiconductor storage device having good retention characteristics can be provided. In addition, the charge holding part 31 has a structure interposed between the dissipation suppressing dielectric 32 (the first dielectric 32a and the second dielectric 32b), thereby injecting it into the gate electrode and the other node during the write operation. Dissipation of the charged charges is suppressed and the charge injection efficiency is improved, whereby a faster recording operation can be achieved.

The manufacturing method for this semiconductor storage device may basically be the manufacturing method of Figs. 12A to 12D described in the eleventh embodiment. However, in this embodiment, a step after formation of the structure shown in Fig. 13, that is, after impurity implantation for the formation of the source / drain diffusion region 13, is performed.

Thereafter, as shown in Fig. 15A, an anisotropic etching back is further performed to remove a part of the silicon nitride (material of the charge holding portion 31) existing outside the recess 50, so that the recess ( A step for leaving silicon nitride in 50) is performed. Therefore, the processing effect of miniaturization of the memory functional body 11 can be obtained and a sufficient offset width is secured. In the etching step of the memory functional body 11, it is more preferable to use anisotropic etching because the miniaturization in both the height direction and the width direction can be simultaneously performed. Further, this etching is preferably performed under conditions in which the material constituting the memory functional body can be selectively etched and the materials of the gate electrode 3 and the semiconductor substrate 1 are hard to be etched. For example, a wet etch process using hot phosphoric acid may be used.

However, when the same material as the semiconductor substrate 1 or the gate electrode 3 is used for the memory function, that is, the memory function has polysilicon or silicon dots and the semiconductor substrate is formed of silicon or the electrode is made of polysilicon. In the general case of forming, etc., a sufficient selectivity between these materials cannot be obtained, for example, when anisotropic etching is performed with hydrogen fluoride used as an etchant, polysilicon or The silicon dot remains unetched. In this case, it is preferable to perform further oxidation to etch with hydrogen fluoride to oxidize the etching residue to remove the residue.

Next, as shown in Fig. 15B, the deposition dielectric film 15 is formed substantially uniformly. As the deposition dielectric film, a film having good step coverage such as HTO (High Temperature Oxide) or a film using CVD (Chemical Vapor Deposition) may be suitably used. In the case of using HTO, the film thickness may be about 10 nm to 100 nm.

Next, as shown in Fig. 15C, the deposition dielectric film 15 is etched by using an etching back process, so that the second dielectric 32b forming a part of the deposition dielectric film 15 is formed as a sidewall. . The deposition dielectric film 15 is anisotropically etched so that the memory functional bodies 11 constituting the first dielectric 32a, the charge holding portion 31, and the second dielectric 32b are formed on both sides of the gate stack 8, respectively. Are formed as side walls, respectively. This etching is preferably performed under the condition that the deposition dielectric film 15 can be selectively etched and the etching selectivity to the semiconductor depth 1 is large.

In addition, as described in the eleventh embodiment, impurity implantation for the formation of the source / drain diffusion region 13 can also be made before the formation of the charge holding portion 31, and is applicable to this embodiment as well. In this case, however, the etching process for the silicon nitride 17 is performed after the step of impurity implantation.

(Example 14)

16A to 16D, a semiconductor storage device of a fourteenth embodiment of the present invention will be described.

The semiconductor reservoir of this embodiment is substantially the same as the structure of the semiconductor reservoir of the thirteenth embodiment, as shown in Fig. 16D. However, the present embodiment is characterized in that the charge holding portion 31 is formed not only inside the recess 50 but also along the entire side surface of the gate electrode 3 (via the first dielectric 32a). The charge holding part 31 may be formed so as to cover most of the side of the gate electrode 3, not the whole.

In this structure, the charge holding portion 31 made of silicon nitride, which forms a part of the memory functional element 11 and has a function of holding charge, has a dissipation preventing dielectric 32 (first dielectric 32a and a first dielectric). It is interposed between the two dielectric materials 32b. Therefore, a semiconductor storage device can be provided in which dissipation of sustain charges is suppressed and the retention characteristics are good. By providing a structure interposed between 32a and the second dielectric 32b, dissipation of charge injected into the gate electrode and other nodes during the write operation is suppressed, thereby improving charge holding efficiency and achieving high speed operation. Can be.

The manufacturing method for this semiconductor storage device may first be the manufacturing method up to FIG. 12C described in the eleventh embodiment. That is, the structure of Fig. 12C is formed in accordance with the method described in the eleventh embodiment.

Then, as shown in FIG. 16A, a first dielectric film 9 made of oxide is formed substantially uniformly along the exposed surface of the gate stack 8 and the semiconductor substrate 1. In this case, since the first dielectric film 9 in which the oxide is used is a dielectric film through which electrons pass, it is preferable that the first dielectric film 9 is a film having high withstand voltage, low leakage current, and high reliability. For example, an oxide film such as a thermal oxide film, an N ₂ O oxide film, or an NO oxide film is used as the material of the gate insulator 2. It is preferable that the thickness of an oxide is 1 nm-20 nm. In addition, when the dielectric film 9 is formed thin so that the tunneling current flows, the voltage required for injecting or erasing charges can be made low, thereby reducing power consumption. It is preferable that the general film thickness in this case is 1 nm-5 nm. In this case, since the silicon nitride 17 having the function of storing charges is in contact with the semiconductor substrate and the gate electrode through the dielectric film by forming the first dielectric film 9, leakage of sustain charges is caused by the dielectric film. This can be suppressed. Therefore, a semiconductor reservoir with good charge holding characteristics and high reliability for a long time can be realized.

Next, as the material of the charge holding portion, silicon nitride 17 is deposited substantially uniformly so that the recess 50 is buried. In this case, silicon nitride is used, but instead of silicon nitride, a material capable of holding or inducing charge, such as an oxide having an oxynitride or an oxide having a charge trap, can hold a material having charge such as electrons and holes. Material, or a material such as a ferroelectric material capable of inducing charge on the surface of a memory functional body by polarization or other phenomenon, or a material having a structure in which an oxide film contains a floating material such as polysilicon or silicon dot capable of maintaining charge You can also use In addition, when using these materials, the same processing effect occurs. However, in the case of using the conductive film, it is necessary to block the charge holding portions 31 and 31 on both sides (left and right) of the gate electrode so as not to short-circuit each other.

In this case, the film thickness of the silicon nitride 17 may be, for example, about 2 nm to 100 nm.

Next, a second insulating film, not shown, which forms at least a portion of the dissipation control insulator and is made of oxide is formed substantially uniformly along the exposed surface of the silicon nitride 17. As the second insulating film, a film having a good step coverage such as HTO or a film using CVD may be suitably used. When an oxide is used as the second dielectric film, the film thickness may be about 5 nm to 100 nm. The second dielectric film may also be formed by film surface treatment of silicon nitride by heat treatment.

Next, the second dielectric film is anisotropically etched to form second dielectrics 32b and 32b on both sides of the gate stack 8 through the first dielectric film 9 and the silicon nitride 17 as shown in FIG. 16B. Form. This etching is preferably performed under the condition that the second dielectric film 9 is selectively etched and the etching selectivity to silicon nitride is large.

Next, as shown in FIG. 16C, impurity implantation for forming the source / drain diffusion region 13 is performed. When impurities are implanted on the silicon nitride 17 and the first dielectric film 9 as in this step, it is unnecessary to form a sacrificial oxide film to prevent the surface of the semiconductor substrate from roughening. Therefore, the process can be simplified and an inexpensive semiconductor storage device can be formed.

Alternatively, this impurity implantation for forming the source / drain diffusion region 13 may be performed after the formation of the memory functional body 11. This step may also be performed on the first dielectric film 9 during formation of the memory functional body 11, that is, after formation of the charge holding portion 31 by etching the silicon nitride 17.

Next, as shown in Fig. 16D, the silicon nitride 17 is etched isotropically or anisotropically using the second dielectric 32b as an etching mask, so that the charge holding portion 31 made of silicon nitride is made of the first dielectric. It is formed on both sides of the gate stack 8 through the film 9. In this case, it is preferable that the silicon nitride 17 is selectively etched and etching is performed under conditions in which the etching selectivity with respect to the first dielectric film 9 and the second dielectric film 32b made of oxide is large.

Next, the first dielectric film 9 is anisotropically etched to form a first dielectric 32a on the sidewall of the gate stack 8. In this case, it is preferable that the first dielectric film 9 is selectively etched and etching is performed under conditions in which the etching holding ratio with respect to the charge holding portion made of silicon nitride and the gate electrode 3 and the semiconductor substrate 1 is large. .

Now, a memory functional body 11 each composed of the first dielectric 32a, the gate electrode 3, and the semiconductor substrate 1 is formed.

However, in some cases, when both the first dielectric material 32a and the second dielectric material 32b are made of the same material as an oxide, an etching selectivity may not be obtained. Therefore, in such a case, it is necessary to reduce the etching amount at the time of forming the second dielectric 32b in consideration of the etching amount of the second dielectric 32b at the time of etching the first dielectric film.

In addition, the charge holding portion 31 made of silicon nitride also tends to be somewhat etched thereon. However, this does not cause a problem, especially since it causes the miniaturization of the charge holding section, and conversely, the processing effect of the miniaturization of the charge holding section described in the thirteenth embodiment can occur.

Also, impurity implantation forming the source / drain diffusion region 13 is performed on the first dielectric film 9 and silicon nitride 17 described with reference to FIG. 16C, and implantation on the first dielectric film 9 is performed. In any case where the injection is made after the formation of the memory functional body, the source / drain diffusion region 13 can be formed by adding a desired heat treatment thereafter.

In addition, the process from the structure of FIG. 16B to the structure of FIG. 16D may be performed in one step (step of forming a source / drain diffusion region is not considered). That is, all of the first dielectric film 9, the second dielectric film, and the silicon nitride 17 can be etched, and the etching selectivity with respect to the material of the gate electrode 3 and the material of the semiconductor substrate 1 is large using the conditions. By performing anisotropic etching, it becomes possible to perform a process which originally required three steps in one step. Therefore, the number of process steps can be reduced and manufacturing costs can be reduced.

Now, through this step, the memory functional body 11 is formed. The semiconductor storage device using these memory functional bodies 11 has the following operation effects.

When charge is held in the charge holding portion 31 of the memory functional body 11, part of the channel forming region is strongly influenced by the charge, and the drain current value changes. Thus, a semiconductor storage device is formed which distinguishes the presence or absence of electric charges according to the change of the dray current value.

In addition, since the gate insulator 2 and the memory functional body 11 are disposed apart from each other, different kinds of scaling may be performed. Thus, a semiconductor storage device having a good memory effect by suppressing the short channel effect can be provided.

In addition, since the charge holding part 31 (made of silicon nitride) of the memory functional body 11 is in contact with the semiconductor substrate 1 and the gate electrode 3 through the dielectric film, the leakage of the charge held by the dielectric film This can be suppressed. As a result, a semiconductor storage device having good charge holding characteristics and high reliability for a long time is formed.

In addition, when an electric conductor or a semiconductor is used as the material of the memory functional body, when a positive voltage is applied to the gate electrode, polarization occurs in the memory functional body, and electrons are induced near the gate electrode sidewall portion, thereby forming a channel forming region. The electrons in the vicinity are reduced. As a result, electron injection from the substrate or the source / drain diffusion region can be accelerated, so that a semiconductor storage device having a high writing speed and high reliability can be formed.

(Example 15)

The semiconductor memory device of this embodiment makes it difficult for the memory functional bodies 161 and 162 to retain charges (which may be a film storing charges, which may be a film having a function of retaining charges), and to prevent charges from escaping. An area (which may be a film having a function of making it difficult for charges to escape) is included. For example, the device has an ONO structure as shown in FIGS. 17A and 17B. More specifically, the silicon nitride film 142 is sandwiched between the silicon oxide film 141 and the silicon oxide film 143 to form the memory functional bodies 161 and 162. Here, the silicon nitride film 142 exhibits a function of holding charge. In addition, the silicon oxide films 141 and 143 represent a role of a film having a function of making it difficult to release charges stored in the silicon nitride film 142.

Further, regions in which the charges in the memory functional bodies 161 and 162 can be retained (silicon nitride film 142) overlap the source / drain diffusion regions 112 and 113, respectively. Here, overlapping means that at least some of the regions capable of holding charge (silicon nitride film 142) are present on at least some of the corresponding source / drain diffusion regions 112 and 113. Reference numeral 111 denotes a semiconductor substrate, reference numeral 114 denotes a gate insulator, reference numeral 117 denotes a gate electrode, and reference numeral 171 denotes an offset region (between the gate electrode 117 and the diffusion regions 112 and 113). Although not shown, the outermost surface portion of the semiconductor substrate 111 under the gate insulator 114 becomes a channel formation region.

An advantage based on the fact that the charge retaining regions 142 in the memory functional bodies 161 and 162 overlap with the source / drain diffusion regions 112 and 113 respectively will be described.

18A and 18B are enlarged views of the memory functional body 162 and its peripheral portion on the right side in Figs. 17A and 17B. W1 represents an offset amount between the gate electrode 117 and the diffusion region 113. W2 represents the width of the memory functional element 162 in the channel longitudinal direction as seen from the cross section of the gate electrode 117. In the memory functional body 162, since the end of the silicon nitride film 142 far from the gate 117 coincides with the end of the memory functional body 162 far from the gate electrode 117, The width is defined as W2. The overlapping amount of the memory functional body 162 and the diffusion region 113 is represented by W2-W1. Especially important is that in the memory functional body 162, the silicon nitride film 142 overlaps with the diffusion region 113, that is, satisfies the relationship of W2 &gt; W1.

By the way, as shown in FIGS. 19A and 19B, in the memory functional body 162a, the end of the silicon nitride film 142a far from the gate electrode 117a is far from the gate electrode 117a. If it does not coincide with the end of 162a, the width W2 may be defined from the end of the gate electrode to the end of the silicon nitride film 142a far from the gate electrode 117a.

As a drain current in the erased state (holes are stored) in the structures shown in Figs. 18A and 18B, a sufficient current value is obtained in the configuration in which the silicon nitride film 142 and the diffusion region 113 overlap each other. However, in the configuration in which the silicon nitride film 142 and the diffusion region 113 do not overlap, the drain current abruptly decreases according to the distance between the silicon nitride film 142 and the diffusion region 113, and 3 orders (at a distance of about 30 nm). order) decreases.

Since the drain current value is almost proportional to the speed of the read operation, the memory performance deteriorates rapidly as the distance between the silicon nitride film 142 and the diffusion region 113 increases. On the other hand, in the range where the silicon nitride film 142 and the diffusion region 113 overlap, the decrease of the drain current is alleviated. Therefore, it is preferable that at least a portion of the silicon nitride film 142 and the source / drain regions overlap with each other.

In view of the above results, the memory cell array was fabricated by fixing the width W2 to 100 nm and setting the width W1 to 60 nm and 100 nm as design values. When the width W1 is 60 nm, the silicon nitride film 142 and the corresponding source / drain diffusion regions 112 and 113 overlap 40 nm as the design value, and when the width W1 is 100 nm, it does not overlap as the design value. As a result of measuring the read time of the memory cell array, the read access time was 100 times faster when the width W1 was set to 60 nm as the design value, compared with the worst case considering the deviation. In practice, it is known that the read access time is preferably 100 nanoseconds or less per bit, but it is known that such a requirement cannot be achieved under the condition of W1 = W2. In addition, in consideration of manufacturing variation, it was found that W2-W1> 10 nm is more preferable.

When reading information stored in the memory functional body 161 (region 181), the drain region 113 is used by using the source / drain diffusion region 112 as the source electrode and the diffusion region 113 as the drain region. It is preferable to form a pinch-off point on the side of the channel formation region close to the?). That is, when reading the information stored in one of the two memory functional bodies, it is preferable to form the pinch-off point in the region close to the other memory functional body of the channel forming region. Thus, regardless of the storage situation of the memory functional body 162, the stored information of the memory functional body 161 can be detected with high sensitivity, which is an important factor in realizing the 2-bit operation.

On the other hand, when information is stored in only one of the two memory functional bodies or when the memory is used with the two memory functional bodies in the same storage state, it is not necessary to always form a pinch-off point in the read mode.

Although not shown in Figs. 17A and 17B, it is preferable to form a well region (P type well in the case of an N-channel element) on the surface of the semiconductor substrate 111. By forming the well region, the impurity concentration of the channel forming region is optimized for memory operations (rewrite operation and read operation) while controlling other electrical characteristics (withstand voltage, junction capacitance, short channel effect).

From the viewpoint of improving the retention characteristics of the memory, each memory functional body preferably includes a charge holding portion and an insulating film capable of functionally retaining charge. In this embodiment, a silicon nitride film 142 having a level trapping charge is used as the charge holding portion, and silicon oxide films 141 and 143 which function to prevent dissipation of charge stored in the charge holding portion are used as the insulating film. Doing. Since the memory functional body includes the charge holding portion and the insulating film, the retention characteristics can be improved by preventing the dissipation of the charges. In addition, the volume of the charge holding portion can be appropriately reduced as compared with the case where the memory functional body is composed of only the charge holding portion. By appropriately reducing the volume of the charge holding portion, it is possible to restrict the movement of charges in the charge holding portion and to suppress any characteristic change due to charge movement in the storage holding state.

In addition, each memory functional body includes a charge holding portion disposed substantially parallel to the surface of the gate insulator, that is, the upper surface of the charge holding portion in the memory functional body is preferably disposed at the same distance from the top surface of the gate insulator. Do. Specifically, as shown in FIGS. 20A and 20B, the charge holding portion 142a of the memory functional element 162 has a surface substantially parallel to the surface of the gate insulator 114. In other words, the charge holding part 142a is preferably formed at a uniform height from a level corresponding to the surface of the gate insulator 114.

Since the charge holding portion 142a is substantially parallel to the surface of the gate insulator 114 in the memory functional element 162, the inversion layer in the offset region 171 depends on the amount of charge stored in the charge holding portion 142a. The ease of formation can be effectively controlled, and furthermore, the memory effect can be increased. In addition, since the charge holding part 142a is substantially parallel to the surface of the gate insulator 114, even if the offset amount W1 is dispersed, the change in the memory effect can be kept relatively small, and thus dispersion of the memory effect can be suppressed. . In addition, movement of charges above the charge holding portion 142a can be suppressed, and any change in characteristics due to charge movement in the storage holding state can be suppressed.

In addition, the memory functional element 162 is formed on an insulating film (eg, an offset region 171) that isolates the charge holding portion 142a substantially parallel to the surface of the gate insulator 114 and the channel forming region (or the well region). Part of the silicon oxide film 141 placed on the substrate. By this insulating film, dissipation of the charge stored in the charge holding unit 142a can be suppressed, and a semiconductor memory device having better retention characteristics can be obtained.

Further, by controlling the film thickness of the charge holding unit 142a and by controlling the film thickness of the insulating film (part of the silicon oxide film 144 placed on the offset region 171) under the charge holding unit 142a constant, The distance from the surface of the semiconductor substrate 111 to the charge stored in the charge holding portion 142a can be maintained substantially constant. That is, the distance from the surface of the semiconductor substrate to the charge stored in the charge holding portion 142a is determined by the minimum film thickness value of the insulating film under the charge holding portion 142a and the maximum film thickness value of the insulating film under the charge holding portion 142a. And the sum of the maximum film thickness values of the charge holding unit 142a. Thus, it becomes possible to generally control the density of the electric line of force generated by the charge stored in the charge holding section 142a, and to make the variation in the intensity of the memory effect of the memory element very small.

(Example 16)

In this embodiment, as shown in FIGS. 21A and 21B, the charge holding portion 142 of the memory functional element 162 has a substantially uniform film thickness, and is substantially parallel to the surface of the gate insulator 114. It is arranged (indicated by arrow 181) and has a configuration (indicated by arrow 182) that is disposed substantially parallel to the side surface of the gate electrode 117.

When a positive voltage is applied to the gate electrode 117, the electric line of force in the memory functional element 162, i.e., the electric field, moves the silicon nitride film 142 as shown by arrow 183 (arrow 182 and arrow ( Section 181) twice. In addition, when a negative voltage is applied to the gate electrode 117, the direction of the electric line of force is reversed. Here, the dielectric constant of the silicon nitride foil 142 is about 6, and the dielectric constant of the silicon oxide films 141 and 143 is about 4. Therefore, the effective relative dielectric constant of the memory functional body 162 in the direction of the electric force line (arrow 183) becomes larger than the case where only the charge holding portion indicated by the arrow 181 exists, and the potential difference between both ends of the electric force line is increased. It can be made small. That is, a large part of the voltage applied to the gate electrode 117 is used to strengthen the electric field in the offset region 171.

The charge is injected into the silicon nitride film 142 during the rewrite operation because the generated charge is attracted by the electric field in the offset region 171. Therefore, by including the charge holding portion indicated by the arrow 182, the charge injected into the memory functional body 162 during the rewriting operation increases, and the rewriting speed is increased.

By the way, when the silicon oxide film 143 portion is also replaced by the silicon nitride film, that is, when the charge holding portion is not uniform with respect to the level corresponding to the surface of the gate insulator 114, the movement of charge upward of the silicon nitride film is remarkable. As a result, the retention characteristics deteriorate.

It is more preferable for the same reason that the charge holding portion is formed of a high dielectric constant having a very high dielectric constant such as hafnium oxide instead of the silicon nitride film.

The memory functional element further includes an insulating film (part of the silicon oxide film 141 placed on the offset region 171) that isolates the charge holding portion substantially parallel to the surface of the gate insulator and the channel forming region (or well region). It is preferable. By this insulating film, dissipation of the charge stored in the charge holding portion can be suppressed, and the retention characteristics can be further improved.

Further, the memory functional body preferably further includes an insulating film (part of the silicon oxide film 141 in contact with the gate electrode 117) that isolates the gate holding portion and the charge holding portion extending substantially in parallel with the side surface of the gate electrode. This insulating film can prevent the electrical characteristics from changing due to charge injection from the gate electrode to the charge holding portion, and improve the reliability of the semiconductor memory device.

In addition, the film thickness of the insulating film (part of the silicon oxide film 141 placed on the offset region 171) under the charge holding portion 142 is controlled to be constant, and the insulating film (gate is disposed on the sidewall of the gate electrode). It is preferable to constantly control the film thickness of the portion of the silicon oxide film 141 in contact with the electrode 117. Thus, leakage of the charge stored in the charge holding unit 142 can be prevented.

According to an aspect of the present invention, at least a portion of the gate insulator and at least a portion of the memory functional body may each be made of an oxide film, the gate insulator of the substrate located below the memory functional body from the sidewall of the gate electrode opposite the memory functional body. It may have an equivalent oxide film thickness that is thinner than the equivalent oxide film thickness of a path extending through the memory functional body to the surface. Here, the "oxide equivalent thickness" is obtained by multiplying the thickness of the insulating film by the ratio of the dielectric constant of the oxide film to the dielectric constant of the insulating film. When the insulating film is composed of some dielectric layers and one of the layers is not made of an oxide film, the oxide film equivalent thickness is determined in consideration of the equivalent thickness of the nitride film layer.

The above-described structure has a structure in which the electric field strength in the path extending from the gate electrode to the substrate through the gate insulator when the voltage is applied between the gate electrode and the substrate under the gate electrode is opposite to that of the memory functional body. It means less than the electric field strength in the path extending through the memory function from the sidewall to the surface of the substrate located below the memory function. That is, in the case of the structure shown in FIGS. 21A and 21B, the gate insulator 114 is moved by an arrow 183 extending from the sidewall of the gate electrode 117 opposite the silicon nitride film 142 to the surface of the semiconductor substrate 11. It may have an equivalent oxide film thickness thinner than the equivalent oxide film thickness of the path shown. The path may be through the silicon oxide film 141, the silicon nitride film 142 and the silicon oxide film 141, or the silicon oxide film 141, the silicon nitride film 142, the silicon oxide film 143, the silicon nitride film 142, and the silicon oxide film. Extends through 141.

In view of the above description, since the equivalent oxide film thickness of the gate insulator may be smaller than that of the path extending through the memory function from the sidewall of the gate electrode opposite the memory function to the semiconductor substrate, for example, the gate insulator in this case. The threshold voltage of is used as the threshold voltage of the MOSFET can be set low, and low voltage driving with low read voltage can be realized. Therefore, a semiconductor memory device having low power consumption can be provided.

In addition, at least a part of the gate insulator and at least a part of the memory functional body may each be formed of an oxide film, and the gate insulator functions from the sidewall of the gate electrode opposite the memory functional body to the surface of the substrate located below the memory functional body. The equivalent oxide film thickness may be thicker than the equivalent oxide film thickness of the path extending through the sieve. That is, in the structure shown in FIGS. 21A and 21B, the gate insulator 114 may have an equivalent oxide film thickness that is thicker than the equivalent oxide film thickness of the path indicated by the arrow 183.

According to the embodiment described above, information can be recorded by using potentials of 10 V and 0 V for the gate electrode and the source / drain diffusion region, respectively, and -10 V and the gate electrode and the source / drain diffusion region, respectively. The information can be erased using the potential of 0V, respectively, and the drain current does not flow because the potentials of the source / drain diffusion region and the other region are the same. In addition, since the gate insulator is thick, the leakage current flowing through the gate insulator is suppressed. Therefore, a semiconductor memory device with reduced power consumption is provided. In addition, since no hot carrier is generated and no charge is injected into the gate insulator, variations in the threshold voltage due to charge injection into the gate insulator can be suppressed, and a highly reliable semiconductor memory device can be provided.

(Example 17)

This embodiment relates to the optimization of the distance between the gate electrode, the memory functional body and the source / drain regions. As shown in Figs. 22A and 22B, reference A is the length of the gate electrode viewed from the cross section in the channel longitudinal direction, reference B is the distance between the source / drain regions (channel length), and reference C is one memory function. The distance from the end of the sieve to the end of the other memory functional body, that is, from the end of the film (the side away from the gate electrode) having the function of retaining charge in one memory functional body in the cross section in the channel longitudinal direction The distance to the end (side away from the gate electrode) of the film having a function of retaining charge in the memory functional body on the side is shown.

First, it is preferable that B <C. In the channel formation region, an offset region 171 exists between a portion under the gate electrode 117 and the source / drain diffusion regions 112 and 113. By the relation B <C, the ease of inversion in all the regions of the offset region 171 is effectively changed depending on the charge stored in the memory functional bodies 161 and 162 (silicon nitride film 142). Therefore, the memory effect is increased, and in particular, the speed of the read operation is realized.

In addition, when the source / drain diffusion regions 112 and 113 are offset from the gate electrode 117, that is, when A <B, the offset region 171 when voltage is applied to the gate electrode 117. Since the ease of inversion of?) Varies greatly depending on the amount of charge stored in the memory functional body, the memory effect can be increased and the short channel effect can be reduced. However, if the memory effect occurs, the offset area 171 does not necessarily need to exist. Even if the offset region 171 does not exist, if the impurity concentration of the source / drain diffusion regions 112 and 113 is sufficiently low, the memory effect may appear in the memory functional bodies 161 and 162 (silicon nitride film 142). have.

Therefore, it is most preferable that A <B <C.

(Example 18)

As shown in Figs. 23A and 23B, the semiconductor memory device of this embodiment has a configuration substantially the same as that of the eighth embodiment except for replacing the semiconductor substrate with the SOI substrate. Here, since the substrate floating effect peculiar to the SOI substrate tends to appear, the thermoelectron generation efficiency can be improved and the recording speed can be increased.

In this semiconductor memory device, a buried oxide film 188 is formed on a semiconductor substrate 186, and an SOI layer is further formed thereon. Source / drain diffusion regions 112 and 113 are formed in the SOI layer, and other regions form the body region 187.

Further, in the semiconductor memory device, the same operation and advantages as those of the semiconductor memory device of the eighth embodiment are achieved. In addition, since the junction capacitance between the source / drain diffusion regions 112 and 113 and the body region 187 can be significantly reduced, it is possible to speed up the operation speed of the device and to reduce the power consumption.

(Example 19)

As shown in Figs. 24A and 24B, in the semiconductor memory device in this embodiment, a P-type high concentration region 191 is added adjacent to the channel side of the N-type source / drain diffusion regions 112 and 113. Except for the above, the structure is substantially the same as that of the fifteenth embodiment.

More specifically, the concentration of impurities (for example, boron) affecting the P-type in each P-type high concentration region 191 is higher than the concentration of the impurities affecting the P-type in the P-type region 192. The P-type impurity concentration in the P-type high concentration region 191 is preferably, for example, approximately 5 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 . In addition, the P-type impurity concentration in the P-type region 192 may be set to, for example, 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

When the P-type high concentration region 191 is disposed in this manner, the junction between the source / drain diffusion regions 112 and 113 and the semiconductor substrate 111 is sharply below the memory functional bodies 161 and 162. Therefore, hot carriers are more likely to occur during the write and erase operations, and the voltages of the write and erase operations can be lowered, or the write and erase operations can be made faster. In addition, since the impurity concentration of the P-type region 192 becomes relatively light, the threshold voltage when the memory is in the erased state is low, and the drain current becomes large. As a result, the reading speed is improved. Therefore, a semiconductor memory device having a low rewrite voltage, a high rewrite speed, and a high read speed can be obtained.

24A and 24B, below the memory functional bodies 161 and 162 in the vicinity of the source / drain regions 112 and 113 (that is, not directly under the gate electrode 117). By forming the P-type high concentration region 191, the threshold as a whole of the transistor is raised significantly. The extent of this rise is significantly larger than the case where the P-type high concentration region 191 is directly under the gate electrode 117. When the write charge (the former when the transistor is an N-channel type) is stored in the memory functional body, the difference in the threshold voltage is further increased. On the other hand, when sufficient erase charges (holes when the transistor is an N-channel type) are stored in the memory functional body, the threshold voltage as the entire transistor is formed in the channel formation region (P-type region 192) under the gate electrode 117. It falls to the threshold determined by the impurity concentration. That is, the threshold voltage at the time of erasing does not depend on the impurity concentration in the P-type high concentration region 191, while the threshold voltage at the time of writing is greatly influenced by the impurity concentration. Therefore, by arranging the P-type high concentration region 191 near the source / drain region under the memory functional body, only the threshold voltage at the time of writing varies greatly, and the memory effect (the threshold at the time of writing and erasing) is changed. Difference between voltages) can be increased significantly.

(Example 20)

In the semiconductor memory device of this embodiment, as shown in Figs. 25A and 25B, in the fifteenth embodiment, the insulating film 141 which separates the charge holding portion (silicon nitride film 142) from the channel forming region or the well region. Has a substantially identical configuration except that the thickness T1 is thinner than the thickness TG of the gate insulator 114.

The gate insulator 114 has a lower limit on its thickness TG from the request of the withstand voltage for the memory rewrite operation. However, the thickness T1 of the insulating film can be made thinner than the thickness TG regardless of the request for the withstand voltage. By reducing the thickness T1, the injection of charges into the memory functional bodies 161 and 162 becomes easy, and the voltages of the write and erase operations can be lowered, or the write and erase operations can be made faster. In addition, since the amount of charge induced in the channel forming region or the well region increases when the charge is stored in the silicon nitride film 142, the memory function may be enhanced.

Therefore, by setting T1 &lt; TG, it is allowed to lower the voltage of the write operation and the erase operation, or to speed up the write operation and the erase operation without lowering the breakdown voltage performance of the memory.

In addition, the thickness T1 of the insulating film 141 is more preferably 0.8 nm or more, which can maintain a constant level of uniformity and film quality by the manufacturing process, and is a limit in which the retention characteristics do not deteriorate to the extreme.

(Example 21)

In the semiconductor memory device of this embodiment, as shown in Figs. 26A and 26B, in the fifteenth embodiment, an insulating film 141 which separates the charge holding portion (silicon nitride film 142) from the channel forming region or well region. Has a substantially same configuration except that the thickness T1 is thicker than the thickness TG of the gate insulator 114.

The gate insulator 114 has an upper limit on its thickness TG from the request for preventing the short channel effect of the device. However, the thickness T1 of the insulating film 114 can be made thicker than the thickness TG regardless of the request for short channel effect prevention. By thickening the thickness T1, the charge stored in the charge storage region 142 is prevented from being lost, and the retention characteristics of the memory can be improved.

Therefore, by setting T1> TG, the retention characteristics can be improved without deteriorating the short channel effect of the memory.

In addition, the thickness T1 of the insulating film 141 is preferably 20 nm or less in consideration of the decrease in the rewriting speed.

(Example 22)

A twenty-second embodiment of the present invention is described with reference to FIGS. 30A and 30B. 30A and 30B are diagrams each showing the configuration of the IC card. As shown in Fig. 30A, an MPU (Micro Processing Unit) unit 401 and a connector unit 408 are incorporated in the IC card 400A. In the MPU unit 401, there are a data memory unit 404, a calculation unit 402, a control unit 403, a read only memory (ROM) 405, and a random access memory (RAM) 406. It is formed on one chip. In the MPU unit 401, the semiconductor device of the present invention is assembled. The various components are interconnected by wiring 407 (including data buses, power lines, and the like). When the IC card 400A is mounted on an external reader / writer, the connector 408 and the reader / writer 409 are connected, and power is supplied to the card 400A and data is exchanged. .

The characteristic of this embodiment is that the MPU unit 401 and the data memory unit 404 are formed on one semiconductor chip, thereby forming the MPU unit 401 which coexists with the data memory unit 404. As the data memory unit 404, a semiconductor memory device capable of reducing manufacturing costs is used as described in the present invention.

Since the semiconductor memory device is easy to be miniaturized and capable of 2-bit operation, the area of the memory cell array in which such devices are arranged is also easily reduced. Thus, the cost of the memory cell array can be reduced. When this memory cell array is used as the data memory section 404 of the IC card 400A, the cost of the IC card 400A is reduced.

In addition, since the data memory section 404 is included in the MPU section 401 and formed on one chip, the cost of the IC card 400A can be further reduced.

The semiconductor memory device of the present invention is used for the data memory section 404, and the semiconductor device of the present invention is used for the logic circuit section, that is, the MPU section 401 is formed of the semiconductor device of the present invention. Therefore, the elements constituting the logic circuit section (operation section 402 and control section 403) of the MPU section 401 and the formation process thereof are very similar to the case of using a flash memory, for example, and the data memory section 404 Since the and logic circuit portions can easily coexist, the coexistence mounting process is remarkably simplified. Therefore, the cost reduction effect is particularly large by forming the MPU unit 401 and the data memory unit 404 on one chip.

In addition, the ROM 405 may be composed of the semiconductor memory device. In this manner, the ROM 405 in which the program for driving the MPU unit 401 is stored can be rewritten from the outside, and the performance of the IC card 400A can be dramatically improved. Since the memory element can be easily miniaturized and two-bit operation can be performed, even if the mask ROM is replaced with the memory element, the chip area is hardly increased. In addition, since the process of forming the semiconductor memory element is almost similar to a normal CMOS forming process, coexistence with the logic circuit portion is easy.

Next, as shown in FIG. 30B, the MPU unit 401, the RF interface unit 410, and the antenna unit 411 are incorporated in the IC card 400B. In the MPU section 401, there are a data memory section 404, a calculation section 402, a control section 403, a ROM 405, and a RAM 406, which are formed on one chip. The various components are interconnected by wires 407 (including data buses, power lines, etc.).

The IC card 400B of FIG. 30B differs from the IC card 400A of FIG. 30A in that it is of a non-contact type. Therefore, the control unit 403 is connected to the RF interface unit 410 instead of the connector unit 408. The RF interface unit 410 is further connected to the antenna unit 411. The antenna unit 411 has a function of communicating with an external device and collecting power. The RF interface unit 410 has a function of rectifying and supplying power to a high frequency signal transmitted from the antenna unit 411, and has a function of modulating and demodulating the signal. In addition, the RF interface unit 410 and the antenna unit 411 may be mounted in coexistence with the MPU unit 401 on one chip.

Since the IC card 400B of this embodiment is of a non-contact type, this can prevent electrostatic breakdown that may occur through the connector portion. In addition, since it is not necessary to be in close contact with an external device, the degree of freedom of use is increased. In addition, the semiconductor memory device constituting the data memory unit 404 operates at a power supply voltage (for example, approximately 9V) lower than that of a conventional flash memory (power supply voltage of about 12V). The circuit can be miniaturized, which can reduce the cost.

(Example 23)

A twenty-third embodiment of the present invention is described with reference to FIG. The semiconductor memory device or the semiconductor device described in one of the above embodiments can be used in battery-powered portable electronic devices, in particular, portable information terminals. As a portable electronic device, a portable information terminal, a mobile telephone, a game device, etc. are mentioned. 31 shows an example of a mobile phone. In the MPU unit 501, the semiconductor device of the present invention is assembled.

Since the semiconductor device of the present invention is used in a portable electronic device, the manufacturing cost of the control circuit is reduced, so that the cost of the portable electronic device itself can also be reduced. Alternatively, the nonvolatile memory included in the control circuit can be increased in capacity, and the performance of the portable electronic device can be enhanced.

As shown in FIG. 31, in the cellular phone 500, an MPU unit 510, a man-machine interface unit 508, an RF (radio frequency) circuit unit 510, and an antenna unit ( 511 is built-in. In the MPU section 501, there are a data memory section 504, a calculation section 502, a control section 503, a ROM 505, and a RAM 506, which are formed on one chip. The various components are interconnected by wires 507 (including data buses, power lines, and the like).

The characteristic of this embodiment is that the MPU unit 501 and the data memory unit 504 are formed on one semiconductor chip, thereby forming the MPU unit 501 which coexists with the data memory unit 504. As the data memory unit 504, a semiconductor memory device capable of reducing manufacturing costs as described in the present invention is used.

Since the semiconductor memory device can be easily miniaturized and can perform 2-bit operation, the area of the memory device array in which such devices are arranged is also easily reduced. Thus, the cost of the memory element array can be reduced. If this memory element array is used as the data memory section 504 of the cellular phone 500, the cost of the cellular phone 500 is reduced.

In addition, since the data memory unit 504 is built in the MPU unit 501 and formed on one chip, the cost of the cellular phone 500 can be greatly reduced.

The semiconductor memory device of the present invention is used for the data memory section 504, and the semiconductor device of the present invention is used for the logic circuit section, that is, the MPU section 501 is formed of the semiconductor device of the present invention. Therefore, the elements constituting the logic circuit section (operation section 502 and control section 503) of the MPU section 501 and the forming process thereof are very similar to the case of using a flash memory, for example, and the data memory section 504. Since the and logic circuit portions can easily coexist, the coexistence mounting process is remarkably simplified. Therefore, the cost reduction effect is particularly large by forming the MPU unit 501 and the data memory unit 504 on one chip.

The ROM 505 may also be comprised of the semiconductor memory device. In this manner, the ROM 505 in which the program for driving the MPU unit 501 is geared can be rewritten from the outside, and the performance of the cellular phone 500 can be dramatically improved. Since the memory element can be easily miniaturized and can perform 2-bit operation, even if the mask ROM is replaced with the memory element, the chip area is hardly increased. In addition, since the process of forming the semiconductor memory element is almost similar to a normal CMOS forming process, coexistence with the logic circuit portion is easy.

The present invention has many advantages.

According to the semiconductor memory device of one embodiment of the present invention, since the charge holding portion of each memory functional body is formed not on the gate insulator of the field effect transistor but on the side of the gate electrode, the problem of over-erasing and reading failure associated therewith is substantially Is eliminated.

In addition, since there is a loss-proof insulating film for suppressing the loss of charge from the charge holding portion of the memory functional body, the charge holding time is improved.

The distance T2 between the side of the gate electrode and the charge holding portion opposing the side is formed differently from the distance T1 between the bottom portion located on the semiconductor substrate of the charge holding portion and the surface of the semiconductor substrate. Thus, for example, when the distance T1 is thinner than the distance T2, the charges injected from the semiconductor substrate can be suppressed from passing through the memory functional body to the gate electrode, and conversely, the distance T1 is larger than the distance T2. In the thick case, the charge injected from the gate electrode can be suppressed from passing through the memory functional body to the semiconductor substrate. Therefore, it is possible to obtain a semiconductor memory device having a high charge injection efficiency and a high write / erase speed.

In addition, according to the semiconductor device of one embodiment of the present invention, a semiconductor device in which a source / drain diffusion region is not offset with respect to an end of a gate electrode, and an offset semiconductor memory device are coexisted and mounted on the same substrate, The memory functional body having the function of storing is arranged on the sidewalls of the gate electrode of each of the semiconductor element and the semiconductor memory element. However, since the manufacturing process of both devices is not very different, for example, coexistence of a nonvolatile memory including a semiconductor memory element and a logic circuit including the semiconductor element is very easily realized. In addition, since the thickness of the gate insulator is not limited, a semiconductor device can be provided in which the most advanced MOSFET fabrication process can be easily applied.

In addition, according to the IC card of the embodiment of the present invention, since a nonvolatile memory, its peripheral circuit portion, a logic circuit portion, an SRAM portion, and the like can easily coexist and be mounted, a semiconductor device capable of reducing the cost can be included. Cost-saving IC cards can be provided.                     

In addition, according to the portable electronic device of the present invention, for example, the mobile phone may include a semiconductor device in which a nonvolatile memory, its peripheral circuit portion, a logic circuit portion, an SRAM portion, etc. can be easily coexist and mounted, and the cost thereof can be reduced. As a result, a cost-effective mobile phone can be provided.

In addition, according to the manufacturing method of an embodiment of the present invention for a semiconductor memory device, the film thickness of the portion of the insulating film of the semiconductor memory device in contact with the gate electrode of the device and the film thickness of the portion of the semiconductor memory device in contact with the semiconductor substrate It can be formed so as to be different from each other, thereby suppressing erasing failure during erasing or speeding up the write / erase speed. More specifically, in the case where the film thickness of the insulating film in the portion in contact with the gate electrode is formed thin, the erasure failure during erasing or the charge injected from the semiconductor substrate is suppressed. Since the exit to the gate electrode can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high writing / erasing speed can be provided. On the contrary, when the film thickness of the first insulating film in the portion in contact with the gate electrode is formed thick with respect to the film thickness of the portion in contact with the gate electrode, charges injected from the gate electrode flow out to the semiconductor substrate. Since the semiconductor device can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided.

In addition, since the source / drain diffusion region of the semiconductor memory element can be formed so as to offset the gate electrode, and can also be formed so as to overlap the charge storage region, the memory effect is good and the read operation of the semiconductor memory device. The current value at the time is greatly improved as compared with the case where the source / drain diffusion regions do not overlap. Therefore, since the read speed is also greatly improved, a semiconductor memory device having a high read speed is provided.

In addition, according to another manufacturing method of an embodiment of the present invention for a semiconductor memory device, since the semiconductor substrate and the gate electrode of the semiconductor memory device are formed using a material having a different component, the film of the portion in contact with the gate electrode of the insulating film The thickness and the film thickness of the portion in contact with the semiconductor substrate can be formed to be significantly different, thereby suppressing the erasing failure during erasing or increasing the recording / erasing speed.

Further, the step of forming the first insulating film of the semiconductor memory element so as to have a different film thickness between the portion in contact with the gate electrode and the portion in contact with the semiconductor substrate can be performed only by the usual insulating film forming process without using an etching process or the like. As a result, a semiconductor memory device which does not require complicated processes and which is low in manufacturing cost can be provided.

In addition, since the source / drain diffusion region of the semiconductor memory element can be formed so as to offset the gate electrode of the element, and can also be formed so as to overlap by the charge storage region of the element, the memory effect is good, and the semiconductor The current value during the read operation of the memory device is greatly improved as compared with the case where the source / drain diffusion region does not overlap. Therefore, since the read speed is also greatly improved, a semiconductor memory device having a high read speed is provided.

In addition, according to another manufacturing method of an embodiment of the present invention for a semiconductor memory device, since the impurity concentration of the gate electrode of the semiconductor memory device is 5 × 10 ¹⁹ cm ^-3 or more, the effect of the impurity strengthening oxidation is remarkable Appears. In the semiconductor substrate, an impurity region lower than the impurity concentration of the gate electrode is formed, and an insulating film by heat treatment is formed on the semiconductor substrate and the gate electrode. Therefore, since the film thickness of the portion in contact with the gate electrode of the first insulating film and the film thickness of the portion in contact with the semiconductor substrate can be formed differently, a semiconductor memory device having low manufacturing cost without requiring complicated processes such as etching is provided. Can be.

When the film thickness of the first insulating film in the portion in contact with the semiconductor substrate is formed thin with respect to the film thickness of the portion in contact with the gate electrode in the semiconductor memory cell, the charges injected from the semiconductor substrate are transferred to the gate electrode. Since the exit can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided.

Further, according to another manufacturing method of one embodiment of the present invention for a semiconductor memory device, the gate electrode of the semiconductor memory device has a impurity concentration of 1 × 10 ²⁰ cm ^-3 or less and lower than the semiconductor substrate of the device, so that the gate electrode In this case, it is possible to set conditions under which the effect of impurity strengthening oxidation does not occur. Since the effect of impurity strengthening oxidation starts to be remarkably higher than the impurity concentration of the gate electrode in the semiconductor substrate and is 5 × 10 ¹⁹ cm ⁻³ or more, the semiconductor As a result of forming an insulating film by heat treatment on the substrate and the gate electrode, since the film thickness of the portion in contact with the gate electrode of the first insulating film and the film thickness of the portion in contact with the semiconductor substrate can be formed significantly different, no complicated process is required and the production is unnecessary. An inexpensive semiconductor memory device can be provided. In addition, since the film thickness of the portion in contact with the gate electrode of the first insulating film and the film thickness of the portion in contact with the semiconductor substrate are significantly different, a semiconductor memory device with a remarkably fast write / erase speed can be provided.

In addition, since the film thickness of the portion in contact with the semiconductor substrate is thick with respect to the film thickness of the portion in contact with the gate electrode, the charge injected from the gate electrode can be suppressed from escaping to the semiconductor substrate. A semiconductor memory device having a good charge injection effect and a high write / erase speed can be provided.

In addition, when the film thickness of the first insulating film in the portion in contact with the semiconductor substrate is formed thin with respect to the film thickness of the first insulating film in the portion in contact with the gate electrode of the semiconductor memory device, the charge injected from the semiconductor substrate is transferred to the gate electrode. Since the exit can be suppressed, a semiconductor memory device having a good charge injection efficiency and a high write / erase speed can be provided.

Claims (57)

In a semiconductor memory device including memory cells, each memory cell, A gate insulator formed on the semiconductor substrate; A gate electrode formed on the gate insulator; A channel formation region under the gate electrode; A pair of source / drain regions disposed on both sides of the channel forming region and having a conductivity type opposite to that of the channel forming region; And A charge holding part made of a material which functions to store electric charges, and a dissipation preventing dielectric which functions to prevent dissipation of stored charges by isolating charge storage parts from both the gate electrode and the semiconductor substrate, and A memory functional body located at both sides of the gate electrode, And the distance (T2) between the sidewalls of the gate electrodes facing each other and the side of the charge holding portion is different from the distance (T1) between the bottom of the charge holding portion and the surface of the substrate. The semiconductor memory device of claim 1, wherein the distance (T2) increases as the distance from the semiconductor substrate increases. The semiconductor memory device of claim 1, wherein the distance (T2) is greater than the distance (T1). The semiconductor memory device according to claim 1, wherein an oxynitride film is formed between the charge holding portion and the gate electrode. The semiconductor memory device according to claim 1, wherein a deposition insulating film is formed between the charge holding portion and the gate electrode. 6. The semiconductor memory device according to claim 5, wherein a thermal insulator having a thickness of 1 nm to 10 nm is disposed between the deposition insulator and the semiconductor substrate. The semiconductor memory device according to claim 1, wherein the gate electrode is formed of a material having a composition different from that of the semiconductor substrate, and the distance (T2) is different from the distance (T1). The semiconductor device of claim 1, wherein the charge holding portion of the memory functional body is isolated from both the gate electrode and the semiconductor substrate by the anti-dissipating dielectric. The semiconductor substrate and the gate electrode are made of silicon, The impurity concentration in the region where the semiconductor substrate faces the memory functional body is different from the impurity concentration in the region where the gate electrode faces the memory functional body, and the distance T2 is different from the distance T1. A semiconductor memory device. The method of claim 8, wherein the impurity concentration of the gate electrode is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and the impurity concentration of the semiconductor substrate is lighter than that of the gate electrode. A semiconductor memory device. The memory of claim 1, wherein at least a portion of the gate insulator and at least a portion of the memory functional body are each made of an oxide film, and the gate insulator passes through the memory functional body from a sidewall of the gate electrode opposite the memory functional body. And an equivalent oxide film thickness thinner than an equivalent oxide film thickness of a path extending below the memory functional body to a surface of the semiconductor substrate. 2. The semiconductor memory device according to claim 1, wherein the charge holding portions respectively located on both sides of the gate electrode are configured to independently store charge. The memory of claim 1, wherein at least a portion of the gate insulator and at least a portion of the memory functional body are each made of an oxide film, and the gate insulator passes through the memory functional body from sidewalls of the gate electrode on the opposite side of the memory function. And an equivalent oxide film thickness thicker than an equivalent oxide film thickness of a path extending below the memory functional body to a surface of the semiconductor substrate. The semiconductor memory device of claim 12, wherein at least a portion of the source region and the drain region are disposed under the gate electrode. The semiconductor memory device according to claim 1, wherein the anti-dissipating dielectric of the memory functional body is made of a silicon oxide film or a silicon oxynitride film, and the charge holding part of the memory functional body is made of a silicon nitride film. The semiconductor memory device according to claim 1, wherein at least a part of the charge holding part of the memory functional body is disposed on the source or drain region. 16. The semiconductor memory device according to claim 15, wherein the charge holding portion of the memory functional body has a surface substantially parallel to the surface of the gate insulator. 17. The semiconductor memory device according to claim 16, wherein the charge holding portion of the memory functional body includes a portion extending substantially parallel to a side of the gate electrode. 17. The semiconductor device according to claim 16, wherein the semiconductor memory device includes an insulating film that isolates the charge holding portion of the memory functional body from the semiconductor substrate, wherein the insulating film has a thickness of 0.8 nm or more and thinner than the gate insulator. Memory device. 17. The semiconductor memory according to claim 16, wherein the semiconductor memory device includes an insulating film that isolates the charge holding portion of the memory functional body from the semiconductor substrate, wherein the insulating film is thicker than the gate insulator and has a thickness of 20 nm or less. Device. In a semiconductor device comprising a semiconductor memory cell and a semiconductor element, each semiconductor memory cell and semiconductor element, A gate insulator formed on the semiconductor substrate; A gate electrode formed on the gate insulator; A channel formation region under the gate electrode; A pair of source / drain regions disposed on both sides of the channel forming region and having a conductivity type opposite to that of the channel forming region; And A charge holding part made of a material which functions to store electric charges, and a dissipation preventing dielectric which acts to prevent the stored charges from dissipating, and a memory functional body respectively located at both sides of the gate electrode; , The distance between the sidewall of the gate electrode and the charge holding portion side facing each other is different from the distance between the bottom of the charge holding portion and the surface of the substrate, The source / drain region of the memory cell is disposed outside the region below the gate electrode of the memory cell, And a portion of the source / drain region of the semiconductor element is disposed under the gate electrode of the semiconductor element. An IC card comprising the semiconductor memory device according to claim 1. A portable electronic device comprising the semiconductor memory device according to claim 1. Forming a gate insulator on the semiconductor substrate and forming a gate electrode having sidewalls on the gate insulator; Forming a first insulating layer on the gate electrode and the semiconductor substrate; Partially removing the first insulating film so that the first insulating film remains on at least a sidewall of the gate electrode; A second insulating film is formed on the sidewalls of the semiconductor substrate and the gate electrode so that the second insulating film portion covering the sidewall of the gate electrode is thicker than the second insulating film portion covering the semiconductor substrate by either an oxidation or oxynitride process. Doing; Forming a charge storage region on a sidewall of the gate electrode through the second insulating layer; And Forming a source / drain region by implanting impurities into the semiconductor substrate using the gate electrode, the first and second insulating layers present on sidewalls of the gate electrode, and the charge storage region as an injection mask; A method of manufacturing a semiconductor memory, characterized in that the. Forming a gate insulator on the semiconductor substrate, and forming a gate electrode on the gate insulator, which has sidewalls and is made of a material having a composition different from that of the semiconductor substrate; Forming an insulating film on sidewalls of the semiconductor substrate and the gate electrode using heat treatment such that the thickness of the insulating film portion covering the substrate is different from the thickness of the insulating film portion covering the gate electrode sidewalls; Forming a charge storage region on a sidewall of the gate electrode through the insulating layer; And Forming a source / drain region by implanting impurities into the semiconductor substrate using the gate electrode, the insulating film on the gate electrode sidewall, and the charge storage region as an injection mask; Method of manufacturing a memory device. Forming a gate insulator on a semiconductor substrate made of silicon; A gate electrode made of silicon and having sidewalls having an impurity concentration of greater than 5 × 10 ¹⁹ cm ^{−3 and} greater than 1 × 10 ²¹ cm ^{−3 and} less than an area of the semiconductor substrate located near the surface of the gate electrode; Forming; Forming an insulating film on the sidewalls of the semiconductor substrate and the gate electrode using heat treatment such that the thickness of the insulating film portion covering the substrate is different from the thickness of the insulating film portion covering the gate electrode sidewalls; Forming a charge storage region on a sidewall of the gate electrode through the insulating layer; And And forming a source / drain region by implanting impurities into the semiconductor substrate using the gate electrode, the insulating film on the sidewall of the gate electrode, and the charge storage region as an injection mask. Method of manufacturing the device. Forming a gate insulator on a semiconductor substrate made of silicon and having an impurity concentration of at least 5 × 10 ¹⁹ cm ⁻³ and less than 1 × 10 ²¹ cm ^−3, near the surface of the semiconductor substrate; Forming a gate electrode made of silicon and having sidewalls, the impurity concentration being lighter than an impurity region near the surface of the semiconductor substrate and having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less; Forming an insulating film on sidewalls of the semiconductor substrate and the gate electrode using heat treatment such that the thickness of the insulating film portion covering the semiconductor substrate is different from the thickness of the insulating film portion covering the gate electrode sidewalls; Forming a charge storage region on a sidewall of the gate electrode through the insulating layer; And Forming a source / drain region by implanting impurities into the semiconductor substrate using the gate electrode, the insulating film present on the sidewall of the gate electrode, and the charge storage region as an injection mask; Method of manufacturing the device. An IC card comprising the semiconductor device according to claim 20. A portable electronic device comprising the semiconductor device according to claim 20. In a semiconductor memory device including memory cells, each memory cell, Semiconductor substrates; A pair of source / drain regions formed on said semiconductor substrate and isolated by channel formation regions; A gate insulator formed on the channel formation region; A gate electrode formed on the gate insulator; And Located on both sides of the gate electrode, including a memory functional element including a charge holding portion and the anti-dissipation dielectric, The charge holding region is spaced apart from the semiconductor substrate by a first distance T1 and is spaced apart from the gate electrode by a second distance T2 which is not equal to the first distance T1. . 30. The semiconductor memory device according to claim 29, wherein the second distance (T2) increases as the distance from the semiconductor substrate increases. 30. The semiconductor memory device according to claim 29, wherein the second distance T2 is greater than the first distance T1. 30. The semiconductor memory device according to claim 29, wherein the gate electrode is formed of a material having a composition different from that of the semiconductor substrate. 30. The method of claim 29, wherein the impurity concentration of the gate electrode is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, and the impurity concentration of the semiconductor substrate is lighter than that of the gate electrode. A semiconductor memory device. 30. The semiconductor memory device according to claim 29, wherein the anti-dissipating dielectric comprises a silicon oxide film or a silicon oxynitride film, and the charge holding part comprises a silicon nitride film. A field effect transistor having a gate electrode formed on the semiconductor substrate through the gate insulator and a pair of source / drain diffusion regions formed on the surface of the semiconductor substrate in a range corresponding to both sides of the gate electrode, Recesses are formed respectively so that the cross sections gradually widen laterally between both sides of the gate electrode and the surface of the semiconductor substrate, A memory functional body each consisting of a charge holding portion made of a material having a function of storing charge and a dissipation preventing dielectric having a function of preventing dissipation of stored charges is formed on both sides of the gate electrode so that the recess is buried. A semiconductor memory device. 36. The surface of the semiconductor substrate according to claim 35, wherein a surface of the semiconductor substrate is inclined adjacent to both sides of the flat portion with respect to a gate longitudinal direction to form a portion of the flat portion facing the bottom surface of the gate electrode through the gate insulator and the concave portion. And a bottom surface portion adjacent to the outer side of the inclined portion, respectively. 36. The semiconductor memory device according to claim 35, wherein a space is provided between the bottom surface of the gate electrode and the source / drain diffusion region in the gate longitudinal direction. The side surface of the said gate electrode has a flat part perpendicular | vertical to the surface of the said gate insulator, and the inclined part adjacent to the lower side of this flat part so that a part of the said recessed part may be formed, The anti-dissipating dielectric may be substantially inclined to not only the charge holding portion and the gate electrode but also the bottom portion and the slope portion of the surface of the semiconductor substrate as well as the inclined portion and the flat portion of the side of the gate electrode so that the charge holding portion and the semiconductor substrate are separated from each other. And a first dielectric covered with a uniform film thickness. 36. The semiconductor memory device of claim 35, wherein at least a portion of the charge holding portion overlaps a portion of the source / drain diffusion region. 36. The semiconductor memory device according to claim 35, wherein the charge holding portion has a portion parallel to the surface of the gate insulator. The side surface of the said gate electrode has a flat part perpendicular | vertical to the surface of the said gate insulator, and the inclined part adjacent to the lower side of this flat part so that a part of the said recessed part may be formed, And the charge holding portion includes a portion extending in parallel to the flat portion of the side surface of the gate electrode. 36. The semiconductor memory device according to claim 35, wherein the thickness of the portion of the anti-dissipating dielectric that isolates the charge holding portion and the semiconductor substrate from each other is thinner than the film thickness of the gate insulator and is 0.8 nm or more. 36. The semiconductor memory device according to claim 35, wherein the thickness of the portion of the anti-dissipating dielectric that isolates the charge holding portion and the semiconductor substrate from each other is thicker than 20 nm and less than the film thickness of the gate insulator. 38. The semiconductor memory device of claim 37, wherein at least a portion of the source / drain diffusion region is disposed on an inclined portion of the surface of the semiconductor substrate. 38. The counter region of claim 37, wherein a counter region that is more heavily doped than a channel forming region located directly below the bottom surface of the gate electrode inside the pair of source / drain regions has a conductivity opposite to that of the source / drain diffusion region. And a semiconductor memory device. 38. The semiconductor memory device according to claim 37, wherein the source / drain diffusion region has an extension on one side where a channel forming region exists, and a junction depth of the extension portion is shallower than a junction depth of portions other than the extension portion. . The semiconductor memory device according to claim 46, wherein an impurity concentration of the extension portion is lighter than an impurity concentration of a portion of the source / drain diffusion region other than the extension portion. 38. The semiconductor memory device according to claim 37, wherein said charge holding portion of said memory functional body is accommodated in a recessed portion. A memory region having a semiconductor memory element and a logic circuit region having a semiconductor switching element, wherein both the memory region and the logic circuit region are provided on a semiconductor substrate, The semiconductor memory device and the semiconductor switching device are respectively operated by field effect transistors each having a pair of source / drain diffusion regions and gate electrodes formed in portions of the surface of the semiconductor substrate corresponding to both sides of the gate electrode, In either of the semiconductor memory element and the semiconductor switching element, recesses each formed to have a wider cross section laterally are formed, and a charge holding portion made of a material having a function of storing charge and preventing the dissipation of stored charges are prevented. Memory functional bodies each composed of a dissipation preventing dielectric having a function are formed on both sides of the gate electrode such that the recess is buried, The semiconductor memory device, when a voltage is applied to the gate electrode, based on the level of charge held in the charge holding portion, the amount of current flowing from one source / drain diffusion region to the other source / drain diffusion region. Is designed to change, And the semiconductor switching element is configured to perform a switching operation irrespective of the level of charge held in the charge holding portion. An IC card comprising the semiconductor memory device according to claim 35 mounted thereon. An IC card comprising the semiconductor device according to claim 47 mounted thereon. A portable electronic device comprising the semiconductor memory device according to claim 35 mounted thereon. A portable electronic device comprising the semiconductor device according to claim 47 mounted thereon. In the step of forming a semiconductor memory device consisting of a field effect transistor, Forming a gate electrode on the semiconductor substrate surface through the gate insulator; Forming a beak dielectric film having a laterally wider cross section between both sides of the gate electrode and the surface of the semiconductor substrate; Removing the beak film to form a recess in which the cross-section is gradually widened in a position where the beak dielectric film is removed; Forming a memory functional body on both sides of the gate electrode such that the recess is filled with a charge holding part made of a material having a function of storing charge and a dissipation preventing dielectric having a function of preventing the dissipation of stored charge; Using the gate electrode and the memory functional body as a mask, implanting impurities into surface portions of the semiconductor substrate corresponding to both sides of the mask to form a pair of source / drain diffusion regions; Method of manufacturing a memory device. 55. The method of claim 54, wherein forming the memory functional body Forming a first insulating layer between at least one of the recesses to form at least a portion of the anti-dissipating dielectric material with a substantially uniform film thickness along the exposed surface of the semiconductor substrate and the gate electrode; Forming silicon nitride as a material of the charge holding part on the exposed surface of the first insulating film so that the recess is buried; And Etching the silicon nitride and the first insulating film on both sides of the gate electrode so that the memory functional bodies remain on both sides of the gate electrode, respectively. 56. The method of claim 55, wherein in the etching of the silicon nitride and the first dielectric film, portions of the silicon nitride other than the recess are removed such that portions of the silicon nitride existing in the recess remain. Method of manufacturing a semiconductor memory device. A method of manufacturing a semiconductor device in which semiconductor memory elements each composed of field effect transistors are formed in a memory region set on a semiconductor substrate, and semiconductor switching elements each composed of field effect transistors are formed in a logic circuit region set on a semiconductor substrate. Forming a gate electrode on a portion of a surface of the semiconductor substrate corresponding to the memory region and the logic circuit region through a gate insulator, respectively; In both the memory region and the logic circuit, a bird dielectric film is formed in which the cross-section is gradually widened laterally between the semiconductor substrate surface and the both side portions of the gate electrode, and is laterally cross-section in place of the bird dielectric film being removed. Removing the beak dielectric film to form a gradually widening recess; Forming a first doped region in the logic circuit to form a portion of a source / drain diffusion region by introducing impurities into the logic circuit region using the gate electrode as a mask so as not to introduce impurities into the memory region; In both the memory region and the logic circuit region, a charge holding portion made of a material having a function of storing charge and a dissipation preventing dielectric having a function of preventing dissipation of stored charge on both sides of the gate electrode such that the recess is buried. Forming a memory functional body each composed of; A second dope forming the at least a portion of the source / drain diffusion region by using the gate electrode and the memory functional body as a mask and implanting the same impurities as the conductive type of the previous step into the memory region and the logic circuit region, respectively; And forming a region.

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