TWI248201B - Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card - Google Patents

Abstract

A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on opposite sides of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) is adapted to differ from a distance between a bottom of the charge retaining portion and a surface of the substrate (T1).

Description

[Technical Field] The present invention relates to a semiconductor memory device, a semiconductor device, and a method of manufacturing the same, a portable electronic device, and an IC card. In particular, the present invention is well suited for use in electronic erasable and programmable semiconductor memory devices and methods of fabricating the same. [Prior Art] Electronic erasable and programmable memory elements are, for example, flash memory. A cross-sectional view of the structure of a general flash memory device is shown in FIG. This element has a structure in which a floating gate 906 made of polycrystalline germanium is disposed over the semiconductor substrate 901 via the first oxide film 904, and a control gate 907 made of polysilicon is formed via the second oxide film 905. The floating gate 906 is disposed on the floating gate 906, and the pair of source diffusion regions 902 and the drain diffusion region 903 are disposed on and in the surface of the semiconductor substrate 901. The control gate 907 can be used as a gate electrode of a field effect transistor (FET) in a flash memory. Further, the first oxide film 904, the floating gate 906, and the second oxide film 905 are interposed between the control gate 907 and the semiconductor substrate 901. That is, the flash memory is a memory in which a memory film (floating gate) is disposed in a gate oxide film portion of the FET, thereby changing the FET according to the amount of charge stored in the memory film. The function of the limit voltage (refer to, for example, "Handbook of Flash Memory Technology" edited by Fujio Masuoka, published by Kabushiki Kaisha Science Forum, August 15, 1993, pp. 55-58). The flash memory of the above structure causes a problem of so-called "over-erase". 91971.doc 1248201 More specifically, (iv) the erase operation of the memory is to reduce the limit voltage of the FET in the flash memory by capturing the electrons stored in the floating pole or injecting the hole into the floating gate. . However, since the erase operation is excessively performed, any electric power a is not applied to the gate electrode, and is turned on under the influence of the charge stored in the floating gate under the gate electrode (9), that is, the control gate). Therefore, current will flow through the source diffusion region and the drain diffusion region. This phenomenon is caused by the structural characteristics of the flash memory below: the control gate of the gate electrode of the fet and the floating gate of the memory film of the memory are extremely vertically stacked. Therefore, no voltage is applied to the control gate. F Ε τ will only turn on due to the stored charge of the floating gate. This can result in leakage currents in unselected memory cells. Therefore, such a defective reading occurs because the leakage current cannot detect the read current of the selected memory cell. SUMMARY OF THE INVENTION The present invention has been made in view of such a situation and includes providing a semiconductor memory

Devices, semiconductor devices, and methods of manufacture thereof, portable electronic devices, and IC cards have all been modified for over-erasing and defective readings associated therewith. A specific embodiment of the present invention may provide a semiconductor memory device including a memory cell, each memory cell comprising: a gate insulating film formed on a semiconductor substrate; one of the gate insulating films formed on the gate insulating film a gate electrode; a channel region under the gate electrode; one of the source region and the drain region disposed on the opposite side of the channel region, and the conductivity type of the source region and the gate region is opposite to the channel region And a memory functional unit respectively located on the opposite side of the gate electrode, each memory functional unit includes: a charge 91971.doc 1248201 guaranteed = part and a primary resistant insulator, the charge retaining portion is made of a material for storing charge Formed, the anti-consumable insulator is used to separate the electric (four) remaining portion from the "ping gate electrode and the substrate to prevent the consumption of the stored charge, wherein the gate electric wall and the charge retaining portion are adapted to be opposite each other The distance (T2) between one side is different from the distance (τι) between the bottom of the charge retaining portion and the surface of the substrate. + According to a semiconductor memory device according to an embodiment of the present invention, the charge retention portions are respectively located on opposite sides of the closed electrode, not on the gate insulating film of the field effect transistor, so that there is no excessive erasure and related thereto The defective delta buy problem. Further, there is an anti-consumable insulating film capable of suppressing the charge consumption of the charge-retaining portion of the memory functional unit, so that the time of charge retention can be increased. The above distance (Τ2) is different from the above distance (Ti), so that when the distance T1 is made, for example, less than the distance D2, the electro-optical tooth-filled 3 functional unit injected from the semiconductor substrate can be restricted. Entering the gate electrode, conversely, when the distance T1 is made larger than the distance D2, it is possible to restrict the charge injected from the gate electrode from penetrating the memory functional unit into the semiconductor substrate. Therefore, a semiconductor memory device with high charge injection efficiency and high write/erase speed can be obtained. [Embodiment] A semiconductor memory device according to an embodiment of the present invention includes: a semiconductor memory device mainly including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, formed in the gate insulating a gate electrode on the film is disposed in one of the channel regions under the gate electrode, and is disposed on one side of the channel region on a pair of source diffusion regions and a drain diffusion region, and a conductivity type thereof and the 91971.doc 1248201 channel The opposite side of the conductivity type of Q and the memory function unit disposed on both sides of the gate electrode, and each memory function unit include: a charge retention portion made of a material having a function of storing charge, and having a stored charge prevention portion One of the functions of charge dissipation is the resistance to the insulator, wherein the distance between the sidewall of the gate electrode and the charge-retaining portion opposite to the sidewall (T2) and the distance between the side of the semiconductor substrate and the bottom of the charge-retaining portion on the front surface of the semiconductor substrate (T1) is different. As used herein, the terms "source region and bungee region" refer to a diffusion region that can serve as a source region or a bungee region. These source and drain regions are sometimes referred to individually as "source regions" or "bungee regions"; however, it should be understood that any region can be source or drain depending on the circuit configuration. A semiconductor memory device according to a specific embodiment of the present invention is basically a MOS circuit, and it is preferable to adhere a circuit including a MOS circuit to an early + conductor substrate. In the semiconductor memory device of the semiconductor memory device according to the specific embodiment of the present work, the path w μ and the dry distance Τ 2 may increase as the distance from the measurement distance of the substance increases. In the above aspect, the charge-retaining portion is formed such that the distance between the upper portion and the gate electrode is lower than the lower portion of the gate electrode. Therefore, it is possible to suppress the excess electricity g from being injected into the upper portion of the remaining portion. It can suppress the net dispersion of excess current. It is also effective to suppress, for example, erasing the electron injection of the gate phase which occurs in the taper. Going again, the lower part is not as far as the upper part, so it can form what will be retained without having to be separated from the channel area. By the above, it is not necessary to reduce the difference between the read/erase mode of read a ^, 91971.doc -10- 1248201 can suppress the injection and dissipation of excess current. In the semiconductor memory device, the distance 2 is greater than the distance T1. In the above aspect, since the distance D is smaller than the distance D2, the electron injection of the gate electrode in the erasing mode can be suppressed, and a semiconductor memory device in which the erasing of the defect is suppressed can be provided. Furthermore, in a specific embodiment of the semiconductor memory device, an oxygen nitride film can be formed between the charge retention portion and the gate electrode. In the above aspect, the electron injection of the closed electrode in the erasing mode can be remarkably suppressed, so that it is possible to provide a semiconductor memory that has been suppressed from being erased, or a specific implementation in the +conductor memory device. In the column, a deposited insulating film is formed between the charge-retaining portion and the gate electrode. In the above aspect, a thick film of a deposited insulator having a good uniformity can be formed between the charge-retaining portion and the closed electrode, and deterioration due to occurrence of irregularities (ie, coarse build-up) on the gate electrode can be suppressed. Therefore, it is possible to suppress the electron injection of the intermediate electrode of the mode, and to provide a semiconductor memory device which has been suppressed from being erased. Further, in the embodiment of the semiconductor memory device, the deposition insulator and the semiconductor substrate are disposed to have a thickness of between ι Mn^. (10) Thermal insulation between (including 1 and 10). Nm, in the above aspect, between the insulating film and the semiconductor device, the insulating film and the thickness of the dielectric film are included (including the thermal insulator). Therefore, between the thermal body and the semiconductor substrate The interface has a good, ·, good shape, can suppress the current 91971. Doc 1248201, and can get a larger drive current, the mobility of the interface through the interface is degraded, thus providing a semiconductor memory device with faster read speed. In addition, since the film thickness of the thermal insulator is at least i nm, the interface characteristics can be effectively increased, and since the film thickness is at most 1〇11111, deterioration due to unevenness can be suppressed. In a specific embodiment of the semiconductor memory device, the gate electrode has a different material composition than the substrate, and the distances T2 and T1 are different. When the material composition of the gate electrode is different from that of the substrate, the distance 仞 and the distance T1 (that is, the thickness of the anti-consumable insulating film formed on the semiconductor substrate and the sidewall of the gate electrode) can be made very different, and a higher charge injection efficiency can be provided. And a semiconductor memory device with high write/erase speed. In a specific embodiment of the semiconductor memory device, the charge retention portion of the memory functional unit can be separated from the gate electrode and the substrate by the anti-consumption insulator, and the substrate and the gate electrode are made of tantalum, and The impurity concentration of the region of the substrate facing the memory functional unit is different from the region of the gate electrode facing the memory functional unit, and the distances D and T1 are different. Here, the wording "made of 矽" can be expressed in detail as "a substance made of ruthenium as the main raw material". Specifically, the main material may be a single crystal germanium, a polycrystalline germanium, or an amorphous germanium containing impurities. In the above aspect, the semiconductor substrate and the gate electrode can be formed by a conventional semiconductor device material, and thus can constitute a semiconductor program which is very similar to a usual semiconductor process, and a semiconductor memory device which provides a low manufacturing cost. Furthermore, in a specific embodiment of a semiconductor memory device, the gate is 91971. Doc -12 - 1248201 The impurity concentration of the electrode is 1 χ ΙΟ 20 cm -3 or more, and the impurity concentration of the substrate is lower than that of the gate electrode. In the above aspect, the film having the lower impurity concentration and the anti-consumable insulator may be relatively thinner with respect to any of the gate electrode and the semi-body substrate made of Shi Xi. Furthermore, since the number of miscellaneous beetles is at least 1 X 1 〇 2 〇 cm-3, the effect of enhanced oxidation of impurities will be apparent, and the film on the corresponding region will become thicker. Therefore, the difference in film thickness can be significant. Thus, it is possible to provide a semiconductor memory device with significantly good charge injection efficiency and a significantly high write/erase speed. However, since the concentration of impurities contained in the crucible is still limited, it is taken as: 21 cm-3. Further, the impurity concentration should preferably be at least 1 , because the impurity concentration of the semiconductor substrate is generally 1 〇 15 cnT3. Alternatively, in a specific embodiment of the semiconductor memory device, the impurity concentration of the gate electrode of the semiconductor: memory element may be at least 〇2. The impurity concentration of the cm* semiconductor substrate may also be lower than that of the gate electrode. In the above aspect, the impurity concentration of the gate electrode which is made up of the chip is higher than that of the conductor substrate, and the insulating film of the side wall of the electrode becomes thicker. Furthermore, it is determined by the fact that the _ degree of the electrode is at least 〇2. - 'The effect of the enhanced oxidation of the shells will be noticeable' & The film on the gate electrode will become thicker, so the difference in film thickness will be apparent. Thus, it is possible to provide a semiconductor memory device with significantly good charge injection efficiency and a significantly high write/erase. However, since the impurity concentration of the person 3 in the second is limited, that is, the 绂L L ^ 15 3 homing, and the maximum is 1〇21 cm-3. In addition, the impurity concentration should preferably be at least 10 cm·3, and the impurity concentration of the semiconductor substrate is 10i5 91971. Doc -13- 1248201 cm"*3 rating. In a specific embodiment of the semiconductor memory device, the gate insulating film is made of an oxide film and the gate insulating film is oxidized by at least a portion of the gate insulating film and at least a portion of the memory functional unit. The equivalent thickness of the film is less than the equivalent of the oxide film equivalent of the oxide film extending from the sidewall of the gate to the opposite side of the functional unit of the memory element, and the path of the substrate to the surface of the substrate under the functional unit of the memory. And order. Here, the "equivalent thickness of the oxide film" is an equivalent thickness of the oxide film obtained by comparing the thickness of the insulating film, the dielectric constant of the oxide film, and the dielectric constant of the insulating film. When the insulating film contains some dielectric layers and one of the layers is not made of a tantalum oxide film, but is made of, for example, a nitride film, the nitride film layer or the like is considered in determining the equivalent thickness of the oxide film. Value thickness. The above structure means that an electric field intensity is applied between the gate electrode and the substrate under the gate electrode, and the electric field intensity in the path extending from the gate insulating film to the substrate is less than that from the opposite side wall of the gate electrode and the memory functional unit. § The electric field strength of the functional unit in the path of the substrate surface under the memory functional unit. In the above aspect, since the equivalent thickness of the oxide film of the gate insulating film is smaller than the path from the gate electrode and the opposite side wall of the memory functional unit to the semiconductor substrate through the memory function sheet 70, the case may be In the middle (for example, in the case where the gate insulating film is used as the gate insulating film of the MOSFET), the write-off a is low, so that low-voltage driving with a low read voltage can be realized. Therefore, it is possible to provide a semiconductor memory device with low power consumption. Furthermore, in a specific embodiment of the semiconductor memory device, the charge retention portion on the opposite side of the gate electrode can be adjusted to independently store electricity. Doc -14- 1248201 Lotus. In the above aspect, the charge can be retained in the two mutually independent charge retaining portions VIII, so that each memory cell can store four values of δ ΐ ' and thus can provide an increased capacity of the semiconductor memory. In a specific embodiment of the semiconductor memory device, at least a portion of the gate insulating film and at least a portion of the memory functional unit are each formed of an oxide film, and an oxide film of the gate insulating film has an equivalent thickness greater than The sidewall opposite the gate electrode and the memory functional unit extends through the memory functional unit to the oxide film equivalent thickness of the path of the substrate surface under the memory functional unit. In the above aspect, for example, by applying a potential of 10 volts and 0 volts to the gate electrode and the source diffusion region and the drain diffusion region, respectively, the beixun can be written by the gate electrode and The source diffusion region and the drain diffusion region respectively impose a potential of -10 volts and volts to erase the information, so the buckling current is the same because the potential of one of the source diffusion region and the drain diffusion region is the same. Will not flow. Further, the gate insulating film is thick, and it is possible to suppress leakage current through the gate insulating film (4). Therefore, a semiconductor memory device which reduces power consumption can be provided. Moreover, no hot carrier is generated, and no charge is injected into the gate, so that a constant voltage difference due to charge injection into the dummy insulating film can be suppressed, thereby providing a highly reliable semiconductor memory. Device. Further, in the semiconductor 5 memory element, at least a portion of the source region and the drain region may be disposed under the gate electrode. In the above aspect, the six-member J body|body embodiment, since the source region and the 汲 91971. Doc -15- Ϊ248201 At least a part of the polar region is disposed under the gate electrode, so the semiconductor memory device has the same structure as the ordinary field effect transistor, so that the vertical system can be changed to a flat f field with a specific practical result to this point. Electro-optic crystal program, = Semiconductor memory device capable of providing low manufacturing cost. In a specific embodiment of the semiconductor memory device, the highest position of the charge retention is lower than the highest position of the gate electrode. In the above aspect, the charge retention portion can be disposed only near the channel. As a result, electrons injected by writing can be confined near the channel: thus can be easily removed by erasing. Because of this, you can prevent the error from being erased. Moreover, the number of singular electrons is not changed by limiting the charge retention portion, and the electron density is increased, so that it is possible to effectively write a semiconductor memory device with a high write/erase speed. In a specific embodiment of the semiconductor memory device, the highest position of the charge retaining portion is lower than the highest position of the first insulating film. In the above aspect, since the highest position of the charge retaining portion is lower than the highest position of the first insulating film, the shortest distance between the gate electrode and the charge retaining portion becomes long. As a result, it is possible to prevent the gate electrode and the region made of the material having the charge storage function from being short-circuited during the deuteration, the wiring step, and the like, so that a high usable percentage of the semiconductor memory device can be formed. In a specific embodiment of the semiconductor memory device, the charge retention portion comprises a plurality of crystal grains having a function of storing charge. In the above aspect, the charge retention portion can be restricted to a smaller area, so that erroneous erasure can be prevented more effectively. Moreover, since the charge retention portion is divided into crystal #, even if a leak occurs, the shallow drain region contains only: 91971. Doc -16- l2482〇l Summer granules can thus improve retention characteristics. Moreover, since a region made of a material having a function of storing a charge can be formed, for example, a shape of a nano-dots, it is possible to particularly enhance the memory effect due to the Coulomb blocking effect, thereby forming a semiconductor having extremely long-term reliability. Memory component. In a specific embodiment of the half V body a body member, the anti-consumable insulator may also include a separate charge retaining portion and a gate electrode and a separate insulating material to protect the substrate from the first insulating film, and in the charge retaining portion. The side wall portion of the side wall portion opposite to the 2 bar and the ruthenium film has a side wall and a rim body; and the package portion can also be sandwiched between the first insulating film and the side wall insulator. In the aspect described, 'the electrons injected by the writing can be confined in the charge retaining portion' and thus can be easily removed by erasing, thereby preventing erroneous erasure. Moreover, the volume of the charge retention portion can be reduced without changing the amount of charge injected, so that the amount of charge per unit volume can be increased, the electrons can be efficiently written/erased, and the semiconductor memory providing high write/erase speed can be obtained. Device. Further, in a specific embodiment of the semiconductor memory device, the charge retention portion may be covered by the first insulating film and the second sidewall insulator. In the above aspect, since the charge retaining portion is covered with the second side wall insulator, it is possible to prevent the charge remaining portion and the contact from being short-circuited at the step of forming the gate electrode contact. m is that the design tolerance of the size of the contact portion can be made smaller, so that a finer semiconductor device can be manufactured. Therefore, it is possible to provide a semiconductor memory device with reduced cost. Alternatively, in a specific embodiment of the semiconductor memory device, the anti-consumer insulator of the memory functional unit can also be oxygen-cut or nitrided = 91971. Doc -17- 1248201 made, made. And the charge retention portion of the memory functional unit can also be nitrided. In this case, a large hysteresis can be obtained due to the tantalum nitride film, in which many levels of trapping are included. ^ » Special student. Moreover, the electron retention time of the nitrided hair film is very long, and the problem of charge = caused by the leak path is relatively poor, so that favorable retention characteristics can be obtained. Moreover, the materials that are most commonly used in their materials' can therefore reduce manufacturing costs. In a specific embodiment of the semiconductor memory device, the charge retention portion includes: a plurality of crystal grains having a (IV) charge storage function, and a plurality of crystal grains and gate electrodes and a plurality of crystal grains and a semiconductor substrate. A semiconductor film or a conductor film. In the above aspect, the influence of the position and size spread of the crystal grains on the threshold voltage of the field effect transistor can be suppressed by inserting the semiconductor or the conductor, and thus it is possible to provide a semiconductor memory device which is less likely to have a reading error. Alternatively, in a specific embodiment of the semiconductor memory device, at least a portion of the charge retention portion of the memory functional unit can be disposed over the source region or the non-polar region. In the above aspect, the current value of the reading operation of the semiconductor memory device can be remarkably improved, and the reading speed of the device can be remarkably improved, so that a semiconductor memory device having a high reading speed can be provided. Moreover, in a specific embodiment of the semiconductor memory device, the charge retention portion of the memory functional unit has a surface substantially parallel to the surface of the gate insulating film. In the above aspect, the number of charges remaining in the electron-retaining portion can be 91971. Doc • 18- 1248201 The amount effectively controls the convenience of forming a reverse layer in the offset region, thus enhancing the memory effect. Further, even if there is a difference in the offset size, a relatively small memory effect change can be maintained, so that the spread of the memory effect can be suppressed. Still further, in a specific embodiment of the semiconductor memory device, the charge retention portion of the memory functional unit includes a portion that extends substantially parallel to the side of the gate electrode. In the above aspect, the charge injected into the charge retaining portion is increased in the rewriting operation', and thus the rewriting speed can be improved. Furthermore, in a specific embodiment of the semiconductor memory device, the semiconductor memory device may also include an insulating film separating the charge retention portion from the substrate in the memory functional unit, and the insulating film is thicker and thicker than the gate insulating film. Is 0. 8 nm or more. In the above aspect, it is helpful to inject a charge into the charge retaining portion, and it is possible to lower the voltage of the writing operation and the erasing operation or to increase the speed thereof. In addition, the number of charge charges in the channel region or the well region is increased when the charge is retained in the charge retention portion, thereby enhancing the memory effect. Further, since the thickness of the insulating film separating the charge retaining portion and the semiconductor substrate is at least 0. 8 nm, thus suppressing extreme degradation of retention characteristics. Alternatively, the semiconductor memory device according to an aspect of the present invention may further comprise an insulating film separating the charge remaining portion and the substrate in the memory functional unit, the insulating layer being thicker than the gate insulating film and having a thickness of 20 nm or less. In the above aspect, since the thickness of the film separating the charge retaining portion and the semiconductor substrate is larger than the thickness of the gate insulating film and at most 2 〇 leg, since 91971. Doc -19- 1248201 This can improve the retention characteristics of the memory without deteriorating its channel effect. Further, since the thickness of the insulating film separating the charge remaining portion and the semiconductor substrate is at most 20 nm, the reduction in the rewriting speed can be suppressed. A specific embodiment of the present invention further provides a semiconductor device of the present invention, the device comprising: a semiconductor memory unit and a semiconductor component, the semiconductor memory cell and the semiconductor component each comprising: one formed on a semiconductor substrate a gate insulating film; a gate electrode formed on the gate insulating film; a channel region located under the gate electrode; and a source region and a drain region disposed on opposite sides of the channel region, the source The conductivity type of the polar region and the non-polar region is opposite to the channel region; and the memory power month b unit respectively located on the opposite side of the gate electrode, each memory functional unit includes: a charge retention portion and an anti-consumption insulator The charge retention portion is made of a material for storing a charge for preventing consumption of the stored charge, wherein a distance between a sidewall of the gate electrode and a side of the charge retention portion opposite to each other is adapted to The distance between the bottom of the __charge retention portion and the surface of the substrate is different, wherein the source region and the drain region are configurable in the memory unit in the memory unit Outside the region under the gate electrode of the element, and the portion of the source region and the gate region can be disposed under the electrode between the semiconductor elements in the semiconductor element. Therefore, the semiconductor diffusion element which is not offset from the end portion of the gate electrode and the semiconductor portion of the (4) political region, and its offset semiconductor memory device, are coexistent on the same substrate, ... will have a stored charge The function of the memory 匕 匕 70 is placed in each semiconductor element and semiconductor memory element, 'although the side wall. However, due to the small difference in the process of these two components, g 91971. Doc -20-1248201 = Easy to implement, for example, the coexistence of a non-memory body formed of a semiconductor memory element and a logic circuit formed of a semiconductor element. Since =' does not limit the thickness of the gate and the insulating film, it is possible to provide a semiconductor device that can be easily applied to the most advanced MOSFET process. Furthermore, in a specific embodiment of the semiconductor device of the present invention, the non-electrical memory portion includes a semiconductor memory device. In the above aspect, the non-electrical memory portion is composed of a plurality of such half-body memory elements and the logic circuit portion is constituted by such a semiconductor element. Therefore, it is possible to realize a semiconductor device including a non-electric memory portion and a logic circuit portion which are easily adhered to the same substrate. Furthermore, the semiconductor device 1 of one embodiment of the present invention includes logic portions that are driven lower than the supply voltage supplied to the non-electrical memory portion. In the above aspect, the high supply voltage can be supplied to the non-electrical memory blade as an example, and thus the writing/erasing speed can be remarkably improved. Further, the low supply voltage can be supplied to the logic circuit portion, so that degradation of the transistor characteristics due to the gate insulating film can be suppressed, and low power consumption can be achieved. Therefore, it is possible to realize a semiconductor device including a portion of a logic circuit which is easy to adhere to a high reliability on the same substrate, and a non-electrical memory portion having a particularly high write/erase speed. Moreover, the semiconductor device according to an embodiment of the present invention further includes a static random access memory composed of the ijL conductor, and the logic circuit portion and the static random access memory. 91971. Doc -21 - 1248201 is made up of half-body components, -,, and raw. The part of the body is made up of semiconductors. Therefore, it is possible to realize a semiconductor device including a portion in which the same circuit portion, a static random access memory (4), and a non-electrical portion are easily coexisted. Furthermore, SRAM coexistes as a high-speed operating memory or temporarily staggering memory for more performance. According to the invention, the 1c card of the present invention comprises the above semiconductor memory device or + conductor device. Therefore, the card can include a non-electrical memory and its peripheral circuit portion, the X-circuit circuit portion, the SRAM portion, etc., which are easily adhered to each other and can reduce the cost thereof, thereby providing a low-cost IC card. Furthermore, the portable electronic device of the present invention includes the above semiconductor memory device or semiconductor device. Therefore, the 'for example' portable telephone may include a non-electrical memory and its peripheral circuit portion, a logic circuit portion, an SRAM portion, etc., which are easily adhered to and coexist and can reduce the cost of the semiconductor device', thereby providing a low-cost portable telephone. . In another aspect, the present invention provides a method of fabricating a semiconductor memory device, the method comprising a bamboo column (4): forming a gate insulator on the semiconductor substrate and forming an inter-electrode on the gate insulating film; Forming a "first" insulating film on the gate electrode and the semiconductor substrate; partially removing the first insulating film such that the first insulating film remains on at least a sidewall of the closed electrode; Forming a first insulating film on the substrate and the sidewall of the gate electrode, so that the second insulating layer covering the sidewall of the gate electrode is 91971. Doc -22- 1248201 The film is divided by a portion of the second insulating film overlying the substrate; a charge storage region is formed on the sidewall of the gate electrode via the second insulating film; and the gate electrode is present by using the gate electrode The first insulating film and the second insulating film on the sidewall of the gate electrode and the charge storage region serve as implant masks to implant impurities into the substrate to form a source region and a drain region. Therefore, the thickness of the contact portion of the element insulating film of the semiconductor memory with the gate electrode and the thickness of the contact with the semiconductor substrate can be made very different, thereby suppressing the defective erasing of the erase mode or increasing the writing/erasing speed. More specifically, in the case where the portion where the insulating film is in contact with the semiconductor substrate is formed to be thin with respect to the portion where the insulating film is in contact with the gate electrode, the defective erase of the eraser type can be suppressed, or the semiconductor substrate can be prevented from being blocked. The injected charge penetrates the insulating film to reach the gate electrode, and thus can provide a semiconductor memory device with good charge injection efficiency and south write/erase speed. Conversely, in a case where a portion where the first edge film is in contact with the semiconductor substrate is formed thicker than a portion where the first insulating film is in contact with the inter-electrode, the charge injected from the gate electrode can be prevented from penetrating the first insulating film to the semiconductor. The substrate can thus provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. Moreover, the formation of the source diffusion region and the drain diffusion region of the semiconductor memory device can be offset with respect to the gate electrode and can overlap with the charge storage region, so that the memory effect is favorable, and the source diffusion region is higher than that in the source diffusion region. The fact that the polar diffusion region does not overlap with the charge storage region significantly increases the current value of the readout of the semiconductor memory device. As a result, the reading speed can be remarkably increased, and thus a semiconductor memory device with a high reading speed can be provided. On the other hand, the present invention further provides the production of a semiconductor memory device 9197l. D〇, -23- 1248201, the method comprising the steps of: forming a gate insulating film on a semiconductor substrate and forming a gate electrode on the (tetra) insulating film, the gate electrode being made of a different material composition than the substrate Forming an insulating film on the substrate and the sidewall of the dummy electrode using heat treatment, such that a portion of the insulating film covering the substrate is different in thickness from a portion of the insulating film covering the sidewall of the gate electrode; the gate is via the insulating film Forming a "charge storage region" on the side wall of the electrode; and by using the gate electrode, the insulating film existing on the sidewall of the gate electrode, and the material of the charge storage region implanting the substrate (4) into a source region and Polar zone. Therefore, since the semiconductor substrate and the gate electrode of the semiconductor memory device are formed using materials of different compositions, the thickness of the contact portion of the insulating film and the gate electrode and the thickness of the contact portion of the insulating film and the semiconductor substrate can be made very different. In addition to the defective erasure of the mode, or increase the write/erase speed. Further, it is not necessary to employ an etching step or the like, as long as the insulating film forming the first semiconductor memory element is caused to form a portion in contact with the gate electrode and a portion in contact with the semiconductor substrate by a usual insulating film forming step. There are steps of different film thicknesses, thus enabling the provision of semiconductor memory devices that do not require any complicated steps and that are inexpensive to manufacture. Moreover, the formation of the source diffusion region and the drain diffusion region of the semiconductor memory device can be offset from the gate electrode and can overlap with the charge storage region, so that the hidden body effect is advantageous, and is better than in the source diffusion region. The fact that the drain diffusion region does not overlap with the charge storage region significantly increases the current value of the semiconductor memory device that is read. As a result, the reading speed can be significantly increased, and thus 9197i. Doc •24· 1248201 to provide a high read speed semiconductor memory device. The other side φ, the present invention provides a method for producing an I-conductor memory device. The method of beta includes the following steps: forming a gate film of a gate on a semiconductor substrate made of tantalum; forming one of the alloys The inter-electrode, the closed electrode, the butadiene/denier is greater than the impurity concentration X if or more in the region of the substrate near the surface; heat treatment is used on the substrate. An insulating film is formed on the sidewall of the electrode of the gate electrode, such that the portion of the insulating film covering the substrate is different in thickness from the portion covering the sidewall of the closed electrode; the edge of the electrode of the Leito Forming a charge storage region thereon; and forming the source region by using the insulating film on the sidewall of the gate electrode and the charge storage region as a implant material to form the source region And > and polar regions. The impurity concentration of α 2 at the gate electrode of the semiconductor memory device is at least 0 cm, so that the effect of enhanced oxidation of impurities may occur remarkably. Further, the semiconductor substrate is formed with a region in which the impurity concentration is lower than the impurity concentration of the gate electrode, and the insulating film is formed on the semiconductor substrate and the closed electrode according to the heat treatment to form a thickness such that the first insulating film and the gate electrode are in contact with each other. The thickness of the contact portion of the semiconductor substrate is extremely different, so that any complicated steps (such as etching) and its bulk memory device can be provided. Further, in the case where the portion where the first insulating film is in contact with the semiconductor memory board is formed to be thin relative to the body of the semiconductor body, the portion of the electrode which is in contact with the electrode is prevented from injecting an insulating film from the semiconductor substrate to the gate. Thunder 杬 electric lamp 遝 遝 ' 'electrode' thus can provide good charge injection efficiency and 91971. Doc -25- 1248201 High memory write/erase speed semiconductor memory device. In another aspect, the present invention provides a method of fabricating a semiconductor memory device, the method comprising the steps of: forming a gate insulating film on a semiconductor substrate made of tantalum, the substrate having an impurity region near the surface of the substrate The impurity intensity is 5 X 1〇19 cm_3 or more; forming a gate electrode made of Shi Xi', the impurity concentration of the gate electrode is less than the impurity concentration and the impurity concentration of the impurity region close to the surface of the substrate is 丨x 1 〇2〇cm·3 or less; forming an insulating film on the substrate and the sidewall of the gate electrode using heat treatment, such that a portion of the insulating film covering the substrate is different in thickness from a portion covering the sidewall of the gate electrode; An insulating film forms a charge storage region on the sidewall of the gate electrode, and implants impurities into the substrate by using the gate electrode, the insulating film existing on the sidewall of the gate electrode, and the charge storage region as an implant mask A source region and a drain region are formed. Therefore, since the impurity concentration of the gate electrode of the semiconductor memory device is at most 1×1 〇2G cm·3 and the impurity concentration of the semiconductor substrate is low, the condition that the effect of the impurity-enhanced oxidation is not formed can be set for the 7-electrode, and When the impurity concentration of the semiconductor substrate is higher than the impurity concentration of the gate electrode and at least $ > 1 〇 Cm 扦, the effect of enhancing the oxidation of the impurities in the semiconductor substrate begins to occur. Therefore, when the insulating film according to the heat treatment is formed on the semiconductor substrate and the gate electrode, the thickness of the portion where the first insulating film is in contact with the gate electrode and the thickness of the portion where the first insulating film is in contact with the semiconductor substrate are inevitably different. It is possible to provide a semiconductor memory device which does not require any complicated steps and has a low manufacturing cost... The thickness of the contact portion of the first insulating film and the gate electrode and the thickness of the contact portion of the first insulating film and the semiconductor substrate are 91971. Doc -26 · 1248201 is a different semiconductor memory device that can provide significantly higher write/erase speeds. Moreover, the portion of the first insulating film of the semiconductor memory device and the portion contacting the semiconductor substrate is thicker than the portion in contact with the gate electrode, and therefore, the charge injected from the gate electrode can be prevented from penetrating the first insulating film to the semiconductor substrate, thereby enabling multiple sentences. A semiconductor memory device that provides good charge injection efficiency and high write/erase speed. Further, in the case where the thickness of the portion where the first insulating film is in contact with the semiconductor substrate of the semiconductor memory element is smaller than the thickness of the contact portion of the first insulating film and the gate electrode of the element, the charge penetration from the semiconductor substrate can be prevented. An insulating film reaches the gate electrode, and thus can provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. In a semiconductor memory device according to an embodiment of the present invention, a semiconductor memory device including a memory cell is provided, each memory cell including a semiconductor substrate; a film formed on the substrate and separated by a channel a source region and a drain region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; and a memory functional unit located on the opposite side of the gate electrode, Each memory functional unit includes: a charge retention portion and an anti-consumption insulator, wherein the charge retention region is separated from the substrate by a first distance (T1) and a second distance that is not equal to the first distance (T1) (Τ2) is separated from the gate electrode. In the above semiconductor memory device, the second distance (?2) may increase as the measurement distance from the substance increases. Furthermore, the second distance (Τ2) is greater than the first distance (Τ1). 91971. Doc -27- 1248201 In one embodiment described above, the semiconductor memory device and the gate electrode are formed of a different material composition than the substrate. Furthermore, the impurity concentration of the gate electrode is greater than or equal to 丨x l〇2〇 cm·3 , and the impurity concentration of the substrate is lower than the impurity concentration of the gate. In the above semiconductor memory device, the anti-consumption insulator includes a hafnium oxide film or a hafnium nitride film, and the charge retention portion contains a tantalum nitride film. In another aspect of the present invention, a semiconductor memory device including: a field effect transistor having an electrode formed on a semiconductor substrate via a gate insulating film and formed on a surface of a semiconductor substrate corresponds to One of the two sides of the gate electrode is a source diffusion region and a drain diffusion region, wherein a recess is formed between the two sides of the gate electrode and the surface of the semiconductor substrate to gradually widen from the side in the cross section; And the memory functional unit' each includes: a charge retention portion (made of a material having a function of storing a charge) formed on both sides of the gate electrode in such a manner as to hide the recess, and an anti-consumption insulator (having prevention of Store charge consumption function). In the above semiconductor memory device, the surface of the semiconductor substrate has: a flat portion that faces the bottom surface of the gate electrode via the gate insulating film, and an inclined portion that forms a partial recess near both sides of the flat portion with respect to the length direction of the gate electrode, and Each of the bottom portions adjacent to the outer side of the inclined portion. Further, in a specific embodiment of the semiconductor memory device, a space may be provided between the bottom surface of the electrode and the source diffusion region and the drain diffusion region with respect to the gate length direction. In the above semiconductor memory device, one side of the gate electrode has a flat portion which is generally perpendicular to a surface of the gate insulating film, and is flat near this 91971. Doc -28- 1248201 part of the bottom side to form a slanted portion of the partial recess; and the anti-consumable insulator comprises a first dielectric having a uniform film thickness on the babe, according to the charge retention portion and the gate electrode and the charge retention portion The semi-conductive plate is respectively covered with the flat portion and the inclined portion of the side surface of the gate electrode and the inclined portion and the bottom portion of the surface of the semiconductor substrate. Further, in the above semiconductor memory device, at least a part of the charge retention portion overlaps with a part of the source diffusion region and the drain diffusion region. Moreover, the electron retention portion has a portion which is generally parallel to the surface of the gate insulating film. In the above semiconductor memory device, a side surface of the gate electrode has: a flat portion generally perpendicular to a surface of the gate insulating film, and a slope portion near a bottom side of the flat portion to form a partial recess, and the charge retention portion includes A portion that is generally parallel to the flat portion of the side of the gate electrode is extended. Furthermore, the thickness of the portion of the anti-consumer insulator that separates the charge-retaining portion from the semiconductor substrate from each other is thicker than the film thickness of the gate insulating film and larger than 〇8 nm °, and the portion of the anti-consumption insulator that separates the charge-retaining portion from the semiconductor substrate The thickness is thinner than the film thickness of the gate insulating film and is less than 2 〇 nm. In a specific embodiment of the above semiconductor memory device, at least a portion of the source diffusion region and the drain diffusion region may be disposed in a sloped portion of the surface of the semiconductor substrate. Furthermore, in the side-to-source diffusion region and the non-polar diffusion region, the opposite region of the channel region higher than the channel region directly under the gate electrode surface may be opposite to the conductivity type of the source diffusion region and the drain diffusion region. The conductivity type is formed. 91971. Doc -29- 1248201 and 'the source diffusion region and the drain diffusion region each have an -extension portion on one side thereof (the channel region is present thereon), and the joint depth of the extension portion is shallower than the joint depth of the portion other than the extension portion . In a specific embodiment of the above semiconductor memory device, the impurity concentration of the extended portion is lower than the impurity concentration of the source diffusion region and the non-polar diffusion region portion other than the extended portion. Furthermore, in the above semiconductor memory device, the charge retention portion of the memory function unit can be mounted in the recess. In another embodiment of the present invention, there is provided a semiconductor memory device comprising: a memory region having a semiconductor memory device and a logic circuit region having a semiconductor switching device, the memory region And the logic circuit regions are all disposed on a semiconductor substrate, wherein each of the gate diffusion electrodes and the drain diffusion are formed on the surface of the semiconductor substrate corresponding to the two sides of the $ pole. a field effect transistor in which a semiconductor memory element and the semiconductor switching element are respectively implemented, and in one of the semiconductor memory element and the semiconductor switching element, a recess is formed to gradually widen from the side in a cross section, and Memory strength month b unit, each containing. Forming a charge retention portion (made of a material having a function of storing a charge) and an anti-consumption insulator (having a function of preventing stored charge consumption) formed on both sides of the gate electrode in such a manner as to hide the recess The body element is configured to be capable of changing a flow from one of the source diffusion region and the drain diffusion region to the source according to a charge level retained in the charge retention portion when a voltage is applied to the gate electrode The amount of current in the other of the polar diffusion region and the drain diffusion region, and the semiconductor 91971. Doc -30- 1248201 Qiuchang 7G is constructed to perform the switching operation regardless of the level of charge remaining in the electrical part. The 1C card of the device is provided in the other aspect of the present invention. The semiconductor memory device is also provided to provide the semiconductor memory device. ELECTRONICS: A further aspect of the invention is to provide a method of fabricating a semiconductor memory, in which a semiconductor body element formed of a field effect transistor is formed, the method comprising the steps of: on a semiconductor substrate surface: Forming a closed electrode via a gate insulating film; forming a bird edge-shaped dielectric film gradually widened from the side in the cross section between the both side portions of the gate electrode and the surface of the semiconductor substrate; removing the bird edge shape a dielectric medium to thereby form a recess that is gradually widened in the cross section from the side where the bird-shaped dielectric film has been removed; forming a memory on both sides of the gate electrode in accordance with the manner in which the recess is thereby hidden a body function unit, each of the memory function units comprising: a charge retention portion made of a material having a storage function; and an anti-consumption insulator having a function of preventing stored charge consumption; and the electrode and the memory The functional unit acts as a mask to implant impurities into portions of the surface of the semiconductor substrate corresponding to both sides of the mask to thereby form a pair of source diffusion regions and drain diffusion regions. 8. In the above semiconductor memory device manufacturing method, the step of forming a memory functional unit includes the steps of: forming a gate electrode along which the recess is formed and an exposed surface of the semiconductor substrate to form a substantially uniform film thickness Forming at least a portion of the anti-consumable insulator - the first dielectric film; in accordance with 91971. Doc -31 - 1248201 by means of a recessed portion cut into a nitride material as a material for the charge-retaining portion on the exposed surface; and etching the nitride on both sides of the gate electrode a dielectric film such that the memory functional units are respectively left on both sides of the gate electrode. Further, in the step of etching the tantalum nitride and the first dielectric film, a portion of the tantalum nitride other than the recess may be removed to leave a portion of the tantalum nitride in which the recess exists. According to another aspect of the present invention, a semiconductor device manufacturing method is provided as follows: a semiconductor memory device each formed of a field effect transistor is formed in a memory region provided on a semiconductor substrate, and is provided on a semiconductor substrate. Forming a semiconductor switching element each composed of a field effect transistor in the logic circuit region, the method comprising the steps of: corresponding to a portion of the semiconductor substrate corresponding to each of the memory region and the logic circuit region via a gate insulating film; Forming a gate electrode; forming a bird-shaped dielectric film gradually widened from the side in the cross section between the two sides of the gate electrode and the surface of the semiconductor substrate in the memory region and the logic circuit region; Removing the bird-shaped dielectric film to thereby form a recess that is gradually widened from the side in the cross section where the ostrich-shaped dielectric film has been removed; implanting the impurity with the gate electrode as a mask The logic circuit region is provided with a mask for preventing impurities from being implanted in the memory region, thereby forming a partial source diffusion region in the logic circuit a first doped region of the drain diffusion region; in the memory region and the logic circuit region, a memory functional unit is formed on both sides of the gate electrode in such a manner as to thereby hide the recess, each of the memory functions The unit contains a charge retention portion made of a material having a charge storage function and 91971. Doc -32- 1248201 has an anti-consumable insulator for preventing the stored charge consumption function; and implanting the same type of impurity with the same conductivity as the previous step with the gate private pole and the memory functional unit as a mask And the logic circuit region to thereby form at least a portion of the source diffusion region and the second diffusion region of the drain diffusion region. The invention will be described in detail below with reference to the accompanying drawings. Incidentally, the invention should not be limited by the specific embodiments. (First Embodiment) As shown in FIG. 1(a), the semiconductor memory device of this embodiment is characterized in that it mainly includes a gate electrode 3 formed on a semiconductor substrate 1 via a gate insulating film 2, and is disposed in One channel region 19 under the gate electrode 3 is respectively disposed on both sides of the channel region 19 and a pair of source diffusion regions and drain diffusion regions 13 opposite to the conductivity type and the channel region 19, and are respectively formed on the gate electrode 3 memory functional units 3 on both sides and each having a charge storage function, wherein each memory function unit 30 includes a charge retention portion 31 capable of retaining charges, and an anti-consumption insulator 32 capable of suppressing charge dissipation, and a charge The remaining portion 31 is separated from the gate electrode 3 and the semiconductor substrate by the anti-consumer insulator 32. The semiconductor substrate i and the gate electrode 3 are formed of materials having different compositions, and the distance T2 between the charge retention portion 3i and the gate electrode 3 and the charge The distance T1 between the remaining portion 31 and the semiconductor substrate i is different. Here, in the case where the distance T2 between the gate electrode 3 and the charge retention portion is not fixed, the distance closest to the portion of the charge retention portion 3 i is set to the distance D. Further, an aspect of the present invention corresponds to The gate electrode 3 and the semiconductor substrate i are made of tantalum and their impurity concentrations are different from each other. In this case, 91971 is not required. Doc -33· 1248201 To take any special steps, such as etching, as long as the film formation rate is affected by the influence of the impurity concentration of the oxide film formed on the crucible (so-called "impurity-enhanced oxidation") Provides thickness films of different distances from Ding and Ding]. Here, the definition of the naming function unit and its constituents are as follows. As shown in Fig. (a), the memory function unit 30" represents a region having a function of storing a charge, and is formed on a side surface of the gate electrode 3, respectively. Further, each of the body function units 30 includes a charge retention portion 31 belonging to a portion capable of retaining electric charges and an anti-consumption insulator 32 belonging to a portion for suppressing charge dissipation. Incidentally, numeral 8 in Fig. 1 (4) represents a gate stack @ including the gate insulating film 2 and the inter-electrode 3. The number 2() represents the offset area. The symbol buckle represents the thickness of the idler insulating film 2. This ^, as shown in Figure 1 (b), each of the memory function unit 30 - aspect

The consuming insulator 32 can be divided into a case where the first insulator 仏 and the second insulating spectroscopy 3 2b. This virtual, -I # For convenience, the area of the memory function unit 30 other than the insulator 32 & that is, the area containing the charge bf 32b should be referred to as "charge storage area 33". However, the electric storage area 33 sometimes contains only the charge retention portion η as described below. And = (?, each memory functional unit 30 includes a first-insulator melon; a portion 31 does not include a second insulation_. In this case, the storage region 33 contains only the charge retention portion 31. Electric ==, charge The storage area is not formed in the field effect as described in the prior art, and thus is substantially formed in the side of the gate electrode, but is formed on the side of the gate electrode, and the problem of over-erasing in the technique can be described. For example, the etching step 91971.doc -34-!248201, which is specially applied to films of different thicknesses, forms a first insulator step of different film thickness, which can be a very simple 32a ° variable resistance effect, semi-transistor and memory. In addition, according to the memory function, the single-conductor memory device can be used as the § memory unit with the selected month b. In the second brother, the substrate and the gate electrode are preferably composed of a material composed of half a m. In the semiconductor substrate and the inter-electrode system, a π-semiconductor, which is often used as a material of a semiconductor device, can be used as a semiconductor program of the prior art, thereby providing a semiconductor with low manufacturing cost. Memory device. * In the specific embodiment of the semiconductor memory device of the present invention, when the field component stores information of two or more bits therein, it can also be used as a storage of four or more. The memory element of the numerical value. Further, the shape of the semiconductor memory element shown in Fig. 1 is such that the distance T2 is widened with the distance from the semiconductor substrate. Therefore, the gate portion of the charge-retaining portion is formed to be away from the gate electrode. Farther than the lower part, @ can suppress the excess part of the motor to be injected into the upper part of the charge retention portion. For example, t can strongly suppress the electron injection gate electrode that will occur in the erase mode. Moreover, since the I side is not like The upper part is so far away that there is no need to distance the channel area / this P can form the charge to be retained, so it can effectively maintain the effect of the number of retained charges to provide the number of driving currents. Because of the above, there is no need to reduce the current in the write/erase The difference between the modes can suppress the inflow and shoulder dispersion of the excess current. At the same time, in Fig. 1, in order to explain the distance T2 in detail, the state of the distance is not clear. However, in other specific embodiments, that is, 91971.doc -35-1248201 is not particularly shown, it goes without saying that the same aspect is also employed, and thus the attendant benefits can be achieved as well. The semiconductor memory device of the embodiment is constructed as follows. The semiconductor memory device can store four or more values in a manner of storing two or more values in a memory functional unit. The semiconductor memory element can be used as a memory unit having a function of selecting a transistor and a memory transistor, because of the variable resistance effect of the memory function soap 7L. Semiconductor memory components are not always considered to store information for four or more values, but can also be stored as, for example, two numerical values. The semiconductor memory device of the present invention is preferably formed on a semiconductor substrate or on a well region of the same conductivity type as that formed in the semiconductor substrate. The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. The proposed semiconductor substrate is, for example, a semiconductor substrate made of an elemental semiconductor such as germanium or germanium or a composite semiconductor such as germanium, GaAs, InGaAs, ZnSe or GaN. It is also possible to use a semiconductor substrate having a semiconductor layer on its front surface, for example, a substrate such as a soi (insulator) or a multilayer sI substrate, or a substrate of a glass substrate or a plastic substrate overlapping the semiconductor layer. Among these substrates, a tantalum substrate or an SOI substrate formed of a tantalum layer on the front surface thereof is preferred. The semiconductor substrate or the semiconductor layer may be any one of a single crystal (based on, for example, stray growth), polycrystalline, and amorphous materials, although the amount of current flowing therein is somewhat different. When the SOI substrate is used, the source diffusion region and the drain diffusion region and the semiconductor substrate can be limited to a minimum capacity, and thus 91971.doc -36· 1248201 can provide a semiconductor device capable of high-speed operation. Preferably, the element isolation region is formed on the semiconductor substrate or the semiconductor layer. Further, the semiconductor device may be formed in a single layer or a multilayer structure in combination with a semiconductor substrate or a semiconductor layer and elements such as a transistor, a capacitor and a resistor, a circuit formed of elements, other semiconductor devices, and an interlayer insulating film. Incidentally, the element isolation region may be formed of any of the different element isolation films of the film, the trench film, and the STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and at least the first conductivity type (p_type or ... type) well region is preferably formed in the semiconductor substrate. The semiconductor substrate and the well area of the well region are between the ranges known in the related art. Further, in the case where the s〇i substrate is used as the semiconductor substrate, the well region may be formed on the surface semiconductor layer and the body region may remain under the channel region. In this manner, the conductivity type of the well region and the body region formed in the semiconductor substrate and the φ semiconductor layer is opposite to that of the source diffusion region and the drain diffusion region, and can be adjusted to an appropriate impurity concentration. More specifically, by forming the well region and the body region, it is possible to reduce the current leakage from one of the source diffusion region and the drain diffusion region to another region. Therefore, the floating effect of the substrate which causes problems when the SOI substrate is used can also be eliminated. In order to make the insulating film of the gate electrode and the insulating film y on the semiconductor substrate have different thicknesses, it is recommended to set the impurity concentration of the well region in the insulating film forming region to be the gate electrode when forming the insulating film. The impurity concentration is different. It is preferable that when the impurity concentration is set to be low, it is at most 1 X 1 〇 20 cnT3, and when it is set to be high, it is at least 5 χ 1 () 19 (10)'. In this case, the insulating film of the gate private electrode And the insulating film on the semiconductor substrate can be effectively formed into a different thickness from 91971.doc -37-1248201. In this regard, the degree of formation on the substrate for channel implantation or the like can meet the above conditions. If the impurity region formed near the surface and the threshold voltage are adjusted, the impurity region is generally used for the semiconductor device, and the gate insulating film or the insulating film is not particularly limited. It may be used, for example, with an oxygen film and An insulating film of a nitrogen cut film and a single layer film or a laminated film of any one of a high dielectric film such as an oxidized film, a titanium oxide film, a oxidized film, and an oxidized film. Among these films, the oxidized stone film is Good. The gate insulators form a suitable thickness, for example 1 (four) factory is best about "negotiating. The gate insulating film may be formed only directly on the gate electrode I or may be formed to be larger than (wider than) the gate electrode. Depending on the structure and procedure, a relatively wide gate insulating film can also be used as an insulating film under the charge storage region to simplify the process of the semiconductor memory device. The shape of the gate electrode or electrode formed on the gate insulating film is usually in the shape of a half body device or a shape having a recess in the lower end portion. Incidentally, the "single gate electrode" represents a gate electrode formed into an overall shape and not separated by a single layer or a plurality of layers of a conductive film. In addition, the gate electrode will be on the side wall: there is a side: {edge film. Further, the gate electrode is formed on the gate insulating film. In addition, the gate electrode is formed using a material commonly used for a conductive film of a semiconductor device, such as a polycrystalline germanium, a metal such as copper or aluminum, such as tungsten, titanium or a button, and a refractory metal. A single layer of $ or ® film made of either of them. In particular, a material different from that of the semiconductor substrate can be selected. Generally, a semiconductor substrate will employ a germanium substrate. Therefore, in the case of the second month, the 'free electrode material is best to be such as copper or metal of the Ming, such as Zhen, Qin 91971.doc -38-1248201

A single-layer film or a laminated film made of any one of M metal, 10,000+, and M π and 3 refractory metal telluride. In this case, the insulating film on the body substrate can be formed into a very large insulating film and a semiconducting film to be formed to have extremely different thicknesses. The gate electrode should be formed to have an appropriate thickness, for example, about 50-400 fine. Incidentally, the channel region can be formed under the interlayer electrode. Preferably, the channel region is shaped to include a gate electrode and also includes an & field at the end of the gate end in the length direction of the interpole. The portions of the channel region that are not covered by the gate electrode are 11::^ = importantly, during the formation of the first insulator 32a, the leather of the closed electrode and the + conductor substrate are different. More specifically, the determination of the gate electrode material and the semiconductor substrate material causes the material T1 of the insulating film formed on the semiconductor substrate to be formed on the sidewall portion of the gate electrode when the length of time required for forming the material is formed. The thickness of the insulating crucible is not so that the straw can be made into a film thickness in a self-aligned manner by a simple step, thereby providing a half-body memory device which does not require complicated steps and has a low manufacturing cost. The bain body 32a may be such that the thickness T1 of the portion in contact with the semiconductor substrate is smaller than the thickness τ2 of the portion in contact with the gate electrode 3. Therefore, the charge penetrates the insulator to prevent the germanium semiconductor substrate from being injected into the gate. The electrode, thus capable of providing a semiconductor memory device with good charge injection efficiency and high write/erase speed. In the first embodiment of the present invention, the insulator can be contacted with the semiconductor substrate. The thickness T1 of the portion is larger than the thickness T2 of the portion in contact with the gate electrode 3 91971.doc -39 - 1248201. Therefore, the charge injection from the gate electrode can be prevented from being worn. The insulator reaches the semiconductor substrate, and thus can provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. The composition of each memory functional unit includes, at least, a function of retaining charge or storing and retaining charge or having a trap a film or region that carries a charge or a polarization-retentive function of the charge. The material for performing this function is nitrite; stone sulphate; bismuth silicate glass containing impurities such as phosphorus or boron; carbonized stone eve; a highly dielectric substance such as cerium oxide, cerium oxide or oxidizing button; zinc oxide; a ferroelectric substance H g thereof. The memory, body functional unit may be formed, for example, in a single layer or a bismuth layer structure, and the structure is one of the following Film made of an insulator film including a tantalum nitride film; an insulator film including a conductive film or a semiconductor layer; an insulator film including at least a conductor dot or a semiconductor dot, and a ferroelectric including an internal electric field polarized by an electric field and a polarization state remaining Insulating film of a material film. Among these films, the nitrogen film can obtain a large hysteresis due to the presence of many levels of trapped charges. The property n, which can exhibit a long charge retention time length and no electrical problems due to the occurrence of a leakage path, thus has good retention characteristics. Moreover, since it is a material commonly used in LSI programs, it is advantageous. When an insulating film including an insulating film of a nitrogen-removing film having a charge retention function is used in the functional unit of the memory, the suspicion of storage retention can be improved. The reason is that the tantalum nitride film is an insulator, Even if the P-cutter is leaking, the entire tantalum nitride film will not be lost immediately. When configuring a plurality of semiconductor memory components, even if the distance between the semiconductors and the semiconductors is When the adjacent memory function unit 91971.doc -40-1248201 is in contact with %, when the memory functional unit is made of a conductor, the information items stored in each of the 2 memory functions h are not lost. Moreover, the contact plug configuration can be relatively close to the memory function unit and sometimes configurable to overlap the memory function unit, thus facilitating microfabrication of the semiconductor memory device. Furthermore, in order to improve the reliability of the storage retention, it is not always necessary to use an insulating "film" having a charge retention function. However, it is preferable to disperse an insulator having a charge retention function in the insulating crucible. Specifically, it is preferable that the insulator of the material (10) which is difficult to retain the charge (e.g., oxygen cut) can be dispersed in a dot shape. 2, In addition, conductors or semiconductors can also be used as the material of the charge storage region. Therefore, the amount of charge injected into the conductor or semiconductor can be freely controlled, thereby producing the advantage of a semiconductor memory device which is easy to constitute a multi-value. When the edge film is used as a material for a charge storage region including at least one conductor point or semiconductor dot, it is easy to write/erase the f charge by directly wearing it. Produce the benefits of reduced power consumption. In addition, it is also possible to use a device such as a milk machine that is modified by an electric field as a material for the raindrops of the six-spotted pancreas (polarization direction - / (4) storage area. In this case, the Ray-on-the-shoulder system # is polarized. The other surface generated in the state of charge retention im:, and the guarantee that the "two films can be obtained and have the same hysteresis characteristics as the film with the trapped charge" In addition, the ferroelectric material film can also be externally charged, and it can be used only by the film to eliminate the need to write/erase information from the same room. The step _ includes - the area that flows out, or the film that makes it difficult to discharge the electric charge. It is difficult to carry out the film of the moon b. The proposed film 9I971.doc -41 . 1248201 The film whose function of the charge is difficult to flow out is the oxidized stone film. Or the like. The charge-retaining portion included in the read-body functional unit is directly or via the two sides of the closed electrode and can be directly disposed on the semiconductor substrate (pure, body) via the interlayer insulating film or Zone or source zone and no pole:", diffusion Above, the formation of the charge-retaining portion on both sides of the gate electrode may preferably cover the sidewall of the gate electrode completely or partially, directly or via an insulating barrier. As an application example, the gate electrode has a recess at a lower end portion thereof. The formation of the charge-retaining portion may fill the recess completely or partially, directly or via an insulating film. The gate electrode is preferably only on the sidewall of the wire memory functional unit or preferably not over the upper portion of the memory functional unit. Such a configuration 'contact plug can thus be relatively close to the gate electrode, thus contributing to the microfabrication of the semiconductor memory device. Moreover, the +conductor memory device having such a simple configuration can be easily fabricated, thereby increasing the usable percentage. When a conductive film is used as each charge retaining portion, it is preferable to dispose the charge retaining portion via the insulating film so as not to be in direct contact with the semiconductor substrate (well region, body region, = source region, and gate region or diffusion region) or the gate electrode. The charge retention portion is 'for example: a stacked structure containing a conductive film and an insulating film, and a conductive film dispersed in the insulating film a structure in which a dot or the like is formed, or a structure in which a conductive film is disposed in a sidewall insulating film portion formed on a sidewall of a gate, a source diffusion region and a non-polar diffusion (four) are respectively disposed in charge storage with respect to the gate electrode On the opposite side of the region, the diffusion region is opposite to the conductivity type of the substrate or the well region. The bonding between the source diffusion region and the drain diffusion region and the semiconductor substrate or well region is preferably steep. The impurity gradient of the whistle. 9l97l.doc -42- 1248201 /, the reason 疋 can effectively make the electron or thermoelectric hole from the 鲈徊a + r in the low voltage, so the high speed ^ ^ A 乍 can be achieved by the voltage lower than the rutting The joint depths of the source diffusion regions and the bungee micro-politics regions are not particularly limited... particularly limited, but can be adapted to the performance of the semiconductor memory device to be obtained.

^ ^ ^ Putian 5 weeks. In addition, when the SOI diode is used as the semiconductor substrate, the connection between the source diffusion region and the non-diffusion region is smaller than the thickness of the surface semiconductor layer of the SOI substrate, but the bonding depth is equal to the surface semiconductor layer. thickness. The source region and the drain region may be arranged to overlap the end of the gate electrode, be aligned with the terminal of the gate electrode, or be offset relative to the end of the gate electrode. Especially in the case of the offset configuration, when a voltage is applied to the gate electrode, the offset convenience under the charge retention portion is greatly changed depending on the amount of charge stored in the memory functional unit. Therefore, it is best to increase the memory effect and thus reduce the short channel effect. However, when the source region and the drain region are excessively offset, the drive current between the source and the gate is significantly reduced. Therefore, the intensity of the offset, that is, the length direction of the gate electrode, the distance from the end of the gate electrode to the near end of the source region and the drain region is preferably shorter than the thickness of the charge retention portion in the gate length direction. . It is particularly important that at least a portion of the charge retention portion of the memory functional unit overlaps the source region and the drain region of the diffusion region. This is because the semiconductor memory device constituting the semiconductor memory device of this embodiment of the present invention is essentially based on the voltage between the gate electrode portion of the memory functional unit and the gate electrode of the source region and the drain region. The difference is stored across the electric field of the memory functional unit. Each source region and the drain region may partially extend to a position higher than the front surface of the channel region, that is, the lower surface of the gate insulating film. In this case, a conductive film integral with the source region and the drain region should be appropriately stacked and formed on the source region and the drain region formed in the semiconductor substrate of the semi-conductive 91971.doc - 43 - 1248201. The material of the conductive film to be mentioned is, for example, a semiconductor of polycrystalline or amorphous, or a metal of the above. Among these materials, polycrystalline stone is preferred. The reason is that the impurity diffusion rate of the genus is more than that of the semiconductor substrate. Therefore, the bonding depth between the source region and the non-polar region in the semiconductor substrate is easily shallowed, so that the short channel can be easily suppressed. effect. Further, in this case, the positions of the source region and the =polar region portion preferably sandwich at least a portion of the memory functional unit with the gate electrode. /, Ben: The semiconductor memory device of the Ming can be formed by the usual semiconductor program ::, for example, the same method as the method of forming a single-layer junction:: sidewall spacer on the sidewall of the inter-electrode. The specific method, such as leaving 'after forming the inter-electrode or electrode, will be formed: including a charge: a two-layer film, or a laminated film including a charge-retaining portion, for example: "protecting the separation / insulating film, insulation The charge retention portion/insulating film, the iron after the knives, or the insulating 貘/ leaving the shape of the sidewall spacer: there is also a 回= condition to rewind the film to form an insulating film or charge retention portion & Among them, the shape will be shaped to leave the shape of the sidewall spacers, and then the return-retaining portion will be carried out under the condition of the =, then the #人' will form an insulating film or an electric shape. There are also two = conductor substrates that can be used. Applying or splicing, the middle will be in the semi-material including the gate electrode, and then in the appropriate condition: the shape of the insulating film of the granular charge-retaining material. There is also a feasible square σ etch to leave the sidewall isolation. After the gate electrode is formed, the above-mentioned early film or laminated film is formed in 91971.doc 1248201, and then the mask is patterned. Another specific method is: in the case of the electrode or Before the electrode, the shape: including the charge retention a film, or a charge including a charge retaining portion, as a charge retaining portion/insulating film, an insulating film/charge retaining portion, a film/charge retaining portion/insulating film, forming an opening in the film region to form A gate electrode material film is formed over the entire area of the formed structure, and then the closed electrode material film is patterned to include an opening and a shape larger than the opening. In the case where the semiconductor memory element of the present invention is disposed to constitute a memory unit array The best mode of the semiconductor memory device can meet the following requirements, for example, (1) the plurality of semiconductor memory device gate electrodes are on both sides of the whole 'and the word line K2) memory function sheet. In particular, a nitride film that retains charge in the memory. (4) The memory functional unit is made of 0N0 (oxide nitride oxide) film and the surface of the nitride film is substantially closed and closed. The surface is parallel. (5) The nitrogen film in the memory functional unit is separated from the word line and channel by the oxidized stone film. (6) Memory functional unit; gasification stone film (7) The thickness of the insulating film separating the channel region or the semiconductor layer and the nitride film (the surface is substantially parallel to the surface of the gate insulating film) is different from the thickness of the gate insulating film. (8) A semiconductor memory The input operation and erase operation of the body element are performed by a single-word line. (9) The electrode (word line) having the function of assisting the write operation and the erase operation does not exist on the memory function unit. (10) The conductivity type is opposite to that of the diffusion type. The impurity concentration is in the direct position in the memory functional unit and in contact with the diffusion area. -45-91971.doc 1248201, although it meets all requirements, it can provide the best forever. Achieving all the requirements. X - Tian Ran does not - set ^ in case of two or more requirements, there will still be a particularly favorable group a. The combined example may correspond to the following H > · (3) It is an insulator 'special 疋 can be retained in its own memory function unit. The private tantalum nitride film, (9) has the function of assisting the writing and erasing operations. The electrode (word line) of the knife does not exist on the top, and (6) in the memory function unit. The insulating film (nitrogen ^ ^ in , is an insulator that can retain the memory functional unit and has the function of assisting the writing operation and the function of the 昤 诛 抹 抹 抹 抹 抹 抹 抹 不 不 不 不 不 不 不In the above case, it is known that it is preferable to overlap the insulating film (nitriding film) and the diffusion layer only in the memory functional unit, that is, in the case of meeting requirements (3) and (9). In the middle, the =5 requirement (6) is particularly advantageous. On the other hand, it is present on the memory functional unit if it is a conductor that can retain charge in the memory unit or has an electrode that assists in writing and erasing operations. The case is such that the writing operation can be performed even in the case where the insulating film in the memory functional unit is not overlapped with the diffusion layer. However, the charge is retained in the functional unit instead of being in the insulator function. Conductor or assisted write operation eraser The function of the electrode does not exist in the memory function unit, it will be a great advantage, as described below. The contact plug's position is close to the far-recovery functional unit, even in multiple When the memory energy unit interferes with the shortening of the distance between the body and the body of the body, it is also possible to preserve the poor memory stored in the left & owe, and thus contribute to the semiconductor memory device. 91971.doc -46-1248201 Microfabrication. Moreover, since the component structure is simple, the number of steps can be reduced and the available percentage can be increased, so that the semiconductor memory device can easily coexist with a transistor that can constitute a logic circuit or an analog circuit. Moreover, the verified write operation and the erase operation can be operated at a low voltage of 5 V or less. In view of the above, it is particularly advantageous to be able to meet the requirements (3), (9) and (6). The semiconductor memory device or the semiconductor memory device combined with the logic component is suitable for a battery-driven portable electronic device, and is particularly suitable for a portable information terminal. The portable information terminal can be A telephone, a gaming machine, or the like is referred to as a portable electronic device. V. Reference will now be made in detail to the preferred embodiments of the present invention. FIG. In the following specific embodiment, the case where Ν· is used as the memory will be explained, but it is also possible to use the G-type component as the memory to understand the use of the P-channel type component as the memory. In the case, the conductivity type of all the shellfish from the right side can be reversed. In addition, the part that uses the same material and substance will be designated by the same symbol when displaying the same month and month. , the ancient shape. k two-points do not always represent the same shape W, that is, the outline of the invention (4) is a schematic diagram, please note that the relationship between thickness and flat size, individual layers or individual is not the same. Therefore, the $degree and size ratio of the Knife Temple is determined in the following description: the thickness or size should be the ratio or ratio in between. Of course, the schema contains dimensions and the door (3) has different parts. (First Specific Embodiment) The second aspect of the present invention will be carried out with reference to W2(4)·Fig. 2(d) 1 91971.doc -47-1248201. As shown in FIG. 2(d), in a specific embodiment, the memory element constituting the semiconductor memory device is as follows: the interlayer electrode 3 is formed on the half-body substrate 1 via the gate insulating layer (10). The first insulator 32a of the film thickness is formed on the side surface of the semiconductor substrate 1 and the pole stack: e 8 including the interlayer insulating film 2 and the gate electrode 3, and the charge storage regions of the sidewall shape respectively have at least two The first insulator 膜 of the film thickness is formed on both sides of the gate electrode 3. Further, a pair of source diffusion regions and a non-polar diffusion region 13 are formed under the charge storage region 33. There is no need for special addition, for example, an etching step for operating two or more film thicknesses, that is, two or more film thicknesses can be imparted to the first insulator 32a each having at least two film thicknesses by a very simple procedure. Further, the source diffusion region and the drain diffusion region 13 are shifted with respect to the end portion of the gate electrode 3. That is, in the front surface of the semiconductor substrate ,, the source extension region and the non-polar diffusion region 13 are not located under the gate electrode 3, but are each spaced apart from the gate electrode 3 by a width of the offset region 2〇. . That is, in the front surface of the semiconductor substrate 1, the channel region 19 between the source diffusion region and the drain diffusion region 13 is disposed under the charge storage region 33 as the number of the offset regions 2〇. Therefore, electrons and holes can be efficiently injected into the charge storage region 33, so that a memory element having a high writing and erasing speed can be formed. Further, since the source diffusion region and the drain diffusion region 13 are offset from the gate electrode 3 in the memory element, when a voltage is applied to the gate electrode 3, the charge retention portion is based on the amount of charge stored in the charge storage region 33. The reverse convenience of the portion of the offset region 20 under 33 varies greatly, and thus the memory effect can be increased. Furthermore, compared to a conventional MOSFET, the memory device can effectively prevent short-channel effects and the gate length can be further shortened by 91971.doc -48-1248201. Further, since the ">remembrance element is suitable for its structure and suppresses the short channel effect, it can be made of a gate insulating film thicker than the gate insulating film of the logic transistor, so that the reliability can be improved. Further, the formation of the charge storage region 33 of the memory transistor is independent of the gate insulating film 2. Therefore, the memory function generated by the charge storage region 33 and the transistor operation function generated by the gate insulating film 2 can be separated from each other. Moreover, the charge storage region 33 can be formed by selecting a material suitable for the function of the memory. The memory element can be formed by the same steps as the steps of a normal logic transistor. The process will now be described in accordance with the appropriate procedures of Figures 2(a) - 2(d). As shown in FIG. 2(a), a gate insulating film 2 having a M〇s (metal_oxide-semiconductor) structure and having a MOS generating program and a gate electrode 3 (that is, a gate stack 8) are formed On the p-conductive semiconductor substrate 1. A typical MOS generation procedure is as follows. First, in the semiconductor substrate 1 made of tantalum and having a p-type semiconductor region, an element isolation region is formed by a known method. The element isolation region prevents leakage current from flowing between adjacent elements through the substrate. However, such an element isolation region is not required to be formed in a device that shares a source diffusion region and a drain diffusion region between adjacent elements. The "known method of forming the element isolation region" may be a known method using a LOCOS oxide film, a known method using a trench isolation region, or any other known method as long as the purpose of the isolation element can be achieved. . The element isolation region is not specifically shown in the figure. 91971.doc -49 - 1248201 After eight, although not specifically shown, the impurity diffusion region is formed in the vicinity of the front surface of the semiconductor: bare portion of the board 1. The impurity diffusion region adjusts the threshold voltage and increases the impurity concentration in the channel region. Further, as a particularly important reason, the insulating film of the gate electrode and the insulating film on the semiconductor substrate 1 can be formed to have different thicknesses, and the impurity concentration of the surface of the semiconductor substrate in the insulating film forming region can be formed when the insulating film is formed. It is set to be different from the impurity concentration of the gate electrode 3. Preferably, when the impurity concentration is set to be low, it is at most 1 X 1 〇 2 〇 CHT3, and when it is set to be high, it is at least 5 χ 1 〇 19 CW3. . In this case, the insulating film of the W electrode 3 and the insulating film on the semiconductor substrate 1 can be effectively formed to have different thicknesses. Thereafter, an insulating film is formed on the entire exposed surface of the semiconductor region. Since the insulating film can suppress the film, it is also possible to use any of the following oxide films, nitride films, synthetic films containing oxide films and nitride films, and highly dielectric insulating such as hafnium oxide or hafnium oxide films. A film, and a synthetic film containing a highly dielectric insulating film and an oxide film. Furthermore, since the insulating film becomes a gate insulating film of the MOSFET, it is preferable to form a gate insulating film such as a gate insulating film by a step including oxidation, NO oxidation, post-oxidation nitridation, or the like. A good performance film. "A film that provides good performance as a gate insulating film" represents the following insulating film. · It can suppress an insulating film that promotes microfabrication of m〇sfet and improves all the disadvantages in performance, and can suppress, for example, a short channel of a MOSFET. The effect, the leakage current that is unnecessary to flow through the gate, the current of the gate film, and the diffusion of the gate electrode impurities into the channel region of the MOSFET, while suppressing the empty insulating film of the gate electrode impurity. A typical example of a film and its residence is 'a thickness between 1 and 6 for an oxide film such as 91971.doc -50-!248201 thermal oxide film, tantalum oxide film or NO oxide film. In order to promote the formation of polycrystalline whiskers with impurities. Add % ^ (five) conductivity so that polycrystalline germanium can be used as a gate electrode, and heavy work 疋 ' in order to obtain the so-called "impurity enhancement of oxygen oxide oxidization rate increase" effect two t miscellaneous ΒΒ ^ 月 ^ By using the difference between the semiconductor substrate 1 and the heterogeneous oxidation effect, the thickness of the first insulator MM to be formed on the same second plate 1 and the gate electrode 3 can be given. It is also necessary to give the same impurity concentration as the impurity t of the polycrystalline silicon and the semiconductor substrate 1 at the same time, and compare the impurity concentration of the semiconductor substrate with the impurity concentration of the semiconductor substrate! The high 0 is higher than the impurity of the semiconductor substrate 1 'the gate electrode 3_f is relatively high, the semiconductor base impurity/concentration is preferably at most 1 X 1 〇 2 ° cm_3, and the mismatch of the gate electrode 3 is taken. It is at least 5 χ 1〇19cm.3. Therefore, since the impurity level of the gate electrode 3 is at least 5 x (10) cm', the effect of enhancing the oxidation of impurities starts to be significant. Further, since the impurity concentration in the channel region is at most 1 X 1〇20 m therefore does not appear under certain conditions such as the length of oxidation time The effect of the impurity-enhanced oxidation. Moreover, since the impurity concentration of the gate electrode 3 is relatively higher than the impurity concentration of the semiconductor substrate 1, the portion of the insulating film that is in contact with the gate electrode 3 can be self-aligned. The thickness Τ2 is different from the thickness T1 of the portion in contact with the semi-body substrate 1, and the former □2 can be made larger than the latter T1. Therefore, the charge injected from the semiconductor substrate 穿透 can be prevented from penetrating the insulating film to the gate electrode 3, and thus A semiconductor memory device capable of providing good charge injection efficiency and high write/erase speed at low cost, requiring any complicated steps. Here, the thickness of the polysilicon film is preferably about 5 〇. -4 〇〇 nm. Further, although doped polycrystalline as the material of the gate electrode 3 is used here, a film made of undoped polycrystalline germanium may be used, and a metal such as butyl or w may be used. The formed film, or a film made of the composite of the above metal and ruthenium, covers the doped polycrystalline germanium. Undoped polycrystalline germanium may also be stacked and formed on the doped polycrystalline germanium. Thereafter, The shadowing step forms a desired photoresist pattern on the gate electrode material, and then uses a photoresist pattern as a mask to perform gate etching to etch the gate electrode material and the gate insulating film, thereby forming FIG. 2 (a) The structure shown, that is, the gate insulating film 2 and the gate electrode 3 are formed, thus forming a gate stack 8 containing both. Although not shown, there is no need to etch the gate insulating film at this time. In the case where the gate insulating film is used as the implantation protective film of the dolomite implant in the next step and etching is not performed, the step of forming the implant protective film may be omitted. Incidentally, the gate insulating film 2 and the gate electrode The material of 3 may be the material used in the logic procedure in accordance with the time scale rule, as described above, and the invention is not limited to these materials. Further, the gate stack 8 can be formed by the method described below. The same gate insulating film as described above is formed on the entire exposed surface of the semiconductor substrate 1 having the type + conductor region. Thereafter, the same gate electrode material (4) as described above is formed on the gate insulating film. Thereafter, a mask insulating film of an oxide film, a nitride film or an oxygen nitride film is formed on the gate electrode material. Thereafter, the same photoresist pattern as described above is formed on the mask insulating film, and then the insulating film is masked at 91971.doc -52 - 1248201. Thereafter, the photoresist pattern is removed, and then the mask insulating film is used as a surname mask to etch the gate electrode material. Thereafter, the exposed portion of the insulating film and the gate insulating film is masked, thereby forming the structure shown in FIG. 3 (in the case where the gate stack 8 is formed in this manner, the etching selectivity ratio is also That is, the selection ratio between the gate electrode material and the gate insulating film material can be set to be large, and the gate insulating film can be etched into a film without etching the substrate 1. Although not shown in the drawing, for the same reason It is not necessary to silver enclose the insulating film. Thereafter, as shown in Fig. 2(b), a film of the first insulator 32a is formed on the gate stack 8 and the exposed surface of the semiconductor substrate. The thermal step of the furnace is used as a film forming method to form the first insulator 32a such that the thickness 71 of the portion formed on the semiconductor substrate 1 is different from the thickness T2 of the portion formed on the gate electrode 3 under the above-described impurity concentration conditions. And causing the thickness T1 to be smaller than the thickness of dic. 2. These facts all utilize the effect that the thickness of the insulating film using the thermal step can be changed by impurities, and does not require any special steps, such as etching, which can be simple. The film thickness difference is given. Therefore, the present invention can be carried out without increasing the manufacturing cost. Further, since the first insulator 32a can suppress leakage, it can be formed of an oxide film, a nitride film, an oxide film, and a synthetic film of a nitride film, or a highly dielectric insulating film such as a hafnium oxide film or a zirconium oxide film. Further, since the first insulator 32& becomes an insulating crucible through which electrons pass, it is preferable that the high-voltage is subjected to voltage and low waves. Leakage current and high reliability film. For example, the first insulator 32a can be made of the following oxide film: thermal oxide film, 91971.doc -53-1248201 n2 tantalum oxide film or N0 oxide film' and closed The material of the pole insulating film 2 is the same. If it is an oxide film, it is recommended to have a thickness of about 丨 to plus nm. Further, in the portion for injecting/erasing charges (that is, a portion in contact with the semiconductor substrate) The thickness η can be as small as the extent to which the current flows through the insulating film, which can reduce the voltage required to inject/erase the charge, thereby reducing the power consumption. The typical thickness in this case is preferably about 1-6 _ Here Due to the formation of the first insulator 32a, each memory functional unit includes an insulating film and the semiconductor substrate 丨 and the gate electrode 3 are in direct contact with each other, so that it is possible to prevent leakage of charges by the insulating film. As a result, a good charge can be formed. A memory element that retains characteristics and long-term reliability. Thereafter, it can be deposited substantially as a polycrystalline stone that can form a material of the charge storage region. Here, the material of the charge storage region 33 can be: Or a charge-generating material, such as, for example, capable of retaining nitridation of electrons and holes; a material of a film or an oxygen nitride film, or an oxide film having a charge trapping; thus hunting for charge storage by polarization or the like A material that produces a charge of a substance (including PZT or PLZT) on the surface of the region; or a material having a structure capable of retaining a charge in the oxide ruthenium (such as a floating polycrystalline or a stone point). If a nitride film or polycrystalline is used, the film thickness of the material forming the charge storage region 33 is about 2_1 G () nm. The film thickness is an important parameter for forming the source diffusion region and the non-polar diffusion region 13 which are offset with respect to the gate electrode 3. Therefore, the film thickness can be adjusted within the consideration of the offset size and considering the film thickness of the first insulator 二. After that, as shown in Fig. 2(4), the charge storage (4), 枓 is formed anisotropically, thereby forming a charge storage region 在 on the sidewall of the gate stack 8. Eclipse 91971.d0 < -54 - 1248201 The material capable of selectively etching the charge storage region 33 can be selectively etched under conditions which provide a large etching selectivity ratio with respect to the first insulator 32a. Thus, the meta-etch will cause the highest portion of each charge storage region 33 to be flush with or lower than the highest portion of the gate electrode 3. The reason is that although the gate electrode 3 and the charge storage region 33 may be short-circuited by etching the first insulator 32a at a later step, the shortest distance between the gate electrode 3 and the charge storage region 33 may be changed by the previous etching described above. Large, so it can suppress short circuits. The term "short circuit" as used herein also includes the telluride step of the gate electrode 3 and the short circuit of the contact step. Further, when the anisotropic etching is performed such that the highest portion of the charge storage region 33 is lower than the highest portion of the gate electrode 3, the charge storage region 33 is disposed only in the vicinity of the channel. More anisotropic etching can be performed to make the charge storage region 33 smaller. Because of this, electrons injected by writing are confined near the channel, making it easier for electrons to be removed by erasing. Therefore, error erasure can be prevented. Further, assuming that the amount of injected electrons is not changed by the limitation of each charge retention portion, the electron density in the charge retention portion can be increased, so that electrons can be efficiently written/erased, and thus high writing/erasing speed can be formed. Semiconductor memory device. However, in the case where the magnitude of the offset between the gate electrode 3 and the source diffusion region and the drain diffusion region 13 is insufficient due to the above configuration, the step of forming the sidewall spacer must be further performed. In this case, in the case where a substance having conductivity (typically, for example, a conductor or a semiconductor, or a polysilicon) is used as the material of the charge storage region 33, after the charge storage region 33 is formed, electrons must be performed on the right and left sides. insulation. Therefore, as shown in Fig. 28(a), the file (private area) of the charge storage region 33 91971.doc - 55 - 1248201 is removed by etching. The removal method is to pattern the photoresist by a known lithography step to cover the portion of the region 33 except for its removal region 21. Thereafter, an anisotropic etch is performed to remove the removed regions of the bare knives belonging to the charge storage region. As long as the charge storage region 33 can perform selective rhyme and can be performed under the condition of providing a larger (four) selection ratio with respect to the first insulator 32a, it is not necessary to always have an anisotropic rhyme, and wet etching can also be employed. The removal zone 21 is preferably located above the component isolation zone and is damaged by the worm. From the following 'as shown in Fig. 2(d), there will be an anisotropic (four) _ insulator 仏, : this only selectively etches its exposed portion to complete the first insulator" etching can selectively remark the first Shaoluo, heart The edge 32a, and may be provided under the condition that a material of the material y of the gate electrode 3 is provided with a larger etching selectivity than the material forming the charge storage (4). - the insulator 32a corresponds to a portion of the portion not covered by: the sub-Q 33 (the portion rR eight with the taste of the semiconductor substrate, the previous step corresponds to the port P of the removal region 21 of the charge storage (four). Conversely, The state of the lower dip and the mouth knife (the portion in contact with the side wall of the gate) is as shown in Fig. 28(b). Here, the portion of the first p, ,, and the edge 32a will remain in Fig. 28())). The shape and the cover electrode 3 are connected to the hammer 4, which can suppress the source contact and the high-density packaging of the memory between the drain contact and the gate electrode 3. This is helpful for micro-manufacturing and implementation. The step of forming a charge storage step can be performed by the second step and forming the first insulator 32a. Indeed, it is possible to selectively etch the first insulator 32a and the material forming the charge 91971.doc _ 56 - 1248201 2 (4) and to use a larger material that provides the material relative to the gate electrode & The condition of the ratio is used to use the two steps that are usually required, so that the number of steps can be reduced, and in this case, when a material containing a conductive semiconductor is used as the charge storage region 33, the load is stored. The area 33 shirt (four) row is electrically insulated. Therefore, as shown in Fig. 28(b) = electricity will be removed by etching to store the charge in F 1 , the same as above. ^33 part (removed area). The removal method can be "its After the 'use of the gate electrode 3, the first insulator 32a and the charge reservoir 33 source and the drain implant mask area as a mask to perform the source and the poleless ', implant and then know Heat treatment, thereby forming a source diffusion region and a non-polar diffusion region. If an implanted protective film (not shown) is formed on the exposed portion of the semiconductor substrate, it is preferable to prevent the surface of the semiconductor substrate from being ion implanted. People turn brown sugar to suppress unnecessary deep The film thickness T2 of the touch portion is different, and the former T1 is smaller than the latter T2. Moreover, these events utilize the effect of the thickness variation of the insulating film using the thermal step by the change of the miscellaneous' and do not require any special The steps, such as etching, can give a difference in film thickness in a simple step. Therefore, the present invention can be carried out without increasing the manufacturing cost. Moreover, according to the semiconductor memory device, it is possible to specifically store 2 bits per transistor. Here, the writing/erasing and reading method for realizing each transistor to store 2 bits will be described in detail below. Here, according to the semiconductor memory device, the formation of the first insulator 将 will be formed. The film thickness T1 of the portion on the semiconductor substrate 1 and the case where the gate electrode 3 is connected to the gate electrode 3 1971.doc -57 - 1248201 body 7G are of the N-channel type. In the case where the memory element belongs to the p_channel type, the description is also made by inverting the voltage sign. Incidentally, the ground potential can be imposed on the nodes (source and drain, gate and substrate) to which voltage is not specified. If a poor signal is written to the memory device, a positive voltage is applied to the gate and the positive voltage is almost greater than or equal to the gate voltage at which the drain is applied. At this time, the charge (electron) supplied from the source is accelerated near the end of the neopolar phase to become a hot electron injected into the charge storage region on the drain side. At this time, there is no electron injection: the charge storage area on the source side. In this way, information can be written to the charge storage area on the finger side. In addition, the (4) pole replaces the 7 pole and writes 2 bits. In addition to the information written in the memory component, Ij can use a thermal hole to apply a positive voltage to the (four) domain (source or immersion) on the side of the charge storage region to be erased. Negative power (four) is applied to the gate. At this time, a hole can be generated by passing between the semiconductor substrate and the diffusion layer region where a positive voltage is applied. The hole will be attracted to the charge store area that has to be erased. In this way, the information on the specified side can be erased. ^ In order to erase the power written on the opposite side = Γ: Γ will apply a positive voltage to the charge storage area on the opposite side. The charge storage area/fetch information written to the memory element will set the area to be read: for: the area is set to the source, and the upper side is expanded to the second side, ie, the positive voltage can be applied Applied to the gate, the positive current of the electromigration is applied to the drain (the source is the source). However, π 士 , 飞 τ δ and this ¥, the electromigration must be small enough to avoid information writing. No 9197l.d0 < -58- 1248201 The polar current can change (4) the stored information as the amount of charge stored in the charge storage area changes. In addition, the source and the drain of the charge storage area on the opposite side of the writer can be replaced with each other. The above writing/erasing and reading method is an example in which a nitride film is used for each charge storage region, but other methods may be employed. Furthermore, even if any other material is used, the above method or a different writer/erase method can be employed. As described above, according to the semiconductor memory device, it is possible to realize that each transistor stores two bits, so that the occupied area of the memory element per bit can be reduced, and thus a large-capacity non-electrical memory can be formed. Further, according to the semiconductor memory device, the charge storage region is disposed on both sides of the gate electrode instead of under the gate electrode. Therefore, the gate insulating film does not have to be used as an electrical storage region, and can be separated from the charge storage region and can only be used as a function of a simple closed insulating film. Therefore, it is not necessary to insert a floating gate between the channel and the control electrode as in the flash memory, and it is not necessary to use a (10) ruthenium film which imparts a memory function like the gate insulating film, and thus it is possible to adopt a micro compliant film. The manufactured gate insulating film is the same as N·, and the influence of the electric field of the gate electrode on the channel becomes stronger, so that the memory memory function of the semiconductor memory device can be specifically and/or has a short channel effect. Manufacturing can increase the integration density and thus provide a low-cost semiconductor memory device. In addition, the retention of charge in the electrical portion is strongly influenced by the charge. Therefore, the discernible charge is formed. Further, the value of the 'then' threshold current of the channel region changes due to the case of each charge storage region. No semiconductor memory device. The electrode is in contact with the semiconductor substrate 91971.doc -59 - 1248201 via the insulating film, so that it can leak. Therefore, T, ,, and the margin of "suppressing the retention of charge" can form a good charge-storing semiconductor memory device. π long-distance characteristics and long-term reliability <Bai Cai according to the method of forming a semiconductor memory device, without using any hard steps (such as the remaining, or without knowing the use of the following _ _ χ虱), hunting can be compared with a single step , the semiconductor 32a: the film thickness of the sidewall portion of the gate electrode (Τ2) > the film thickness (T1) on the substrate is relatively small. (Third embodiment) The present invention; In the method of the first method of the insulator ,, the steps of 2:: are different from those of the second embodiment. For the step of the step, by using the steps described in the second embodiment, Forming the semiconductor μ fish μw. Mainly in accordance with the appropriate procedure f - specific focus of the third embodiment of the different embodiments. The upper protection P1 has not shown in Figure 3 (a) will be through the interlayer insulating film 2 The semiconductor substrate 1 has two electrodes 3, that is, a mesa stack 8 is formed. Thereafter, a thickness of the initial insulating film 34 is formed to cover the semiconductor substrate 1.  The front surface of the material is 8 . The method of forming the respective configurations is as follows. "The method of forming the inter-electrode 3 on the semiconductor substrate 1 by the gate insulating film 2 (i.e., the method of forming the second embodiment in Fig. 2 (4) of the second embodiment, and in this embodiment, even if it is closed The electrode 3 does not contain any miscellaneous shells and can still achieve the effect of containing impurities, so the method will be relatively simple. On the exposed surface of the semi-conducting substrate 1 and the gate stack 8, the initial 91971 is formed. Doc -60 - 1248201 The method of starting the insulating film 34 may be a flat method. Here, in the case where the oxide film is doped with nitrogen: the film shape is used as the insulating film 34, the effect of the heat treatment is adopted, and the effect of leakage is adopted by using (4). The interface characteristics of the film of the like are compared with those of the second deposition or the like, and the interface characteristics of the dry substrate 1 are good. Therefore, the drive current will be relatively large. An oxide film or a mouse film can be formed into a substantially uniform sentence by using a rut or a hunt. In this case, the Jinding and the primary insulating film 34 will eventually form the first, ^^ formed on the sidewall portions of the gate electrode 3.  / In the sacral pancreas, it becomes an insulating plate of this thickness, and it must suppress the leakage of stored charge. Therefore, the effect can be improved when the same formation method of the closed-electrode insulating film forming method of the second embodiment is employed. Here, in the case of forming, for example, Ν as the initial insulating film 34, the thickness thereof is preferably substantially - between (4) coffee. The film thickness of any other material can also be adjusted to about 1 to 20 nm in terms of the equivalent thickness of the oxide film. Thereafter, as shown in FIG. 3(b), a film which becomes the first insulator 3 2 a is formed on the surface of the semiconductor substrate 丨 and the gate stack 8 , that is, the gate electrode 3 is formed. The thickness (T2) of each side wall portion is smaller than the insulating film of the film thickness (T1) on the semiconductor substrate 1. The formation of the insulating film is as follows. The initial etching of the insulating film 34 is performed by using an anisotropic etching method, whereby the initial insulating film 34 is operated such that the film thickness of the sidewall portion of the gate stack 8 is substantially less than or equal to the thickness of the initial insulating film 34, and The film thickness of the semiconductor substrate 1 is made smaller than the thickness of the initial insulating film 34 or completely removed. Therefore, the film thickness (T1) of the semiconductor substrate 1 can be formed to be smaller than the side wall portion of the gate electrode 3 of 91971. Doc -61 - 1248201 The thickness of the first insulator 32 ^ ^ d in this case, the step of adding the film to the film can be added here. Therefore, the damage of the conductor substrate 1 due to the above (4) can be reduced, so that the first insulator 32a capable of being formed can be formed. In this case, the phase method using the method of forming the interlayer insulating film can be reduced, such as the second method. As described in the specific implementation, an additional step of forming an insulating brain is performed. According to the above manner, it is possible to use #士,丄Μ, μ/ into the structure shown in Fig. 3(b). The structure of Fig. 2 (8) of the second embodiment has the same appearance, and the step shown in the second embodiment is used as a subsequent step to form a semiconductor memory device. Therefore, the same advantages as the second embodiment can be attained by this semiconductor memory element or this manufacturing method. However, the method for forming the first insulating film can also achieve different benefits. More specifically, according to the third embodiment, the gate electrode does not have to contain any impurities in advance, and this method becomes a relatively simple step. Moreover, it is also possible to use a double gate 〇 deletion step which is usually employed in a normal CMOS generation program, that is, a step of implanting an impurity gate electrode simultaneously with forming a source diffusion region and a 'diffusion region' implant step. Therefore, 'cm 〇s generation program for f can be applied' thus forming a highly reliable semiconductor memory device. Moreover, it is possible to form a |conductor memory device that easily coexists with a CMOS device. (Fourth embodiment) A fourth embodiment of the present invention will be described with reference to Figs. 4(4) - 4(4). The novel structure and formation method of this embodiment (4) are the semiconductor memory devices described in the above specific embodiments, and are formed on the sidewall portion of the gate electrode 91971. Doc -62 - 1248201 The method of forming an insulating film that can solve the problem caused by unevenness is a new advantage. The semiconductor body 7G piece ' and the first insulator thereof formed by the forming method described in the second embodiment are formed by heat treatment, and the model diagram shown in FIG. 4(b) is a figure. 4(a) The area indicated by the dotted circle. It can be seen from Fig. 4(b) that the side surface of the gate electrode 3 is formed by unevenness. As shown in Fig. 4(b), the case where the polycrystalline seconds surface is "bumpy" is, for example, the gate electrode 3 is made of polycrystal 11, and the anti-corrosion insulator or the first insulating system 2 is formed by an emulsification step. . More specifically, the "roughness" can be regarded as the reason why the roughness of the surface of the surface of the polycrystalline 11 is different from the difference in oxidation convenience. For example, the grain boundary of the polycrystalline silicon is subjected to polycrystalline thermal oxidation. Enhanced oxidation in the middle. An illustration of the unevenness that has been omitted in Fig. 4 (4). Although the unevenness is not shown in the drawings other than FIG. 4, it does not mean that the unevenness is not formed [is not the same as FIG. 4 (4) - the appearance of the unevenness of the unevenness may occur due to the above reasons, regardless of the display Whether or not the formation of the unevenness should be taken into consideration. In the case where the unevenness has occurred due to the formation method of the second embodiment, it is easier to charge the charge from the gate electrode than in the case where the unevenness is not observed. 3 / The main charge retains part 3丨. Therefore, it is relatively easy to occur in the erase mode of the semiconductor memory device. More specifically, in the case where the potential is applied in the erase mode, the negative electric current is applied to the gate electrode 3 and the positive electric current is located at the source diffusion region and the drain diffusion region Π, thereby retaining the charge retention portion 31. The electron emission to the source spreads 9l971. Doc - 63 - 1248201 One side of the region and the drain diffusion region 13 is prone to leakage. Electrons emit electrons from the charge retention portion 31 while injecting charge retention from the gate electrode 3. Therefore, the erasing efficiency deteriorates. The newspaper is prone to a relatively bad erase. On the contrary, when the structure as shown in Fig. 4 (c) or Fig. 4 (4) is formed, the above problem of the comparatively poor erase can be solved. This structure will be described in detail below.圃(6)mu冓 is as follows: a deposition insulator 41 is formed on each side surface of the gate electrode 3; a third insulator 42 is formed on the front surface of the semiconductor substrate outside the deposition insulator; and the charge retention portion 31 and the second I edge body milk system Formed on the surfaces of the deposition insulator 41 and the third insulator 42. Therefore, the contact between the insulator and the gate electrode 3 is a deposition insulator according to (10), unlike the first insulator 32a shown in Fig. 4(b) and the insulator formation method according to the heat treatment. Therefore, the insulator 41 of Fig. 4(c) does not have unevenness due to heat treatment to form an insulator as shown in Fig. Therefore, it is possible to suppress the leakage caused by the unevenness, and thus it is possible to suppress the relatively poor erasure. However, since the third insulator 42 is formed by heat treatment, some irregularities may occur, but the concave: unevenness is suppressed more than the case shown in Fig. 4(b). As a result, a relatively poor erase can be suppressed. The structure of Fig. 4(d) is included in Fig. 4 ((the deposited insulator 41 formed on each side of the electrode 3) is particularly different from the structure of Fig. 4(c) in that it is a thermal insulator of the insulator treated according to ruthenium 43 is formed between the deposition insulator Μ and the gate electrode 3 and between the deposition insulator 41 and the semiconductor substrate 。. Here, the structure of FIG. 4(d) is more advantageous than the structure of FIG. 4(4), and the thermal insulator can suppress channel migration. The rate is due to the ratio between the semiconductor substrate and the deposited insulator 41 compared to 91971. Doc •64-1248201 Poor, the surface characteristics are degraded by the driving power (4). In order to understand the influence of the unevenness, the film thickness of the thermal insulator 43 should be made relatively small. When the hot emulsion film is formed as the thermal insulator 43, it is particularly preferable that the thickness is about 1 Gnm. Therefore, the shape of the interface between the thermal insulator 43 and the semiconductor substrate 1 is advantageous, so that the mobility of the current flowing through the interface can be suppressed from deteriorating, so that the driving current can be obtained, and the semiconductor memory device capable of speeding up two can be accelerated. In particular, since the nm is thermally oxidized, the interface characteristics can be effectively increased, and when it is at most ... m thick, deterioration due to unevenness can be suppressed. Next, the method of forming the structure of Fig. 4 (4) will be explained. The manufacturing method employed by the partial procedure is the same as the partial manufacturing method described in the second embodiment. First, using the same method as in the second embodiment, the interpole stack 8 containing the interpole insulating film 2 and the gate electrode 3 4 5 6 7 is formed on the semiconductor substrate i as shown in Fig. 2(a). Thereafter, CVD is used to form a uniform insulating film on the sinus 皙μ仏a a , which is a small μ μ. As for the oxide film, the thickness of the insulating film can be almost equal to the first insulator 32a of the second embodiment. Further, anisotropy (four) is performed until the semiconductor substrate -65-1 has been exposed" by which the deposition insulator 41 is formed on the closed-electrode sidewall. As for the material of the insulating film 2, the following insulating germanium can be used: an oxide film or an oxygen nitride film which is often used for the side wall of the interlayer electrode 3. 4 Thereafter, a thermal oxide film is formed to form a third insulator 42. At this time, since the deposition insulator 41 has been formed on the side surface of the gate electrode 3, a thick thermal oxide film is not formed on the side surface of the gate electrode as in the surface of the bare semiconductor substrate. Therefore, in the figure t, the thermal oxide film is shown to be formed in the semi-conductive 8 91971. Doc 1248201 The bulk substrate i is on the portion other than the deposited insulator 41, but is slightly over the closed side. Further, since the thermal oxidation step is used as a step of forming the insulator, the thermal oxidation of the gate electrode 3 on the side of the gate is The increase in the thickness of the insulating film is made possible: and since the thickness of the thermal oxidation is much smaller than the thickness of the first insulator 32a in the second embodiment, the formation of the unevenness can be remarkably suppressed. Here, the film thickness of the third insulator 42 is almost equal to that of the first insulator 32a and its formation method may be CVD or heat treatment. Under this consideration, when the insulating film is formed by heat treatment, the interface characteristics between the semiconductor substrate and the insulating film become advantageous, so that the mobility and the driving current can be increased. The method of forming the structure of Fig. 4(d) may be the same as the method of forming the structure of Fig. 4(4), but the difference is that the thermal insulator 43 is formed before the deposition of the insulator 41. This difference has the following advantages: the interface characteristics between the insulating film and the semiconductor substrate 1 can be increased to increase the driving m. The thermal insulator 43 can be made to contain N20 gas according to oxidation or oxygenation (oxynitride film) using heat treatment. The nitriding action of the N0 gas is particularly advantageous because the leakage can be suppressed. In the case of an oxide film, the film thickness of the thermal insulator 43 is preferably about 1 to 2 Å, which is particularly desirable. Therefore, the shape of the interface between the thermal insulator 43 and the half V-body substrate 1 is advantageous, so that the mobility degradation of the current flowing through the interface can be suppressed, so that the driving current can be obtained and the semiconductor memory capable of providing a faster reading speed can be provided. Body device. Youai, because the thermal oxide film is at least 1 Å thick, it can effectively add the interface: when the raw material is mostly 10 nm thick, the beak can suppress the degradation caused by the unevenness. 91971. Doc-66- 1248201 Further, in addition to the above-described structures and methods, a method of suppressing a relatively poor erasure by suppressing leakage due to unevenness is as follows. The first insulator 32_, which is a second specific embodiment, is formed by using a gas or an N gas as the oxidizing gas. Therefore, a nitrogen oxide film, i.e., an oxide film containing nitrogen, can be formed to suppress bubble leakage of the insulating germanium (Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to Fig. 5. This embodiment employs substantially the same steps as the steps of the second embodiment. The difference is the following two: First, the step of forming the charge storage region 33, which makes each charge storage region higher than the second embodiment. The second is the step of engraving the first insulator 仏 to form the L_shaped first-insulator member %, and the step of shifting (10) the first insulator 32a up to the semiconductor substrate to open the electrode. The steps described in the second embodiment are carried out in consideration of the above two points, whereby the structure shown in Fig. 5 is formed. As shown in Fig. 5, the highest position of each charge storage region 33 can be made flush with or lower than the first insulator 32a. The second step of forming the first insulator 32 may be the third or fourth specific method. In this case, it goes without saying that the benefits described in the corresponding specific embodiments can be achieved. In addition, by engraving the first insulator 稍后 by a later contact step, the Z electrode 3 and the source diffusion region can be connected to the wiring. This: Membrane =: An insulator 323 is "engraved, and the same material composition as the material used for the interlayer is used. For example, it will be adopted in 91971. Doc-67- 1248201 uses an oxide film as the interlayer insulating film, and therefore an oxide film can be used as the material of the first insulator 32a. The conditions under which contact etching can be performed are as follows: The oxide film is etched, and the selection ratio of the oxide film to the polycrystalline silicon of the substrate 1 and the gate electrode 3 is high. In addition, even in the case where the first insulator 32a is made of, for example, a tantalum nitride film, it can be used as a stop layer for the contact etching step to avoid meaningless etching with source diffusion regions and diffusion of the drain. The semiconductor substrate 形成 formed in the region 13 is advantageous in preventing short-circuiting between the source diffusion region, the gate diffusion region 13 and the semiconductor substrate 丨. Further, the first insulator 32a can be used as the implantation protective film for implanting the impurity of the source diffusion region and the drain diffusion region 13, so that the step of forming the implant protection film can be omitted. Furthermore, even in the case where the contact between the source diffusion region and the drain diffusion region 13 is disposed on the gate electrode 3 due to no moon, the source diffusion region can be maintained due to the different film thicknesses at the first insulator. The insulation between the electrodeless diffusion region 13 and the interlayer electrode 3. More specifically, as compared with the insulating film on the source diffusion region and the drain diffusion region 13, an insulating film of the gate electrode 3 which is thicker than the car and thicker is formed. Therefore, although the contact hole system is formed on the precursor diffusion region and the drain diffusion region 13, it is not formed on the gate electrode 3, and the insulation can be maintained because of this. Therefore, the alignment tolerance can be designed to be compared to +, resulting in microfabrication and high package density. (Sixth embodiment) A sixth specific embodiment of the present invention will be described with reference to Figs. 6(a) and 6(b). The structure of this embodiment in Fig. 6(a) can be formed using a phase synchronization of substantially the specific embodiment. In addition, it is shown in Figure 6(b). The structure of doc '68-1248201 can be formed using substantially the same steps as the second embodiment. The difference is as follows: in terms of the equivalent thickness of the oxide film, the thickness TG of the gate oxide film 2 can be made relatively large, and the thickness T1 of the portion where the first insulator % is in contact with the semiconductor substrate 1 and its gate The total number of thicknesses T2 between the portions where the electrodes 3 are in contact. Further, impurity implantation of the source diffusion region and the drain diffusion region 13 can be performed after the gate electrode 3 is formed. Due to the above steps, the semiconductor memory device of this embodiment can be driven by a tunneling scheme as described below. Further, the step of forming the first insulator 32a may be the method shown in the third or fourth embodiment. In this case, it is self-evident that the benefits described in the corresponding embodiments can be achieved. However, when the method of forming the first insulator 32a described in the second embodiment is employed in this step, the first insulator 32a shown in FIG. 6(a) or FIG. 6(b) can be given by a simple procedure. The first insulator 32a is shown to have a different film thickness without any special steps, such as etching, for the same reasons as described in the second embodiment. Therefore, the semiconductor memory element can be fabricated by a relatively small number of manufacturing steps, and thus a semiconductor memory element of lower cost can be provided. Further, the film thickness T1 of the portion where the first insulator 32a is in contact with the semiconductor substrate 和 and the film thickness of the portion where the first insulator 32a is in contact with the gate electrode 3 may be different, and any of them may be relatively thick. Here, the driving method in the moon brother whose thickness T1 is smaller than the thickness T2 will be explained, but in the opposite case, the conditions applied to the voltages of the gate private electrode 3 and the source diffusion region and the drain diffusion region 13 can be reversed. In note 91971. Doc -69- 1248201 In / remove the charge on the thin side. Therefore, the benefits described below can be produced. In the case where the thickness of the portion where the insulating film is in contact with the semiconductor substrate 1 is smaller than the thickness of the portion where the insulating film is in contact with the gate electrode 3, the electric charge injected from the semiconductor substrate 1 can be prevented from penetrating the first insulator 32a to the gate electrode 3, thus A semiconductor memory device capable of providing good charge injection efficiency and high write/erase speed. On the contrary, in the case where the thickness of the portion where the insulating film is in contact with the semiconductor substrate is larger than the thickness of the portion where the insulating film is in contact with the gate electrode 3, the charge injected from the gate electrode 3 can be prevented from penetrating the first insulator 32 & reaching the semiconductor The substrate 1 can thus provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. Further, the source diffusion region and the drain diffusion region 13 may be partially disposed under the gate electrode 3, so that the semiconductor memory device can be formed without the step of forming the offset region. Further, since the structure is the same as that of the ordinary field effect transistor, a conventional field effect galvanic program having a specific practical result can be employed, and thus a semiconductor memory device having a low manufacturing cost can be provided.曰 and 'in the case where the formation of the source diffusion region and the non-polar diffusion region 13 is offset with respect to the inter-electrode 3, the same derivative of the flattening guide described in the second embodiment can be achieved. / Silver In addition to the conditions of the first to the fifth specific implementation of the components described above, the tunneling driving method is used, in which the writing/erasing is performed by: using the source diffusion region and the non-polar diffusion region 13 and The potential between the gate electrodes 3 charges through the first insulator 32a to make a contact with the semiconductor substrate: The writing of a semiconductor memory device of a specific structure will be described below = 91971. Doc -70- 1248201 / Example of item selection method. First, the write operation will be explained. Potentials of 1 volt volt and volt volt are applied to the gate electrode 3 and the source diffusion region and the drain diffusion region 13, respectively. Then, the potential of the gate electrode 3 with respect to the source diffusion region and the non-polar diffusion region 13 rises to 10 volts. The potential of the charge storage region 33 is increased to the level required for the generation of the pass current due to its coupling with the capacitance of the inter-electrode (10). Specifically, when the potential of the gate 3 is about, for example, (1) the rise time of nanoseconds, (four) volts: rise to 10 volts, the potential of the charge region 33 (four) "overshoots" and temporarily rises to about 15 volts. . As a result, the source diffusion region and the filament extension 13 are electrically connected to the opposite portion of the ice contacting the semiconductor substrate through the first insulator 32a, and the electrons are injected into the charge storage region on both sides of the gate electrode 3. 33 Even if the potential of the inter-electrode 3 is made lower than the potential after the electrons are injected into the charge storage region 33, the injected electrons remain in the charge storage difference, and the respective regions 33 are surrounded by the insulating film. According to this writing method, one of the source diffusion region and the drain diffusion region 13 and the other one of them have the same potential, so that the infinite current does not flow. Therefore, a semiconductor memory element that reduces power consumption can be provided. Further, since no hot carriers are generated and charges are not injected into the gate insulating film 2, it is possible to suppress a constant voltage difference caused by injecting charges into the gate insulating film 2, thereby providing a highly reliable semiconductor. Memory component. A potential of 10 volts is selectively applied to the gate electrode 3 of any particular memory cell in a plurality of memory cells, and a potential of 0 volt is imposed on the gate electrode 3 of the unselected memory cell. Therefore, it is possible to store only electrons in the charge storage region 33 of the 2 memory unit. 91971. Doc -71 - 1248201 Next, the reading operation will be explained. A potential of 5 volts, volts, and 1 volt is applied to one of the gate electrode 3, the source diffusion region, and the drain diffusion region 13 (for convenience, the source region is assumed), and the other one (for For convenience, the assumption is bungee area). In this embodiment, the threshold voltage of the semiconductor memory device is set to a value below 5 volts (e.g., volts), so that a conductive path can be formed between the source region and the drain region. As a result, electrons migrate from the source region to the drain region, so that a bucker current of a specific strength can be obtained. In this embodiment, the charge storage region 33 is located outside the channel region 19, so that in the case where the charge storage region 33 does not store electrons, the threshold voltage of the semiconductor memory device is f± equal to the charge storage region. The limit voltage for the case of electronic storage. Therefore, in both cases, the same conductive path is formed between the source region and the gate region, and electrons migrate from the source region to the drain region, thereby obtaining a drain current. However, in the case where electrons are stored in the charge storage region 33, the presence of stored electrons increases the diffusion layer resistance (parasitic resistance) of the source diffusion region and the drain diffusion region 13. As a result, the drain current in the charge storage region 33 stores electrons, and the drain current in the case of π 士 卞 becomes lower than the charge current in the case where the charge storage (4) does not store electrons. 4 In the case of the non-electrical memory according to the present invention, according to the threshold voltage intensity of the semiconductor memory device, information of one bit is not stored. In the present invention. ^ 〇σ 令 ’ ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” When a large amount of electrons are stored in the storage area of the Leichens, the source diffusion region near the charge storage region 33 and the i 91971 in the drain diffusion region 13 are considered. The doc -72- 1248201 sub-intensity is affected by the electric field established by the electrons, thus increasing the resistance of this region. Since the inrush current intensity varies with the parasitic resistance of the source diffusion region and the immersed diffusion region, the strength of the drain current can be utilized to identify the lean material. In order to be able to read the data in actual use, the β-electric/;, L-y-page has the intensity of the no-pole current of up to 8〇% in the unwritten data state. In addition, in order to be able to read data without error, it is preferable that the buckling current in the write data state has the intensity of the maximum of the bungee current in the unwritten data state. In order to amplify the accumulation/non-accumulation of the charge in the charge storage region 33 in the drain current, it is more preferable to 'increase the width of the charge storage region 及 and to reduce the portion of the portion where the first insulator 32a is in contact with the semiconductor substrate i. The thickness will then be described as an erase operation. The potentials of _1 () volts and Q volts are imposed on the interrogating electrode 3 and the source diffusion region and the non-polar diffusion region 13. Then, since the capacitance is lightly combined with the electrode 3, the potential of the charge storage (4) can be lowered to a low level. As a result, electrons in the charge storage region 33 are transferred (emitted) from "33" to the source diffusion region nuclear diffusion region 13. = This erase method 'Source diffusion region nucleus diffusion region 13 = The two potentials are equal, so the immersion current does not flow. Therefore: : The low-power consumption of semiconductor memory components. Recombination _ heat carrier, and not #f #,,# "The rabbit is connected to the gate insulating film 2, so it can provide (4) the limit current (4) caused by r=u domain (4) 2, so it can be r A sinful semiconductor memory component. 91971. Doc-73-!248201 As described above, according to the semiconductor memory element of this embodiment, a semiconductor memory element which can reduce power consumption and high reliability can be provided. The manufacturing steps of the semiconductor memory element are less than the manufacturing steps of forming the element by the etch process or the like, and thus a lower cost semiconductor memory element can be provided. (Seventh embodiment) A seventh embodiment of the present invention will be described with reference to Figs. 7(a) to 7(d). The structures shown in Figs. 7(4) and 7(8) in the specific embodiment can be formed using the same steps as those of the second embodiment, which all have the same advantages. Further, the structures shown in Figs. 7(4) and 7(4) can be formed using substantially the phase synchronization with the structures shown in Figs. 6(a) and 6(b) in the sixth embodiment, all of which have the same advantages. Further, the step of forming the first insulator 32a may be the method shown in the third or fourth embodiment. In this case, it is self-evident that the benefits described in the corresponding embodiments can be achieved. The difference is that the charge storage region 33 is further etched after the implantation of the impurity ions forming the source diffusion region and the non-polar diffusion region 13 to thereby limit the range in which the charge can be retained to the side of the semiconductor substrate. The I7 k is also advanced in the charge storage region 3 3, whereby the charge storage region 33 is made very small as shown in FIG. In Fig. 7(a) or Fig., the charge storage region 33 is preferably housed in the offset region 2G, so that the lateral diffusion width-induced charge can be obtained by the lateral (four) disc source and the drain implant region 13. Storage area 33 is used to reduce the size of the structure. Because of the above, electrons injected by writing can be confined to the channel attached to 91971. Doc -74- 1248201 Nearly, it is thus easy to remove electrons by erasing and to prevent false erasure. Moreover, 'the volume of each charge storage area that retains the charge can be reduced without changing the amount of injected charge. Therefore, the amount of charge per unit volume can be increased, thereby enabling efficient writing/erasing of electrons and formation of high write/wipe. A semiconductor memory device other than speed. (Embodiment 8) Fig. 29 (a) shows a plan configuration of a memory unit 200 of a specific embodiment of the semiconductor device of the present invention. In the memory cell 2, the memory cell array 201 including the semiconductor memory element and the peripheral circuit 202 including the semiconductor switching element are disposed on the same semiconductor substrate. The memory cell array 201 is as follows: The semiconductor memory elements described later are arranged in an array. The peripheral circuit 202 is formed by peripheral circuits each composed of a normal MOSFET (Field Effect Transistor), such as a decoder 2〇3, 2〇7, a write/erase circuit, a read circuit 208, an analog circuit 2〇 6. The control circuit 205 and the plurality of 1/〇 circuits 204 are further configured to allow the information processing system (such as a personal computer or a portable telephone) to be constructed as a single wafer, as shown in Fig. 29 (b). In addition to the memory unit 200, it is necessary to arrange the MPU (micro processing unit, cache SRAM (static RAM) 302, logic circuit 3〇3, analog circuit (not shown (5), etc.) in the same semiconductor. Up to now, in order to enable the memory cell array 201 and the peripheral circuit 2〇2 to coexist, a lot of manufacturing costs have been added than forming a standard CMOS. Under the consideration of this, the following clear description of the present invention can suppress Manufacturing costs: increase. 91971. Doc-75-1248201 It will be appreciated from the procedures of the steps described in the second embodiment that the step procedure for forming the semiconductor memory device of the present invention is highly similar to known general MOSFET generation procedures. As is clear from Figure 2, the memory element is constructed close to known general MOSFETs. In order to modify a general MOSFET into a memory device, for example, it is sufficient to use a sidewall spacer of a general MOSFET as a memory function early and not to form an LDD region. Even if the sidewall spacers of the general MOSFETs constituting the peripheral circuit portion of the memory, the logic circuit portion, the SRAM portion or the like have the function of the memory functional unit, as long as the sidewall spacer width is appropriate, the transistor performance is not destroyed, and The MOSFET can operate in a voltage range where rewriting operation does not occur. Therefore, common MOSFET and memory components can use a common sidewall spacer. Further, by further forming an LDD structure only in a memory peripheral circuit portion, a logic circuit portion, an SRAM portion or the like, the memory element can be formed with a memory peripheral circuit portion, a logic circuit portion, an SRAM portion or the like. The general MOSFETs of the object coexist. In order to form the LDD structure, impurity implantation for forming the LDD region can be performed after the gate electrode is formed and before the deposition material constituting the charge storage region. Therefore, as long as the impurity formed by the LDD is implanted, only the memory region is masked by the photoresist, it is easy to make the memory component and the peripheral circuit portion, the logic circuit portion, the SRAM portion or the like constituting the memory. The usual-structure MOSFETs coexist. Further, when the SRAM is composed of a memory element and a normal-structure MOSFET which constitutes a peripheral portion of the memory, a logic circuit portion, and an SRAM portion, it is easy to coexist the semiconductor memory device, the logic circuit, and the SRAM. 91971. Doc •76- 1248201 At the same time, in the case where the voltage is higher than the allowable voltage of the logic circuit part, the SRAM part or the like must be implemented in the memory element, and only the high withstand voltage well forming the mask can be formed and formed. The high withstand voltage gate of the mask _ the insulating film is added to the standard MOSFET to form a mask. So far, the procedure for making EEpR〇M (electronic erasable and programmable ROM) and logic circuit parts coexist on a single chip has been very different from the standard MOSFET program, and it significantly increases the number of necessary masks and processing steps. Quantity. Therefore, the number of masks and the number of processing steps can be greatly reduced as compared with the case where the circuits of the EEPROM and the memory peripheral circuit portion, the logic circuit portion, the sram portion or the like of the prior art coexist. Therefore, the cost of the wafer in which the semiconductor memory device and the memory peripheral portion, the logic circuit portion, the Sram portion or the like of the general MOSFET can coexist can be reduced. Furthermore, since the supplied voltage can be supplied to the memory element, the writing/erasing speed can be remarkably improved. Moreover, since the low supply voltage can be supplied to the logic circuit portion, the SRAM portion or the like, deterioration of the transistor characteristics due to collapse of the gate insulating film or the like can be suppressed, and lower power consumption can be achieved. Therefore, it is possible to realize a highly reliable logic circuit portion and a semiconductor device having a memory element having a particularly high write/erase speed, and it is easy to allow the logic circuit portion and the semiconductor device to coexist on the same substrate. The eighth embodiment of the present invention will be described in detail with reference to Figs. 8(a) to 9(e). In this embodiment, it will be explained that it is easy to form peripheral circuits on the same substrate at the same time without any complicated procedure. Doc • 77- 1248201 MOSFET or its analog and semiconductor memory device. The lithography step will be described in detail in the step of forming the semiconductor memory device described in the second embodiment to separately form the LDD diffusion region and the region where the ldd diffusion region is not formed, thereby being able to be on the same substrate. Automatic fabrication of general MOSFET and semiconductor memory components. The manufacturing steps will now be described in accordance with the appropriate procedures with reference to the drawings. The left and right sides of each figure show separate devices, the left side shows the general M bribes of the peripheral circuit area 4, and the right side shows the memory elements of the memory area 5. (4) The procedure before the step of forming the LDD region may be the same as the second embodiment. That is, as shown in Fig. 8, the structure shown in Fig. 2(a) is formed in each of the peripheral circuit region 4 and the memory region 5. The baby is shown in Fig. 8(b), only in The formation of the LDD region lddf* in the peripheral circuit region 4 causes the photoresist 7 to be formed in the § memory region 5, but is not formed. ^ Here, [DD region 6 has been successfully formed in the peripheral circuit region 4 to form a general transistor of the LDD [Fa, , , °, but does not form a de-sink in the memory region 5, for example, to prevent planting In, it can be any insulating enthalpy that can selectively remove the two specific compound films. Only this step is a special step different from the second and physical J steps, after which the same steps as those of the embodiment can be used. The same steps are not used, and the second insulator is shown in Fig. 2(8) > in the second embodiment. The latter, as shown in Fig. 9(d), the phase synchronization test of Fig. 9(d), and the use of the pen load storage area 33 in Fig. 2(c) in the second embodiment. 91971. Further, as shown in Fig. 9(e), the source diffusion region and the drain diffusion region 13 are formed using the same steps as those in Fig. 2(d) in the second embodiment. Due to the above, the lithography step can be added in the step of forming the semiconductor memory device described in the second embodiment, and the region where the Ldd diffusion region 6 is formed is separated from the region where the LDD diffusion region 6 is not formed, so that no The complex program 'easily and successfully manufactures general MOSFETs and semiconductor memory components on the same substrate. The semiconductor device process of this embodiment different from the above semiconductor device will be described in detail below with reference to Figs. 27(a)-27(d). An example of a semiconductor device of this process is shown in Figures 11(a)-ll(d). In this embodiment, it is shown that a logic circuit or the like and an individual device of the semiconductor switching element in the semiconductor memory element can be simply formed on the same substrate without any complicated procedure. More specifically, it is shown that the semiconductor switching element and the semiconductor storage element can be simultaneously fabricated on one substrate by adding the lithography step to the generation process formed by the semiconductor storage device described in the eleventh embodiment. This arrangement forms one region of the LDD diffusion region and another region where the LDD diffusion region is not formed. This process will be described in order with reference to Figs. 27(4)-27(d). Note that in Figs. 27(a)-27(d), the left side corresponds to the semiconductor switching element of the logic circuit region 4, and the right side corresponds to the semiconductor memory element of the memory region 5. In the case of the step of the electrofilm 9, the same steps as those of the eleventh embodiment can be used. That is, as shown in Fig. 27 (4), the structure described in Fig. 12 (4) can be formed for the logic circuit region 4 and the memory region 5. 91971. Doc -79 - 1248201 Next, as shown in FIG. 27(b), the memory region 5 is covered with the photoresist 7 as an implant mask, and ions are implanted with impurities, thereby forming only in the logic circuit region 4. LDD area 6. In this case, the photoresist 7 is formed in the memory region 5 but the LDD region is not formed. For this purpose, it is preferable to perform impurity implantation at an implantation angle larger than the implantation angle of the extending portion 6 as shown in Fig. 14 (a) because the LDD region can be formed safely to extend under and overlap with the gate electrode. Also, with this step, the LDD region can be formed in the logic circuit region 4 where the general semiconductor switching element is formed, and the LDD region 6 is not formed in the memory region 5. The photoresist is intended to block implantation and must be only a photoresist that can be selectively removed, and it can be a dielectric film such as tantalum nitride. Only this step is a special step different from the eleventh embodiment, and the following later steps may be the same steps as the eleventh embodiment. That is, as shown in Fig. 27(c), the tantalum nitride 17 can be formed by the same steps as in Fig. 12(d) of the eleventh embodiment. Alternatively, the formation in this step can be accomplished in the step of forming the implanted body of the ldd domain or performing the separation of the sidewalls. In either case, the same effect can be produced. Further, as shown in Fig. 27 (d), the memory function unit 11 is formed by using the same steps as those of Fig. 13 of the eleventh embodiment. Furthermore, the same steps can be used until the source diffusion region and the non-polar diffusion region 13 are formed. Due to the above steps, the lithography step can be added in the step of forming the semiconductor memory device described in the eleventh embodiment, so that the region can be divided into the region 4 where the LDD diffusion region is formed and the other region where the LDD diffusion region is not formed. It is not necessary to have any complicated procedure to manufacture semiconductor switching components and semi-conductive (four) memory components on the same substrate at the same time. 91971. Doc -80 - 1248201 When the charge is retained in the memory function, the 70 channel part of the channel will be strongly affected by the charge, causing the bungee current, the stagnation, and the intersection. Therefore, it is possible to form a semiconductor memory element which can be distinguished according to the change of the value of the infinite current and the presence or absence of the blade. Compared with the standard deletion program, the configuration of the inter-pole stack 8 and the memory function sheet can be separated from each other, so that it can be synthesized on a wafer without any large program change. Adhesive semiconductor father replaces π pieces and semiconductor storage components. Therefore, it is possible to reduce the manufacturing cost of synthesizing the adhesive memory region and the memory logic circuit portion on one wafer. Forming the gate electrode and the source region and the drain electrode in the gate storage element and the logic circuit region in which the gate electrode end region and the source region and the secret region are offset by self-alignment similar procedures on a phase (four) substrate The semiconductor switching element which is not offset in the region can synthesize a semiconductor storage element having a high memory effect and a semiconductor switching element which is disposed in a logic circuit region and has a high current driving power without any complicated procedure. Further, according to this semiconductor storage element, since the 2-bit storage of each of the electric crystals can be realized, the semiconductor storage element occupying area per bit can be reduced, and thus a large-capacity semiconductor storage element can be formed. (Different Embodiments of the Invention) A specific embodiment of the present invention will be described with reference to Figs. 10(a)-1(〇). This particular embodiment shows aspects of the construction of each of the charge storage regions 33 of any of the above specific embodiments. In addition to the benefits of the corresponding embodiments, there are benefits as described below. 91971. Doc -81 - 1248201 The charge storage area shown in Fig. 10(a) is as follows: The second insulator 32b contains a layer of defects 1 〇. The method of mounting 4, after forming the first insulator 32a, forms a chip 1 〇, which in turn forms a deposited insulating film and performs an etch back step and a residue removing step, thereby fabricating the structure shown. The individual steps are now detailed. The method of forming the defect 1 如下 is as follows. Use CVD by using acetonitrile, ruthenium as the starting material gas and at the press and substrate temperatures. The growth point 10 was maintained for 2 minutes under conditions of c. The size of each defect is approximately 5 nm. Under this consideration, the size of each defect is preferably about 1-50 urn. It is about M5 nm, and it is better to have a size that exhibits a quantum effect such as Coulomb blockade. The conditions of the raw material gas, pressure, substrate temperature, and growth time in the CVD can be appropriately modified and adjusted to optimize the size, degree, etc. to form the defect 1 〇. Further, in order to take into consideration that the dot diameter is caused by the oxidation of the next step, the defect 10 is appropriately formed into a relatively large size in advance, thereby forming the flaw 10 of the optimum shape. Further, although not shown in the figure, the surface of the formed stone point 10 should be oxidized shoulder-effect. The step of oxidizing may be thermal oxidation. In this case, since the size of the name point becomes smaller, the oxidation rate becomes lower, and the scattering of the size of the stone point 10 is suppressed. In addition, since the surface of the stone-like point can be used as an insulating film through which electrons pass, it can be high: a party voltage, a low leakage current, and a high reliability film. This oxide film may be: = for example, an 'N2〇 oxide film or a rib oxide film. In the case of the inertia of the oxide film, including the thickness of the equivalent oxide film of the first insulator 32a, 91971. Doc -82- 1248201 The film thickness of the final shape is about 丄 to 川nm. In the case where the size of each defect is about 1 to 15 nm, the film thickness should preferably be about M 〇 . In the case where the defect 10 is oxidized to a small size in this manner, it is needless to say that in order to reduce the size of each defect at the time of formation, it is necessary to form a somewhat large defect 10 in advance. Furthermore, in the case where a very thin insulating film is formed to allow a tunneling current to flow therethrough, and in the case where the charge is retained by the Coulomb blocking effect according to the double tunneling junction, the injection/erasing charge can be made The required voltage becomes very low, so power consumption can be reduced. The typical oxide film thickness in this case is about 1-3 nm. In addition, the deposition of the defect 10 may be uneven and does not exhibit a uniform height as shown. Next, a method of forming a deposited insulating film by CVD using HTO (High Temperature Oxide) or LPCVD (Low Pressure Chemical Vapor Deposition) can employ a film having a good step coverage. When the HTO film is used, its thickness is about 2 〇 1 〇〇 nm. Incidentally, the subsequent step etches back the deposited insulating film 15 into the shape of the sidewall spacer, and it can serve as an implant mask when implanting impurities to form the source diffusion region and the drain diffusion region. That is, depositing an insulating film becomes an important factor defining the shape of each of the source diffusion region and the drain diffusion region, in particular, defining the offset width with respect to the end of the gate electrode. Therefore, the way to obtain the optimum offset width is to appropriately adjust and modify the thickness of the deposited insulating film, thereby forming the source diffusion regions and the drain diffusion regions of the optimum shape. Thereafter, the insulating film and the defect 10 are anisotropically etched to form a charge storage region containing the defect 1 and the shape of the sidewall spacer on the sidewall of the gate stack 8. At this time, different materials are selected as the first insulator Ua and the material of the insulating film, thereby increasing the selection ratio between the films, and 91971. Doc-83- 1248201 For example, the steps can be performed using nitriding and using an oxide film as an efficient and easy way to deposit. The material film serves as a material of the first insulator 32a, a material of the insulating film. However, in this case, the Shishi substrate is usually used as the semiconductor substrate and the material used as the point, so sometimes it is impossible to record the residue of the (4) dream point and the production of the product. The method is: after the anisotropic etching described above, using hydrofluoric acid or the like to wet-etch anisotropy, the remaining insulation can be etched to oxidize the residue in the case of residual residue. The surface or the entire residue, by using hydrofluoric acid or its analogs to remove the residue by wet etching. In this way, a structure capable of retaining charge at a time point can be used, so even if leakage of the insulating film occurs to deteriorate the retention characteristics of the memory, all of the retained electricity does not leak - only the defect near the leak portion of the insulating film is retained. The charge will leak. Therefore, it is possible to provide a memory device with good retention characteristics. Furthermore, due to the oxidation of the surface of the (four), it is possible to suppress the dispersion of the size of (iv) - thus readable semiconductor memory devices having very few differences in power supply characteristics. Next, the charge store area shown in Fig. 10(b) has the following structure: The first edge body 32b contains two layers (four) 1G. The manufacturing method is such that, in the formation of the first insulator 3, the surface of (iv) iq, __: 〇 is formed by the method shown in Fig. 1G(4). After that, the same method is used to further form the defect 10. After t, a sinking (four) edge film is formed, and then a regression step and a residue shift step are performed. The structure shown can then be fabricated. The individual steps can be the methods described in Coba 10 (a). ^No. Figure 91971. Doc -84 - 1248201 Due to this structure, the defect 10 can constitute two or more multiples in the vertical direction, which is more effective than the single layer. Again, because. The number of defects in the invisible functional film becomes larger than that in the single layer: therefore, the retained charge increases. Therefore, the constant current 'and the drive 1 & difference increase' in the writing and erasing can form a semiconductor memory element with a large voltage tolerance and improved reliability. Next, the charge storage region shown in Fig. 10 (4) has the following structure: the second insulator 32b contains three layers of dream points 1 (). The manufacturing method is such that, after the first insulator 32a is formed, the surface of the stone point 10 and then the oxidized stone point 10 is formed by the method shown in Fig. 10 (4). Furthermore, it will form a defect 10 and oxidize its surface. After that, it will advance to form (4) 1G. Thereafter, a deposited insulating film is formed, and then the lamp returning step and the residue removing step are carried out. Then, the structure shown can be made. The individual steps may be the methods described with reference to Figure 10 (4). Due to this structure, the defect 10 can constitute three or more multi-focuses in the vertical direction, and thus the memory retention effect can be improved more than the single layer or two layers. Furthermore, since the number of defects 10 in the memory function 臈 becomes larger than that in the single layer or two layers, the retained charge increases. Therefore, the limit voltage difference and the drive current difference in writing and erasing are increased, and the second is to increase the voltage tolerance and improve the pure semiconductor body element. y Figure 10(4)# is a stacked charge storage area that can substantially fill the film thickness of the memory functional film. The manufacturing method is such that the formation of the method of Fig. 10 (4)] 〇 (4) and the number of steps of the oxidized stone eve 10 are repeated. It will improve memory retention performance more than single layer, two layer or three layer. Furthermore, since the number of defects 10 in the memory functional film becomes larger than that of the single 91971. Doc -85- 1248201 曰 or two or two layers are still large, so the retained charge will increase. Therefore, the limit voltage difference and the drive current difference in writing and erasing are increased, so that a non-electrical memory capable of forming a large electric power tolerance and improving reliability can be formed. Fig. 1 〇(e) is not structured such as T: a deposition insulating film 15 having a shape of a very small side wall is formed in the second insulator 32b close to the charge injection portion. The manufacturing method is that, after the formation of the first insulator 32a, the polycrystalline stone is deposited by a method of good step coverage (such as LPCVD), and then (4), whereby deposition is formed only in the corner portion of the charge-charged region where the charge is injected. The insulating film 15 is as shown. After that, a deposition, an insulating film, and a back step are formed, and the structure shown can be produced. Due to this structure, the electrons attached to the person can be restricted to the channel, so that the electron can be easily removed by erasing and the error can be erased. Furthermore, 'without the double injection of the amount of charge, the volume of the charge-storing area that retains the charge can be reduced. Therefore, in order to increase the amount of charge per unit volume, it is effective to write/erase electrons and provide A semiconductor memory device with a high write/erase speed. This advantage is the same as that of the fifth embodiment. However, with the above-described structure, the second insulator milk can cover the deposition of the insulating film 15 in a stepwise manner, thereby preventing the deposition of the insulating film and the contact step in the contact step of the gate electrode and the source diffusion region and the drain diffusion region. Here, it is important that the interlayer insulating film and the sidewall insulating system are made of different materials, for example, the contact tolerances designed by the oxide film and the nitride structure H, respectively, are small and advantageous, thereby making the device finer. Because of A, a low-cost semiconductor memory device can be provided. The structure shown in Fig. 10 (1) is as follows: the second insulator 32b is close to the charge injection portion 91971. Doc -86 - 1248201 / The blade contains a deposited insulating film 15 having a narrow side wall. The formation method can be the same as in Fig. 10(4), and the structure can be formed by adjusting the thickness of the deposited film and the amount of money of the polycrystalline stone. Also, the benefits are the same as in Figure 1(e). The structure shown in Fig. 10(g) is as follows: The charge storage region contains the second insulator milk and the L-shaped deposition insulating film 15. The formation method i deposits a polycrystalline stone in a method of forming a first insulator ❿ after a good step coverage (e.g., LPCVD), and then forms a deposited insulating film. After that, (4) polycrystalline ♦ and deposited insulating film. Then, the structure shown can be formed. Due to this structure, the same benefits as in Fig. 10(e) can be achieved. Further, in the semiconductor memory device having the charge storage region of the structure shown in Fig. 10(g), the first insulator 32a shown in Fig. 1 is made of oxidized oxide film or nitrided oxygen (four). In the middle, and in the case of changing the immersion film 15 into a gasification film, a preferred semiconductor memory device can be obtained at each point of the following materials. Since there are many levels of trapped charges, a large hysteresis characteristic can be obtained. In addition, the charge retention time is long, and the charge leakage problem caused by the leakage path does not occur, so the retention characteristics are advantageous. Furthermore, since the material is extremely commonly used in the order, the manufacturing cost can be reduced. The method of forming the individual films can be achieved in conjunction with the second embodiment or the formation of the materials in this embodiment. However, the nitride film is preferably deposited by a good step coverage method such as LPC VD. The structure shown in Fig. 10(h) is as follows: The charge holding region contains the second insulator 32b, the L-shaped deposited insulating film 15, and the defect 1〇. The formation method is that after the formation of the first insulator 32a, a good step coverage method (such as LpcvD) is used in 91971. Doc -87- 1248201 deposits polycrystalline germanium, oxidizes its surface, and then forms a defect, and then forms a deposited insulating film. The formation of this structure uses the steps of Fig. 10 (a) and Fig. i (h). Due to this structure, a semiconductor or a conductor film exists between the semiconductor substrate and a plurality of crystal grains, thereby suppressing the influence of the position or size spread of the crystal grains on the threshold voltage of the field effect transistor. Therefore, it is possible to provide a semiconductor memory device that suppresses erroneous reading. In addition, the following steps can also be employed. After the formation of the 32a, the polycrystalline stone is deposited by a good step coverage method (e.g., LpcvD), and the surface thereof is oxidized. Thereafter, t is executed under the same conditions as the deposition of polycrystalline stone. Due to the difference in roughness of the underlying oxide film in the first-poly 7 deposition step and the step at this time, defects are formed at the step at this time. When performing such defect formation, if the defect is too small, the Coulomb blocking effect will be too strong and the charge will be difficult to inject. If the defect is too large, the defect will become very thin. Therefore, the optimum thickness of the polycrystalline germanium film is about 丨 to 2 〇 nm. As in the typical example, as with the polycrystalline germanium film described above, it can be at 62 Å by low pressure chemical vapor deposition (LPCVD). The formation of 5 (10) polycrystalline lithosphere and Shi Xi Tu (4) in the Qiu environment requires the removal of the gate around the gate (removal zone 21) as shown in Fig. 28 (4) and Fig. 28 (b). Part to prevent short circuits between the right and left charge storage areas. Further, regarding the polycharge of the charge storage region shown in Figs. H)(4) - Fig. 10(8), any substance other than the polycrystalline stone can achieve the same advantage as long as it has a charge retention function. It may be, for example, a bismuth film, a conductor or a ferroelectric substance of PZT or PLZT. 91971. Doc - 88 - 1248201 (Tenth embodiment) A semiconductor memory device of a tenth embodiment of the present invention will be described with reference to Figs. 11(a)-ll(d). The semiconductor storage device of this embodiment is, as shown in FIG. 11(a), includes an FET having a gate electrode 3 formed on the semiconductor substrate 1 via the gate insulating film 2, and a pair of source diffusion regions and 汲The polar diffusion regions 13, 丨3 are formed on the surface of the semiconductor substrate corresponding to both sides of the gate electrode 3. A region between the pair of source diffusion regions and the non-polar diffusion regions 13, 13 corresponds to the channel region 19. The gate insulating film 2 and the gate electrode 3 may constitute a gate stack 8. Recesses 5, 5, which are gradually widened from the side in the cross section, are formed between the both side portions of the gate electrode 3 and the surface of the semiconductor substrate. The side surface of the gate electrode 3 has a flat portion 3a which is generally perpendicular to the surface of the gate insulating film 2, and an inclined portion 3b which is adjacent to the bottom side of the flat portion to form a partial recess 5'. The surface of the semiconductor substrate has a flat portion 1a which is opposed to the bottom surface of the gate electrode 3 via the gate insulating film 2, and is respectively close to the flat portion 4b on both sides with respect to the longitudinal direction of the gate to form a partial recess 5〇, lb And the bottom surface portions ic, lc near the outer sides of the inclined portions 1b. The memory function unit 丨丨, u is formed on both sides of the gate pole 3 in such a manner as to hide the recesses 5〇, 5〇. The memory function unit 丨丨 includes a charge retention portion 31 made of a material having a function of storing a charge, and an anti-consumption insulator having a function of preventing stored charge consumption (for convenience, it is generally designated as numeral 32). In this example, the anti-consumer insulator 32 comprises a first dielectric 32a, which was in 91971. Doc -89 - 1248201 The film thickness is substantially uniform, and the charge retention portion 31 and the gate electrode 3 and the charge retention portion 3 and the semiconductor substrate are respectively formed in accordance therewith! The manner of isolating from each other 'covers the flat portion 3a and the inclined portion 3b on the side of the gate electrode and the inclined portion 1b and the bottom portion ic of the surface of the semiconductor substrate. The interval (offset region) 20 is provided between the bottom surface of the gate electrode 3 and the source diffusion region and the drain diffusion region 丨3 with respect to the gate length direction. Each interval 2 is covered by the memory function unit 11. That is, in the semiconductor storage device including the FET, an expanded portion is formed in the surface of the semiconductor substrate 1, and a lower portion of the side surface of the gate electrode 3 is tapered. The channel region 丨9 is formed between the gate electrode 3 and the pair of source diffusion regions and the drain diffusion regions 丨3, 丨3 of the conductivity type and the channel region formed on both sides of the channel region 19. On the side wall of the gate electrode 3, memory functional units 11 are formed, each of which contains: a charge retention portion 3 J having a function of storing a charge of nickel nitride, and an anti-consumption insulator having a function of preventing stored charge consumption. 32. Since the offset region 20 is covered by the memory function unit 11, respectively, η Τ is changed from the source diffusion region when the voltage is applied to the gate electrode 3 in accordance with the charge 4 remaining in the Μ function Μ π. And the amount of current flowing from one of the drain diffusion regions η to the other of the source diffusion region and the drain diffusion region 13. = shown in the figure, since the charge-retaining portion is not formed in the portion where the FET performs the closed-pole function as shown in the prior art, but the second---in addition to the (four)-pole, it is possible to solve the over-wiping known in the prior art. In addition to the problem. The source diffusion region and the non-polar diffusion region 13, 13 are disposed on the bottom surface portion le, le of the semiconductor substrate, and the gate stack 8 is on the semiconductor substrate table 91971. Doc • 90- I248201 7 flat portion la, wherein these members are each opened via the inclined portion (four). Therefore, since the substantial offset width becomes offset from the design (lateral) by the width A, the device can be reduced while maintaining sufficient The offset width. Also, for the reason of the structure, the distance between the source diffusion region and the drain diffusion region 13, 13 becomes substantially larger than the distance of the design basis, thereby suppressing the power of the J and the Crystal operation deteriorates, such as punch-through and short-channel effects... Therefore, it is sufficient to provide a semiconductor memory device suitable for shrinking and allowing to reduce manufacturing costs. - Although the source diffusion region and the non-polar diffusion region 13 are not formed to extend to the inclined portion 1b of the surface of the semiconductor substrate as shown, this is not limitative. That is, if it is to be formed to extend to the inclined portion, the source diffusion region and the drain diffusion region 13 are formed such that the source diffusion region and the gate diffusion region 13 can be shifted to form the gate stack 8 on the surface of the semiconductor substrate. The bottom portion of the gate electrode). Furthermore, by doing so, the efficiency of injecting hot electrons generated during writing into the memory functional unit can be improved. Further, with such a configuration, since the offset region 2 can be formed to cover the gate electrode, the short channel effect can be suppressed, so that the reduction can be achieved. Moreover, when the charge is injected or discharged by the voltage of the gate electrode 3, since the gate electrode 3 is positioned above the offset region 2, the charge can be injected or discharged more efficiently. Therefore, the writing speed can be increased. Further, for structural reasons, the voltage of the gate electrode 3 effectively affects the vicinity of the channel of the memory functional soap 70 11' 11, so that it is easier to inject and erase the charge. Therefore, it is possible to provide a semiconductor storage device which can suppress writing/erasing or reading failure and high=since. Furthermore, since the (four) of the gate electrode 3 can have 91971. Doc •91 - 1248201 affects the offset portion of the channel, so _ provides a semiconductor memory device in which the drive current in the erase operation is large enough to suppress misreading and high read speed. Furthermore, due to the variable resistance effect of the memory functional unit u, the conductor storage device can function as a memory unit having the function of a selective transistor and a memory transistor.半导体 The semiconductor substrate 1 and the inter-electrode 3 are preferably formed of a material made of dreams. In this case, since the semiconductor substrate is formed by the gate electrode 3 as a semiconductor device material, it is possible to establish a semiconductor memory device H which is highly compatible with the conventional semiconductor process and which can provide a semiconductor memory device having a low manufacturing cost. Furthermore, in a specific embodiment of the semiconductor memory device of the present invention, two or more bit information is stored in one component, thereby enabling the semiconductor memory device to be stored in four or more values. Memory component. The semiconductor storage device of the present invention may have the configuration shown below. Now define the naming of the memory functional unit and its individual parts as follows. Assuming that the memory functional unit u, as shown in FIG. u(4) to FIG. ((4)), comprises: - a charge retention portion 3 is formed beside the gate electrode 3 and is made of a material having a function of storing a charge; and - is resistant to consumption The insulator has the function of preventing the stored charge from being stored. In this case, the anti-consumer insulator 32 may have a first dielectric ... and a: tf 32b ( 11 (b) '11 (C)) ' or have a first dielectric but no second dielectric ( Figure 11 (a)). The formation of the first dielectric material 32a allows the charge retention portion 3i and the closed electrode to be recognized. Doc - 92 - 1248201 The semiconductor substrate 1 is isolated, and the second dielectric 32b can be formed as a sidewall spacer outside the charge retention portion 31. Both the first dielectric 32a and the second dielectric 32b have a stored charge dissipation prevention. The function. As a result, the charge retention characteristics can be improved. Further, as shown in Figs. 11(a) to 11(d), the source diffusion region and the drain diffusion region 13 are spaced apart from the gate electrode 3 in the channel direction on the surface of the semiconductor substrate 1. More specifically, the gate stack 8 including the gate electrode 3 and the gate insulating film 2, and the source diffusion region and the drain diffusion region 13 are spaced apart from each other in the surface portion of the semiconductor substrate, that is, 'on the semiconductor substrate 1. On the surface, there is no source diffusion region and drain diffusion region 13 (via the gate insulating film 2) directly under the bottom surface of the gate electrode 3, and a range in which the width of the offset region 20 is spaced apart. That is, the channel region 19 between the source region and the drain region can be disposed under the memory function unit 超过 beyond the width of the offset region 20 of the surface of the semiconductor substrate 1. As a result, electrons and injection holes can be efficiently injected into the memory function unit, so that a semiconductor memory device with fast writing and erasing speed can be formed. Therefore, in the semiconductor memory device, since the source diffusion region and the drain diffusion region 13 are offset from the gate electrode 3, the amount of charge stored in the memory function unit 11 can largely change the offset of the memory function unit 1 The degree of reversibility of the region when the voltage is applied to the gate electrode 3 can thus increase the memory effect. Furthermore, the short channel effect can be suppressed as compared with a MOSFET of a general structure, so that the gate length can be reduced. Compared with the logic transistor having no offset configuration, the structural suitability of the short channel effect suppression for the above reason can be made by using a gate insulating film having a relatively large film thickness, and thus reliability can be improved. Furthermore, the formation of the memory functional unit 1 of the semiconductor memory device is unique. Doc -93- 1248201 stands outside the gate insulating film 2. Therefore, the transistor operation functions provided by the memory function unit «1 and the gate insulating film 2 can be separated from each other. There are also some reasons for choosing a memory function unit 丨i for materials that are suitable for memory functions. In this case, as shown in Fig. 11 (c), the formation of the charge retention portion 31 of the memory function unit u can be curved along the configuration of the gate electrode 3 of the semiconductor substrate i. Although this figure shows the charge retention portion 31 in a curved line, for the sake of simplicity, the subsequent partial pattern will omit the curved portion. Therefore, individual configurations must be considered to properly interpret the configuration. Furthermore, as shown in FIG. 11(d), the conductive type and the source diffusion region and the drain diffusion region can be formed in a pair of source diffusion regions and drain diffusion regions 13, 13 (i.e., offset regions). And an extension portion 6, 6 having a shallower joint depth than the source region and the drain region. The source diffusion region and the drain diffusion region 18 including the extension portion are formed to form the source region and the drain region including the extension portion 6 (generally designated as the multi-test number 18) to extend to the inclined portion lb. At the same time, the short channel effect is suppressed. Therefore, the efficiency of injecting hot electrons into the memory functional unit can be improved, so that writing can be efficiently achieved. Further, since the upper portion of the offset region can be formed to cover the gate electrode 3, the short channel effect can be suppressed, so that the reduction can be achieved. Further, since the gate electrode 3 is positioned above the offset region, it is possible to more efficiently inject and discharge the charge at the voltage of the gate electrode 3, thereby increasing the writing speed. In this case, if the doping concentration of the extended portion 6 is lower than that of the other portion 13 of the source diffusion region and the drain diffusion region 18, the short passback effect is more suppressed, and conversely, if the doping concentration of the extended portion is Higher, it can further improve the efficiency of hot carrier generation. 91971. Doc -94- 1248201 In the following cases, the source diffusion region and/or the nuclear region 18 including the extension portion 6 may be doped with the opposite conductivity type of the source diffusion region and the drain diffusion region. The impurity concentration ratio is higher in the channel region directly below the bottom surface of the gate electrode

In the opposite region 22, it is possible to push the efficiency of the generation of hot electrons on the top of the mountain, and to increase the writing efficiency. The port 1' can also improve the writing efficiency even if the opposite region b' is formed in the source diffusion region and the drain diffusion regions 13, 13, i.e., in the offset region of the semiconductor memory device described in Figures u(4)·u(4). Furthermore, the semiconductor memory device can also be implemented in the following modes. A semiconductor storage element forming a memory of the semiconductor memory device of the present invention is mainly a L 3 gate insulating film, a gate electrode formed on the gate insulating film, and a memory functional unit formed on both sides of the gate electrode of the semiconductor memory device a channel region formed under the gate electrode, and a source diffusion region and a drain diffusion region formed on both sides of the upper channel region and opposite to the conductivity type and the channel region. The semi-V body storage 7C piece can store two or more values of information in one memory function unit, thereby serving as a semiconductor storage element for storing information of four or more values. Due to the variable resistance effect of the memory functional unit, the semiconductor storage element can also be used as a memory unit having both the function of the selector transistor and the memory transistor. However, the semiconductor memory component does not necessarily have to form information capable of storing four or more values and as such a component, it can also form a function of storing information of two values. The semiconductor memory element constituting the semiconductor device of the present invention is preferably formed on the semiconductor substrate or in the same well region formed in the semiconductor substrate and in the channel region of the conductive type and the semiconductor substrate. 91971. Doc -95 - 1248201 The semiconductor substrate is not limited to a specific one used in current semiconductor devices, but different substrates can be used, such as a substrate made of an elemental semiconductor including germanium and germanium, including SiGe, GaAs, InGaAs, A substrate made of a composite semiconductor of ZnSe and GaN, an SOI (insulator) substrate, a multilayer SOI substrate, and a substrate having a semiconductor layer on a glass or plastic substrate. Among these substrates, a tantalum substrate or an SOI substrate having a tantalum surface layer is preferred. The semiconductor substrate or the semiconductor layer may be a single crystal (e.g., a single crystal obtained by stupid growth), polycrystalline, or amorphous, although the amount of current flowing therein is somewhat different. Preferably, the device isolation region is formed in a semiconductor substrate or a semiconductor layer, more preferably in combination with elements such as a transistor, a capacitor and a resistor, a circuit composed thereof, a semiconductor device, and an interlayer insulating film or film to form a single layer or Multi-layer structure. Note that the device isolation region can be formed by any of a variety of device isolation membranes, including: LOCOS (local enthalpy oxide) membranes, trench oxide membranes, and STI (shallow trench isolation) membranes. The semiconductor substrate may be of a p-type or N-type conductivity type and preferably form at least one first conductivity type (P-type or N-type) well region in the semiconductor substrate. The desired impurity concentration of the semiconductor substrate and well region is within the ranges known in the art. Note that in the case where the s?I substrate is used as the semiconductor substrate, the well region may be formed in the surface semiconductor layer, or the body region may be provided under the channel region. The example of the gate insulating film is not particularly limited and may include those used in a typical semiconductor device, such as an insulating film including a hafnium oxide film and a tantalum nitride film; and an oxide film including a single layer film or a multilayer film, and oxidation. High dielectric film of titanium film, oxidized film, and yttrium oxide film. Among these films, a ruthenium oxide film is preferred. A suitable thickness of the gate insulating film is, for example, about the thickness of the equivalent insulator 丄 91971. Doc -96 - 1248201 to 20 nm, preferably 1 to 6 nm. The gate insulating film may be formed only under the gate electrode or may be formed larger than the gate electrode (width). The gate electrode or electrode formed on the gate insulating film is in a shape usable in the semiconductor device or in a shape having a concave portion at the lower end portion. Here, the "single gate electrode" can be defined as a single or multi-layer conductive film and 幵y becomes a single inseparable gate electrode. The gate electrode may have a sidewall insulating film on each side. As long as it can be used for a semiconductor device, the gate electrode is generally not particularly limited, and may have a conductive film as follows: polycrystalline %; metal including copper, aluminum; high melting metal including tungsten, titanium, and button; and single layer Or a sulphate of a molten metal in the south. The gate electrode should be suitably formed with, for example, a film thickness of about 50 to 400 nm. Note that the channel area is formed under the gate electrode. The memory functional unit includes at least a film or region having a function of preserving charge, storing and retaining charge, trapping charge, or retaining charge polarization. Materials for achieving these functions include: nitrogen cutting; dreams; inclusion of impurities such as constitutive or boron (tetra) acid salt glass; carbon cutting; cascading clay; high dielectric substances such as oxidative, oxidative, or oxidizing groups; And metal. The memory functional unit may be formed as a single layer or a multilayer structure: for example, an insulating film containing a nitrogen cut film; an insulating film of an internal conductive film or a semiconductor layer; and an insulation containing - or a plurality of conductor dots or semiconductor dots membrane. In some of the slave structures, nitrogen is better, because it can reach a large hysteresis characteristic due to the presence of the charge level of the money' and has the following good retention characteristics: the charge retention time is very long and almost no cause The leakage path creates a charge leakage, and further because it is commonly used in LSI programs 91971. Doc -97- 1248201 material. The use of an insulating film having a charge retention function inside the insulating film, such as a tantalum nitride film, can increase the reliability of memory retention. Since the tantalum nitride film is an insulator, even if a part of the charge leaks, the charge of the entire tantalum nitride film is not lost immediately. Furthermore, in the case of arranging a plurality of storage devices, even if the distance between the storage devices is shortened and the adjacent memory functional units are in contact with each other, the memory is not lost as if the memory functional unit was made of a conductor. Information stored in the functional unit. Also, a contact plug that is closer to the memory function unit can be configured, or in some cases, the contact plug configuration can be overlapped with the memory function unit, thereby contributing to the reduction of the load device. In order to improve the reliability of the memory retention, the insulator having the function of retaining the charge does not have to be a film shape & and the insulator having a function of retaining charge is preferably present in the insulating film in a dispersed manner. More specifically, the insulator is preferably dispersed in dots on a material that is difficult to retain charge, such as oxidized stone. There is also inside. The insulator film containing a conductive medium or a semiconductor layer as a functional unit of a memristor can be freed from controlling the amount of charge of a conductor or a semiconductor, thereby generating an effect contributing to the achievement of a multi-level cell. Furthermore, the use of an insulator film containing - or a plurality of conductor dots or semiconductor dots as a memory functional unit contributes to performing writing and erasing due to direct charge wear, thereby producing an effect of reducing power consumption. Moreover, it is very suitable to use a ferroelectric film such as PZT (the wrong acid titanate ePLZT), as a functional unit of the memory, because its polarization direction can be electrically 91971. Doc -98- 1248201 Field change. In this case, the charge is substantially generated on the surface of the ferroelectric film by polarization and will remain in this state. Therefore, the charge can be supplied from the outside of the film having a memory function, and the same hysteresis characteristics as the film in which the charge is trapped can be obtained. In addition, since it is not necessary to inject a charge from the outside of the film, hysteresis characteristics can be obtained only by the charge in the polarizing film, so that high-speed writing and erasing can be achieved. Preferably, the memory functional unit further includes an area that prevents the charge from flowing out or a film that prevents the electrical discharge function. Materials that can perform the function of preventing charge outflow include oxidized ground. The charge-retaining portion contained in the memory functional unit is formed on both sides of the inter-electrode directly or via an insulating film, and is directly disposed on the semiconductor substrate via the closed-electrode insulating film or the insulating film (well region, body region or source) Polar diffusion zone and 汲, scatter or diffusion zone). Preferably, the charge retention knives on either side of the gate electrode cover all or part of the sidewalls of the gate electrode either directly or through an insulating film. In the application in which the gate electrode has a concave portion on the lower edge side, the charge-retaining portion may form the entire concave portion or the partial concave portion directly or via the insulating film. Preferably, the gate 4 electrode is formed only on the sidewall of the memory functional unit or forms an upper portion that does not cover the functional unit of the memory. In this configuration, the contact interposer configuration can be placed closer to the gate electrode, thereby helping to shrink the semiconductor storage 7G device. Also, a semiconductor memory element having such a simple configuration is easy to manufacture, and thus the yield can be increased. If a conductive film is used as the charge retention portion, it is preferable to dispose the charge retention portion with the insulating film so that the charge retention film does not collide with the semiconductor substrate 91971. Doc -99- !248201 (well zone, body zone or source diffusion zone and drain diffusion zone or diffusion layer zone) or gate electrode direct contact. This can be implemented by a structure including, for example, a multilayer structure including a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape in an insulating film, and a sidewall insulating film partially formed on a sidewall of a gate. The structure of the conductive film. The source diffusion region and the drain diffusion region may be disposed on opposite sides of the memory functional unit from the gate electrode as the diffusion region (the opposite of the conductivity type and the semiconductor substrate or the well region). In the portion where the source diffusion region and the drain diffusion region are bonded to the semiconductor substrate or the well region, the impurity concentration is preferably relatively high. This is because high impurity concentrations can effectively produce low-voltage hot electrons and thermoelectric holes, allowing high-speed operation at lower voltages. The depth of bonding of the source diffusion region and the drain diffusion region is not particularly limited, and therefore it may be adjusted depending on the performance of the manufactured memory device and the like as needed. Note that if the s〇i substrate is used as the semiconductor substrate, the bonding depth of the source diffusion region and the drain diffusion region may be smaller than the film thickness of the surface semiconductor layer, but the bonding depth is preferably almost equal to the film thickness of the surface semiconductor layer. The source diffusion region and the drain diffusion region may be disposed to overlap or intersect the gate electrode edge or offset from the gate electrode edge. In particular, the source diffusion region and the drain diffusion region are preferably offset relative to the gate electrode edge. This is because in this case, when a voltage is applied to the gate electrode, the reversibility of the offset region under the charge retention portion is largely changed by the charge stored in the memory functional unit, thereby increasing the memory effect and Reduce the short channel effect. However, please note that excessive offset greatly reduces the drive current between the source and drain. Therefore, the offset (from the edge of the gate electrode to the source region or 汲 91971. Doc -100 - 1248201 The distance of the pole region from the gate electrode in the direction of the gate length is preferably shorter than the thickness of the charge retention portion in the gate length direction. It is particularly important that at least a portion of the charge retention portion of the hidden body work target unit overlaps with the source diffusion region and the drain diffusion region as the diffusion layer region. This is because the semiconductor storage element constituting the semiconductor wave device of the present invention is characterized in that the voltage difference between the gate electrode and the source diffusion region and the gate diffusion region which are present only in the wall portion of the core body and the gate diffusion region are utilized. The electric field is overwritten by the electric field across the memory functional unit. ~ The source diffusion region and the non-polar diffusion region of the boring tool can extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is suitable to dispose the conductive film on the source diffusion region and the drain diffusion region formed in the semiconductor substrate integrated with the source diffusion region and the drain diffusion region. Examples of the conductive film include, for example, a polycrystalline germanium and an amorphous germanium semiconductor, a germanide, and the above metal and a highly molten metal. Among these conductive films, polycrystalline germanium is preferred. Since the impurity diffusion speed of the sa-sa is much larger than that of the semiconductor substrate, it is easy to make the junction depth of the source diffusion region and the drain diffusion region in the semiconductor substrate shallow, and the short channel effect can be easily controlled. In this case, the source diffusion region and the drain diffusion region are preferably arranged such that at least a portion of the charge retention film is sandwiched between the pair of source diffusion regions and the drain diffusion region and the gate electrode. The semiconductor memory element of the present invention can be formed using a conventional semiconductor process in the same manner as the side wall spacers forming a single layer or a stacked structure on the sidewalls of the gate electrode or the word line. Specifically, these methods are as follows: A method comprising the steps of forming a gate electrode or a word line, and then forming a single layer film or a multilayer film comprising: a charge retention portion, such as a 91971. Doc • 101 - 1248201 Guaranteed ",, a charge retention part / insulating film - absolute two = film / charge retention part, insulating film, and in the appropriate center = hunting by thin film leaving the shape of the sidewall spacer, including the following ^ Forming an insulating film or a charge-retaining portion, which is formed by thinning in a film leaving a shape of a sidewall spacer, forming a portion or a film of the edge, and under appropriate conditions by thin; sidewall isolation a film of a shape comprising a method of coating or depositing an insulating film material in which a specific charge-preserving material is dispersed on a semiconductor wafer of the electrode and, under suitable conditions, by leaving a side wall A spacer-shaped insulating film material; a method comprising the steps of: forming a single-layer film or a multilayer film after forming the gate electrode, and performing patterning by using a mask, etc. Moreover, the methods are as follows: A method of the following steps: forming a charge retention portion, a charge retention portion/insulating film, an insulating film/charge retention portion, or an insulating film/charge retention portion before forming a free electrode or a -electrode a film forming an opening through a film that becomes a region of the channel region, forming a gate electrode material film on the entire upper surface of the wafer and patterning the gate electrode material film to be larger in size than the opening and surrounding the film A shape of the opening. The best mode for constructing the memory cell array i T semi-body storage element by arranging the semiconductor memory element of the present invention is to comply with, for example, the following requirements: (I) a plurality of semiconductor memory elements The integrated body of the inter-electrode has the function of a word line; (II) the functional unit is recorded on each side of the word line; 9l971. D〇( 1248201 (iii) The material retaining the charge in the memory functional unit is an insulator, in particular, a tantalum nitride film; (iv) the memory functional unit is composed of a 〇N〇 (oxide nitride oxide) film And the surface of the tantalum nitride film is approximately parallel to the surface of the gate insulating film; (v) the tantalum nitride film in each memory functional unit is separated from the word line and the channel by a hafnium oxide film; (vi) The nitriding film in the A functional unit overlaps with the corresponding diffusion region; (5) separating the nitriding film (the surface is approximately parallel to the surface of the gate insulating film) and the thickness and gate of the insulating film of the channel region or the semiconductor layer The thickness of the pole insulating film is different; (viii) the writing and erasing operation of the semiconductor memory element is performed by a single word line; (IX) each memory function unit does not have an electrode for assisting the writing and erasing operation functions (Word line); and (X) a portion in contact with the diffusion region directly under each memory functional unit has a region in which the electric type is opposite to the conductivity type of the diffusion region. The best mode is a model that meets all of these requirements, but not necessarily all of the requirements. When you meet some of the above requirements, you will also have the best combination of requirements. For example, the best, 'and. Lie. (U1) The material retaining the charge in the memory functional unit is, "Ba", the luxury body, in particular, is a nitride film; (ix) there are no electrodes on each memory functional unit that assist in writing and erasing functions. (Word line); and the insulator (gas-cut film) in the functional unit of the second memory and the corresponding diffusion area are heavy 91971. Doc 1248201 璺. According to the discovery by the inventors, when the insulator retains 2 charges in the memory functional unit and has no electrodes therein, it is only in each memory functional unit on each memory functional unit having the function of assisting the writing and erasing operation. The insulator (nitriding film) overlaps with the corresponding diffusion region in order to perform the writing well. That is, when the requirements (4) and (8) are met, it is best to meet the requirements (5). On the other hand, if the conductor can retain the charge in the memory functional unit or if there is an electrode, on each memory functional unit having the function of assisting the writing and erasing operations, even the insulator in each memory functional unit The corresponding diffusion areas overlap and the write operation can still take effect. However, if the , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , benefit. That is, the contact plug configuration can be made closer to the memory functional unit. Alternatively, even if the semiconductor storage elements are placed close to each other in distance, the plurality of memory functional units do not interfere with each other, and thus the stored information can be retained. Therefore, it contributes to semiconductor storage elements. On the other hand, since the component structure is very simple, the number of manufacturing steps can be reduced, thereby increasing the yield. Also, it is advantageous to combine the transistors constituting the logic circuit and the analog circuit. Moreover, we have determined that the writing and erasing operations can be performed at a low voltage of no more than 5 V. This is why it is especially best to meet requirements (iii), (ix) and (vi). The semiconductor device of the present invention incorporating a semiconductor storage element and a logic element can be used for battery-operated portable electronic devices, particularly mobile terminals. In addition to mobile messaging terminals, examples of portable electronic devices are mobile phones and gaming machines. Q1071 dnr.  1248201 A tenth embodiment illustrates an N-channel device. However, the device may also belong to a P-channel in which the conductivity type of the impurity should be reversed. Moreover, in the drawings, like reference numerals refer to the Moreover, it should be noted that the drawings are schematic diagrams, and the dimensional relationship between the thickness and the plane, the thickness and the dimensional ratio between the layers and the portions, and the like are not the same as the actual ones. Therefore, the specific dimensions of thickness and size should be determined in the following description. Moreover, of course, there are also parts whose mutual dimensional relationships and ratios are different between the drawings. Moreover, unless otherwise stated, the thickness and dimensions of the various layers and portions described in this patent description are the dimensions of the final shape in the stage of forming the semiconductor device. Therefore, please note that the size of the final shape may vary somewhat depending on the thermal history of subsequent processes, etc., compared to the size immediately after film formation, impurity area, and the like. (Eleventh Embodiment) A semiconductor storage device according to an eleventh embodiment of the present invention will be described with reference to Figs. 12(a)-12(d) and Fig. 13. The process will be described in order along the following Figures 12(a)-12(d). As shown in FIG. 12(a), the gate insulating film 2 and the gate electrode 3 having the MOS structure and the m〇S (metal-oxide-semiconductor) generating program, that is, the gate stack 8' are formed on the P conductive On the substrate 1 of the type. A typical MOS generation procedure is as follows. First, a device isolation region made of a stone-like and having a p-type semiconductor region is formed on the semiconductor substrate 1 by a known method as needed. Device isolation area can be 91971. Doc -105 - 1248201 Prevent leakage current from flowing through the substrate between adjacent devices. However, it is not necessary to form such a device isolation region even if the devices adjacent to each other 'related to the common source diffusion region and the = pole diffusion region 13'. Forming the device isolation region prevents leakage current from flowing between adjacent devices through the substrate. Note that adjacent devices sharing the source diffusion region and the drain diffusion region do not have to form such device isolation regions. The above known device isolation region forming method may be any method which can isolate the devices from each other, whichever is known to use a LOCOS oxide method or a method known to use a trench isolation region or other known methods. Here, the method of not forming the device isolation region will not be described, and the device isolation region will not be shown in the drawings. Although not specifically shown, the impurity diffusion region is formed on and near the exposed surface of the semiconductor substrate. This hetero-f diffusion region is not used to control the threshold voltage, but to increase the impurity concentration of the channel region. # A suitable impurity diffusion region can be formed by a known method of obtaining a suitable voltage limit. Next, a dielectric film is formed entirely on the exposed surface of the semiconductor region. The dielectric film 'can be formed as a high dielectric film, a high dielectric film, and an oxide film, a nitride film, a combination of an oxide film and a nitride film, or the like, as long as it can suppress leakage. Material L: film formation. Further, since the film can form the gate insulator of the MOSFET, it is preferable to form a film having good performance as a gate insulator by a process including N2 ruthenium oxidation, NO oxidation, post-oxidation nitridation, and other steps. A film having good performance as a dielectric insulator means a dielectric film as follows: it can suppress each of the disadvantages in promoting the reduction of the MOSFET and the improvement of the efficiency, for example, suppressing the short channel effect of the MOSFET, suppressing the flow from passing through the interpole 91971. Doc •106- 1248201 The leakage current of the current of the second edge and the suppression of the gate electrode. The two SFET channel regions simultaneously suppress the impurities of the empty gate electrode. Like $, = T = = thick = ... - heart. The degree of oxygenation is between 1 nm and 6 nm. A closed electrode material is formed on the dielectric crucible. As for the gate electrode material, any material can be capable of exhibiting the performance of a MOSFET such as a silicon germanium, doped polysilicon or other semiconductor, germany, m or other metal, which is in all cases. Polycrystalline liturgate. For example, in the formation of this situation, the thickness of the enamel film is preferably 50 nm to 4 〇〇 nm. Then, the desired photoresist pattern is formed on the inter-electrode material by the lithography process, and the photoresist pattern is used as a mask, and the gate electrode material and the gate electrode material are The insulating film is formed to form the structure of the figure (4). That is, the gate insulating film 2 and the gate electrode 3 and the gate stack 8 formed therewith can be formed. Although not shown in the figure, in this procedure, the gate insulating film may not be engraved. In the subsequent step of impurity implantation, the step of forming a protective film of the implant can be simplified by using the non-existing inter-electrode insulation. The materials of the month, the gate insulating film 2, and the gate electrode 3 may be materials used in a logic program conforming to the current proportionality law, and are not limited to the above materials. Furthermore, the gate stack 8 can also be formed by the following procedure. The gate insulating film constructed as described above can be completely provided? The exposed surface of the semiconductor substrate 1 of the type semiconductor region is formed. Next, an inter-electrode material having the above-described f is formed on the gate insulating film. Next, a mask dielectric film of oxide, rat, oxygenated or the like is formed on the free electrode material. Next, a photoresist pattern as described above is formed on the mask "electrofilm, and then etched 91971. Doc -107- 1248201 2 cover dielectric film. Then, the photoresist pattern is removed, and the mask dielectric is used as an etch mask, the gate electrode package is etched, the exposed saddle is etched, the exposed portion of the mask dielectric gate insulating film is etched, and the knife is hunted to form a pattern. Structure of 12(a). In this way, the gate stack is formed in this way, and the etched and etched gate insulating material of the gate (4) x, the choice of the gate electrode material for the plant position, and the margin of the boat edge, that is, the inter-membrane pole Insulator. In this two big:: no need for the seesaw but for the same reason as above, no: = Although not shown in the figure, the gate is insulated with a gate insulating film. The thermal oxidization is performed by the extreme enthalpy and the semi-conductance = Γ, thereby forming a black-striped dielectric film between the two sides of the surface of the inter-electric and h-body substrate i, respectively. Having a portion gradually widened from the side in the cross-sectional plane, l8a. The formation of such a bird's beak (a portion gradually widened in cross section = 8a) can be formed by performing thick oxidation to form the extension gate electrode 3 And a vaporized 4^ oxide film between the interfaces of the semi-body substrate 1. In this case, a thick film of oxide must be formed, if it is etched under the "·ρ stop_protection, even thin oxidation The shape of the bird can also be formed. That is, the conditions under which oxidation should be performed are as follows: The reactive species (oxygen or oxidation) is sufficiently extended to the inter-electrode and the semiconductor substrate, that is, the reactivity is compared with the general oxidation conditions. The type is at a higher pressure or higher temperature or at a higher pressure or a higher temperature to make a partial pressure. Although an oxide film is used as the bird-shaped dielectric film 18: a vaporized film can be used, It can also be replaced by a version of nitride and oxide. Hunting this step can be done in half The surface of the bulk substrate i is swollen, and the step of forming the lower portion of the gate electrode 3 of the reverse tapered shape. The connector, as shown in Fig. 12(c), removes the bird-shaped dielectric film μ. Take this in 91971. Doc -108 - 1248201 = where the bird-shaped dielectric film 18 is removed, that is, where the two sides of the gate electrode 3 and the surface of the semiconductor substrate 1 are formed, a recess is formed which is gradually widened from the side in the cross section. . Thereafter, the first dielectric film 9 made of an oxide is formed along the exposed surface of the inter-three-inch and 8- and half-substrate substrates in which the recesses 5, 5, and the recesses have been formed. This first dielectric film 9 can be formed after partial anti-consumption insulation. The first dielectric film 9, in this case, uses an oxide, which is a dielectric film through which electrons pass, and therefore preferably has high resistance to electric waste, small leakage current, and high reliability. Membrane to provide. For example, as the material of the gate insulating film 2, an oxide film such as a thermal oxide film, an n(4) oxide (tetra) film, and the like can be used. The oxide film thickness is preferably from 1 nm to 20 nm.爯去, a啦:山人^ Dan is making this dielectric film so thin that it can be worn with electricity/7"IL, the electricity required to inject or erase the charge can be lower / and can be reduced Power consumption. The typical film thickness in this case is preferably 3 nm to 8 nm. In this procedure, 'after the formation of the dielectric film, the dielectric film is removed' and then a thinner dielectric is formed again. In addition to this procedure, the electric film 1 is known to have such a procedure as follows. That is, in the gate electrode generating program described in Fig. 12 (a), the portion below the side surface of the gate electrode becomes an inverted cone. = mode to perform the stenciling process. In this step, under the condition that the deposit is placed on:, it is engraved to the vicinity of the gate oxide surface. These deposits are thicker upward in the upper portion. The etch of the oxide is completely removed, and the two deposits are thin or unmanned, and the etched on the same day is etched on the lower side of the side of the gate electrode where the deposit is very thick. Under the side of the side of the Buwan mouth knife and the structure of the recess. Then, by 91971. Doc 1248201 A guanine-shaped oxide film made of an oxide is formed by performing ordinary oxidation or under such conditions as forming a thin oxide film as described in Fig. 12 (b). Therefore, it is possible to form the same structure as that shown in Fig. 12(c), or a structure in which the semiconductor substrate is very flat and only the gate electrode is the same. Even if the semiconductor substrate is very flat, the following steps can be performed using the same steps as in the case where the semiconductor substrate is not flat. If the semiconductor substrate is flat, the operational effect that the uneven semiconductor substrate can produce cannot be produced as compared with the unevenness of the semiconductor substrate, but an operational effect of increasing the drive current can be produced. Next, as shown in Fig. 12 (d), tantalum nitride 17 which is normally uniformly deposited as a material of the charge retaining portion in accordance with the manner in which the recess 5 掩 is hidden. The semiconductor storage device of the tantalum nitride 17 may be, for example, 2 11111 to 1 〇〇 nm. This film thickness is an important parameter for forming a source diffusion region and a drain diffusion region which are offset from the gate electrode 3, and can be controlled within the film thickness range in consideration of the offset amount. Although tantalum nitride is used in this case, in addition to tantalum nitride, a material which retains a charge generating property, for example, a nitrogen capable of retaining a substance having an electron and a hole charge and the like, may be used. An oxidizing material, or an oxide having a charge trapping, or a ferroelectric material capable of being produced by polarization or other phenomena: a charge on a surface of a functional unit of a memory, or a floating substance having a polycrystalline germanium, such as an oxide film. Or a material that retains the structure of the charge. Also, when these materials are used, the same operational effects as when using nitrogen are produced. In this case, the nitriding button having the charge storage function by forming the first dielectric film 9' is in contact with the semiconductor substrate and the gate electrode via the dielectric film, so that the leakage of the retained charge can be suppressed by the dielectric film. . Therefore, it can be 91971. Doc 110-1248201 A semiconductor storage device with good charge retention characteristics and long-term reliability. Then, as shown in FIG. 13, the tantalum nitride 17 and the first dielectric film 9' are etched to thereby include the first dielectric 32a and the charge retention portion 31 on both sides of the gate stack 8. The memory functional unit η, 丨丨 is formed as a sidewall. The first dielectric 32a is formed by a portion of the first dielectric film 9, and the charge retention portion 31 is made of a portion of tantalum nitride. Furthermore, by using the gate electrode 3 and the memory function unit U, 丨丨 as a mask, impurity implantation for forming the conventional source diffusion region and the drain diffusion region 13 can be performed, and then the required heat treatment is performed, thereby forming Source diffusion region and drain diffusion region 13. In this case, the source diffusion region and the drain diffusion region 13 may be formed before the formation of the memory functional unit , or after the formation of the memory functional unit ,, and in principle, the same effect may be produced. However, when the source diffusion region and the drain diffusion region are formed before the formation of the memory functional unit U, it is not necessary to implant a protective film, so that the procedure can be simplified. Here, the case where the source diffusion region and the drain diffusion region 13 are formed after the memory functional unit is formed has been described. The procedure for forming the above-described memory function list & will now be described in detail as follows. First, the tantalum nitride 17 is anisotropically etched, thereby leaving the nitride 17 as the sidewall on the sidewall of the gate stack 8 via the first dielectric film 9. In this case, it is preferable to perform the engraving under the condition that the selectivity of the (iv) first dielectric film 9 and the first dielectric film 9 made of oxide is large. Next, the first dielectric film 9 is anisotropically patterned, whereby a first dielectric 32a made of a portion of the first dielectric film 9 is formed on the sidewall of the interpole stack 8. In 91971. Doc -111 - !248201 In this case, it is preferable to perform selective etching on the condition that the first dielectric film 9 and the tantalum nitride 17 and the gate electrode 3 and the semiconductor substrate 1 can be selectively etched. . In this way, the memory function unit 11, U can be formed as a side wall on both sides of the gate stack 8 in such a manner as to thereby hide the recess 5?. Then, a source diffusion region and a drain diffusion region 会3 are formed. That is, with the gate electrode 3 and the memory function unit 1!, 丨丨 as a mask, it is possible to implant an impurity having a conductivity type opposite to that of the channel region, and performing a heat treatment for conventional activation. As a result, the source diffusion region and the drain diffusion region 13, 13 having a specific junction depth can be formed in a self-aligned manner. In this case, since impurities are implanted into the semiconductor substrate 1 without passing through the coating film, the shallow implant impurity can be a film thickness of the coating film which is not present under the control of the implantation energy, and thus the bonding can be formed. For a specific depth. Now through the above steps, the memory function unit has been formed. Semiconductor memory devices employing these memory functional units have the following operational effects. When the s electricity remains in the charge retention portion 31 of the memory function unit ,, part of the channel region is strongly affected by the charge, causing the value of the drain current to change. Therefore, it is possible to form a semiconductor memory device which can distinguish the presence or absence of the charge based on the change in the value of the drain current. Further, since the gate insulating film 2 and the memory functional unit u are separated from each other by the arrangement, different types of scaling can be performed. Therefore, it is possible to provide a semiconductor memory device which can suppress the short channel effect to have a good memory effect. Also, due to the tantalum nitride 17 in the memory functional unit via the dielectric film and 91971. Doc - 112 - 1248201 The semiconductor substrate 1 and the gate electrode 3 are in contact, so that the shallow leakage of the retained electricity can be suppressed by the dielectric film. Therefore, it is possible to form a semiconductor memory device having good charge retention characteristics and high long-term reliability. Further, if an electron conductor or a semiconductor is used as the memory function unit, a positive voltage is applied to the gate electrode, and polarization occurs in the memory functional unit, causing electrons to be generated in the vicinity of the sidewall portion of the gate electrode, resulting in the vicinity of the channel region. The electrons are reduced. Therefore, the injection of electrons from the substrate or the source diffusion region and the drain diffusion region can be accelerated, so that a semiconductor memory device with high writing speed and high reliability can be formed. (Twelfth Embodiment) A semiconductor memory device according to a twelfth embodiment of the present invention will be described in detail with reference to Figs. 14(a)-14(c). As shown in Fig. 14 (c), the semiconductor memory element in this embodiment is generally the same as that of the semiconductor memory element of the eleventh embodiment. However, this embodiment is characterized in that such an L-cutter 6 and/or an opposite region 22 as shown in Figure u(d) is provided. With this particular embodiment, the above structure can be formed in accordance with self-alignment without adding any special mask. Furthermore, an extended F-knife 6 having a junction depth shallower than the source diffusion region and the drain diffusion region 丨3 is formed in the pair of source diffusion regions and the drain diffusion regions 13, 13 (i.e., in the offset region). The germanium type is the same as the source diffusion region and the gate diffusion region, thereby forming a source diffusion region and a drain diffusion region 18 including an extension portion. Therefore, under the suppression of the short channel effect, the source diffusion region and the drain diffusion region 18 including the extension portion to be close to the slope portion can be formed, whereby the efficiency of the hot electron injection memory functional unit can be increased to perform the writing efficiently. Also, 91971. Doc - 113 - 1248201 Since the upper portion of the offset region can be formed to cover the gate electrode 3, it is possible to suppress the short channel effect and further reduce it. Further, since the gate electrode 3 is positioned above the offset region, the charge can be injected and discharged more efficiently with the voltage of the gate electrode, so that the writing speed can be increased. In this case, by making the impurity concentration of the extended portion 6 lower than the other portion 13 of the source diffusion region and the drain diffusion region 18, the short channel effect can be more effectively suppressed, and conversely, the impurity concentration is higher. Increase the efficiency of hot carrier generation. Furthermore, in the source diffusion region and the drain diffusion region 包括8 including the extension portion, when the conductivity type is opposite to the source diffusion region and the non-polar diffusion region and the impurity concentration is higher than the opposite region 22 of the channel region, Further increase the efficiency of generating hot electrons and greatly increase the writing efficiency. Even when the opposite region 22 is formed within the source diffusion region and the drain diffusion region 13 (i.e., in the offset region), the writing efficiency can be improved as well. Further, since the joint depth of the extended portion 6 is shallower than the other portion 13 of the source diffusion region and the drain diffusion region 18, the lateral change can be suppressed as compared with the portion 13 having a deeper joint depth. Therefore, since the variation in the width of the offset region and the direction (channel direction) can be suppressed low, a highly reliable semiconductor storage device can be formed. However, it is also possible to form the source diffusion region and the drain diffusion region to overlap on the inclined portion only by implanting impurities forming the normal source diffusion region and the drain diffusion region. However, in this case, the variation reducing effect in the lateral direction (channel direction) width is not generated as compared with the case of forming the extended portion, but the operational effect of the simplified procedure is generated. As a method of manufacturing the semiconductor storage device, the manufacturing method of Figs. 12(a)-12(d) described in the eleventh embodiment can be basically used. However, 91971. Doc - 114 - 1248201 I' As a characteristic step of this embodiment, the step of forming the extended portion and/or the opposite region may be increased. Although Fig. 14 (4) - 14 (4) shows the case where the extended portion is formed separately, the following description also includes the case where the opposite region is formed. 7 卩 As shown in Fig. 14(a), the structure shown in Fig. 12(4) will be formed first, but the first L-extension knife 6 will be known to be the same as the source diffusion region and the non-polar diffusion region. & can be achieved by performing impurity implantation with an implantation energy lower than the source diffusion region and the drain diffusion region. However, it is not necessary to complete the heat treatment at this stage, which can be performed simultaneously with the later formation of the source diffusion region and the 汲 (4) political region. , in the source diffusion region and the drain diffusion region 18, the portion of the shallow junction depth that can be formed in b below the other portion 13 (see Figure 14(c)) "results" can form an extension The change in the direction of the change in the diffusion region of the portion 6 is smaller than that in the portion 13 in which the deeper joint depth is formed. , 吏 ', so the variation in the offset region can be suppressed to a small change. Therefore, in particular, it is possible to suppress a change in the number of charge injections in the memory functional unit, thereby forming a semiconductor memory device capable of suppressing variations in characteristics of the agricultural device and high reliability. At this stage, if the impurity implantation forming the opposite region is further performed to obtain a conductivity type opposite to the source diffusion region and the non-polar diffusion region, the column can form a reverse region. As with the formation of the extension, the heat can be performed in a later procedure: instead, the opposite must be formed in the extended region as shown in Figure U(4), by implanting the implant with an implant angle larger than the extension form. Also, if the opposite region is formed separately without forming an extension, it will be 91971. Doc 115- 1248201 forms a structure in which the source diffusion region and the drain diffusion region and the opposite region are in contact with each other. Next, as shown in Fig. 14 (b), the tantalum nitride 7 which is a material of the charge-retaining portion is formed in such a manner as to hide the recess 5?. The procedure of Fig. 12(d) of the eleventh embodiment can provide a method of forming tantalum nitride 17. Next, as shown in Fig. 14 (c), memory functional units 11 each containing a charge retention portion 31 and a first dielectric 32a are formed on both sides of the gate stack 8. The program of Fig. 13 of the eleventh embodiment can provide a method of forming the memory functional unit 11. Thus, a semiconductor storage device in which the opposite region and/or the extended portion have been formed has been formed. (Twelfth Detailed Embodiment) A semiconductor memory device according to a thirteenth embodiment of the present invention will be described in detail with reference to Figs. 15(a)-15(c). . 15(c), the semiconductor memory device in this embodiment is generally the same as the semiconductor memory device of the tenth embodiment. However, the specific embodiment is characterized in that 4 can be separately mounted. At the recess 5 (the charge retention portion 31 is restricted from being formed, so that the southernmost position of each charge retention portion becomes lower than the highest position of the gate electrode 3. Therefore, the tenth-and-semiconductor storage element phase described in the embodiment In comparison, it is possible to form a charge retention portion that is limited to the vicinity of the product/, and the carrier, so that it is easier to erase the electrons injected by the write operation, and it is less likely to cause erasure failure and increase. Secondly, while the number of main incoming powers remains unchanged, it can reduce the volume of the charge retention part of the central guarantee, so 91971. Doc -116- 1248201 : To increase the amount of charge per unit volume. Therefore, it is possible to achieve electronic writing/erasing and to provide a semiconductor storage device for writing/erasing speed. In the structure, the partial memory functional unit 11 and the charge retention portion 31 made of tantalum nitride having a charge storage function are sandwiched between the anti-consumable insulator 32 (the first dielectric 32a and the second) Between dielectrics 32b). Therefore, the dispersion of the retained charge can be suppressed, and a semi-body storage device with good retention characteristics can be provided. Further, by providing the charge retention portion 3 丨 sandwiched between the anti-consumable insulator 32 (the first dielectric material 32a and the second dielectric material 32b), the charge injected by the writing operation can be suppressed from being dispersed to The gate electrode and other nodes can improve the charge injection efficiency and achieve high-speed operation. Basically, the manufacturing method of Figs. 12(a) to 12(d) described in the eleventh embodiment can provide a method of manufacturing the semiconductor storage device. However, in this specific embodiment, the step after the formation of the structure shown in Fig. 13 is performed, that is, the step after the implantation of the impurity forming the source diffusion region and the drain diffusion region 13 is performed. Thereafter, as shown in FIG. 15(a), anisotropic etch back is further performed to remove a portion of the tantalum nitride (material of the charge retaining portion 3A) existing outside the recess 50, thereby performing nitrogen removal. The step of leaving the crucible in the recess 5〇. Therefore, the operational effect of the reduced memory function unit 11 can be obtained while ensuring a sufficient offset width. In the step of the # memory function unit 11, it is preferable to use isotropic etching because it can be simultaneously reduced in the height direction and the width direction at one time. In addition, the execution conditions of this narration are as follows: · It is possible to select the substance that constitutes the functional unit of the memory, and it is difficult to name the gate 91971. Doc •117- 1248201 The material of electrode 3 and semiconductor substrate i. For example, a wet button engraving procedure (using heat scaly acid) can be used. However, in the case where the memory functional unit uses the same material as the semiconductor substrate or the gate electrode 3, that is, the memory functional unit has a polycrystalline stone or a defect, and the semiconductor substrate is formed with germanium or the gate electrode is formed of polysilicon. In the case of the code or other similar cases, the selection ratio in these materials will not be achieved, and when the isotropic etching is performed using, for example, hydrogen fluoride as an etchant, the polysilicon or defect in the memory functional unit will remain unchanged. Etched. In this case, it is suitable to perform further oxidation to oxidize the etching residue, and thus etching of hydrogen fluoride can be performed to remove the residue. Next, as shown in Fig. 15 (b), a generally uniform deposited dielectric film 15 is formed. As the deposited dielectric film, a film having a good step coverage such as HTO (High Temperature Oxide) or a film using CVD (Chemical Vapor Deposition) can be used. When using HTO, the film thickness is about 1 〇 11111 to 1 〇〇 nm. Then, as shown in FIG. 15(c), the dielectric film 15 is etched by using an etch back process, whereby partial deposition can be performed. The illustrated second dielectric 32b formed by the dielectric film 15 is formed as a sidewall. The deposited dielectric film 5 is anisotropically etched, whereby the memory functional units 11 each containing the first dielectric 32a, the charge retention portion 31, and the second dielectric 32b are formed as gate stacks 8, respectively. Side walls on both sides. The execution condition of this remaining moment is preferably as follows: the etching selectivity ratio at which the dielectric film 15 and the semiconductor substrate 1 can be selectively etched is large. Further, although the eleventh embodiment is also explained, the impurity implantation for forming the source diffusion region and the non-polar diffusion region 13 can also be completed before the formation of the charge retention portion 31. This is also applicable to this specific embodiment. However, here 91971. Doc -118- !248201 情 =中 The closing phase of the nitrogen cut 17 is completed after the step of implanting impurities. (Fourteenth embodiment) A semiconductor storage device according to a fourteenth embodiment of the present invention will be described with reference to Figs. 16(a)-16(d). Fig. 16(4) shows that the semiconductor memory element in this embodiment is generally the same as the semiconductor memory element of the thirteenth embodiment. However, this embodiment is characterized in that not only the electric line retaining portion 3 but also the entire side along the idle electrode 3 (via the first medium 1 32a) is formed in the recess 5〇. The charge retention portion 31 may be formed to cover the side of the gate electrode 3 which is not entirely but also mostly. In this structure, the partial memory functional unit 11 and the charge retaining portion 31 which is formed by cutting the nitrogen having the function of the staggered charge are sandwiched between the edge dielectric-dielectric 32a and the second dielectric f32b). Therefore, the dispersion of the retained charge can be suppressed, and the semiconductor storage device with good retention characteristics can be provided. By arranging the structure in which the charge retaining portion 31 is sandwiched between the anti-consumable insulator 32 (the first dielectric layer and the second dielectric f32b), the charge injected into the gate can be dispersed to the gate electrode and Other nodes can improve charge injection efficiency and achieve high speed operation. Basically, the manufacturing method to 12 (C) described in the eleventh embodiment can provide a method of manufacturing the semiconductor storage device. That is, the structure of Fig. 12(c) is formed according to the method described in the eleventh embodiment. After that, as shown in Fig. I6(4), a first dielectric film 9 which is generally uniformly made of an oxide is formed along the gate stack 8 and the exposed surface of the semiconductor substrate (5). This first dielectric film 9, in this case, will use an oxide since it will become an electron 91971. Doc -119- 1248201 The dielectric film that passes through it is therefore best provided with a film with high withstand current and high reliability. For example, as the leak is small, an oxide film such as a thermal oxide film, an n2 tantalum oxide: film, a material of the film 2 and the like can be used. The oxide film thickness is the best: 0 broad film nm. Further, when the first dielectric film 9 is formed to be in the following state, the voltage required for injecting or erasing the electric charge can reduce the force rate by 4 with the motor flow. The typical film thickness in this case is preferably in this case, by forming the first dielectric film 9, the tantalum nitride 17 having the charge storage power enthalpy will pass through the dielectric film and the half junction m L , , The conductor substrate and the gate electrode are in contact, and the mouth can suppress the retention of the charge (4) by the dielectric film. Therefore, a semiconductor 7G device with good charge retention and high long-term reliability is realized. In accordance with the manner in which the recess 50 is thereby concealed, it is generally uniformly deposited as a material of the remaining portion of the material of the nitride stone 7 wire. Although nitrite is used in this case, in addition to nitriding, a material capable of retaining charge generation can be used, for example, nitriding such as a substance capable of retaining charges of electrons and holes and the like. An oxygen material, or an oxide having a charge trapping, or a ferroelectric material capable of generating a charge on a surface of a functional unit of a memory by a polarization or other phenomenon, or having an oxide film such as a polycrystalline stone A floating material or a material that retains the structure of the charge. Also, the same operational effects are produced when using these materials. However, when the conductive film is used, the charge retaining portions 31, 31 on both sides (right and left sides) of the gate electrode must be interrupted from each other to prevent them from being short-circuited to each other. In this case, the film thickness of the nitride nitride 17 is about, for example, 2 faces to (10) 91971. Doc 1248201 nm ° then 'will be formed along the exposed surface of the nitride argon 17 to generally form a second dielectric film, which is formed to form at least a portion of the anti-consumable insulator and is made of an oxide. As the second dielectric film, a film having a good step coverage such as HTO or a film using CVD is suitable. In the use of an oxide as the second dielectric film, the film thickness is about 5 nm to 1 〇〇 nm. Further, the second dielectric film can be formed by subjecting the nitriding film to a surface treatment by heat treatment. Next, the second dielectric film is anisotropically etched, thereby forming a second dielectric 32b, 32b' on both sides of the gate stack 8 via the first dielectric film 9 and the tantalum nitride 17 as shown in FIG. 16(b). ) shown. The execution conditions of this etching are preferably as follows: the etching selectivity ratio of the second dielectric film 9 and the tantalum nitride 17 can be selectively selected. Next, as shown in Fig. 16 (c), impurity implantation for forming the source diffusion region and the drain diffusion region 13 is performed. When impurities are implanted on the tantalum nitride 17 and the first dielectric film 9 in this step, any sacrificial oxide film must be formed to prevent roughening of the surface of the semiconductor substrate. Therefore, the program can be simplified and a low-cost semiconductor storage device can be formed. Alternatively, the impurity implantation step of forming the source diffusion region and the drain diffusion region 13 may be performed after the formation of the memory functional unit. Moreover, this step can be completed during the formation of the memory function unit 11, i.e., after etching the nitride 17 to form the charge retention portion 31, on the first dielectric film 9. Next, as shown in FIG. 16(d), the second dielectric 3 is used as an etch mask, and the tantalum nitride 17 is isotropic or anisotropically etched, thereby passing through the first dielectric film 9, A charge retention portion 31 made of tantalum nitride is formed on both sides of the gate stack 8. In this case, it is preferable to selectively etch nitrogen 91971. The doc-121 - 1248201 etched 17 and the first dielectric film 9 made of oxide and the second dielectric material 32b are etched under conditions which are larger than those reported. Next, the first dielectric film 9 is anisotropically etched, thereby forming a first dielectric 32a on the sidewall of the gate stack 8. In this case, it is preferable to perform etching under the condition that the selective dielectric etching of the first-dielectric film 9 and the charge-retaining portion made of the nitride nitride, the idle electrode 3, and the semiconductor substrate 很大 are large. Now, already. A memory functional unit 丨i each including a first dielectric 32a, a charge retention portion Η, and a second dielectric 32b is formed. However, there are cases where the first dielectric material 32a and the second dielectric material 3 are made of the same material (e.g., oxide), in which case a large etching selectivity cannot be obtained. Therefore, in this case, it is necessary to take into consideration the amount of the second dielectric material 32b when etching the first dielectric film, and reduce the amount of the remaining amount when forming the second dielectric material 3 2b as needed. In addition, there is a tendency that the upper portion of the electron-preserving portion 31 made of tantalum nitride is more or less etched. However, this is not important, especially because it can reduce the charge retention portion, and conversely, it can produce a reduction in the operational effect of the charge retention portion described in the thirteenth embodiment. Furthermore, in any of the following cases: impurity implantation for forming the source diffusion region and the drain diffusion region 13 is performed on the tantalum nitride 17 and the first dielectric film 9 as described with reference to FIG. 16(c). In the case of the implantation on the first dielectric film 9, and the completion of the implantation after the formation of the memory functional unit, the source diffusion region and the drain may be formed by adding a subsequent heat treatment required thereafter. Diffusion zone 13. 91971. Doc -122- 1248201 The procedure of the structure of Figure 16(b) to the structure of Figure 16(d) can be performed in one step t (the steps of forming the source diffusion region and the non-polar diffusion region are not taken into account) By performing the anisotropic etch under the following conditions, it is possible to perform a procedure which generally requires three steps. · The first dielectric film 9, the first, the cladding film, and the tantalum nitride 17 can be etched. And the material of the gate electrode 3, the etching selectivity of the material of the semiconductor substrate 1 is large. Therefore, the number of program steps can be reduced, and the manufacturing cost can be reduced. Now, through the above steps, the memory function unit U has been formed. The semiconductor memory device using these memory function units U has the following operational effects. When the charge remains in the charge retention portion η of the memory function unit u, part of the channel region is strongly affected by the charge, causing the drain current value f to be changed. Therefore, it is possible to form a semiconductor memory device which can distinguish the presence or absence of the charge based on the change in the value of the drain current.

Also, the gate insulating film 2 and the memory function sheet are separated by the configuration, so that different types of scaling can be performed. Therefore, it is possible to provide a semiconductor memory device which can suppress the short channel effect to be a good memory effect. Appropriately, since the charge retention portion 31 (made of nitride nitride) in the memory functional unit 11 is in contact with the semiconductor substrate 1 and the inter-electrode 3 via the dielectric film, D suppresses the retained charge by the dielectric film. leak. Therefore, it is possible to form a semiconductor memory device which has good retention characteristics and high long-term reliability. Further, if a material conductor or a semiconductor is used as a material of the memory functional unit, when a positive voltage is applied to the gate electrode, polarization occurs in the memory functional unit 91971.doc -123 - 1248201, causing the vicinity of the sidewall portion of the gate electrode. Electrons are generated, resulting in a decrease in electrons near the channel region. Therefore, the injection of electrons from the substrate or the source diffusion region and the drain diffusion region can be accelerated, so that a semiconductor memory device having a high writing speed and high reliability can be formed. (Fifteenth Embodiment) The semiconductor memory device in this embodiment is as follows: each of the memory function units 161, 162 includes: a region in which a charge can be retained (a region in which a charge can be stored and which can be a film having a function of retaining charge) ), and a region where the charge is difficult to flow out (may be a film having a function of making it difficult for the charge to flow out). For example, the device has a meandering structure as shown in Figs. 17(a) and 17(b). More specifically, the tantalum nitride film 142 is interposed between the hafnium oxide film 141 and the hafnium oxide film 143, thereby constituting the memory function unit 161 or 162. Here, the nitride film 142 can perform a charge retention function. Further, the oxidized stone film 141 has a function of making it difficult for the charge stored in the tantalum nitride film 142 to flow out. Further, in the memory function unit 丨6丨, i62, the region where the charge can be retained (the tantalum nitride film 142) overlaps the source diffusion region and the drain diffusion region 112, 113, respectively. Here, "overlapping" means that at least a portion of the charge-retaining region (ytterbium nitride film 142) exists over at least a portion of the corresponding source diffusion region and drain diffusion region 112 or 113. Incidentally, the numeral lu represents a semiconductor substrate, numeral 114 represents a gate insulating film, numeral 117 represents a gate electrode, and numeral i7i represents each offset region (between the gate electrode 117 and the diffusion region 112 or 113). Although not shown in the drawing, the highest front surface portion of the semiconductor substrate lu under the gate insulating film 114 may become a channel region. 91971.doc - 124 - 1248201 The benefit will be explained by the fact that the regions 142 capable of retaining charge in the memory functional units 161, 162 overlap the source diffusion region and the drain diffusion regions 112, 113, respectively. 18(a) and 18(b) are enlarged views of the memory function unit 162 of Fig. 17 (a) and Fig. 17 (b) and its vicinity. Symbol W1 represents the magnitude of the offset between the gate electrode 117 and the diffusion region 113. Further, the symbol W2 represents the width of the memory function unit 162 seen in the cross section of the gate electrode 117 from the channel length direction of the memory function unit 162. In the memory function unit 162, the end of the tantalum nitride film 142 remote from the gate electrode 117 coincides with the end of the memory function unit 162 remote from the gate electrode 117, and the width of the memory function unit 162 is defined as W2. The size of the overlap between the memory function unit 162 and the diffusion area U3 is represented by (W2-W1). It is particularly important that in the memory function unit 162, the tantalum nitride film 142 overlaps the diffusion region 113, that is, conforms to the relationship of W2 >. Further, in the case shown in Figs. 19(a) and 19(b), in the memory function unit 162a, the end of the tantalum nitride film 142& away from the gate electrode 117a and the farther from the gate electrode 117a. The end of the memory function unit 162a, the visibility W2, can be defined as an extension from the end of the gate electrode to the end of the nitride film 142a away from the gate electrode 117a. As a drain current in the erased state (storable hole) in the structure shown in FIGS. 18(a) and 18(b), a sufficient current value can be obtained in the arrangement in which the tantalum nitride film 142 overlaps the diffusion region 113. . However, in the configuration in which the tantalum nitride film 142 does not overlap the diffusion region 113, the drain current is abruptly decreased with the distance between the tantalum nitride film 142 and the diffusion region 113, and it can be lowered at a distance of about 3 〇 nm. Three levels. 91971.doc -125- 1248201 Since the value of the drain current is substantially proportional to the speed of the read operation, the memory efficiency degrades rapidly as the distance between the tantalum nitride film 142 and the diffusion region 113 increases. Conversely, in the range in which the tantalum nitride film 142 overlaps the diffusion region 113, the decrease in the drain current is relatively moderate. Therefore, the tantalum nitride film 142 which is at least partially a film having a function of preserving charge preferably overlaps the source region and the drain region. With the above results in mind, a memory cell array can be fabricated by setting a width of 2 to 1 〇〇 nm and setting a width of 6 〇 nm & 100 nm to the design value. If the width W1 is 60 nm, the tantalum nitride film 142 and the corresponding source diffusion region and the drain diffusion region 112 or 113 overlap by 4 〇 nm as designed values, and if the width "1 is 10 〇 11 „1, then it will not Overlap as design values. The number of reads of the memory cell array can be measured. As a result, in the case of the worst spread, the read access time was 100 times, which was shorter than the width...丨 set to the design value of 6〇11111. In actual use, the read access time is preferably 00 nanoseconds or less per bit. It has been found that this requirement can never be achieved under the condition of Wl = W2. It is known that the condition of W2_W i > 1Qnm is better even when the manufacturing is spread. When reading the information stored in the memory function unit 161 (area 181), the source diffusion region and the non-polar diffusion region 112 are used for the source electrode and the diffusion region U3 as the non-polar region, preferably near the bungee A locking point is formed on the side of the passage area of the zone 113. That is, the reading of the Bellows _ lock point stored in one of the two memory function units is preferably formed in an area close to the 〇f channel area of the other memory function unit. Therefore, regardless of the memory of the memory function unit 162, it is possible to detect the information stored in the memory function unit 16 i, which is an important factor for the 2_bit operation. Similarly, in the case where the poor news is only stored in one of the memory functional units 91971.doc -126 - 1248201 the functional unit enters the same same storage shape does not need to be in the reading mode t formation, or by making two In the case of memory, in the case of using memory, the locking point. ::: Although not shown in Figures 17(4) and (8), the Ρ•well is preferably shaped on the front surface of the semiconductor substrate (1). Due to the formation of the well region, it is optimized along with the channel region operation (rewrite operation and read operation), which helps to control the two properties (tolerance, junction capacitance, and short channel effect from improving memory) From the standpoint of retention characteristics, each memory function sheet 70 preferably includes a charge retention portion and an insulating film functionally capable of retaining charges: in this embodiment, a nitride nitride film having a level trapped charge may be employed. 142 is used as an electric # reserved portion, and an oxygen cut film 141 which can prevent the electric charge stored in the charge retaining portion from being dissipated, (4) as an insulating film. Since the self-hidden limb function includes the charge retaining portion and the insulating film, The retention characteristics can be improved by preventing the charge from being dissipated. Further, the volume of the charge retention knives can be made smaller than that of the ** charge γ retention portion of the 5 hexameric functional unit. A small charge is appropriately formed. When a part of the volume is reserved, it is possible to limit the electric charge of the remaining part of the person's and to suppress any characteristic change caused by the charge transfer occurring in the storage retention state. Preferably, the unit includes a charge-retaining portion disposed substantially parallel to the surface of the gate insulating film, that is, the upper surface of the charge-retaining portion of the memory that is formed into a single-turn can be disposed to be positioned on the upper surface of the gate insulating film. Specifically, as shown in FIG. 2A(a) and FIG. 20(1), the charge retention portion 142a of the memory function unit 162 has substantially the gate insulating film 114 with 91971.doc -127-1248201. The surface is parallel to the plane. That is, it is preferable to form the charge retention portion 142a at a uniform height from the height corresponding to the front surface of the gate insulating film 114. The charge on the front surface of the gate insulating film 114 is parallel. The reserved portion 142a is present in the memory function unit 162, and therefore, according to the amount of charge stored in the charge trap 142a, the convenience of forming the reverse layer in the offset region J 7 i can be effectively controlled, and relatively Further, since the memory retention portion 142& is substantially parallel to the front surface of the gate insulating film 114, even if the offset size (W1) has been dispersed, it can be kept relatively small. Since the memory effect is changed, it is possible to suppress the dispersion of the memory effect, and it is possible to suppress the upward-upward transfer of the charge of the charge-retaining portion 142a and to suppress any characteristic change caused by the charge transfer occurring in the storage retention state. Preferably, the memory function unit 162 includes an insulating film that can separate the charge retention portion 142 & and the channel region (or well region) substantially parallel to the front surface of the gate insulating film 114 (for example, the yttrium oxide film 141 is biased) The portion on the transfer region 171. Due to the insulating film, it is possible to suppress the dissipation of charges stored in the charge retention portion 142 & and to obtain a semiconductor memory device having better retention characteristics. 'By the way, from the semiconductor substrate 丨丨The distance from the front surface of the crucible to the electric charge stored in the electric charge retaining portion 142a can be kept approximately constant in the following manner: the film thickness of the charge retaining portion 142a can be controlled, and the charge retaining portion 142a can be controlled (the tantalum oxide film 141 is biased) The portion of the transfer region m) has a thickness of the lower insulating film. That is, it is possible to control the distance from the surface of the semiconductor substrate to the charge stored in the charge retaining portion 142a of 91971.doc -128-1248201 to be the lowest thickness value of the insulating film under the charge retaining portion 142a and the charge retention portion. The highest thickness value and the highest film thickness value of the charge retention portion (10) may be approximately the same as the power line density generated by the charge stored in the charge retention portion (10), and the memory bank strength of the memory element is dispersed. Become small. (Sixteenth embodiment) In this embodiment, as shown in Figs. 21 (4) and 21 (b), the charge retention portion 142 of the memory energy unit 162 has a substantially uniform film thickness, and has the following configuration The arrangement is substantially parallel to the front surface of the gate insulating film ι4 (indicated by arrow 181) and is also substantially parallel to the side surface of the gate electrode 117 (indicated by arrow 182). In the case where a positive voltage is applied to the gate electrode 117, the power line (i.e., electric field) in the memory function unit 162 passes through the tantalum nitride film 142 twice, as indicated by arrow 183 (portions indicated by arrows 182 and 181). . Incidentally, when a negative voltage is applied to the gate electrode 117, the effect of the power line is reversed. Here, the relative dielectric constant of the tantalum nitride film 142 is about 6, and the tantalum oxide film i4i, 143 is about 4. Therefore, in the direction of the power line (arrow 183), the memory function unit 162 is effective relative; | % the number of hangs is relatively large, and the potential difference between the ends of the power lines can be made smaller than the charge retention portion indicated by only the arrow 181 Happening. That is, a larger portion of the voltage applied to the gate electrode 丨i 7 can be used to enhance the electric field in the offset region 171. The reason for injecting charges into the tantalum nitride film 142 in the rewriting operation is that the electric field in the offset region 171 attracts the generated charges. Since the charge retention portion of 91971.doc -129 - 1248201 shown by the arrow ι82 is included, the charge injected into the memory function unit 1 62 in the rewriting operation can be increased, and the rewriting speed can be increased. Further, in the case where the portion of the yttrium oxide film 143 is also replaced by a tantalum nitride film, that is, in the case where the charge retention portion does not coincide with the height corresponding to the front surface of the gate insulating film 丨14, the tantalum nitride film The upward migration of charge can be significant, and the retention characteristics deteriorate. For the same reason, the charge-retaining portion is preferably formed of a highly dielectric substance having a very large relative dielectric constant, such as ruthenium oxide, in place of the ruthenium nitride film. Further, the memory functional unit preferably includes an insulating plate (the portion of the oxidized second film 141 on the offset region 171) which can separate the charge retaining portion and the channel region (or well region) substantially parallel to the front surface of the gate insulating film. ). Due to the insulating film, the dissipation of charges stored in the charge-retaining portion can be suppressed, and the south retention characteristics can be further improved. Further, the memory function unit preferably further includes an insulating film (the portion of the oxide oxide film 141 and the contact gate electrode 117) which separates the gate electrode and the charge retention portion extending in parallel with the side of the gate electrode. Due to the insulating film, it is possible to prevent the electrical characteristics from being changed by injecting charges from the gate electrode into the charge retaining portion and to improve the reliability of the semiconductor memory device. Further, the thickness of the insulating film (the portion of the ytterbium film 141 on the offset region 171) under the charge retaining portion 142 is preferably controlled to be fixed, and an insulating film (the yttria film 141 and the ytterbium oxide film 141 are disposed on the sidewall of the gate electrode). The thickness of the portion contacting the gate electrode 117 is preferably controlled to be fixed. Therefore, it is possible to prevent the charge stored in the charge retention portion 142 from leaking. 91971.doc •130· 1248201=In this aspect of the matter, at least part of the gate insulating film and at least the function of the memory function are at least the same as the thickness of the oxide film of the E (8) f-electrode film. The sidewall of the gate electrode opposite to the memory functional unit extends through the memory functional unit to reach the equivalent thickness of the oxide film under the memory functional unit = the surface of the substrate. Here, the "oxide film temple value" is an oxide film equivalent thickness obtained by multiplying the thickness of the insulating film by the ratio of the dielectric constant of the oxide film to the dielectric constant of the insulating film. When the insulating film contains some dielectric layers and one of the layers is not made of an oxide film, but is made of, for example, a nitride film, 刖 + + 6 γ is considered in the equivalent thickness of the ruthenium oxide film. The thickness of the zircoid of the nitride film layer. The above structure means that when electric power is applied between the substrate under the closed electrode and the gate electrode, the electric field intensity in the path extending from the closed electrode to the substrate via the interpole insulating film is smaller than the side wall opposite to the functional unit from the gate electrode and the memory functional unit Extending the electric field strength in the path of the substrate surface under the memory functional unit through the memory functional unit. That is, in the case of the structure of FIGS. 21(4) and 21(8), the oxide film of the gate insulating film 114 has an equivalent thickness smaller than that of the arrow (8) and extends from the sidewall of the gate electrode 14217 of the bismuth telluride film 142 to the semiconductor substrate. The path of the m surface. The path extends through the oxidized stone film (4), the nitriding film 42 and the oxygen film 141 or the oxygen film (4), the nitriding film 142, the yttrium oxide film 143, the tantalum nitride film 142, and the yttrium oxide film. . In the above aspect, since the equivalent thickness of the oxide film of the gate insulating film is smaller than a path extending from the opposite electrode and the side wall of the memory functional unit through the static body function unit to the semiconductor substrate, in this case, (For example, in the case where the gate insulating film is used as the gate insulating film of the MOSFET, the threshold voltage of 91971.doc -131 - 1248201 is set to be low', so that low-interference of low-reading electromigration can be achieved. Providing a semiconductor memory device with low power consumption. Further, the gate of the gate insulating film is made of 臈, and at least a part of the memory functional unit is made of oxide yttrium, and the interlayer insulating film is oxidized. The equivalent thickness of the film is larger than the oxide film extending from the side wall of the open electrode and the functional unit of the memory through the J-resonant functional unit to the edge of the substrate to the surface of the substrate under the body functional unit. In the case of the structure of Fig. 21 (4) and Fig. 21 (8), the equivalent thickness of the oxide film of the interlayer insulating film 114 is larger than the path indicated by the arrow 183. In the above aspect, for example, In other words, by applying a potential of 10 volts and volts to the gate electrode and the source diffusion region and the polar diffusion region, respectively, it can be written on the gate electrode and the source diffusion region and the non-polar diffusion region. Imposing - Π) volts and 0 volts of potential can erase the information, so the immersed current does not flow because one of the source diffusion region and the non-polar diffusion region has the same potential as the other. Further, the gate insulating film is thick, so that leakage current through the interlayer insulating film (four) can be suppressed. Therefore, a + conductor memory device that reduces power consumption can be provided. Further, no hot carrier is generated, and any charge is not injected into the closed-electrode insulating layer, so that a limit voltage difference due to charge injection into the two-pole insulating film can be suppressed, and the conductor memory device can be suppressed. The half of the supply reliability (seventeenth embodiment) This embodiment relates to the optimization of the distance between the gate electrode, the memory functional unit, and the source region and the drain region. As shown in Fig. 22(a) and Fig. 22(b), the second mother A represents the length of the gate electrode seen in the section from the length of the channel, the word 91971.doc -132 - 1248201 distance (channel length), and the letter c

The distance of the gate electrode). The distance B between the source B and the drain region of the mother B represents the distance from the end of one memory functional unit to the other, that is, from the length of the channel.

It is assumed that the gate electrode 11 7 is B < C. In the channel region, the offset region 171 is stored between the source diffusion region and the drain diffusion region 丨12, 113. Due to the relationship of B < c, the reverse convenience in the entire offset region 171 can be effectively varied in accordance with the charge stored in the memory function unit 161, 162 (tantalum nitride film 142). Therefore, the memory effect can be increased, and in particular, the higher speed of the reading operation can be achieved. In addition, in the case where the source diffusion region and the drain diffusion regions 112, 113 are offset with respect to the gate electrode 117, that is, in the case of maintaining A < B, it may be stored in the memory functional unit. The amount of charge greatly changes the inversion convenience of the offset region 171 when a voltage is applied to the gate electrode Π 7, so that the memory effect can be increased and the short channel effect can be reduced. However, the offset region 171 does not need to exist all the time in the range in which the memory effect rises. Even if the offset region 171 does not exist, if the impurity concentration of the source diffusion region and the drain diffusion regions 112, 113 is sufficiently low, the memory effect in the memory functional units 161, 162 (tantalum nitride film 142) rises. Therefore, it is best to keep A < B < C. (Eighteenth embodiment) As shown in Figs. 23(a) and 23(b), the semiconductor memory 91971.doc - 133 - 1248201 body device in this embodiment has substantially the same as the eighth embodiment. The configuration is except that the semiconductor substrate is replaced with an SOI substrate. Here, the floating effect of the substrate unique to the SOI substrate is likely to occur, so that the generation efficiency of the hot electrons and the south writing speed can be improved. The semiconductor memory device is as follows: a buried oxide film i88 is formed on the semiconductor substrate 186' and covered by the SOI layer. The source diffusion region and the drain diffusion regions 112, 113 are formed in the SOI layer, and the common regions form the body region 187. Also, in the semiconductor memory device, the same operations and advantages as the semiconductor memory device of the eighth embodiment can be achieved. Furthermore, the junction capacitance between the source diffusion region and the drain diffusion region 丨12, 113 and the body region 187 can be made significantly smaller, so that the operation speed can be improved and the power consumption of the device can be reduced. (19th embodiment) As shown in Figs. 24(a) and 24(b), the semiconductor memory device in this embodiment has substantially the same configuration as the fifteenth embodiment except for the addition. The P-type high concentration region 191 is adjacent to the channel side of the N-type source diffusion region and the drain diffusion regions 112, 113. More specifically, the P-type impurity (e.g., boron) concentration in each of the P-type high concentration regions 丨91 is higher than the P-type impurity concentration provided in the P-type region 192. A suitable P-type impurity concentration in the P-type high concentration region 191 should be, for example, 'about 5 X 1017-1 X 1 〇 19 cm-3. Further, the P-type impurity concentration in the P-type region 192 can be set, for example, to 5 X 1016 -1 X 1 〇18 cm-3. When the P-type high concentration region 191 is disposed in this manner, the bonding between the source diffusion region and the non-polar diffusion regions 112, 113 and the semiconductor substrate 111 is directly in the memory 91971.doc - 134 - 1248201 functional unit 161, 丨 62 It became a steep sigh. Therefore, it is easy to generate a hot carrier in the writing operation and the erasing operation, so that the voltage of the writing operation and the erasing operation can be lowered or the speed can be increased. Furthermore, since the impurity concentration of the P_type region 192 is relatively low, the threshold voltage of the erasing state of the memory is low, and the = pole current becomes large. Therefore, the reading speed can be increased. Thus, a semiconductor sensible device having a low overwrite voltage or a high rewrite speed and a high read speed can be obtained. Further, referring to Figs. 24(a) and 24(b), the P_type high concentration region ΐ9 is arranged under the memory function units 161, 162 in the vicinity of the source region and the drain regions 112, 113 (i.e., It is not directly under the gate electrode 117), so that the entire electro-crystal (4) limit electromigration can rise significantly. The degree of rise is much higher than the case where the high concentration region i9i is directly positioned under the gate electrode 117. In the case where the write charge (electrons in the case where the transistor is an N-channel type) has been stored, the limit voltage difference is amplified more. The other side... In other cases, in the case where the memory has already stored enough erased charge (the transistor is a hole in the channel type), the limit voltage of the entire transistor will be The decrease is determined by the impurity concentration of the lower channel region (P-type region 192) of the gate electrode 117, that is, the impurity concentration of the P_type high concentration region 191 does not affect the erased threshold voltage '. The limit voltage of the input mode is affected by the thickening of the impurities. Therefore, when the ρ· type high concentration region 191 is disposed in the vicinity of the memory force month b 7G161, 162 and the source region and the drain region 112, 113, only the limit voltage of the write pull type fluctuates greatly, and Memory effects can be significantly enhanced (differences between the threshold voltages of the write and erase modes). (Twentyth embodiment) 91971.doc -135 - 1248201 As shown in Figs. 25(a) and 25(b), the semiconductor memory device in this embodiment has the essence of the fifteenth embodiment The same configuration except that the thickness (τι) of the insulating film 141 which can separate the charge remaining portion (tantalum nitride film 142) and the channel region or the well region is smaller than the thickness (TG) of the gate insulating film 114. The gate insulating film 114 has a lower limit value of its thickness TG because of the withstand voltage requirement of the memory rewriting operation. However, the thickness τι of the insulating film 114 can be made smaller than the thickness TG regardless of the withstand voltage requirement. When the thickness D is made smaller, it contributes to charge injection into the memory function unit 丨6丨 or 丨62, thereby reducing the voltage of the writing operation and the erasing operation or increasing the speed thereof. Moreover, when the charge has been stored in the tantalum nitride film 142, the amount of charge generated in the channel region or the well region is increased, thereby enhancing the memory function. Therefore, while maintaining Tl < TG, the voltage of the write operation and the erase operation can be lowered or increased, and the memory effect can be enhanced without deteriorating the memory endurance. Incidentally, the thickness T1 of the insulating film 141 is preferably at least 〇·8 ηηι, which is capable of maintaining homogeneity and process-based film characteristics at a specific standard and without greatly deteriorating the retention characteristics. (Different Embodiment) As shown in FIGS. 26(a) and 26(b), the semiconductor memory device in this embodiment has substantially the same configuration as that of the fifteenth embodiment. The thickness (Τ1) of the insulating film 141 except the separable charge-retaining portion (tantalum nitride film 142) and the channel region or the well region is larger than the thickness (TG) of the gate insulating film 114. The gate insulating film 114 has an upper limit value of its thickness TG because of the requirement of the element to prevent short-channel effects. However, the thickness of the insulating film 114 can be made large by a thickness of 1971, doc - 136 - 1248201 regardless of the thickness TG required to prevent the short channel effect. When the thickness ΤΙ is made large, the charge stored in the charge storage region 142 can be prevented from being dissipated, and the retention characteristics of the memory can be improved. Therefore, when Tl > TG is maintained, the retention characteristics of the memory can be improved without deteriorating the short channel effect therein. Incidentally, the thickness Τ1 of the insulating film 141 is preferably at most 20 nm in consideration of reducing the rewriting speed. (Twenty-second embodiment) A twenty-second embodiment of the present invention will be described with reference to Figs. 30(a) and 30(b). 30(a) and 30(b) are diagrams showing the structure of the 1C card. As shown in Fig. 30 (a), an MPU (Micro Processing Unit) portion 401 and a connector portion 408 are provided in the 1C card 400A. The MPU portion 401 includes therein a data memory portion 404, a calculation portion 402, a control portion 403, a ROM (read only memory) 405, and a RAM (random access memory) 406, all formed on a single wafer. The semiconductor device of the present invention is incorporated in the MPU portion 401. Various configurations can be interconnected by line 407 (including: data bus, power line, etc.). Further, when the 1C card 400A is stuck on the external reader/writer 409, the connector portion 408 and the reader/writer 409 are connected to supply power to the 1C card 400A, and to exchange data. The features of this embodiment are as follows: The MPU portion 401 and the data memory portion 404 are formed on a single semiconductor wafer, thereby forming an MPU portion 404 having a coexisting data memory portion 401. The semiconductor memory device capable of reducing the manufacturing cost as described in the present invention is employed as the data memory portion 404. Since the semiconductor memory device is easy to be microfabricated and capable of performing 2-bit operation, the position of the memory cell array in which such a device is disposed is also easily reduced. Therefore, the cost of the memory cell array can be reduced. When the memory cell array is used as the data memory portion 4〇4 of the 1C card 400A, the cost of the 1C card 400A can be reduced. In addition, since the data memory portion 404 is included in the Mpu portion 4〇1 and formed on a single wafer, the cost of the redundant card 4 can be greatly reduced. Further, the semiconductor memory device of the present invention is used in the data memory portion 404, and the semiconductor device of the present invention is used in the logic circuit portion, that is, the MPU portion 401 is formed by the semiconductor device of the present invention. Therefore, the components constituting the logic circuit portion (the calculation portion 4〇2 and the control portion knife 403) of the MPU portion 401 and thus the generation program are very similar to those in the case of using a flash memory, and the data memory portion can be easily obtained. The 4〇4 and logic circuit sections coexist, which can significantly simplify the coexistence of the adhesion process. Therefore, the advantage of reducing the cost based on the formation of the MPU portion 4〇1 and the data memory portion 4〇4 on a single wafer can become very large. Incidentally, the ROM 405 can be constituted by a semiconductor memory element. In this way, the ROM 405, which can store the program for driving the MPU portion 401, can be rewritten from the outside, thereby increasing the efficiency of the card by one (the effect of the card is very simple. Since the memory element is easily microfabricated and capable of 2_ In the bit operation, even if the mask ROM is replaced with a memory element, it is difficult to increase the wafer area. Moreover, since the program for forming the semiconductor memory element is almost the same as the normal program, the logic circuit is Part of the coexistence is also easy. Next, as shown in Fig. 30 (b), the Mpu portion 401, the RF interface portion 41, and the antenna portion 411 are disposed in IC + 4 〇〇 B. The Mpu portion 4 〇 1 is in 91971 .doc - 138 - 1248201 includes: data memory portion 404, computing portion 402, control portion 403, ROM 405, and RAM 406, all formed on a single wafer. By line 407 (including: data bus, power line, etc.) The various configurations can be interconnected. The 1C card 400B of Fig. 30(b) differs from the 1C card 400A of Fig. 30(a) in that the former is of a contactless type. Therefore, the control portion 403 is connected to the RF interface portion 410 instead of Connecting connector portion 408. RF interface Portion 410 may be further connected to the antenna portion 411. The antenna portion 411 has an external device and a communications and

Collect power functions. The RF interface portion 41 has a function of rectifying a radio frequency signal transmitted from the antenna portion 411 to provide a power supply, and has a function of modulating and demodulating a variable signal. Incidentally, on the single wafer, the RF interface portion 41 and the antenna portion 411 can be adhered and coexist with the Mpu portion 4?1. Since the 1c card 400A in this embodiment is of a non-contact type, it is possible to prevent electrostatic breakdown which may occur through the connector portion. In addition, it does not need to be in constant contact with external devices, so it is more versatile in use, and the semiconductor memory cells that constitute part of the data memory

The device can supply a voltage (for example, Q vuj such as about 9 v), which is lower than the prior art flash memory (about 12 V for the night, k ', μ package £), so the rf can be reduced. The circuit size of the interface portion 410 is to reduce cost. (Twenty-third embodiment of the present invention) The twenty-third embodiment of the present invention will be described with reference to FIG. 31, and the semiconductor of any one of the specific embodiments will be described. The portable electronic device driven by the Cui + sub-bathroom memory can be called "portable electronic two: two, portable telephone, swim, and ready". Figure 31 shows an example of a portable telephone 91971.doc - 139 - 1248201. The semiconductor device of the present invention is incorporated in the Mpu portion 5〇丨. When the semiconductor device of the present invention is applied to a portable electronic device, the manufacturing cost of the control circuit can be reduced, so that the cost of the portable electronic device can be reduced. Alternatively, the non-electrical memory included in the control circuit can be amplified in capacity, thereby improving the performance of the portable electronic device. As shown in Fig. 31, the portable telephone 5 includes therein a human interface portion 508, an RF (Radio Frequency) circuit portion 51A, and an antenna portion 511. The MPU portion 501 includes therein a data memory portion 5〇4, a calculation portion 502, a control portion 503, an R〇M 5〇5, and a RAM 5〇6, all of which are formed on a single wafer. Various configurations can be interconnected by the line 5〇7 (including data bus, power line, etc.). The features of this embodiment are as follows: Mpu portion 5〇1 and data memory portion 504 are formed on a single semiconductor wafer, thereby forming an MPU portion 501 having a coexisting data memory portion 504. A semiconductor memory device capable of reducing manufacturing cost as described in the present invention is employed as the data memory portion 504. Since the semiconductor memory device is easily microfabricated and can perform 2_bit operations, it is also easy to reduce the area of the memory cell array in which such components are disposed. Therefore, the cost of the memory cell array can be reduced. When the memory cell array is used as the data memory portion 504 of the portable telephone 5, the cost of the portable telephone 5 can be reduced. In addition, since the data memory portion 504 is included in the Mpu portion 5〇1 and formed on a single wafer, the cost of the portable telephone 5 can be greatly reduced. 91971.doc -140- 1248201 Furthermore, the semiconductor memory device of the present invention is applied to the data memory portion 504, and the semiconductor device of the present invention is applied to the logic circuit portion, that is, the MPU portion 501 is based on the present invention. A semiconductor device is formed. Therefore, the τ component of the logic circuit portion (the calculation portion 5〇2 and the control portion 503) constituting the MPU portion 501 and thus the generation program are very similar to those in the case of using a flash memory, and the data memory portion can be easily obtained. The coexistence of the 5〇4 and logic circuits partially simplifies the coexistence of the adhesion process. Therefore, the benefit of reducing the cost based on the formation of the MPU portion 5〇1 and the data memory portion Μ* on a single wafer can become very large. Incidentally, the ROM 505 can be constituted by a semiconductor memory element. In this manner, the R〇M5〇5, which can store the program for driving the MPU portion 501, can be rewritten from the outside, thereby greatly improving the performance of the portable telephone. Since the memory device is easily microfabricated and capable of 2_bit operations, it is difficult to increase the wafer area even if the mask ROM is replaced with a memory device. Moreover, since the program for forming the semiconductor memory element is almost identical to the flat f CM s generation program, it is also easy to coexist with the logic circuit portion. The invention can produce many, many benefits. <The semiconductor memory device of one embodiment of the present invention, wherein the charge retention portion of the memory functional unit is formed on the side of the gate electrode instead of the gate insulating film portion of the field effect transistor, and thus substantially eliminates Excessive erasure and defective read problems associated with it. , and the anti-consumable insulating film capable of suppressing the charge retention of the memory functional unit to dissipate, so that the charge retention time can be increased to make the gate electrode sidewall and the charge retention portion opposite to the sidewall; 91971.doc The distance (T2) of -141 - 1248201 is different from the distance (Τ1) of the bottom of the charge retention portion on the side of the semiconductor substrate. Therefore, when the distance τ 1 is made smaller than the distance Τ 2, for example, it is possible to prevent the charge injected from the semiconductor substrate from penetrating the memory function unit to reach the gate electrode, and conversely, when the distance T1 is made larger than the distance 12, the gate can be blocked. The charge injected by the electrode penetrates the memory functional unit to reach the semiconductor substrate. Therefore, a semiconductor memory device having high charge injection efficiency and high write/erase speed can be obtained. Further, in a semiconductor device according to an embodiment of the present invention, the source diffusion region and the drain diffusion region are not offset from the semiconductor portion 70 of the gate electrode portion, and the shifted semiconductor memory device, The memory functions that are co-existing on the same substrate and having a function of storing charges are disposed on the sidewalls of the gate electrodes in the respective semiconductor elements and semiconductor memory elements. However, since the processes of the two components are not significantly different, it is easy to coexist, for example, the coexistence of non-electrical memory including semiconductor memory elements and logic circuits including semiconductor elements. Moreover, since the thickness of the gate insulating film is not limited, it is possible to provide a semiconductor device which can easily apply the most advanced MOSFET process. According to the present invention, the specific embodiment (four) card can be used to include the Di1 domain and its peripheral circuit parts, and the logic circuit part of the Zhuangsi, which has coexistence and its cost can be reduced. It is easy to provide a reduced cost ic card. According to the portable electronic device of the present invention, the portable telephone can be used for example, wherein the non-electrical memory and its peripheral-segment are easy to coexist and its cost can be: 91971.doc -142 - 1248201 semiconductor device, thus providing a cost-reducing portable phone. In addition, according to a specific embodiment of the present invention, a method for manufacturing a half device can make a germanium element gate, a semiconductor device, a 70-gate electrode, a semiconductor, a thickness of an insulating film portion of the body member, and It is in contact with the element semiconductor substrate: the thickness of the portion is different, whereby the defective erase of the erase mode can be suppressed or the writing/erasing speed can be improved. More specifically, in the case where the thickness of the contact portion of the insulating film of the insulating film is smaller than the contact portion of the insulating film and the gate electrode, the defective erasing of the erasing mode can be suppressed, or the semiconductor substrate can be stopped. The injected charge penetrates the insulating film to reach the gate electrode, and thus can provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. Conversely, 'in the case where the thickness of the portion where the first insulating film is in contact with the semiconductor substrate is larger than the thickness of the first insulating film and the gate electrode contact portion, τ is to prevent the charge injected from the gate electrode from penetrating the first insulating film to reach the semiconductor. The substrate can thus provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. Furthermore, the formation of the source diffusion region and the drain diffusion region of the semiconductor memory device can be offset with respect to the gate electrode of the device and can overlap with the charge storage region of the device, so that the memory effect is advantageous and the source diffusion region is comparable. The case where the bungee expansion area is not heavy is more conducive to the current value of the read operation of the semiconductor memory device. Therefore, it is possible to increase the reading speed a lot, and thus it is possible to provide a semiconductor memory device with a high reading speed. Further, another manufacturing method for a semiconductor memory device according to an embodiment of the present invention 'the semiconductor substrate and the gate electrode of the semiconductor memory device are formed using materials of different compositions, so that the element 91971.doc - The thickness of the portion of the 143 - 1248201 in contact with the gate electrode is different from the thickness of the portion in contact with the semiconductor substrate, whereby the defective erase of the erase mode can be suppressed or the writing/erasing speed can be improved. Further, the step of forming the first insulating germanium of the semiconductor memory device may be performed by a usual step of forming the insulating film to be different in thickness from a portion contacting the gate electrode and a portion contacting the semiconductor substrate, and It is not necessary to use the characterization step or the like, and therefore (4) provide a semiconductor memory device which does not require any complicated steps and which is inexpensive to manufacture. Moreover, the source diffusion region and the drain diffusion region of the +conductor S memory element are offset from the element gate electrode and can be heavier than the element charge storage region, so the memory effect is advantageous and the comparable source The case where the polar diffusion region and the drain diffusion region do not overlap further increases the read current value of the semiconductor memory device. Therefore, it is possible to increase the reading speed of a plurality of semiconductor memory devices which can provide a south reading speed. In addition, there is also another method for fabricating a semiconductor memory device according to an embodiment of the present invention. The sensor electrode of the semiconductor memory device has a miscellaneous wave of at least 5 X 1 〇 19 cm.3, thus The effect of enhanced oxidation of impurities will occur. Further, an impurity region in which the concentration of each impurity is lower than the impurity concentration of the closed electrode is formed in the semiconductor substrate, and an insulating film according to the heat treatment is formed on the semiconductor substrate and the gate electrode. Therefore, the thickness of the portion where the first insulating film is in contact with the gate electrode and the thickness of the portion thereof in contact with the semiconductor substrate can be made very different, so that it is possible to provide a complicated process (such as etching) and a manufacturing cost of 4 艮 low. Conductor memory device. Furthermore, in the case where the thickness of the portion where the first insulating film is in contact with the semiconductor substrate of the semiconductor memory element 91971.doc - 144 - 1248201 is smaller than the thickness of the contact portion of the gate electrode of the first insulating film and the element, the The charge injected into the semiconductor substrate penetrates the first insulating film to reach the gate electrode, and thus can provide a semiconductor memory device with good charge injection efficiency and high write/erase speed. In addition, there is another manufacturing method for a semiconductor memory device according to an embodiment of the present invention, wherein the gate electrode of the semiconductor memory device has an impurity concentration of at most ix 1 〇 2 〇 cm · 3 and lower than the device. The impurity concentration of the semiconductor substrate can be set for the gate electrode without the effect of the effect of enhancing the oxidation of the impurity, and when the impurity concentration is higher than the gate electrode and at least 5 X 1019 cm-3, it starts in the semiconductor substrate. Significantly, the effect of enhanced oxidation of impurities occurs. Therefore, when the insulating film according to the heat treatment is formed on the semi-body substrate and the gate electrode, it is inevitable that the thickness of the contact portion of the first insulating film and the gate electrode and the thickness of the portion in contact with the semiconductor substrate are extremely different, and thus it is possible to provide There is no need for any complicated steps and semiconductor memory devices that are inexpensive to manufacture. Further, the thickness of the contact portion of the first insulating film and the gate electrode and the thickness of the portion in contact with the semiconductor substrate are extremely different, which is sufficient to provide a semiconductor memory device having a significantly high writing/erasing speed. Moreover, the portion of the first insulating film of the semiconductor memory device that is in contact with the semiconductor substrate $ is thicker than the portion that is in contact with the gate electrode, and therefore, the charge from the gate packet can be prevented from passing through the first insulating film to reach the semiconductor; On the contrary, it is possible to improve the semiconductor memory device with good charge injection efficiency and high write/erase speed. Furthermore, in the case where the thickness of the portion where the first insulating film is in contact with the semiconductor substrate of the semiconductor memory element 91971.doc -145 - 1248201 is smaller than the thickness of the first insulating film and the gate electrode of the element = thickness, the The semiconductor substrate has a charge-through rate first, and the e-edge film reaches the gate electrode, and the semiconductor memory device capable of providing a good charge injection effect and an inter-write/erase speed can be provided. BRIEF DESCRIPTION OF THE DRAWINGS The figure shows a semiconductor according to a first embodiment of the present invention. a cross-sectional view of the structural shape of a hidden device;

2(a)-2(4) are cross-sectional views showing a process of a semiconductor memory device in accordance with a second embodiment of the present invention; and FIG. 3(4)') is a view showing the configuration of a memory device according to a third embodiment of the present invention. Cross-sectional view; integrated diagrams 4(a)-4(d) are cross-sectional views showing the structural outline of a half-memory device according to a fourth embodiment of the present invention; =5 is a fifth embodiment according to the present invention. A cross-sectional view of the structural shape of a semiconductor memory device of the example;

® 6(4)6(b) is a (four) plan view showing the structural outline of the memory device according to the sixth embodiment of the present invention; W. Fig. 7(4)7(d) is a view showing the structure of the semiconductor memory device according to the seventh embodiment of the present invention. FIG. 8(a) 8(e) is a cross-sectional view showing a process of a memory device according to an eighth embodiment of the present invention; a cow body image (4) 9(e) is a display according to the present invention. A cross-sectional view of a subsequent process of the memory device of the eighth embodiment; Fig. 1 (a) '1 〇 (1) is a 91971.doc - 146 - 1248201 body according to a ninth embodiment of the present invention. Figure 1 is a cross-sectional view showing the structure of a semiconductor memory device in accordance with a tenth embodiment of the present invention; Figure 1 is a cross-sectional view showing the structure of a semiconductor memory device in accordance with a tenth embodiment of the present invention; 12(a)-12(d) is a cross-sectional view showing a process of a semiconductor memory device according to a tenth embodiment of the present invention; =13 is a semiconductor memory device according to a tenth embodiment of the present invention. Cross-sectional view of the structure; Figure H(a)_14(e) shows the twelfth according to this (four) Cross-sectional view of the process of the conductor memory device of the embodiment: 15(a).15(4) is a cross-sectional view showing the process of the conductor memory device according to the thirteenth embodiment of the present invention; ^ 16(a)_16 (d) is a cross-sectional view showing a process of the fourteenth conductor memory device according to the present invention; (4) · (8) is a cross section showing the structural shape of the semiconductor § memory device according to the fifteenth embodiment of the present invention Figure 18(a)-18(b) is a display of the conductor memory device according to the fifteenth embodiment of the present invention. Figure 19 (a) - 19 (b) is another cross-sectional view of the structural shape of a half-inch device according to a fifteenth embodiment of the present invention; Figure 20 ( a) -20(b) is a cross-sectional view showing the structural shape of the memory device of the fifteenth embodiment of the fifteenth embodiment of the present invention; FIG. 21(a)- 21(b) is a structural outline of the root conductor memory device::: FIG. 12A is a half of the embodiment. FIG. 22(a)_22(b) is a dry phase, and X is according to the seventeenth aspect of the present invention. A half of the embodiment 91971.doc -147 - 1248201 is a cross-sectional view of a gentleman's shape of a conductor memory device; Figure 23 (a) - 23 (b) is a clever ^ not according to the present invention The semiconductor memory device of the eighteenth embodiment is according to a cross-sectional view of the configuration; FIG. 24(a)-24(b) A sea-, 4, ,, and the member are not according to the nineteenth embodiment of the present invention. A cross-sectional view of a semiconductor memory device of an embodiment is shown in FIG. 25(a)_25(b) A, , ), and a semiconductor memory according to a twentieth embodiment of the present invention. Figure 26 (a) 26 (b) is a cross-sectional view showing the structural shape of a semiconductor memory device according to a twenty-first embodiment of the present invention; Figure 27 (a) - 27(d) is a cross-sectional view showing the process of the half V body device according to the eighteenth embodiment of the present invention; and Figs. 28(a)-28(b) are diagrams showing the separation according to the second embodiment of the present invention. FIG. 29(a)-29(b) are diagrams showing an MPU, a cache SRAM, and a diagram thereof; the memory device, the peripheral circuit, and the class of the present invention; The structure of the semiconductor memory device of the object

30(4)-30(b) are block diagrams showing the twenty-second embodiment of the present invention; and FIG. 31 is a block diagram showing the portable electronic device of the twenty-second and one embodiment of the present invention. Figure 32 is a cross-sectional view showing the structural outline of a conventional semiconductor memory device. [Description of main component symbols] !,111,186, 901 Semiconductor substrate 91971.doc 148- 1248201 la, 3a Flat portion lb? 3b Slanted portion 1 c Bottom portion 2, 114 Gate insulating film 3, 117, 117a Gate electrode 4 Peripheral circuit area 5 Memory area 6 LDD area 7 Photoresist 8 Gate stack 9 First dielectric film 10 11 points 11, 30, 161, 162, 162a Memory function unit 13, 18, 112, 113 Source diffusion Zone and drain diffusion region 15 Dielectric film 17 Tantalum nitride 18 Beak-shaped dielectric film 19 Channel region 20, 171 Offset region 21 Removal region 22 Opposite region 31 Charge retention portion 32 Anti-consumption insulator 91971.doc -149 - 1248201 32a First insulator 32b Second insulator 33 Charge storage region 34 Initial insulating film 40 Rugged 41 Deposited insulator 42 Third insulator 43 Thermal insulator 50 Recess 141, 143 Oxidation film 142, 142a Tantalum nitride film 187 Body Area 188 Hiding oxide film 191 P-type high concentration region 192 P-type region 200 Memory unit 201 Memory cell array 202 Peripheral circuit 2 03, 207 decoder 204 I/O circuit 205 control circuit 206 analog circuit 208 read circuit 91971.doc -150-1248201 209 write/erase circuit 300 memory device 301 MPU (micro processing unit) 302 cache SRAM ( Static RAM) 303 logic circuit 400A, 400B 1C card 401, 501 MPU (micro processing unit) portion 402, 502 calculation portion 403, 503 control portion 404, 504 data memory portion 405, 505 ROM (read only memory) · 406 506 RAM (Random Access Memory) 407, 507 Line 408 Connector Section 409 External Reader/Writer 410 RF Interface Section 411, 511 Antenna Section 500 Portable Telephone 508 Human Interface Section 510 RF (Radio Frequency) circuit portion 902 source diffusion region 903 > and polar diffusion region 904 first oxide film 91971.doc -151 - 1248201 905 second oxide 906 floating gate 907 control gate 91971.doc -152-

Claims (1)

1248201 X. Patent application garden: 1 · A semiconductor memory device including a memory unit, each memory unit comprising: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate a channel region, which is located under the gate electrode; a pair of source regions and a drain region disposed on opposite sides of the channel region, the conductivity type of the source region and the drain region The opposite of the channel region; and the memory functional unit, which are respectively located on the opposite side of the inter-electrode, each memory function, the unit includes: - a charge retention portion and - an anti-consumption insulator f, the electron retention portion is used to store the charge Made of a material for preventing the stored charge from being consumed by separating the charge retaining portion and the inter-electrode and the substrate; wherein a distance between a sidewall of the gate electrode and a side of the charge-retaining portion opposite to each other The (T2) adjustment is different from the distance (T1) between the bottom of the charge retention portion and the surface of the substrate. 2. 3. 4. 5. 6. If the measurement distance of the half substrate of the read item 1 is further increased, the semiconductor memory device of claim 1 wherein the distance Τ2 is greater than T, such as the semiconductor memory device of the request W, One of the oxygen nitride films is formed between the charge retention portion and the gate electrode. A semiconductor memory device as claimed in claim 1, wherein a deposition insulating film is formed between the charge holding portion and the gate electrode. A semiconductor memory device according to claim 5, wherein a thermal insulation system having a thickness between 1 nm and 91971.doc 1248201 nm (including 1 and 1 Å) is disposed between the deposition insulator and the semiconductor substrate. 7. The semiconductor memory device of claim 1, wherein the gate electrode is formed of a different material composition than the substrate, and the distance is different from that of the crucible. The semiconductor memory device of claim 1, wherein the charge retention portion of the memory functional unit is separated from the gate electrode and the substrate by the anti-consumption insulator, the substrate and the gate electrode being made of Shi Xi And the difference in impurity concentration between the substrate facing the memory functional unit and the region of the gate electrode facing the memory functional unit, and the distance Τ2 is different from Τ1. As in the + conductor memory device of claim 8, the impurity concentration of the closed electrode in # is 1 X 1G2. Or more and the impurity concentration of the substrate is lower than the impurity concentration of the gate electrode. The semiconductor memory device of claim 1, wherein at least a portion of the gate insulating film and at least a portion of the memory functional unit are each formed of an oxide film, and an oxide film equivalent thickness of the gate insulating film Less than the equivalent thickness of the oxide film from one of the surfaces of the surface to the memory function unit opposite to the memory function unit. If the semiconductor memory of the requester is shaken, the charge retention portion respectively located on the opposite side of the gate electrode can be adapted to independently store the charge. The semiconductor memory device of the request, wherein at least a portion of the gate insulating film and at least a portion of the memory functional unit are each formed of a layer of oxygen 91971.doc 1248201, and an oxide film of the gate insulating film The equivalent thickness is greater than k «the thickness of the oxide film of the path of the substrate opposite to the functional unit of the memory element through the memory function unit and the surface of the substrate under the memory function unit . The semiconductor memory device of claim 12, wherein at least a portion of the source region and a portion of the drain region are disposed under the gate electrode. The semiconductor memory device of claim 1, wherein the tamper-resistant insulating system in the memory functional unit is made of a ruthenium oxide film or a ruthenium nitride film and the charge retention portion in the memory functional unit It is made of a tantalum nitride film. The semiconductor memory device of claim 1, wherein at least a portion of the charge retention portion of the memory functional unit is disposed over the source region or the non-polar region. The semiconductor memory device of claim 15, wherein the charge retaining portion of the memory function unit has a surface of ff that is parallel to a surface of the gate or the insulating film. The semiconductor memory device of claim 16, wherein the charge retention portion of the memory function unit comprises a portion extending substantially parallel to a side of the gate electrode. The semiconductor memory device of claim 16, wherein the semiconductor memory 1 includes an insulating film that separates the charge retention portion from the memory function and the substrate, and the insulating film is thinner than the gate insulating film The thickness is 〇·8 nm or more. The semiconductor memory device of claim 16, wherein the semiconductor memory 91971.doc 1248201 device comprises separating the charge retention portion of the memory functional unit and an insulating film of the substrate, the insulation being thicker than the gate insulating film The thickness is nm or less. 2. A semiconductor device including a semiconductor memory cell and a semiconductor device. The semiconductor memory cell and the semiconductor device include: a gate insulating film formed on a semiconductor substrate; and a gate electrode formed On the gate insulating film; a channel region, which is located under the gate electrode; a pair of source regions and a drain region, which are disposed on opposite sides of the channel region, and the source region and the drain region are electrically conductive The type is opposite to the channel region; and the memory functional units are respectively located on opposite sides of the gate electrode, and each of the memory functional units includes: a charge retention portion and an anti-consumption insulator, the charge retention portion is for storing The charge-resistant material is used to prevent the stored charge from being consumed; wherein a distance between a sidewall of the gate electrode and a side of the charge-retaining portion opposite to each other is adapted to the bottom of the first-charge-retaining portion and the substrate The distance between the surfaces is different, wherein the source region and the drain region in the memory unit are disposed in a region under the gate electrode of the memory unit And a portion of the source line region and drain region of the semiconductor element arranged in the gate electrode of the semiconductor element. 21. A redundant card containing a semiconductor memory device as claimed. 22. A portable electronic device comprising a semiconductor memory device as claimed. 1248201 23 - A method for manufacturing a semiconductor memory device in half, comprising the steps of: forming a gate insulating film on a semiconductor substrate and a gate electrode having a sidewall on the gate insulating film, Forming a first-first insulating film on the electrode and the semiconductor substrate; partially removing the first insulating film such that the first insulating film remains on at least a sidewall of the gate electrode; "by an oxidation process or an oxygenation process Forming a second insulating film on the substrate and the sidewall of the gate electrode, such that a portion of the second insulating film covering the sidewall of the gate electrode is thicker than a portion of the second insulating film covering the substrate; Forming a charge storage region on the sidewall of the gate electrode by using the first, and the rim film, by using the gate electrode, the first one present on the sidewall of the gate electrode Impurities are implanted into the substrate to form a source region and a drain region. 24. A method of fabricating a semiconductor memory device comprising the steps of: forming a gate insulating film on a semiconductor substrate and insulating the gate Different from the substrate; forming an insulating film on the substrate and the sidewall of the gate electrode by using heat treatment, such that a portion of the insulating film covering the substrate is different in thickness from a portion of the insulating film covering the sidewall of the gate electrode; The insulating film is in the snow, and the F is said to be A t__ 91971.doc 1248201 The film, and the charge storage region, as an implant mask, implants impurities into the substrate to form a source region and a non-polar region. A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate insulating film on a semiconductor substrate made of tantalum; forming a gate electrode made of tantalum and having sidewalls, the gate electrode The impurity concentration is greater than a region of the substrate adjacent to the surface of the gate electrode and has an impurity concentration of 5×1019 cm·3 or more; an insulating film is formed on the substrate and the sidewall of the gate electrode by heat treatment, so that a portion of the insulating film covering the substrate has a thickness different from a portion of the insulating film covering the sidewall of the gate electrode; forming a charge holding region on the sidewall of the gate electrode via the insulating film; and presenting the gate electrode by using the gate electrode The insulating film on the sidewall of the gate electrode and the charge storage region serve as an implant mask to implant impurities into the substrate to form a source region and a non-polar region. 26. A method of fabricating a semiconductor memory device, comprising the steps of: forming a gate insulating film on a semiconductor substrate made of Shi Xi, the substrate having an impurity region having an impurity concentration close to the surface of the substrate 5 X 1019 cm—3 or more; forming a gate electrode made of Shi Xi and having sidewalls, the impurity concentration of the gate electrode being less than the impurity concentration and the impurity concentration of the impurity region close to the surface of the substrate is 1×102(} cnT3 or less; forming a _, insulating film on the substrate and the sidewall of the gate electrode using heat treatment, such that a portion of the insulating film covering the substrate has a thickness different from a portion of the insulating film covering the sidewall of the gate electrode; 91971. Doc 1248201: forming a charge storage region on the sidewall of the gate electrode by the insulating film; and - using the gate electrode, the insulating film present on the sidewall of the gate electrode, and the charge storage region as an implant mask Impurity is implanted into the substrate to form a source region and a drain region. 27. A card comprising a semiconductor device as claimed in claim 2, 28. A semiconductor comprising the claim 2 Portable electronic device of the device. 29. A semiconductor memory device comprising a memory unit, each memory unit comprising: a semiconductor substrate; a pair of source regions and a drain region formed on the substrate and a channel is divided; a gate electrode is formed on the channel region; a gate electrode is formed on the gate insulating film; and a memory functional unit is located on the opposite side of the gate electrode In addition, each of the memory functional units includes a charge retention portion and an anti-consumption insulator, wherein the charge retention region is separated from the substrate by a first distance (T1) and is not equal to one of the first distances (Τ1) The second distance (Τ2) is separated from the gate electrode. 30. The semiconductor memory device of claim 29, wherein the second distance (Τ2) increases as the measured distance from the substance increases. 31. The semiconductor memory device of claim 29, wherein the second distance (Τ2) is greater than the first distance (Τ1). The semiconductor memory device of claim 29, wherein the gate electrode is formed of a different material composition from the substrate . The semiconductor memory device of claim 29, wherein the gate electrode has an impurity concentration of 1 x 1 〇 2 〇 em-3 or more, and an impurity concentration of the substrate is lower than the gate impurity concentration. The semiconductor memory device of claim 29, wherein the anti-consumable insulator comprises a oxidized oxide film or a tantalum nitride film, and the charge retention portion comprises a tantalum nitride film. 35. A semiconductor memory device comprising The % effect transistor is formed on a semiconductor substrate via a gate insulating film and formed on a surface of a semiconductor substrate corresponding to one of the two sides of the gate electrode to the source diffusion region and the drain a diffusion region, wherein a recess is formed between the two sides of the gate electrode and the surface of the semiconductor substrate to gradually widen from the side in the cross section; and the two functional units, each memory functional unit Formed by a charge-retaining portion of a material having a function of storing a charge and a resistive insulator having a function of preventing stored charge consumption, formed in a manner of hiding a recess On both sides of the gate electrode. 36. The semiconductor memory device of claim 35, wherein the surface of the semiconductor substrate has a flat portion opposite to a bottom surface of the gate electrode via the gate insulating film, and a side of the flat portion adjacent to a gate length direction An inclined portion forming a partial recess, and a bottom portion each adjacent to an outer side of the inclined portion. 37. The semiconductor memory device of claim 35, wherein the spacer is disposed between the bottom surface of the gate electrode and the source diffusion region and the drain diffusion region of 91971.doc 1248201 with respect to the length of the gate. 3. The semiconductor memory device of claim 36, wherein one side of the gate electrode has a flat portion that is generally perpendicular to a surface of the gate insulating film, and a bottom portion of the flat portion to form a partial recess. An inclined portion; and the anti-consumable insulator includes a first uniform housing having a substantially uniform film thickness, wherein the charge retention portion and the gate electrode and the charge retention portion and the semiconductor substrate are separated from each other And covering the flat portion and the inclined portion of the side surface of the gate electrode and the inclined portion and the bottom portion of the surface of the semiconductor substrate. The semiconductor memory device of claim 35, wherein at least a portion of the charge retention portion overlaps a portion of the source diffusion region and the drain diffusion region. 40. The semiconductor memory device of claim 35, wherein the charge retention portion has a portion that is generally parallel to a surface of the gate insulating film. 41. The semiconductor memory device of claim 35, wherein one side of the gate electrode has a flat portion generally perpendicular to a surface of the gate insulating film, and a side adjacent to a bottom side of the flat portion to form a partial recess a sloped portion; and the charge retention portion includes a portion extending substantially parallel to a flat portion of the side of the gate electrode. 42. The semiconductor memory device of claim 35, wherein the thickness of the anti-consumable insulator isolates the charge retention portion from the semiconductor substrate 91971.doc 1248201, which is thinner than the gate insulating film and greater than 〇. 8 nm. 43. The semiconductor memory device of claim 35, wherein the thickness of the anti-consumer insulator isolates the charge retention portion from the semiconductor substrate from a thickness of the gate insulating film and less than 2〇11111. 4. The semiconductor memory device of claim 37, wherein at least a portion of the source diffusion region and the drain diffusion region are disposed on a sloped portion of the surface of the semiconductor substrate. 45. The semiconductor memory device of claim 37, wherein In the pair of source diffusion regions and the drain diffusion region, the doping concentration is higher than the opposite region of the channel region directly below the gate electrode bottom surface to form a conductive layer having the source diffusion region and the non-polar diffusion region The semiconductor memory device of claim 37, wherein the source diffusion region and the drain diffusion region each have an extension portion on one side thereof (on which the channel region is present), and the extension The joint depth of the portion is shallower than the joint depth of the portion other than the extended portion. 47. The semiconductor memory device of claim 46, wherein the impurity concentration of the extension portion of the portion 4 is lower than the source diffusion region and the drain diffusion region The semiconductor memory device of claim 37, wherein the charge retention portion of the memory functional unit is mounted in the recess. 49. A semiconductor device, comprising: a memory region having a semiconductor memory component and a logic private region having a semiconductor parent switching component, the memory region and the logic circuit region being disposed in a semiconductor On the substrate, wherein 91971.doc -10- Ϊ 248201, the semiconductor memory device and the semiconductor switching device are respectively implemented by "having a gate electrode and a surface of a semiconductor substrate corresponding to the two sides of the gate electrode" a field effect transistor for the source diffusion region and the drain diffusion region, wherein one of the semiconductor memory element and the semiconductor switching element is formed with a recess to gradually widen from the side in the cross section, and the memory The functional units each include: a charge retention portion (made of a material having a function of storing a charge) formed on both sides of the gate electrode in such a manner as to hide the recess, and an anti-consumption insulator (having a function of preventing stored charge consumption) The semiconductor memory device is configured to be capable of applying a voltage to the gate electrode And changing a current amount flowing from one of the source diffusion region and the drain diffusion region to the other of the source diffusion region and the drain diffusion region according to the charge level retained in the charge retention portion, and The semiconductor switching element is constructed to perform an exchange operation regardless of the level of charge remaining in the charge retention portion. 50 51. 52. 53. 54. An IC card equipped with the semiconductor memory device of claim 35. A redundant card equipped with a semiconductor device as claimed in claim 47. A portable electronic device equipped with a germanium conductor memory device as claimed in claim 35. A portable electronic device equipped with a semiconductor device as claimed in claim 47. In the method of manufacturing a semiconductor memory device, the method comprises the steps of forming a semiconductor memory device formed by a one-effect transistor: 91971.doc 1248201 The gate insulating film forms a gate on a surface of a semiconductor substrate Passing through a pole; between the two sides of the gate electrode and the half J. 攸 攸 攸, forming a bird shape that gradually widens from the side in the cross section a dielectric film; "removing the bird-shaped dielectric film to thereby form a recess that is gradually widened in the cross section from the side where the ostrich-shaped dielectric film has been removed; The method comprises forming a memory functional unit on both sides of the gate electrode, and each of the memory functional units comprises: a device having a storage; a charge energy; the electric dragon retaining portion and having one of functions for preventing stored charge consumption Anti-consumable insulator; and using the gate electrode and the memory functional unit as a mask, implanting impurities into the surface of the semiconductor substrate corresponding to both sides of the material to form a pair of source diffusion regions and drain diffusion regions . The method of fabricating a semiconductor memory device of claim 54, wherein the step of forming the memory functional unit comprises the steps of: forming a recess along the gate electrode and an exposed surface of the semiconductor substrate The film thickness of the substantially uniform sentence forms a first dielectric film capable of forming at least a portion of the secondary anti-consumption insulator; forming a nitride nitride in a manner to thereby hide the recess as the charge retention on the exposed surface of the first dielectric film a portion of the material; and etching the tantalum nitride and the first dielectric film on both sides of the gate electrode such that the memory functional unit is respectively left on both sides of the gate electrode, and the semiconductor memory of claim 55 a device manufacturing method, wherein a portion of the tantalum nitride other than the recess 91971.doc -12 - 1248201 is removed in the step of etching the tantalum nitride and the first dielectric film to leave a tantalum nitride having a recess part. A semiconductor device manufacturing method in which a semiconductor memory device each having a field effect transistor is formed in a memory region provided on a semiconductor substrate while being disposed in a logic circuit region provided on the semiconductor substrate Forming a semiconductor switching element each composed of a field effect transistor, the method comprising the steps of: forming a gate electrode on a surface of a semiconductor substrate corresponding to each of the memory region and the logic circuit region via a gate insulating film Forming a bird-shaped dielectric film gradually widened from the side in the cross section between the two sides of the gate electrode and the surface of the semiconductor substrate in the memory region and the logic circuit region, and removing the a bird-shaped dielectric film whereby a recess that is gradually widened in a cross section in a cross section is formed where the ostrich-shaped dielectric film has been removed; s implanting impurities into the logic with a gate electrode as a mask a circuit region, and a mask is provided to prevent impurities from being implanted into the memory region, thereby forming a partial source diffusion region and a drain in the alpha circuit a first doped region of the bulk region; in the memory region and the logic circuit region, a memory functional unit is formed on both sides of the 3 gate electrode according to the manner of hiding the ground, and each β mouth has its body work &; single 疋 ························································································ Conductive type" first introduced the same impurity into each of the memory region and the logic region 91971.doc 1248201 region to thereby form at least a portion of the source diffusion region and the second dopant region of the drain diffusion region 91971.doc 14-