JP2005150765A - Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the scale-down and increased capacity of a memory in a semiconductor storage device, which consists of an element having a function, which converts a change in the charged quantity into a current quantity. <P>SOLUTION: A semiconductor storage device and a portable electronic apparatus having the semiconductor storage device comprises: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulating film. Scale-down and high-integration are implemented by constituting the memory cell of substantially one device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, a manufacturing method and an operation method thereof, and a portable electronic device. More specifically, the present invention relates to a semiconductor memory device including an element having a function of converting a change in charge amount into a current amount, a manufacturing method and an operation method thereof, and a portable electronic device using such a semiconductor memory device.

Conventionally, MRAM (Magnetic Random Access Memory) has been used as a non-volatile memory that reads the stored information by using the resistance value of the variable resistor as stored information, rewriting the stored information by changing the resistance value, and detecting the resistance value. (M. Durlam et al., Nonvolatile Ram Based on Magnetic Tunnel Junction Elements, International Solid-State Circuits Conference Digest of Technical Papers, pp130-131, Feb. 2000: Non-Patent Document 1).
FIG. 36A shows a schematic cross-sectional view of one memory cell constituting such an MRAM, and FIG. 36B shows an equivalent circuit diagram.

The memory cell is configured by connecting a variable resistor 911 and a select transistor 912 via a metal wiring 917 and a contact plug 918. A bit line 914 is connected to one end of the variable resistor 911.
The variable resistor 911 is composed of MTJ (Magnetic Tunnel Junction), and is sandwiched between the rewrite word line 913 and the bit line extending in the direction orthogonal to the bit line 914.

The selection transistor 912 includes a pair of diffusion regions 920 formed on the semiconductor substrate 919 and a gate electrode, and one of the diffusion regions 920 is connected to a variable resistor 911 via a metal wiring 917 and a contact plug 918. The other is connected to the source line 915. Note that the gate electrode constitutes a selected word line 916.
M. Durlam et al., Nonvolatile Ram Based on Magnetic Tunnel Junction Elements, International Solid-State Circuits Conference Digest of Technical Papers, pp130-131, Feb. 2000

The rewrite operation of the MRAM is performed by changing the resistance value of the variable resistor 911 by a combined magnetic field generated by currents flowing through the bit line 914 and the rewrite word line 913. On the other hand, the reading operation is performed by detecting the value of the current flowing through the variable resistor 911, that is, the resistance value of the variable resistor 911 after the selection transistor 912 is turned on.
As described above, the memory cell of the MRAM includes two elements, that is, the variable resistor 911 that is a three-terminal element and the selection transistor 912 that is a three-terminal element. For this reason, there is a limit and difficulty in realizing further miniaturization and capacity increase of the memory.

The present invention relates to a semiconductor memory device in which a selectable memory cell is substantially composed of one element and can sufficiently cope with miniaturization and high integration, a manufacturing method and an operation method thereof, and such a semiconductor memory. It is an object of the present invention to provide a portable electronic device having a device.
That is, according to the present invention, a first conductivity type region formed in a semiconductor layer, a second conductivity type region formed in contact with the first conductivity type region in the semiconductor layer, and the semiconductor A memory function body arranged on the layer across the boundary between the first and second conductivity type regions, and an electrode in contact with the memory function body and provided on the first conductivity type region via an insulating film A semiconductor memory device is provided.

A first conductivity type region formed in the semiconductor layer; two second conductivity type regions formed on both sides of the first conductivity type region in the semiconductor layer; and Two memory function bodies respectively disposed across the boundary between the first and second conductivity type regions, and in contact with each of the memory function bodies and provided on the first conductivity type region via an insulating film A semiconductor memory device having an electrode is provided.
A channel region formed in the semiconductor layer; a variable resistance region provided on both sides of the channel region; two diffusion regions provided on both sides of the channel region through the variable resistance region; A semiconductor memory device comprising: a gate electrode provided on a gate insulating film thereon; and two memory function bodies arranged on both sides of the gate electrode so as to straddle a variable resistance region and a part of a diffusion region Is provided.

In addition, a gate electrode formed on the semiconductor layer through a gate insulating film, a channel region disposed under the gate electrode, a diffusion disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region There is provided a semiconductor memory device comprising a region and a memory function body for holding electric charges formed on both sides of the gate electrode and overlapping the diffusion region.
Furthermore, a semiconductor substrate, a semiconductor layer disposed on a well region or an insulator provided in the semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate or a well region or an insulator provided in the semiconductor substrate A gate insulating film formed on the gate insulating film, a single gate electrode formed on the gate insulating film, a channel region disposed immediately below the gate electrode, and two diffusion regions disposed on both sides of the channel region, And having at least one memory cell made of a sidewall insulating film formed on both sides of the gate electrode so as to overlap the diffusion region, and the sidewall insulating film has a function of holding charges. A semiconductor memory device is provided.

  Still further, a semiconductor substrate, a first conductivity type well region formed in the semiconductor substrate, a gate insulating film formed on the well region, and a plurality of word lines formed on the gate insulating film A plurality of second conductivity type diffusion regions respectively formed on both sides of the word line, and at least a part of the diffusion region or a part of the well region and a part of the diffusion region. A charge holding film having a function of accumulating or trapping charges formed on both sides of the plurality of word lines, directly or via an insulating film with respect to the word line, well region, and diffusion region; and the diffusion A plurality of bit lines connected to the region and extending in a direction crossing the word line, the word line has a recess at the lower end, and at least a part of the charge retention film is directly or via an insulating film Embedded in the recess The semiconductor memory device characterized by filled-comprising is provided.

  Further, a gate insulating film and a gate electrode are formed on the semiconductor substrate, an insulating film having a function of accumulating or trapping charges is deposited on the entire surface of the obtained substrate, and the insulating film is selectively etched to form a gate electrode. A method of manufacturing a semiconductor memory device is provided, which comprises forming a sidewall insulating film on the sidewall of the semiconductor memory device.

  From another point of view, one gate electrode formed on a P-type semiconductor substrate, a P-type well region formed in the semiconductor substrate, or a P-type semiconductor layer disposed on an insulator, and the one For a semiconductor memory device comprising a channel region disposed under a gate electrode, two N-type source / drain regions located on both sides of the channel region, and a memory function body existing in the vicinity of the source / drain region, The semiconductor layer formed on the semiconductor substrate, the well region formed in the semiconductor substrate, or the insulator, with one source / drain region set as a reference voltage and the gate electrode set to a voltage lower than the reference voltage Is set to a voltage higher than a reference voltage, and the other source / drain region is formed on the semiconductor substrate, the well region formed in the semiconductor substrate, or the insulator. By setting a higher voltage than the conductor layer, a method of operating a semiconductor memory device for injecting holes into the memory functional element is provided.

Furthermore, one gate electrode formed on an N-type semiconductor substrate, an N-type well region formed in the semiconductor substrate, or an N-type semiconductor layer disposed on an insulator, and a channel below the one gate electrode One source / drain region is used as a reference for a semiconductor memory device comprising a region, two P-type source / drain regions located on both sides of the channel region, and a memory function body in the vicinity of the source / drain region. The gate electrode is set to a voltage higher than a reference voltage, and the semiconductor substrate and the semiconductor layer disposed on the well region or insulator formed in the semiconductor substrate are set to a voltage lower than the reference voltage. And the other source / drain region is set to a voltage lower than that of the semiconductor layer disposed on the semiconductor substrate, the well region formed in the semiconductor substrate, or the insulator. By operating method of the semiconductor memory device for injecting electrons into the memory functional element is provided.
In addition, a portable electronic device including the semiconductor memory device is provided.

According to the present invention, the memory cell of the conventional MRAM is composed of two elements, whereas the memory cell can be substantially composed of one element, and further miniaturization and high integration can be achieved. Can be realized.
Further, the configuration of one element is simple, that is, the first conductivity type region formed in the semiconductor layer, the second conductivity type region adjacent thereto, and the first and second regions on the surface of the semiconductor layer. Since it can be configured by a memory function body arranged across the boundary of the two conductivity type region and an electrode in contact with the memory function body and provided on the first conductivity type region via an insulating film Thus, the occupied area can be further reduced, and the reading speed of the semiconductor memory device can be improved.

Furthermore, the first conductivity type region formed in the semiconductor layer, two adjacent second conductivity type regions, and the boundary between the first and second conductivity type regions on the semiconductor layer surface are straddled. Since it has two memory function bodies arranged respectively and electrodes provided in contact with each of the memory function bodies and on the first conductivity type region via an insulating film, the reading speed of the semiconductor memory device is improved. And the degree of integration can be further improved.
In addition, when storing information of 2 bits or more by accumulating charges independently in each of the two memory function bodies, the element area per bit can be reduced. Cost can be reduced.

From another point of view, a channel region, variable resistance regions provided on both sides of the channel region, diffusion regions provided on both sides of the channel region via the variable resistance region, and a gate insulating film on the channel region Read operation of the semiconductor memory device by comprising a gate electrode provided through the two and two memory function bodies arranged on both sides of the gate electrode so as to straddle part of the variable resistance region and the diffusion region Speed can be improved.
In addition, when reading information stored in one of the two memory functional units, if the pinch-off point is formed in the channel region and in a region close to the other memory functional unit, the other memory functional unit Regardless of the storage state, the storage information of one memory function body can be detected with high sensitivity. This is a major factor enabling 2-bit operation.

  Further, since the memory function body is arranged not on the gate electrode but on both sides of the gate electrode, it is not necessary to make the gate insulating film function as the memory function body, and the gate insulating film is separated from the memory function body. Therefore, it can be used only for the function as the gate insulating film, and the design according to the scaling rule of the LSI can be performed. For this reason, it is not necessary to insert a floating gate between the channel and the control gate as in a flash memory, and it is not necessary to use an ONO film having a memory function as a gate insulating film. An insulating film can be employed, and the influence of the electric field of the gate electrode on the channel is increased, so that a semiconductor memory device having a memory function strong against the short channel effect can be realized. Therefore, miniaturization can improve the integration degree and an inexpensive semiconductor memory device can be provided.

Further, only one word line which is necessary for one memory cell and is connected to the gate electrode or having the function of the gate electrode itself can be used as a conventional selection transistor and a memory cell transistor. Therefore, the semiconductor memory device can be further highly integrated.
Furthermore, if the amount of charge in the memory function body is detected by a change in the amount of current flowing from one of the source / drain regions to the other of the source / drain regions, a slight difference in charge in the memory function body can be regarded as a large current difference. Can be determined.

In addition, the resistance value of the variable resistance portion located under the memory function body changes depending on the amount of charge in the charge memory function body, and the presence / absence of charge in the memory function body is changed from one of the source / drain regions to the source / drain region. If detection is performed based on a change in the amount of current flowing to the other side of the region, a slight difference in charge in the memory function body can be determined as a large current difference.
Furthermore, a structure in which a single gate electrode per memory cell is sandwiched between two memory function bodies formed on both sides of the memory cell minimizes the number of electrodes to change the charge amount of the memory function body. To do. Therefore, the area occupied by the memory cell can be reduced.

  Each memory cell has a structure in which a single gate electrode is sandwiched between two memory function bodies formed on both sides thereof, and the amount of charge in the memory function body is reduced in the source / drain regions. The number of electrodes necessary for a detection method for detecting by a change in the amount of current flowing from one side to the other of the source / drain regions, that is, a detection method capable of determining a slight difference in charge as a large current difference is minimized. Therefore, the area occupied by the memory cell can be reduced.

  Further, a single gate electrode per memory cell is sandwiched between two memory function bodies formed on both sides thereof, and the resistance value of the variable resistance portion located under the memory function body is determined as the memory function body. Detection method that detects the amount of charge in the memory function body by changing the amount of current flowing from one of the source / drain regions to the other of the source / drain regions, that is, a slight difference in charge Can be determined as a large current difference, and the number of electrodes necessary for the detection method is minimized. Therefore, the area occupied by the memory cell can be reduced.

  One terminal connected to the semiconductor layer located on the semiconductor substrate or the well region or the insulator film, two terminals connected to the source / drain region, and one terminal connected to the gate electrode A minimum terminal required for a memory cell that can select one memory cell from a plurality of memory cells and write / erase / read it is configured. Therefore, one memory cell can be configured with the smallest number of terminals.

Furthermore, a total of four voltages are applied, that is, a voltage applied to the semiconductor layer located on the semiconductor substrate or well region or insulator, a voltage applied to a single gate electrode, and a voltage applied to each of the two source / drain electrodes. Thus, the operation method for performing any one of the read, write, and erase operations for one memory cell can perform one memory cell operation with the fewest nodes.
In addition, since the gate electrode side wall insulating films formed on both sides of the single gate electrode function as a memory function body, it is easy to mix the circuit constituted by the logic transistor and the memory storage device.

Furthermore, since at least a part of the gate electrode side wall insulating film having a function of holding electric charge overlaps with the source / drain regions, a decrease in read current is suppressed. Therefore, the read operation speed of the semiconductor memory device can be increased.
Further, it is possible to store 2-bit information by one semiconductor memory device, and the memory function bodies arranged on both sides of one gate electrode are completely separated from each other by the gate electrode. It is possible to avoid electrical interference between functional bodies, and a semiconductor memory device that stores multi-value information while realizing further miniaturization can be realized.

In addition, since the semiconductor memory device of the present invention can be used as a transistor constituting a logic circuit as it is, the mixed process of the logic circuit and the memory circuit can be greatly simplified.
A part of the source / drain region is extended to a position higher than the surface of the channel region or the lower surface of the gate insulating film, and at least a part of the memory function body is sandwiched between the gate electrode and a part of the source / drain region. In this case, it is possible to realize shallow junction of the source / drain regions and realize a steep impurity concentration profile at the junction. Therefore, the short channel effect can be suppressed extremely effectively, the device can be further miniaturized, the drain breakdown voltage can be reduced, and the write / erase voltage by electron injection or hole injection can be reduced.

In addition, by sandwiching the memory function body between the gate electrode and the source / drain region, an electric field is directly applied between the gate electrode and the source / drain region, and electrons or holes are injected between the two selected nodes. Can be extracted, and the write / erase efficiency can be improved as compared with hot electron or hot hole injection.
In the case where the source / drain region is disposed offset with respect to the gate electrode end, the parasitic resistance in the offset region under the memory function body when a voltage is applied to the gate electrode is stored in the memory function body. It can be changed greatly depending on the amount, and the memory effect can be increased.

  In the present invention, when the source / drain region is made of an N-type semiconductor, one source / drain region is set to a reference voltage, and the other source / drain region and the gate electrode are set to a voltage higher than the reference voltage. Or one source / drain region is set to a reference voltage, the other source / drain region is set to a voltage higher than the reference voltage, and the gate electrode is set to a voltage lower than the reference voltage, that is, the relative potential of the three electrodes. Therefore, the number of electrodes per memory cell in the semiconductor memory device can be reduced and the cell area can be further reduced because electrons or holes can be selectively injected into the memory function body. .

  Similarly, when the source / drain region is made of a P-type semiconductor, one source / drain region is set to a reference voltage, and the other source / drain region and the gate electrode are set to a voltage lower than the reference voltage. Alternatively, one of the source / drain regions is set to a reference voltage, the other source / drain region is set to a voltage lower than the reference voltage, and the gate electrode is set to a voltage higher than the reference voltage. Since holes or electrons can be injected, the cell area can be further reduced.

When the charge holding film is formed on the well region or the diffusion region directly or via the insulating film at both ends of the gate electrode, the inversion layer is controlled according to the amount of charge in the charge holding film. be able to. Therefore, a large hysteresis (change in threshold value) can be obtained, and a semiconductor memory device with favorable characteristics can be obtained.
When the semiconductor substrate is an SOI substrate having a surface semiconductor layer and the first conductivity type well region is formed as a body region in the surface semiconductor layer, the junction capacitance between the diffusion region and the body region is significantly reduced. Thus, the device can be increased in speed and power consumption can be reduced.

When the charge holding film is in contact with the diffusion region and / or the well region or the body region through the insulating film in the vicinity of the edge of the gate electrode, leakage of the held charge can be suppressed, and the charge holding characteristic can be improved. Can be improved.
When the gate electrode has a recess at the lower end and at least a part of the charge retention film is embedded in the recess directly or via an insulating film, at least a part of the charge retention film is Since it is covered with the gate electrode, the efficiency of hot carrier injection can be improved particularly during erasing, and thus a high-speed erasing operation can be realized.

When the gate electrode has a side wall insulating film on the side wall and a part of the side wall insulating film is formed as a charge holding film, ion implantation for forming a diffusion region is performed using the side wall insulating film as a mask. This makes it easy to control the position of the end of the diffusion region. Therefore, a region where the well region or the body region is in contact with the charge holding film directly or via the insulating film can be formed so that the diffusion region does not reach below the gate electrode. Therefore, a semiconductor memory device having good characteristics can be obtained.
Further, according to the method for manufacturing a semiconductor memory device of the present invention, it is possible to manufacture a semiconductor memory device capable of high performance and high integration by a simple process.

  Furthermore, when the well region or the body region of the semiconductor device of the present invention has a P-type conductivity type, one diffusion region is set as a reference voltage, the gate electrode is set to a voltage lower than the reference voltage, and the well region or The body region is set to a voltage higher than the reference voltage, and the other diffusion region is set to a voltage higher than the voltage of the well region or the body region, so that the reference voltage is fixed from the P-type well region or the body region. A forward current flows through the diffusion region. For this reason, even when only a voltage difference sufficient to generate hot holes due to interband tunneling is not applied at the junction between the P-type well region or body region and the other diffusion region, the diffusion region is fixed to the reference voltage. Electrons injected from the well into the well region or the body region can generate hot holes. Therefore, the effect of injecting holes into the memory function body adjacent to the other diffusion region is increased, and the voltage during operation at the time of hole injection can be lowered.

  Further, when the well region or body region of the semiconductor device of the present invention has an N-type conductivity type, a forward current flows from the N-type well region or body region to the diffusion region fixed to the reference voltage. . Therefore, even when only a voltage difference sufficient to generate hot electrons due to interband tunneling at the junction between the well region or the body region and the other diffusion region is applied, the diffusion region is fixed from the diffusion region fixed to the reference voltage. Alternatively, holes injected into the body region can generate hot electrons. Therefore, the effect of injecting electrons into the memory function body adjacent to the other diffusion region is increased, and the voltage during operation during electron injection can be reduced.

  The memory function body described above is formed of a film having a function of accumulating or trapping charges or maintaining a charge polarization state. For example, an insulating film including a silicon nitride film, an insulating film including a conductive film or a semiconductor layer therein. It is formed of a single layer or a laminated structure such as an insulator film including one or more body films, conductors, or semiconductor dots. In the case of an insulator film including a silicon nitride film, the silicon nitride film has a large hysteresis characteristic because there are many levels for trapping charges, has a long charge retention time, and charge leakage due to the occurrence of a leakage path. Therefore, the retention characteristic is good, and since it is a material that is used very standardly in the LSI process, there is an effect that it can be easily introduced into a mass production factory. In addition, in the case of an insulator film including a conductive film or a semiconductor layer, the amount of charge injected into the conductor or the semiconductor can be freely controlled, so that there is an effect of being easily multi-valued. In addition, in the case of an insulator film including one or more conductors or semiconductor dots, writing / erasing by direct tunneling of electric charge is facilitated, and there is an effect of reducing power consumption. Further, as one form of the charge retention film, a ferroelectric film such as PZT or PLZT whose polarization direction is changed by an electric field may be used. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to polarization, and the charges are held in this state. Therefore, it is possible to obtain the same hysteresis characteristic as a film that supplies charges from outside the film having a memory function and traps charges, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since hysteresis characteristics can be obtained only by polarization of charges in the film, there is an effect that writing / erasing can be performed at high speed.

In addition, since the memory functional unit includes a film having a function of holding charge, and at least a part of the film having the function of holding charge overlaps with the source / drain region, a decrease in read current is suppressed. The Therefore, the read operation speed of the semiconductor memory device can be increased.
Furthermore, when the gate insulating film, the gate electrode, and the memory function body are formed on the semiconductor layer made of the SOI layer, the junction capacitance between the diffusion region and the body region can be remarkably reduced, and the high-speed operation of the device can be achieved. And lower power consumption.
In addition, when a semiconductor layer including a well region is used, other electrical characteristics (breakdown voltage, junction capacitance, short channel) while optimizing the impurity concentration immediately below the gate insulating film for the memory operation (rewrite operation and read operation) Effect) can be easily controlled.

  Furthermore, if the memory function body includes a charge holding film having a function of holding charges and an insulating film, it is possible to prevent charge dissipation and improve holding characteristics. In addition, the volume of the charge holding film can be reduced appropriately compared to the case where the memory function body is composed of only the charge holding film. By appropriately reducing the volume of the charge retention film, the movement of charges in the charge retention film can be limited, and the change in characteristics due to the charge movement during memory retention can be suppressed. Therefore, the retention characteristic of the memory can be improved. In the memory function body, there is a charge holding film that is almost parallel to the surface formed by the gate insulating film, which effectively controls the ease with which the inversion layer is formed in the offset region due to the amount of charge accumulated in the charge holding film. can do. Therefore, the memory effect can be increased. In addition, since the charge retention film is disposed substantially parallel to the surface of the gate insulating film, the change in the memory effect can be kept relatively small even when the offset amount varies. Therefore, variation in memory effect can be suppressed. Furthermore, since the charge holding film is in the form of a film disposed substantially parallel to the surface of the gate insulating film, the upward movement of charges is suppressed. Therefore, it is possible to suppress changes in characteristics due to charge transfer during storage. Therefore, it is possible to obtain a semiconductor memory device having a large memory effect and a small variation and good holding characteristics.

Further, when the memory function body further includes a charge holding film extending substantially in parallel with the side surface of the gate electrode, the rewriting speed can be increased while preventing deterioration of the holding characteristics of the semiconductor memory device.
Furthermore, in the case of further including an insulating film separating the gate electrode and the charge holding film extending substantially in parallel with the side surface of the gate electrode, the charge between the charge holding film extending substantially in parallel with the side surface of the gate electrode and the gate electrode can be reduced. Going in and out can be suppressed. Therefore, the reliability of the semiconductor memory device can be increased.
Further, in the case of further including an insulating film separating the charge holding film extending substantially parallel to the surface of the gate insulating film and the channel region or the semiconductor layer, the charge stored in the charge holding film substantially parallel to the surface of the gate insulating film is dissipated. Therefore, a semiconductor memory device with better holding characteristics can be obtained.

When the film thickness of the insulating film separating the charge holding film and the channel region or the semiconductor layer is smaller than the film thickness of the gate insulating film, the voltage of the write operation and the erase operation is decreased without decreasing the withstand voltage performance of the memory, Alternatively, the writing operation and the erasing operation can be performed at high speed, and the memory effect can be increased.
In addition, when the thickness of the insulating film that separates the charge holding film from the channel region or the semiconductor layer is larger than the thickness of the gate insulating film, the holding characteristics can be improved without deteriorating the short channel effect of the memory. It becomes.

  Further, the first conductivity type semiconductor layer has an impurity concentration that gives the first conductivity under the memory function body and in the vicinity of the source / drain region than in the vicinity of the surface of the first conductivity type semiconductor layer under the gate electrode. Since it has a dark region, the junction between the diffusion region and the semiconductor layer becomes steep immediately below the memory function body. Therefore, hot carriers are likely to be generated during writing and erasing operations, and the voltage for the writing and erasing operations can be reduced, or the writing and erasing operations can be performed at high speed. Further, since the impurity concentration immediately below the gate insulating film is relatively thin, the threshold when the memory is in the erased state is low, and the drain current is large. Therefore, the reading speed is improved. Therefore, it is possible to obtain a semiconductor memory device having a low rewrite voltage, a high rewrite speed, and a high read speed.

When the gate electrode length at the cut surface in the channel length direction is A, the channel length between the source / drain regions is B, and the distance from the end of one memory function body to the end of the other memory function body is C, Since the relationship A <B <C is established, the memory effect is increased, the read operation is speeded up, and the short channel effect is reduced.
Further, when the source / drain regions disposed on the opposite side of the gate electrode of the memory function body are N-type (P-type), when the memory state is changed by injecting electrons (holes) into the memory function body; The magnitude relationship between the voltages applied to one and the other of the source / drain regions is reversed when the storage state of the memory function body is read. Therefore, it is possible to detect the storage status of a desired memory function body with high sensitivity. Furthermore, the resistance to read disturb is improved.
In addition, since the portable electronic device includes the semiconductor memory device of the present invention, the function and the operation speed can be improved, and an inexpensive portable electronic device can be obtained as the manufacturing cost is reduced.

  Hereinafter, a semiconductor memory device, a manufacturing method thereof, and a portable electronic device of the present invention will be described in detail with reference to the drawings. In the following description, the conductivity types may be reversed, and the constituent requirements described in each embodiment may be applied in other embodiments.

Embodiment 1
The semiconductor memory device of the present embodiment has a variable resistor and is substantially constituted by one three-terminal element.
FIG. 1A is a schematic cross-sectional view of a memory cell of a memory device formed on a glass panel of a liquid crystal TFT display element as an example of the semiconductor memory device of the present invention. This storage device is used for image adjustment. FIG. 1B is an equivalent circuit diagram of the memory cell.
As shown in FIG. 1A, this memory cell is formed by contacting a P-type diffusion region 603 formed in a semiconductor layer 602 on a glass panel 601 and a P-type diffusion region 603 in the semiconductor layer 602. The N-type diffusion region 604 formed on the semiconductor layer 602 and the memory function body 605 disposed across the boundary between the P-type diffusion region 603 and the N-type diffusion region 604, and in contact with the memory function body 605, P A single electrode 607 is formed on the mold diffusion region 603 via an insulating film 606 and insulated from the P-type diffusion region 603. Further, a refractory metal silicide film 608 is formed on the surface of the P-type diffusion region 603, and a wiring 609a is connected to the refractory metal silicide film 608. A refractory metal silicide film 608 is also formed on the surface of the N-type diffusion region 604, and a wiring 609b is connected to the refractory metal silicide film 608. The wirings 609a and 609b are connected to the refractory metal silicide 608 via contact plugs 612 that fill contact holes opened in the interlayer insulating film 610, respectively.

  Further, as shown in FIG. 1B, a portion near the surface of the P-type diffusion region 603 and below the electrode 607 has a switching function, and is near the surface of the P-type diffusion region 603 and is a memory. The lower part of the function body 605 is a variable resistor A. The electrode 607 has a function as an input terminal for switching a switch. The switch and variable resistor A are formed adjacent to the electrode 607 and the memory function body 605 formed adjacent to the electrode 607 (formed on the side wall of the electrode 607). That is, the switch and the variable resistor A are formed adjacent to each other at a position defined by the boundary between the electrode 607 and the memory function body 605 and are substantially integrated. Therefore, the switch, the variable resistor, and the electrode 607 are configured by one element 631.

Note that when a memory cell array is formed by arranging a plurality of memory cells, the electrode 607 may be connected to the word line 622 and one end of the element 631 may be connected to the bit line 623.
This memory cell can be read and rewritten by applying predetermined voltages to the P-type diffusion region 603, the N-type diffusion region 604, and the electrode 607 functioning as a selected word line.

  For example, the voltage of the P-type diffusion region 603 is set as a reference potential, and a voltage in the positive direction is applied to the N-type diffusion region 604 with respect to the reference potential. At this time, if the electrode 607 is set in a non-selected state (for example, a reference voltage applied state), the portion under the electrode 607 remains P-type. Therefore, the PN junction between the P-type diffusion region 603 and the N-type diffusion region 604 is in a reverse bias state, and only a PN reverse current flows between the wirings 609a and 609b, and the current value can be almost ignored. On the other hand, when the electrode 607 is in a selected state (for example, a voltage is applied in the positive direction with respect to the reference voltage), the electrode 607 is inverted to an N type, so that a current according to the resistance value of the variable resistor A is generated. Flowing. Therefore, memory information can be read by detecting this current.

  The resistance value of the variable resistor A can be changed according to the amount of charge stored in the memory function body 605, that is, rewriting can be performed. In order to store charges in the memory function body 605, the P-type diffusion region 603 is used as a reference voltage, and the N-type diffusion region 604 has a very large reverse bias voltage compared to that at the time of reading (eg, three times the potential difference at the time of reading By applying the above, an interband tunnel current is used. That is, when the electrode 607 is applied positively with respect to the reference voltage, electrons are stored in the memory function body 605 when they are applied negatively. Further, by using the P-type diffusion region 603 as a reference voltage, a relatively large reverse bias (for example, about 2 to 3 times that at the time of reading) is applied to the N-type diffusion region 604 and simultaneously a positive voltage is applied to the electrode 607. Charges may be stored in the memory function body 605 by channel hot electrons, or charges may be stored in the memory function body 605 by both of them.

When the N-type diffusion region 604 and the P-type diffusion region 603 are of the reverse conductivity type, the rewriting operation can be performed in the same manner by reversing the sign of the applied voltage.
Thus, the memory cell of this embodiment is substantially composed of one element, and one element has only three terminals. Therefore, miniaturization and high integration of the semiconductor memory device can be realized.

  The memory function body 605 includes at least a region for holding charges or a film having a function of storing and holding charges. Furthermore, the memory function body 605 preferably includes a region that makes it difficult to escape charges or a film that has a function that makes it difficult to escape charges. For example, in the memory function body 605, the surface that contacts the P-type diffusion region 603, the N-type diffusion region 604, and the electrode 607 is configured with a region that makes it difficult for the charge to escape, and the region that holds the charge is the direct P-type diffusion region. By preventing contact with 603, the N-type diffusion region 604, and the electrode 607, the reliability of the memory retention time can be dramatically improved. However, in order to improve the reading speed, it is very important that the area for holding charges in the memory function body 605 is arranged across the boundary between the P-type diffusion area 603 and the N-type diffusion area 604. is there.

  The electrode 607 is preferably formed only on the side wall of the memory function body 605 or does not cover the upper portion of the memory function body 605. With such an arrangement, even when the contact plug 612 and the electrode 607 or the contact plug 612 and the memory function body 605 are arranged so as to be close to each other or overlap with each other to achieve miniaturization, the electrode 607 and the wiring 609b are formed. A short circuit can be prevented.

The refractory metal silicide film 608 can be formed by silicide of a refractory metal such as titanium, tantalum, molybdenum, and tungsten, and the P-type diffusion region 603 and the N-type diffusion region 604 and the refractory metal silicide film 608 are ohmic. Either connection or Schottky connection may be used.
As shown in FIG. 2, the wiring 609a and the P-type diffusion region 603 are connected by forming the N-type diffusion region 611 in the P-type diffusion region 603 without forming the refractory metal silicide film 608. Then, this may be done through this N-type diffusion region.

Embodiment 2
In the semiconductor memory device of the present invention, the memory function film 805 may be formed on both sides of the electrode 807 as shown in FIG. In other words, the configuration may be substantially the same as that of the memory cell of the first embodiment except that the memory cell electrode 607 shown in the first embodiment is symmetric with respect to the center.
With such a configuration, the degree of integration can be further improved as compared with the first embodiment.

  In other words, the storage information of the two memory function bodies 805 (resistance information of the variable resistor A according to the amount of charge accumulated in the memory function body 805) flows between the two N-type diffusion regions 804 by the electrode 807. As the amount of current, each can be read out independently. For example, an inversion layer is formed in the P-type diffusion region 803 by applying one of the two N-type diffusion regions 804 as a reference voltage and applying a positive voltage to the electrode 807. At this time, a positive voltage sufficient to cause a part of the inversion layer to disappear (become a depletion layer) is applied to the other N-type diffusion region 804. Thereby, the variable resistor A on the side where the inversion layer disappears substantially loses the variable resistor function due to depletion. Therefore, only the information of the variable resistor A on the one N-type diffusion region 804 side can be read as the amount of current flowing between the two N-type diffusion regions 804.

By such a method, two bits (four values) of information can be stored in one memory cell by accumulating charges independently in each of the two memory function bodies 805 and reading them independently. .
Furthermore, it is possible to increase the storage amount by multi-value (three or more values) of the charge amount accumulated in each memory function body. For example, if 3 values are stored in each memory function body 805, 9 values can be stored per memory cell, and if 4 values are stored in one memory function body, 16 values (4 bits) are stored. If 8 values are stored in one memory function body, 64 values (6 bits) can be stored.

Embodiment 3
As shown in FIG. 4, the memory cell of this embodiment forms a field programmable gate array (FPGA) by combining a logic LSI and a non-volatile memory on an SOI substrate 900 and includes a variable resistor. Region 902 is formed separately.
That is, this memory cell includes a channel region 901 formed of an N-type silicon layer, a variable resistance region 902 formed on both sides of the channel region 901, and on both sides of the channel region 901 via the variable resistance region 902. An N-type diffusion region 903 provided, a gate electrode 905 provided on the channel region 901 with a gate insulating film 904 interposed therebetween, and on both sides of the gate electrode 905, the variable resistance region 902 and the diffusion region 903. It is composed of two memory function bodies 906 arranged so as to straddle a part.

The variable resistance region 902 is a silicon layer into which P-type impurities are predominantly introduced, that is, a P-type impurity concentration is introduced higher than the N-type impurity concentration, and is sandwiched between the channel region 901 and the diffusion region 903. Therefore, it is depleted. This depletion may be complete depletion or partial depletion.
The memory function body 906 is formed of an ONO film (silicon oxide film 9061, silicon nitride film 9062, silicon oxide film 9063), and an L-shaped silicon nitride film is used as a film having a function of storing and holding charges. It was.
Note that the channel region 901 and the diffusion region 903 need not have the same conductivity type. What is important is that a larger amount of impurities having a conductivity type opposite to that of the diffusion region is introduced into the variable resistance region 902 than impurities having the same conductivity type.

  In this memory cell, the resistance of the variable resistance region 902 can be changed by the electric charge stored in the memory function body 906. Specifically, the charge stored in the memory function body 906 causes the P-type property to become stronger or the N-type property to become stronger in the variable resistance region 902. By applying a positive voltage to the gate electrode 905, a barrier between the variable resistance region 902 and the diffusion 903 is lowered by a sneak electric field generated from the side wall of the gate electrode 905, and a current flows between the diffusion region 903 and the channel region 901. Flowing. The current varies with the resistance value of the variable resistance region 902, so that a memory effect occurs.

For example, a positive voltage is applied to the gate electrode 905 with the voltage of one diffusion region 903 as a reference potential. At this time, the voltage applied to the other diffusion region 903 is applied in the positive direction with respect to the reference potential. The voltage applied to the other diffusion region 903 is such that, on the other diffusion region 903 side, the electric field from the other diffusion region 903 is more dominant than the sneak electric field from the side wall of the gate electrode 905, so that the variable resistance region 902 Increase voltage until depleted. Under such a voltage application condition, in the variable resistance region 902 on the other diffusion region 903 side to which a positive voltage is applied, the influence of the diffusion region electric field changes to a dominant depletion layer, and the variable resistance function disappears. To do. Therefore, only the information of the variable resistance region 902 on one diffusion region 903 side (reference voltage application) is read as storage information, that is, the storage information of the variable resistance region 902 is independently read as the amount of current flowing between the two regions 903. be able to. Here, when the variable resistance region 902 is predominantly N-type, that is, when the diffusion region is P-type, the reading operation can be similarly performed by reversing the sign of the applied voltage.
In this embodiment, a region where a current under the gate electrode flows is defined as a channel region.

Embodiment 4
The memory cell constituting the semiconductor memory device of this embodiment is a non-volatile memory cell capable of storing 2 bits. As shown in FIG. 5C, the gate insulating film 2 is formed on the semiconductor substrate 1. Thus, a gate electrode 3 having a gate length comparable to that of a normal transistor is formed, and a memory function body having a side wall spacer (side wall insulating film) shape is formed on the side wall of the gate insulating film 2 and the gate electrode 3. The charge holding film 4 is formed. The surface of the semiconductor substrate under the gate electrode is a channel region 6. Further, on both sides of the channel region 6, a source / drain region composed of an impurity diffusion region having a conductivity type of the channel region, that is, in this embodiment, a conductivity type opposite to the conductivity type on the surface of the semiconductor substrate is formed. The source / drain region includes a high concentration impurity diffusion region 7 and a low concentration impurity diffusion region 8, and the low concentration impurity diffusion region 8 is disposed in the vicinity of the channel region 6.

The memory function body is formed on the source / drain region, and at least a part of the source / drain region located below the memory function body is preferably the low concentration impurity diffusion region 8. The diffusion region 8 is preferably set so that the depletion or the conductivity type is reversed due to the amount of charge stored in the memory function body.
In this memory cell, the memory function body of the memory transistor is formed independently of the gate insulating film. That is, the memory function performed by the memory function body is separated from the transistor operation function performed by the gate insulating film. Therefore, the charge retention film 4 which is a memory function body can be formed of a material suitable for the memory function.

Further, since the high-concentration impurity diffusion region 7 is offset from the gate electrode 3, the low-concentration impurity diffusion region 8 under the charge holding film 4 serving as a memory function body when a voltage is applied to the gate electrode 3 is inverted. The ease can be greatly changed by the amount of charge accumulated in the charge holding film 4 serving as a memory function body, and the memory effect can be increased.
In this memory cell, the low-concentration impurity diffusion region 8 is depleted or inverted when electrons are injected into the memory function body (defined as writing in the case of an N-channel element). Therefore, it appears that the structure is equivalent to a MOSFET in which the source / drain regions are offset with respect to the gate electrode, and the amount of current between the source / drain regions is extremely reduced. On the other hand, in the hole injection into the memory function body (defined as erasure in the case of an N channel type element), the low concentration impurity diffusion region 8 is originally formed, so that the initial state (both electrons and holes are in the memory function body). The current between the source / drain regions does not change significantly as compared with a state in which they are not accumulated or a thermal equilibrium state.

Therefore, this memory cell has a great advantage that non-erasing which is a big problem in a nonvolatile memory (for example, EEPROM or FLASH) does not occur and it is not necessary to provide an over-erasing countermeasure peripheral circuit.
This memory cell can be formed through the same process as a normal logic transistor.

First, as shown in FIG. 5A, a gate insulating film 2 made of a silicon oxynitride film with a thickness of about 1 to 6 nm and polysilicon, polysilicon with a thickness of about 50 to 400 nm are formed on a semiconductor substrate 1. A gate electrode material film made of a laminated film of melting point metal silicide or a laminated film of polysilicon and metal is formed and patterned into a desired shape to form the gate electrode 3.
Note that, as described above, the material for the gate insulating film and the gate electrode may be a material used in a logic process in accordance with the scaling law of that era, and is not limited to the above materials.

  Subsequently, completely separated from the gate insulating film 2, a film made of a silicon nitride film having a thickness of about 20 to 100 nm is formed on the entire surface of the obtained semiconductor substrate 1 as shown in FIG. 5B. Then, by etching back by anisotropic etching, the charge holding film 4 optimum for memory is formed in a side wall spacer shape on the side wall of the gate electrode. Instead of the silicon nitride film, a silicon oxide film with a thickness of about 2 to 20 nm and a silicon nitride film with a thickness of about 2 to 100 nm are sequentially deposited, and etched back by anisotropic etching to hold the charge optimal for storage. More preferably, the film 4 is formed in a sidewall spacer shape on the side wall of the gate electrode.

Thereafter, as shown in FIG. 5C, ion implantation is performed using the gate electrode 3 and the charge holding film 4 as a mask to form source / drain regions (high concentration impurity diffusion region 7 and low concentration impurity diffusion region 8). To do. The low concentration impurity diffusion region 8 may be formed by ion implantation before the step of forming the memory function body 4. The low-concentration impurity diffusion region 8 has a conductivity type opposite to that of the impurity forming the channel, and is 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ³ , and further 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10. It is preferable to have an impurity concentration in the range of ¹⁷ / cm ³ .

In this manner, by disposing the gate insulating film 2 and the charge holding film 4 serving as a memory function body separately, a memory cell transistor having the same short channel effect is formed in the same manufacturing process as a normal transistor. it can. Therefore, a logic circuit portion can be formed by a part of transistors formed on the same chip by the above procedure, and a memory portion (for example, a nonvolatile memory) can be formed by other transistors. In this case, if the logic circuit portion is operated in a voltage range in which no charge is injected into the memory function body, a change in the characteristics of the transistor can be prevented. In the memory portion, sufficient charge is injected into the memory function body. Rewriting can be performed by applying a voltage. That is, it is possible to mount the logic circuit and the nonvolatile memory in a very simple process.
In addition to the variable resistance type two element / cell type nonvolatile memory (MRAM) shown in the prior art, there is an EEPROM as a typical nonvolatile memory.

  As shown in FIG. 6A, the EEPROM is a memory transistor having a selection transistor (STr) connected to the control gate line (CGL) and a charge holding film (MF) connected to the word line (WL). Whereas the memory cell is composed of two transistors (MTr), the memory cell having the above structure has two variables by two memory function bodies as shown in FIG. A memory cell having a function of a selection transistor and a memory transistor can be configured with one gate electrode (that is, one word line, WL) by the resistance effect. That is, it can be considered that the variable resistors arranged under the memory function body on both sides of the gate electrode between the source / drain regions and at both ends of the channel region are connected to the channel region. The memory function body changes the resistance of the diffusion region located under the memory function body by applying a voltage to the gate electrode in accordance with the amount of charge held in the memory function body, and changes the resistance from one diffusion region to the other. The amount of current is changed in the diffusion region. In addition, one memory cell includes only four terminals, one terminal connected to the semiconductor substrate, two terminals connected to the two diffusion regions, and one terminal connected to the gate electrode. ing. Further, this semiconductor memory device performs a read, write or erase operation only by applying four kinds of voltages: a voltage applied to the semiconductor substrate, a voltage applied to the gate electrode, and a voltage applied to each of the two diffusion regions. Either done.

  Accordingly, in order to select one memory cell, it is only necessary to select one word line connected to the gate electrode or having the function of the gate electrode itself. Further, it is not necessary to form two transistors, and further high integration is possible. In other words, in contrast to FIG. 6A in which the number of gate electrodes, that is, control gate lines and word lines is not increased and the cell area is not reduced, in the present invention, one cell can be operated with one word line. it can. For example, if a word line is formed with the minimum processing dimensions (minimum wiring width and minimum wiring interval) and is laid out in the memory cell area, one word line is required to form one memory cell. Has an effect that the cell occupation area can be reduced to 1 / n as compared with the case where n word lines are required. (In FIG. 6A, as an example, two word lines are required to configure a memory cell, and 1 bit (binary) information is stored for each memory cell. In 6 (b), one word line constitutes one memory cell, and there are 2 bits per memory cell (because there are charge holding films on both sides of one gate electrode (word line)), 4 In other words, the memory cell has an occupation area of 1/2 (two word lines versus one) as a memory cell, and there is an effect that the bit area can be reduced to 1/4 occupation area. .

Embodiment 5
As shown in FIGS. 7A to 7E, a wide variety of memory function bodies can be employed in place of the memory function body (charge holding film 4) using the silicon nitride film in the fourth embodiment.
For example, as shown in FIG. 7A, the memory functional unit includes a silicon oxide film 41 having a thickness of about 1 to 20 nm, a silicon nitride film 42 having a thickness of about 2 to 100 nm, and a silicon oxide film having a thickness of about 5 to 100 nm. The ONO film made of the film 43 is formed.
Further, as shown in FIG. 7B, the memory function body may be formed by an ON film made of a silicon oxide film 44 having a thickness of about 1 to 20 nm and a silicon nitride film 45 having a thickness of about 2 to 100 nm. Good.

Further, as shown in FIG. 7C, the memory function body is formed by an ON film composed of a silicon oxide film 46 having a thickness of about 1 to 20 nm and a silicon nitride film 47 having a thickness of about 5 to 100 nm. The silicon nitride film 47 may be in contact with the semiconductor substrate. Note that the silicon oxide film 46 and the silicon nitride film 47 may be interchanged.
Further, as shown in FIG. 7 (d), the memory function body includes a floating gate conductive film made of polysilicon having a thickness of about 10 to 100 nm via an insulating film 48 made of a silicon oxide film having a thickness of about 1 nm to 20 nm. 49 may be formed. Note that in the case of using a conductive film, the surface of the memory film is not illustrated, but is preferably covered with an insulating film.

Further, as shown in FIG. 7E, the memory function body is formed by an insulating film 481 made of an insulating material such as a silicon oxide film, a silicon nitride film, or a high dielectric film having a thickness of about 5 to 100 nm. In the insulating film 481, one or more dot-shaped (about 1 to 8 nm in diameter) floating gate conductive films 491 made of a conductor such as silicon are dispersed.
If a memory function body having the above-described configuration, particularly a silicon nitride film-based memory function body is used, it is very preferable to be easily introduced into a mass production factory. Or a material having a charge retention function (for example, silicon nitride film, silicate glass containing impurities such as phosphorus and boron, silicon carbide, alumina, hafnium oxide, zirconium oxide, tantalum oxide, zinc oxide, ferroelectric material, etc. The semiconductor memory device of the present invention can be basically implemented as long as the insulating film includes a stacked structure film or a material having a discrete charge holding function.

Embodiment 6
As shown in FIG. 8, the memory cell constituting the semiconductor memory device of this embodiment has an N-type first diffusion region 12 and a second diffusion layer formed on the surface of a P-type well 11 formed in a semiconductor substrate. The diffusion region 13 is formed, and a channel region is formed in the uppermost layer portion of the well 11 between these diffusion regions 12 and 13. A gate electrode 17 is formed on the channel region via a gate insulating film 14 made of a silicon oxide film or silicon oxynitride film having a thickness of about 1 to 6 nm. The gate electrode 17 does not overlap with the diffusion regions 12 and 13, and a channel region (71 in FIG. 8) that is not covered with the gate electrode 17 remains slightly. At both ends of the gate electrode 17, in order to store information by accumulating or trapping charges, the gate electrodes 17 are made of silicon nitride films having a film thickness of about 10 to 100 nm (horizontal width of the semiconductor substrate). The holding films 15 and 16 are arranged, and the channel region 71 not covered with the gate electrode 17 is covered with the charge holding films 15 and 16. What is important here is that the diffusion regions 12 and 13 and the charge retention film serving as the memory function body at least partially overlap.

Next, the operation principle of this semiconductor memory device will be described below. The following operation principle can be applied not only to the semiconductor memory device of this embodiment but also to the semiconductor memory device of other embodiments of the present invention.
The principle of write operation of this semiconductor memory device will be described with reference to FIGS. 9 (a) and 9 (b).
Here, writing means injecting electrons into the charge holding film.

  In order to inject (write) electrons into the charge holding film 16 serving as a memory function body, as shown in FIG. 9A, the first diffusion region 12 is used as a source electrode, and the second diffusion region 13 is formed. A drain electrode is used. For example, 0 V may be applied to the first diffusion region 12 and the well 11, +6 V may be applied to the second diffusion region 13, and +2 V may be applied to the gate electrode 17. Under such a voltage condition, the inversion layer 410 extends from the first diffusion region 12 (source electrode), but a pinch-off point is generated without reaching the second diffusion region 13 (drain electrode). The electrons are accelerated by a high electric field from the pinch-off point to the second diffusion region 13 (drain electrode), and become so-called hot electrons. Writing is performed by injecting the hot electrons into the charge holding film 16.

Note that no writing is performed in the vicinity of the charge holding film 15 because hot electrons are not generated. In addition, even when the diffusion regions 12 and 13 and the charge retention film serving as the memory function body do not overlap at all, the generation of hot electrons is suppressed and writing is difficult in a practical applied voltage range (voltage difference of 20 V or less). become.
In this way, writing can be performed by injecting electrons into the charge retention film 16 serving as a memory function body.

On the other hand, in order to inject (write) electrons into the charge holding film 15 serving as a memory function body, as shown in FIG. 9B, the second diffusion region 13 is used as a source electrode, and the first diffusion region is used. 12 is a drain electrode. For example, 0V may be applied to the second diffusion region 13 and the well 11, + 6V may be applied to the first diffusion region 12, and + 2V may be applied to the gate electrode 17. Thus, in the case of injecting electrons into the charge holding film 16, writing can be performed by injecting electrons into the charge holding film 15 by switching the source / drain regions.
Next, the read operation principle of the semiconductor memory device will be described with reference to FIG.

  When reading information stored in the charge retention film 15 serving as a memory function body, the first diffusion region 12 is used as a source electrode, the second diffusion region 13 is used as a drain electrode, and the transistor is operated in a saturation region. For example, 0V may be applied to the first diffusion region 12 and the well 11, + 2V may be applied to the second diffusion region 13, and + 1V may be applied to the gate electrode 17. At this time, if electrons are not accumulated in the charge retention film 15, a drain current tends to flow. On the other hand, when electrons are accumulated in the region 15, the inversion layer 410 is not easily formed in the vicinity of the charge retention film 15, so that the drain current is difficult to flow. Therefore, the stored information of the charge holding film 15 can be read by detecting the drain current. At this time, the presence or absence of charge accumulation in the charge holding film 16 does not affect the drain current because the vicinity of the drain is pinched off. As described above, by operating the transistor in the saturation region at the time of reading (pinch off the vicinity of the drain), it is possible to detect the stored information of the charge holding film 15 with high sensitivity regardless of the storage state of the charge holding film 16. it can. This is a major factor enabling 2-bit operation.

  As is clear from the above description, the roles of the source electrode and the drain electrode in the case where electrons are injected (written) into the charge holding film 15 serving as the memory function body and the case where the stored information in the charge holding film 15 is read out. Has been replaced. In other words, one and the other of the first and second diffusion regions (source / drain regions) when the memory state is changed by injecting electrons into the memory function body and when the memory state of the memory function body is read. The magnitude relationship of the voltage applied to is reversed. Therefore, as described below, it is possible to obtain an effect that resistance to read disturb is improved.

For example, the second diffusion region 13 is used as a source electrode and the first diffusion region 12 is used as a drain electrode in order to read stored information in the charge retention film 15 (that is, the source / drain electrode during the write operation and the read operation). In the same role), a small number of electrons are injected into the charge holding film 15 every read operation. This is because electrons have a relatively high energy on the drain electrode side even with a small drain voltage in the read operation. Therefore, there is a possibility that the stored information of the charge holding film 15 is rewritten when reading is performed many times without performing the rewriting operation.
However, if the roles of the source / drain electrodes are exchanged during the write operation and the read operation, the charge retention film 15 is on the source electrode side during the read operation, so there is no fear of such erroneous writing. Therefore, resistance to read disturb is improved.

  When reading the information stored in the charge retention film 16, the transistor is operated in a saturation region by using the second diffusion region 13 as a source electrode and the first diffusion region 12 as a drain electrode. For example, 0V may be applied to the second diffusion region 13 and the well 11, + 2V may be applied to the first diffusion region 12, and + 1V may be applied to the gate electrode 17. As described above, when the information stored in the charge holding film 15 is read, the information stored in the charge holding film 16 can be read by switching the source / drain regions.

  When the channel region 71 that is not covered with the gate electrode 17 remains, the inversion layer disappears or is formed in the channel region that is not covered with the gate electrode 17 depending on the presence or absence of surplus electrons in the charge holding films 15 and 16. As a result, a large hysteresis (change in threshold value) is obtained. However, if the width of the channel region 71 not covered with the gate electrode 17 is too large, the drain current is greatly reduced, and the reading speed is greatly reduced. In particular, when the charge holding films 15 and 16 and the first and second diffusion regions do not overlap at all, the reading speed is so slow that it no longer functions as a practical storage device. Therefore, it is preferable to determine the width of the channel region 71 not covered with the gate electrode 17 so that sufficient hysteresis and reading speed can be obtained.

  Even when the diffusion regions 12 and 13 reach the end of the gate electrode 17, that is, when the diffusion regions 12 and 13 and the gate electrode 17 overlap, the threshold value of the transistor is hardly changed by the write operation. However, the parasitic resistance at the source / drain ends changed greatly, and the drain current decreased greatly (one digit or more) (in this embodiment, the concentration of the diffusion regions 12 and 13 is high, as in the fourth embodiment). Since the concentration in the vicinity of the channel was not made thin, the conductivity type did not reverse, and the threshold value hardly changed. Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the diffusion regions 12 and 13 and the gate electrode 17 do not overlap.

In addition, when the diffusion regions 12 and 13 are offset from the end of the gate electrode 17 (that is, not overlapping), the short channel effect can be strongly prevented compared to a normal logic transistor. Therefore, further miniaturization of the gate length can be achieved. In addition, since it is structurally suitable for suppressing the short channel effect, it is possible to employ a gate insulating film that is thicker than a logic transistor, and it is possible to improve reliability.
In any case, the channel region that is not covered with the gate electrode 17 by the presence or absence of charges accumulated in the charge holding films 15 and 16 by overlapping the charge holding films 15 and 16 with the first and second diffusion regions. Since the resistance 71 changes greatly, the resistances of the two variable resistors in FIG. 6B in the fourth embodiment can be changed independently.
Further, the erase operation principle of the semiconductor memory device will be described.

First, as a first method, when erasing information stored in the charge retention film 15 serving as a memory function body, a positive voltage (for example, +6 V) is applied to the first diffusion region 12 and 0 V is applied to the well 11. A reverse bias may be applied to the PN junction between the first diffusion region 12 and the well 11 and a negative voltage (for example, −5 V) may be applied to the gate electrode 17. At this time, in the PN junction in the vicinity of the gate insulating film, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, hot holes are generated on the well region 11 side of the PN junction due to the band-to-band tunnel. This hot hole is drawn in the direction of the gate electrode 17 having a negative potential, and as a result, hole injection is performed in the charge holding film 15. In this way, the charge holding film 15 is erased. At this time, 0 V may be applied to the second diffusion region 13.
When erasing information stored in the charge holding film 16, the potentials of the first diffusion region and the second diffusion region may be switched in the above.

  As a second method, when erasing information stored in the charge holding film 15 serving as a memory function body as shown in FIG. 11, a positive voltage (for example, +5 V) is applied to the first diffusion region 12, and the second diffusion is performed. It is only necessary to apply 0 V to the region 13, a negative voltage (for example, −4 V) to the gate electrode 17, and a positive voltage (for example, 0.8 V) to the well 11. At this time, a forward voltage is applied between the well 11 and the second diffusion region 13, and electrons are injected into the well 11. The injected electrons are diffused to the PN junction between the well 11 and the first diffusion region 12, where they are accelerated by a strong electric field and become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. Hot holes generated at the PN junction are attracted toward the gate electrode 17 having a negative potential, and as a result, holes are injected into the charge retention film 15.

According to the second method, the second diffusion region 13 can be applied even when only a voltage sufficient to generate hot holes due to the band-to-band tunnel is applied to the PN junction between the well 11 and the first diffusion region 12. Hot holes can be generated by the electrons injected from. Therefore, the voltage during the erase operation can be reduced.
Note that when erasing information stored in the charge retention film 15, +6 V had to be applied to the first diffusion region 12 in the first erasing method, but in the second erasing method, +5 V was applied. It was enough. Thus, according to the second method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the semiconductor memory device due to hot carriers can be suppressed.

With the above operation method, it is possible to selectively write and erase 2 bits (4 values) per transistor. For this reason, the occupation area per bit can be reduced, and the manufacturing cost of the semiconductor memory device can be reduced. Note that multilevel technology used in flash memory or the like requires extremely precise threshold control. However, when the above operation method is applied to the semiconductor memory device of the present invention, such threshold control is performed. There is no need.
In the above operation method, writing and erasing of 2 bits per transistor are performed by switching the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed and operated as a 1-bit memory. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be halved.
Although the above-described operations of reading, writing, and erasing have been described for the case of an N-channel element, in the case of a P-channel element, the same operation can be performed by reversing the signs of all applied voltages.

Embodiment 7
As shown in FIG. 12, the semiconductor memory device of this embodiment has substantially the same configuration except that the semiconductor substrate in the sixth embodiment is an SOI (Silicon on Insulator) substrate.
In this semiconductor memory device, a buried oxide film 83 is formed on a semiconductor substrate 81, and an SOI layer is further formed thereon. Diffusion regions 12 and 13 are formed in the SOI layer, and the other region is a body region 82.
This semiconductor memory device also has the same effect as the semiconductor memory device of the sixth embodiment. Further, since the junction capacitance between the diffusion regions 12 and 13 and the body region 82 can be remarkably reduced, the device can be increased in speed and power consumption can be reduced.

Embodiment 8
In the semiconductor memory device of this embodiment, as shown in FIG. 13, a gate insulating film 14 is extended between the charge holding films 15 and 16 and the well 11 and the diffusion regions 12 and 13. Other than that, the semiconductor memory device of the sixth embodiment has substantially the same configuration.
That is, the charge retention film is in contact with the diffusion region and / or the well region or the body region (when an SOI substrate is used) through the insulating film at least in the vicinity of the gate electrode.

This semiconductor memory device also has the same effect as the semiconductor memory device of the sixth embodiment. Furthermore, the gate insulating film 14 between the charge holding films 15 and 16 and the well 11 and the diffusion regions 12 and 13 suppresses leakage of the held charges and can improve the holding characteristics. In addition, since the entire surface of the channel region is covered with the gate insulating film 14, the drain current can be increased by suppressing the interfacial scattering of the inversion layer carriers, and thus the reading speed can be improved.
The insulating film under the charge retention film may be designed and formed separately from the gate insulating film. The gate electrode may be designed with priority given to suppressing the short channel effect, and the insulating film under the charge retention film may be formed thicker or thinner than the gate insulating film. The charge holding film is not limited to the silicon nitride film, and may be a film having the above-described configuration and material.

Embodiment 9
As shown in FIG. 14, the semiconductor memory device of this embodiment is similar to that of the semiconductor device of the eighth embodiment except that the charge holding film 19 made of a silicon nitride film constitutes the gate sidewall insulating film of the gate electrode 17. It is substantially the same as the storage device.
In this semiconductor memory device, the charges are actually accumulated or trapped and the memory is held in the regions 20 and 21 in the charge holding film 19.

This semiconductor memory device also has the same effects as the semiconductor memory device of the eighth embodiment. Further, since the side wall of the gate electrode 17 is covered with the charge holding film 19 in the form of a gate side wall insulating film, if ion implantation for forming the diffusion regions 12 and 13 is performed using the charge holding film 19 as a mask, It becomes easy to control the positions of the end portions of the diffusion regions 12 and 13. For example, the channel region that is not covered with the gate electrode 17 is easily left, and the channel region that is not covered with the gate electrode 17 is easily covered with the charge holding film 19. Therefore, a semiconductor memory device having a large hysteresis (change in threshold value) can be easily manufactured.
Further, the insulating film under the charge holding film 19 may be designed separately from the gate insulating film. The gate electrode may be designed and formed with priority on suppressing the short channel effect, and the insulating film under the charge retention film may be formed thicker or thinner than the gate insulating film.

Embodiment 10
In the semiconductor memory device of this embodiment, as shown in FIG. 15, the charge retention film 22 is formed in an L shape on the gate insulating film 14 and is covered with a gate sidewall insulating film 25 made of a silicon oxide film. Except for this, the semiconductor memory device of the ninth embodiment is substantially the same.
In this semiconductor memory device, it is the regions 23 and 24 in the charge holding film 22 where charges are actually accumulated or trapped to hold the memory.
The semiconductor memory device of this embodiment has the same operational effects as the semiconductor memory device of the ninth embodiment. In addition, since the charge retention film 22 is sandwiched between the gate insulating film 14 and the gate sidewall insulating film 25, it has an ONO film structure, which can increase the efficiency of electron and hole injection and increase the operation speed.

A method of manufacturing this semiconductor memory device will be described with reference to FIG. Note that formation of an element isolation region and the like is omitted.
First, as shown in FIG. 16A, a P-type well 11 is made of a silicon oxide film or silicon oxynitride film with a film thickness of about 1 to 6 nm, or a high dielectric film with a film thickness of about 1 to 100 nm. A gate insulating film 14 is formed, and further the gate electrode 17 is patterned.
Next, as shown in FIG. 16B, a silicon nitride film 53 having a thickness of about 5 to 20 nm and a silicon oxide film 54 having a thickness of about 20 to 100 nm are formed on the entire surface of the obtained semiconductor substrate by a CVD method. Deposit in order.

If the patterning process (etching process) is such that the gate insulating film exposed during the patterning process of the gate electrode 17 in FIG. 16A is damaged, the exposed gate insulating film other than under the gate electrode is used. Then, a silicon oxide film or silicon oxynitride film by oxidation or CVD method, or a high dielectric film by CVD method or the like may be formed under the silicon nitride film 53 in advance.
Subsequently, as shown in FIG. 16C, the silicon oxide film 54 and the silicon nitride film 53 are selectively etched back with respect to the gate electrode 17 and the semiconductor substrate. As a result, the charge holding film 22 made of the L-shaped silicon nitride film 53 and the gate sidewall insulating film 25 covering the charge holding film 22 are formed. Thereafter, diffusion regions 12 and 13 are formed.
As described above, the semiconductor memory device of this embodiment can be manufactured by a simple process including an insulating film forming process and an etch back process.

Embodiment 11
In the semiconductor memory device of this embodiment, as shown in FIG. 17, the gate electrode 17 has recesses at both lower ends, and at least a part of the charge holding film 19 made of a silicon nitride film is embedded in the recesses. The semiconductor memory device of the ninth embodiment is substantially the same as that of the ninth embodiment except that the charge holding film 19 and the gate electrode 17 are separated from each other by the silicon oxide film 81.
This semiconductor memory device also has the same effects as the semiconductor memory device of the ninth embodiment.

Further, during the erasing operation, hot holes generated in the vicinity of the region indicated by the arrow 71 in FIG. 17 are attracted to the negative potential gate electrode and are efficiently injected into the charge holding film 19 as indicated by the arrow 72. The operation can be speeded up.
In this semiconductor memory device, the charge is actually accumulated or trapped and the memory is held in the portion of the charge holding film 19 mainly embedded in the recess of the gate electrode (near the tip of the arrow 72). is there.
A method of manufacturing this semiconductor memory device will be described with reference to FIG. Note that formation of an element isolation region and the like is omitted.
First, as shown in FIG. 18A, after forming the gate insulating film 14 and the gate electrode 17 on the P-type well 11, the entire surface is oxidized to form a silicon oxide film 51. The silicon oxide film thickness at this time can be set to 5 nm to 20 nm, for example. At this time, bird's beaks are formed in a wedge shape at both lower ends of the gate electrode 17.

Next, as shown in FIG. 18B, after the silicon oxide film 51 is removed by isotropic etching, the entire surface is re-oxidized to form a silicon oxide film 52. The silicon oxide film 52 becomes an insulating film that separates the charge holding film from the gate electrode, the channel region (well region), and the diffusion region (source / drain region). The silicon oxide film thickness at this time is not particularly limited, but is preferably 4 nm to 20 nm from the viewpoint of achieving both rewrite characteristics and retention characteristics of the semiconductor memory device.
Next, as shown in FIG. 18C, a silicon nitride film is deposited on the entire surface (for example, 20 nm to 200 nm) and then etched back to form a charge holding film 19 in the form of a gate sidewall insulating film. Thereafter, impurity ion implantation and heat treatment are performed using the charge holding film 19 as a mask to form diffusion regions 12 and 13 to complete the semiconductor memory device (upper wiring and the like are omitted).

Embodiment 12
In the semiconductor memory device of this embodiment, as shown in FIG. 19, a charge holding film 82 made of a silicon nitride film, at least a part of which is embedded in the recess of the gate electrode 17, is formed on the silicon oxide films 81 and 83. Except for being sandwiched, it is substantially the same as the semiconductor memory device of the eleventh embodiment.
This semiconductor memory device also has the same operational effects as the semiconductor memory device of the eleventh embodiment. In addition, since the charge holding film 82 has an ONO film structure sandwiched between the silicon oxide films 81 and 83, the injection efficiency of electrons and holes can be increased and the operation speed can be increased.
For example, in the method of forming the semiconductor memory device according to the eleventh embodiment, this semiconductor memory device has a silicon nitride film (for example, 5 nm to 15 nm) and a silicon oxide film (for example, 20 nm to 200 nm) after the state shown in FIG. ) Are deposited in this order, and the silicon oxide film and the silicon nitride film are etched back.

Embodiment 13
As shown in FIG. 20, the semiconductor memory device of this embodiment includes a gate made of a silicon oxide film having a thickness of about 1 to 6 nm on a P-type well 11 formed in a semiconductor substrate having an element isolation region 31. A gate electrode 17 is formed via the insulating film 14. A charge holding film 32 made of a silicon nitride film having a thickness of about 20 to 100 nm is formed on the side wall of the gate electrode 17. Note that the form of the charge retention film is not limited to the form of this embodiment, and there are various forms as described above. Further, sidewalls 26 and 27 made of polysilicon are formed on the sidewall of the charge holding film 32. Further, N-type impurities ooze out on the surface of the well 11 immediately below the sidewalls 26 and 27 to form N-type regions 28 and 29, respectively. Sidewall 26 and N-type region 28 together form a first diffusion region, and similarly, sidewall 27 and N-type region 29 form a second diffusion region. The surface of the element isolation region 31 is covered with the silicon nitride film 30.

In this semiconductor memory device, the charges are actually accumulated or trapped and the memory is held in the regions 23 and 24 in the charge holding film 32.
In this semiconductor memory device, since the diffusion region has a raised structure made of polysilicon, it is very easy to form a shallow junction. Therefore, the short channel effect can be suppressed extremely effectively and the device can be miniaturized.
Although not shown, the margin when providing the contact in the diffusion region can be reduced as compared with the case where the raised structure is not provided. Therefore, the junction area between the diffusion region and the well can be significantly reduced, and the junction capacitance can be reduced. Thereby, it can be operated at high speed and power consumption can be suppressed.

Further, this semiconductor memory device can constitute a logic circuit as a normal field effect transistor capable of reducing power consumption, high speed operation, and miniaturization when operated at a low voltage that does not allow writing. . That is, an element having a completely common structure can be used as an element constituting a logic circuit or an element constituting a memory circuit. Therefore, the mixed mounting process of the logic circuit and the memory circuit can be greatly simplified.
A method for forming this semiconductor memory device will be described with reference to FIGS.

First, as shown in FIG. 21A, a P-type well 11 is formed in a semiconductor substrate, and then an element isolation region 31 is formed by using, for example, the STI method. A gate insulating film 14 made of a silicon oxide film having a thickness of about 1 to 6 nm is formed on the obtained well 11. Next, a polysilicon film to be a gate electrode and an insulating film 55 are deposited in this order. Thereafter, the polysilicon film and the insulating film 55 are patterned using a resist pattern having a predetermined shape as a mask. Alternatively, only the insulating film 55 may be patterned using the resist pattern as a mask, and after removing the resist pattern, the polysilicon film may be etched using the insulating film 55 as a mask. Thereby, the gate electrode 17 having a cap made of the insulating film 55 is formed.
Next, as shown in FIG. 21B, a silicon nitride film 58 is deposited on the entire surface of the obtained semiconductor substrate, and the element isolation region 31 is masked with a resist pattern 56.

Subsequently, as shown in FIG. 21C, the silicon nitride film 58 is etched back using the resist pattern 56 as a mask, whereby a charge holding film made of a silicon nitride film is formed on the side walls of the gate electrode 17 and the insulating film 55. 32 is formed, and the silicon nitride film 30 is left on the element isolation region 31. The silicon nitride film 30 protects the semiconductor substrate and the element isolation region 31 in a subsequent etching process. In particular, it is important in an etch back process when forming side walls 26 and 27 made of polysilicon, which will be described later, an etching process for removing the insulating film 55, and an etching process when forming contact holes on the diffusion region. is there.
Next, as shown in FIG. 22D, a polysilicon film 57 is deposited on the entire surface of the obtained semiconductor substrate.

Next, the polysilicon film 57 is etched back until the insulating film 55 is exposed. At this time, it is preferable that the polysilicon film 57 partially covers the silicon nitride film 30 and completely covers the element isolation region 31 with them.
Thereafter, as shown in FIG. 22E, the insulating film 55 is removed by isotropic etching. In these etchings, the silicon nitride film 30 serves as a stopper, and the element isolation region 31 can be prevented from being over-etched. Subsequently, by using a resist pattern having a predetermined shape as a mask, a part of the polysilicon film 57 is removed by anisotropic etching to form sidewalls 26 and 27 separated from each other. Thereby, when impurities are implanted into the sidewalls 26 and 27, each constitutes a diffusion region (source region or drain region).

Next, impurities are ion-implanted into the gate electrode 17 and the sidewalls 26 and 27, and annealing for impurity activation is performed. Thereby, the impurity ions are diffused into the well 11 to form regions 28 and 29, and the diffusion regions are formed integrally with the sidewalls 26 and 27, respectively.
According to this semiconductor memory device, the short channel effect is extremely suppressed while miniaturization is possible while realizing storage of 2 bits per transistor. In addition, high-speed operation and low power consumption are possible.
Furthermore, since this semiconductor memory device can be used as a transistor constituting a logic circuit as it is, the mixed mounting process of the logic circuit and the memory circuit can be greatly simplified.

In addition, the impurity ions implanted into the sidewalls 26 and 27 are diffused into the well 11 to form a junction between the source / drain region and the well region having a very steep profile. That is, a steep profile junction can be formed between a source / drain region having an impurity concentration of 10 ²⁰ cm ⁻³ or more and a well having an impurity concentration of 10 ¹⁸ cm ⁻³ or more, and 1 V is applied to the gate electrode. The drain withstand voltage can be 3V or less. Therefore, the gate electrode 3V, one of the N-type source / drain regions and the well are set to GND, and the other of the N-type source / drain regions is set to 3V. Electrons can be injected into the charge retention film. Conversely, -2V for the gate electrode, GND for one of the N-type source / drain regions, and 0.8V for the well (voltage about the built-in potential of the PN junction or slightly higher than the built-in potential of the PN junction), By simply setting the other of the N-type source / drain regions to 3V, holes can be injected into the charge holding film near the source / drain region set to 3V. Thus, by designing the junction between the source / drain region and the well region to have a steep profile, the drain withstand voltage can be set low, and the write / erase voltage can be set low due to this effect.

Embodiment 14
A new writing and erasing method of the semiconductor memory device of the present invention will be described.
Since this write / erase method uses an electric field between a bit line and a word line as shown below, for example, the structure of the thirteenth embodiment is effective, but the structure of the other embodiments is effective. It can be applied even if it exists. In this case, a large electric field is applied only to the selected charge retention film by providing a word line connected to the gate electrode or having a function of the gate electrode itself and a bit line connected to the source / drain region. Can be applied.

  The selected bit line is set to a reference potential (for example, 0 V). At this time, + VDD is applied to the selected word line, +2/3 VDD is applied to the non-selected bit line, and +1/3 VDD is applied to the non-selected word line. As a result, the electric field difference VDD is applied to the charge holding film having the selected word line and the selected bit line as counter electrodes, and the electric field difference 1/3 VDD is applied to all the other charge holding films. Random access writing / erasing is possible by using a charge holding film that can be written / erased with an electric field difference VDD and not written / erased with an electric field difference of 1/3 VDD. In this method, since writing / erasing is directly performed by a tunnel current, writing / erasing can be performed with a low current, and there is an effect of reducing power consumption.

In addition, as shown in FIGS. 23A and 23B, the large scale integrated memory using the bulk substrate has a first conductivity type well region 1901 formed in the semiconductor substrate (the surface of the semiconductor substrate). A gate insulating film 1902 formed on the well region 1901, a plurality of word lines 1903 formed on the gate insulating film, and a plurality of second lines formed on both sides of the plurality of word lines 1903, respectively. A conductive type diffusion region 1905 and at least a part of the diffusion region or straddling a part of the well region and a part of the diffusion region on both sides of the plurality of word lines; A charge holding film 1904 having a function of accumulating or trapping charges, formed directly or via an insulating film, with respect to the well region and the diffusion region, and connected to the plurality of diffusion regions, Comprising a plurality of bit lines extending in a direction intersecting with a line (not shown). In FIG. 23A, reference numeral 1910 denotes an element isolation region. FIG. 23B is a cross-sectional view taken along the line AA ′ in FIG. A charge retention film between a terminal (which may be the bit line itself) 1907 and a word line (gate electrode) 1903 connecting a bit line (not shown) and a second conductivity type diffusion region (source / drain region) 1905 It is preferable that 1904 is sandwiched. In this case, an electric field is directly applied between the gate electrode and the terminal, and electrons or holes can be injected between the two selected nodes, and electrons or holes can be extracted. Compared with hot electrons or hot holes, writing / writing is possible. Erase efficiency can be improved.
If the memory cells are not as dense as shown in FIG. 23, an interlayer insulating film is formed between the terminal 1907 connecting the diffusion region (source / drain region) 1905 of the second conductivity type and the charge holding film 1904. Will intervene. As the writing and erasing method in this case, it is preferable to use the method of Embodiment 6 rather than the method described in this embodiment.

Embodiment 15
In the semiconductor memory device according to this embodiment, the memory function bodies 161 and 162 have a region for holding charges (a region for storing charges and may be a film having a function for holding charges) and the charge is difficult to escape. Region (which may be a film having a function of making it difficult for the charge to escape). For example, as shown in FIG. 24, it has an ONO structure. In other words, the silicon nitride film 142 is sandwiched between the silicon oxide film 141 and the silicon oxide film 143 to constitute the memory function bodies 161 and 162. Here, the silicon nitride film functions to retain electric charges. In addition, the silicon oxide films 141 and 143 serve as films having a function of making it difficult for the charges stored in the silicon nitride film to escape.

In addition, the regions (silicon nitride film 142) for holding charges in the memory function bodies 161 and 162 overlap with the diffusion regions 112 and 113, respectively. Here, the term “overlap” means that at least a part of a region (silicon nitride film 142) that retains charges exists on at least a part of the diffusion regions 112 and 113. Reference numeral 111 denotes a semiconductor substrate, 114 denotes a gate insulating film, 117 denotes a gate electrode, and 171 denotes an offset region (a gate electrode and a diffusion region). Although not shown, the uppermost surface portion of the semiconductor substrate 111 below the gate insulating film 114 is a channel region.
A description will be given of the effect of the region 142 that retains charges and the diffusion regions 112 and 113 in the memory function bodies 161 and 162 overlap.

  FIG. 25 is an enlarged view of the periphery of the memory function body 162 on the right side of FIG. W1 represents an offset amount between the gate electrode 114 and the diffusion region 113. W2 indicates the width of the memory function body 162 at the cut surface of the gate electrode in the channel length direction. The end of the memory function body 162 on the side away from the gate electrode 117 of the silicon nitride film 142 is the gate electrode. Since it coincides with the end of the memory function body 162 on the side away from 117, the width of the memory function body 162 is defined as W2. The amount of overlap between the memory function body 162 and the diffusion region 113 is represented by W2-W1. What is particularly important is that the silicon nitride film 142 of the memory function body 162 overlaps with the diffusion region 113, that is, satisfies the relationship of W2> W1.

As shown in FIG. 26, when the end of the silicon functional film 162a away from the gate electrode of the silicon nitride film 142a does not coincide with the end of the memory functional body 162a away from the gate electrode. , W2 may be defined as from the gate electrode end to the end far from the gate electrode of the silicon nitride film 142a.
FIG. 27 shows the drain current Id when the width W2 of the memory function body 162 is fixed to 100 nm and the offset amount W1 is changed in the structure of FIG. Here, the drain current was obtained by device simulation with the memory function body 162 in the erased state (holes accumulated) and the diffusion regions 112 and 113 as the source electrode and the drain electrode, respectively.

  As is apparent from FIG. 27, when W1 is 100 nm or more (that is, the silicon nitride film 142 and the diffusion region 113 do not overlap), the drain current rapidly decreases. Since the drain current value is substantially proportional to the read operation speed, the memory performance deteriorates rapidly when W1 is 100 nm or more. On the other hand, in the range where the silicon nitride film 142 and the diffusion region 113 overlap, the decrease in the drain current is moderate. Therefore, it is preferable that at least a part of the silicon nitride film 142 which is a film having a function of holding electric charge overlaps with the source / drain regions.

  Based on the result of the device simulation described above, a memory cell array was fabricated with W2 fixed at 100 nm and W1 set to 60 nm and 100 nm as design values. When W1 is 60 nm, the silicon nitride film 142 and the diffusion regions 112 and 113 overlap by 40 nm as a design value, and when W1 is 100 nm, they do not overlap as a design value. As a result of measuring the read time of these memory cell arrays, the read access time was 100 times faster when W1 was set to 60 nm as the design value, compared with the worst case in consideration of variations. Practically, the read access time is preferably 100 nanoseconds or less per bit, but it has been found that this condition cannot be achieved when W1 = W2. Further, it was found that W2-W1> 10 nm is more preferable when considering manufacturing variations.

Reading of information stored in the memory function body 161 (region 181) is performed on the side close to the drain region in the channel region using the diffusion region 112 as the source electrode and the diffusion region 113 as the drain region, as in the sixth embodiment. It is preferable to form a pinch-off point. That is, when reading the information stored in one of the two memory function bodies, it is preferable to form the pinch-off point in the channel area and in an area close to the other memory function body. As a result, regardless of the storage status of the memory function body 162, the stored information of the memory function body 161 can be detected with high sensitivity, which is a major factor enabling 2-bit operation.
On the other hand, when information is stored only on one side of two memory function bodies or when two memory function bodies are used in the same storage state, a pinch-off point does not necessarily have to be formed at the time of reading.

Although not shown in FIG. 24, a well region (a P-type well in the case of an N channel element) is preferably formed on the surface of the semiconductor substrate 111. By forming the well region, it becomes easy to control other electrical characteristics (withstand voltage, junction capacitance, short channel effect) while optimizing the impurity concentration of the channel region for the memory operation (rewrite operation and read operation). .
The memory function body preferably includes a charge holding film having a function of holding charges and an insulating film from the viewpoint of improving the holding characteristics of the memory. In this embodiment, a silicon nitride film 142 having a level for trapping charges is used as a charge holding film, and silicon oxide films 141 and 143 having a function of preventing the dissipation of charges accumulated in the charge holding film are used as insulating films. Yes. When the memory function body includes the charge holding film and the insulating film, it is possible to prevent charge dissipation and improve the holding characteristics. Furthermore, the volume of the charge retention film can be reduced appropriately as compared with the case where the memory function body is composed of only the charge retention film. By appropriately reducing the volume of the charge holding film, the movement of charges in the charge holding film can be limited, and the change in characteristics due to the charge movement during memory holding can be suppressed.

  In addition, the memory function body includes a charge holding film disposed substantially parallel to the surface of the gate insulating film. In other words, the upper surface of the charge holding film in the memory function body is positioned at an equal distance from the upper surface of the gate insulating film. It is preferable to arrange | position. Specifically, as shown in FIG. 28, the charge retention film 142a of the memory function body 162 has a surface substantially parallel to the surface of the gate insulating film 114. In other words, the charge holding film 142a is preferably formed to have a uniform height from a height corresponding to the surface of the gate insulating film 114. The presence of the charge holding film 142a substantially parallel to the surface of the gate insulating film 114 in the memory function body 162 makes it easy to form an inversion layer in the offset region 171 due to the amount of charge accumulated in the charge holding film 142a. It is possible to effectively control the memory effect. Further, by making the charge retention film 142a substantially parallel to the surface of the gate insulating film 114, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and the variation in the memory effect is suppressed. can do. In addition, the movement of charges in the upper direction of the charge retention film 142a is suppressed, and it is possible to suppress a change in characteristics due to the charge movement during the storage and retention.

Further, the memory function body 162 includes an insulating film (for example, a portion of the silicon oxide film 144 on the offset region 171 that separates the charge holding film 142a substantially parallel to the surface of the gate insulating film 114 and the channel region (or well region)). ) Is preferably included. With this insulating film, dissipation of charges accumulated in the charge holding film is suppressed, and a semiconductor memory device with better holding characteristics can be obtained.
Note that the surface of the semiconductor substrate is controlled by controlling the film thickness of the charge holding film 142a and controlling the film thickness of the insulating film below the charge holding film 142a (the portion of the silicon oxide film 144 above the offset region 171) to be constant. It is possible to keep the distance from the electric charge stored in the charge holding film substantially constant. That is, the distance from the surface of the semiconductor substrate to the charge stored in the charge holding film is changed from the minimum film thickness value of the insulating film under the charge holding film 142a to the maximum film thickness value of the insulating film under the charge holding film 142a and the charge holding. Control can be performed up to the sum of the maximum film thickness value of the film 142a. This makes it possible to generally control the density of the lines of electric force generated by the charges stored in the charge holding film 142a, and to greatly reduce the variation in the memory effect of the memory elements.

Embodiment 16
In this embodiment, as shown in FIG. 29, the charge holding film 142 of the memory function body 162 is arranged with a substantially uniform film thickness and substantially parallel to the surface of the gate insulating film 114 (arrow 181). The gate electrode 117 has a shape (arrow 182) arranged substantially parallel to the side surface.
When a positive voltage is applied to the gate electrode 117, the electric lines of force in the memory function body 162 pass through the silicon nitride film 142 twice (portions indicated by the arrows 182 and 181) as indicated by an arrow 183. . When a negative voltage is applied to the gate electrode 117, the direction of the electric lines of force is on the opposite side. Here, the relative dielectric constant of the silicon nitride film 142 is about 6, and the relative dielectric constants of the silicon oxide films 141 and 143 are about 4. Therefore, the effective relative dielectric constant of the memory function body 162 in the direction of the electric force lines 183 is increased, and the potential difference at both ends of the electric lines of force is made smaller than when only the charge holding film indicated by the arrow 181 is present. be able to. That is, a large part of the voltage applied to the gate electrode 117 is used to strengthen the electric field in the offset region 171.

The charge is injected into the silicon nitride film 142 during the rewrite operation because the generated charge is drawn by the electric field in the offset region 171. Therefore, by including the charge holding film indicated by the arrow 182, the charge injected into the memory function body 162 during the rewrite operation increases, and the rewrite speed increases.
If the silicon oxide film 143 is also a silicon nitride film, that is, if the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 114, the upward charge of the silicon nitride film Movement becomes remarkable, and the holding characteristics deteriorate.

The charge holding film is more preferably formed of a high dielectric such as hafnium oxide having a very high relative dielectric constant instead of the silicon nitride film.
Further, the memory function body further includes an insulating film (a portion of the silicon oxide film 141 on the offset region 171) that separates the charge holding film substantially parallel to the surface of the gate insulating film and the channel region (or well region). preferable. With this insulating film, dissipation of charges accumulated in the charge holding film is suppressed, and the holding characteristics can be further improved.

The memory function body may further include an insulating film (a portion of the silicon oxide film 141 in contact with the gate electrode 117) that separates the gate electrode and the charge holding film extending in a direction substantially parallel to the side surface of the gate electrode. preferable. With this insulating film, it is possible to prevent electric charge from being injected from the gate electrode into the charge holding film and change the electrical characteristics, and to improve the reliability of the semiconductor memory device.
Further, as in the fifteenth embodiment, the film thickness of the insulating film under the charge holding film 142 (the portion of the silicon oxide film 141 on the offset region 171) is controlled to be constant, and is further disposed on the side surface of the gate electrode. It is preferable to control the thickness of the insulating film (the portion of the silicon oxide film 141 in contact with the gate electrode 117) to be constant. Thereby, the density of the lines of electric force generated by the charges stored in the charge holding film 142 can be generally controlled, and charge leakage can be prevented.

Embodiment 17
This embodiment relates to optimization of the distance between the gate electrode, the memory function body, and the source / drain region.
As shown in FIG. 30, A is the gate electrode length at the cut surface in the channel length direction, B is the distance between the source / drain regions (channel length), and C is the end of one memory function body to the other memory function body. Holds the charge in the other memory function body from the end of the film (the side away from the gate electrode) having the function of retaining the charge in one memory function body at the distance to the end of the channel, that is, the cut surface in the channel length direction The distance to the end of the film having the function of (a side away from the gate electrode) is shown.

First, it is preferable that B <C. An offset region 171 exists between a portion of the channel region below the gate electrode 117 and the source / drain regions 112 and 113. By B <C, the ease of inversion effectively varies in the entire offset region 171 due to the charges accumulated in the memory function bodies 161 and 162 (silicon nitride film 142). Therefore, the memory effect is increased, and in particular, the reading operation is speeded up.
Further, when the gate electrode 117 and the source / drain regions 112 and 113 are offset, that is, when A <B is established, the ease of inversion of the offset region when a voltage is applied to the gate electrode. It varies greatly depending on the amount of charge accumulated in the memory function body, and the memory effect increases and the short channel effect can be reduced. However, as long as the memory effect appears, it does not necessarily exist. Even in the absence of the offset region 171, if the impurity concentration of the source / drain regions 112 and 113 is sufficiently low, the memory effect can be exhibited in the memory function bodies 161 and 162 (silicon nitride film 142).
Therefore, it is most preferable that A <B <C.

Embodiment 18
As shown in FIG. 31, the semiconductor memory device of this embodiment has substantially the same configuration except that the semiconductor substrate in Embodiment 15 is an SOI substrate.
In this semiconductor memory device, a buried oxide film 183 is formed on a semiconductor substrate 181, and an SOI layer is further formed thereon. Diffusion regions 112 and 113 are formed in the SOI layer, and the other region is a body region 182.
This semiconductor memory device also has the same operational effects as the semiconductor memory device of the fifteenth embodiment. Furthermore, since the junction capacitance between the diffusion regions 112 and 113 and the body region 182 can be remarkably reduced, the device can be increased in speed and power consumption can be reduced.

Embodiment 19
In the semiconductor memory device of this embodiment, as shown in FIG. 32, a P-type high concentration region 191 is added adjacent to the channel side of the N-type source / drain regions 112 and 113 in the fifteenth embodiment. Except for the above, the configuration is substantially the same.
That is, the concentration of impurities (for example, boron) that gives P-type in the P-type high concentration region 191 is higher than the concentration of impurities that give P-type in the region 192. An appropriate P-type impurity concentration in the P-type high concentration region 191 is, for example, about 5 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . The P-type impurity concentration in the region 192 can be set to, for example, 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

  Thus, by providing the P-type high concentration region 191, the junction between the diffusion regions 112 and 113 and the semiconductor substrate 111 becomes steep immediately below the memory function bodies 161 and 162. For this reason, hot carriers are likely to be generated during writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the writing and erasing operations can be performed at high speed. Further, since the impurity concentration in the region 192 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current is large. Therefore, the reading speed is improved. Therefore, it is possible to obtain a semiconductor memory device having a low rewrite voltage, a high rewrite speed, and a high read speed.

  In FIG. 32, by providing the P-type high concentration region 191 in the vicinity of the source / drain region and under the memory function body (that is, not directly under the gate electrode), the threshold value of the entire transistor is remarkably increased. To do. The degree of this increase is significantly greater than when the P-type high concentration region 191 is directly below the gate electrode. When write charges (electrons when the transistor is an N-channel type) are accumulated in the memory function body, this difference becomes even larger. On the other hand, when sufficient erasing charges (holes when the transistor is an N channel type) are accumulated in the memory function body, the threshold value of the entire transistor is the impurity concentration of the channel region (region 192) under the gate electrode. Decreases to a determined threshold. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the P-type high concentration region 191, while the threshold value at the time of writing is greatly influenced. Therefore, by arranging the P-type high concentration region 191 under the memory function body and in the vicinity of the source / drain region, only the threshold value at the time of writing varies greatly, and the memory effect (at the time of writing and at the time of erasing). Can be significantly increased.

Embodiment 20
As shown in FIG. 33, in the semiconductor memory device of this embodiment, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 142) from the channel region or well region is the same as that of the fifteenth embodiment. The structure is substantially the same except that it is thinner than the thickness (T2) of the gate insulating film.
The gate insulating film 114 has a lower limit value for the thickness T2 due to a demand for withstand voltage during a memory rewrite operation. However, the thickness T1 of the insulating film can be made thinner than T2 regardless of the demand for withstand voltage. By making T1 thin, it becomes easy to inject charges into the memory function body, and it is possible to reduce the voltage of the write operation and the erase operation, or to speed up the write operation and the erase operation. Since the amount of charge induced in the channel region or the well region when the charge is accumulated in the film 142 increases, the memory effect can be increased.

Therefore, by setting T1 <T2, it is possible to reduce the voltage of the write operation and the erase operation or to speed up the write operation and the erase operation without further reducing the withstand voltage performance of the memory, and to further increase the memory effect. It becomes.
In addition, the thickness T1 of the insulating film can be maintained at a certain level of uniformity and film quality due to the manufacturing process, and is more than 0.8 nm, which is a limit at which the retention characteristics are not extremely deteriorated. preferable.

Embodiment 21
As shown in FIG. 34, in the semiconductor memory device of this embodiment, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 142) from the channel region or well region is the same as that of the fifteenth embodiment. The structure is substantially the same except that it is thicker than the thickness (T2) of the gate insulating film.
The gate insulating film 114 has an upper limit on the thickness T2 due to a request for preventing the short channel effect of the element. However, the thickness T1 of the insulating film can be made larger than T2 regardless of the requirement for preventing the short channel effect. By increasing the thickness of T1, it is possible to prevent the charge accumulated in the memory function body from being dissipated and to improve the retention characteristics of the memory.
Therefore, by setting T1> T2, the retention characteristic can be improved without deteriorating the short channel effect of the memory.
Note that the thickness T1 of the insulating film is preferably 20 nm or less in consideration of a decrease in rewriting speed.

Embodiment 22
A mobile phone which is a mobile electronic device in which the above-described semiconductor memory device is incorporated is shown in FIG.
This cellular phone mainly includes a control circuit 211, a battery 212, an RF (radio frequency) circuit 213, a display unit 214, an antenna 215, a signal line 216, a power line 217, and the like. The semiconductor memory device of the present invention is incorporated. Note that the control circuit 211 is preferably an integrated circuit in which elements having the same structure are also used as a memory circuit element and a logic circuit element as described in the tenth embodiment. Thereby, manufacture of an integrated circuit becomes easy and the manufacturing cost of a portable electronic device can be reduced especially.
In this way, by using a semiconductor memory device capable of storing 2 bits per transistor and easily miniaturized in a portable electronic device, the function and operation speed of the portable electronic device are improved, and the manufacturing cost is reduced. It becomes possible to reduce.

The semiconductor memory device of the present invention mainly includes a memory disposed across the boundary between the first conductivity type region, which is a diffusion region, the second conductivity type region, and the first and second conductivity type regions. It is composed of a functional body and an electrode provided via an insulating film, or mainly a gate insulating film, a gate electrode formed on the gate insulating film, and a memory formed on both sides of the gate electrode A functional unit, a source / drain region (diffusion region) disposed on the opposite side of the gate electrode of the memory functional unit, and a channel region disposed under the gate electrode.
This semiconductor memory device functions as a memory element that stores quaternary or higher information by storing binary or higher information in one charge retention film, and also has a variable resistance effect by the memory function body. As a result, the memory cell also functions as a memory cell having the functions of a selection transistor and a memory transistor.

The semiconductor device of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type well region formed in the semiconductor substrate.
The semiconductor substrate is not particularly limited as long as it is used in a semiconductor device. For example, a bulk substrate made of an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN. Is mentioned. In addition, as a semiconductor layer on the surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer on a glass or plastic substrate may be used. Among these, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or semiconductor layer has some amount of current flowing through it, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.

  An element isolation region is preferably formed on the semiconductor substrate or semiconductor layer, and further, elements such as transistors, capacitors, resistors, etc., a circuit using these elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multi-layer. It may be formed with a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and at least one first conductivity type (P-type or N-type) well region is preferably formed in the semiconductor substrate. . The impurity concentration in the semiconductor substrate and well region can be within the range known in the art. When an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, but a body region may be provided under the channel region.

  The gate insulating film or the insulating film is not particularly limited as long as it is usually used in a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, A single-layer film or a laminated film of a high dielectric film such as a tantalum oxide film or a hafnium oxide film can be used. Of these, a silicon oxide film is preferable. The gate insulating film is suitably about 1 to 20 nm, preferably about 1 to 6 nm, for example. The gate insulating film may be formed only directly under the gate electrode, or may be formed larger (wider) than the gate electrode.

  The gate electrode or electrode is formed on the gate insulating film in a shape usually used in a semiconductor device or a shape having a recess at the lower end. Note that a single gate electrode means a gate electrode that is formed as an integral shape without being separated by one or more conductive films. The gate electrode may have a sidewall insulating film on the sidewall. The gate electrode is not particularly limited as long as it is normally used in a semiconductor device, and conductive film, for example, polysilicon: metal such as copper and aluminum: refractory metal such as tungsten, titanium, and tantalum: Examples thereof include a single layer film or a laminated film such as silicide with a refractory metal. The gate electrode is suitably formed to a thickness of about 50 to 400 nm, for example. A channel region is formed under the gate electrode.

  The memory function body is configured to include at least a film or a region having a function of holding charge, storing and holding charge, trapping charge, or holding a charge polarization state. Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectrics such as hafnium oxide, zirconium oxide and tantalum oxide; zinc oxide; ferroelectric Body; metal and the like. The memory functional unit includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer; an insulator film including one or more conductors or semiconductor dots; Further, it can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. In particular, the silicon nitride film has a large hysteresis characteristic because there are many levels for trapping charges, and it has a long charge retention time, so there is no problem of charge leakage due to the occurrence of a leak path. In addition, it is preferable because it is a standard material used in LSI processes.

By using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability regarding memory holding can be improved. This is because the silicon nitride film is an insulator, so that even if charge leakage occurs in a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. In order to further improve the reliability, the insulating film having a function of holding charges is not necessarily in the form of a film, and it is preferable that insulators having a function of holding charges are present discretely in the insulating film. . Specifically, it is preferably dispersed in a dot shape in a material that does not easily retain electric charges, for example, silicon oxide.
In addition, by using an insulator film including a conductive film or a semiconductor layer as a memory function body, the amount of charge injected into the conductor or semiconductor can be freely controlled, so that there is an effect that multi-value is easily obtained.

Furthermore, by using an insulator film including one or more conductors or semiconductor dots as a memory function body, writing / erasing by direct tunneling of electric charge is facilitated, and there is an effect of reducing power consumption.
Further, as the memory function body, a ferroelectric film such as PZT or PLZT whose polarization direction is changed by an electric field may be used. In this case, charges are substantially generated on the surface of the ferroelectric film due to polarization, and the state is maintained in that state. Therefore, it is possible to obtain the same hysteresis characteristics as a film that supplies charges from outside the film having a memory function and traps charges, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since hysteresis characteristics can be obtained only by polarization of charges in the film, there is an effect that writing / erasing can be performed at high speed.
That is, the memory function body preferably further includes a region that makes it difficult to escape charges or a film that has a function that makes it difficult to escape charges. A silicon oxide film or the like can be cited as a material that makes it difficult to escape charges.

  The charge holding film included in the memory functional unit is formed on both sides of the gate electrode directly or via an insulating film, and directly on the semiconductor substrate (well region, body region or (Source / drain region or diffusion region). The charge retention films on both sides of the gate electrode are preferably formed so as to cover all or part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a recess at the lower end, the recess may be formed directly or via an insulating film so that the recess is completely embedded or partially embedded in the recess. Therefore, it is preferable that the memory function body covers only the side wall of the gate electrode and the gate electrode does not cover the memory function body as described above. In the case where a conductive film is used as the charge holding film, the charge holding film is disposed via an insulating film so as not to be in direct contact with the semiconductor substrate (well region, body region, source / drain region or diffusion region) or the gate electrode. It is preferable. For example, a laminated structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in the insulating film, a structure in which the conductive film is disposed in a part of the side wall insulating film formed on the side wall of the gate, etc. .

  The diffusion region or the source / drain region is disposed on the opposite side of the charge holding film as the diffusion region having a conductivity type opposite to that of the semiconductor substrate or well region. The junction between the source / drain region and the semiconductor substrate or memory function body is preferably a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. When an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the film thickness of the surface semiconductor layer, but approximately the same as the film thickness of the surface semiconductor layer. It is preferable to have the following junction depth.

  The source / drain region may be disposed so as to overlap the gate electrode end, may be disposed so as to coincide with the gate electrode end, or may be disposed offset with respect to the gate electrode end. May be. In particular, when offset is applied, the ease of inversion of the offset region under the charge retention film when a voltage is applied to the gate electrode varies greatly depending on the amount of charge accumulated in the memory function body, thereby increasing the memory effect. In addition, the short channel effect is reduced, which is preferable. However, if the offset is too large, the drive current between the source and the drain is remarkably reduced, so that the offset amount is larger than the thickness of the charge holding film in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the source to the nearer source / drain region is shorter. It is particularly important that at least a part of the charge storage region in the memory functional unit overlaps a part of the source / drain region which is a diffusion region. This is because the essence of the memory of the present invention is that the memory is rewritten by an electric field across the memory function body due to a voltage difference between the gate electrode and the source / drain region existing only on the side wall portion of the memory function body.

  A part of the source / drain region may be extended to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-described metals, refractory metals, and the like. Of these, polysilicon is preferable. This is because polysilicon has a very large impurity diffusion rate compared to a semiconductor substrate, so that it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate and to easily suppress the short channel effect. . In this case, it is preferable that a part of the source / drain region is arranged so as to sandwich at least a part of the memory function body together with the gate electrode.

The semiconductor memory device of the present invention can be formed by a normal semiconductor process, for example, by a method similar to the method of forming a single layer or stacked structure side wall spacer on the side wall of the gate electrode. Specifically, after forming a gate electrode or an electrode, a single layer including a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, etc. A method of forming a film or a laminated film and etching back under appropriate conditions to leave these films in the form of sidewall spacers; forming an insulating film or charge holding film and etching back under appropriate conditions to form sidewalls A method of forming a charge holding film or an insulating film, leaving it in a spacer form, and etching back in the same manner to leave it in a side wall spacer form; dispersing the particulate charge holding material in the insulating film material, A method of coating or depositing on a semiconductor substrate, etching back under appropriate conditions, and leaving an insulating film material in a sidewall spacer shape; after forming a gate electrode, forming the above single layer film or laminated film And patterning the with a mask. Further, before forming the gate electrode or electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, etc. are formed, and channel regions of these films are formed. And forming a gate electrode material film on the entire surface, and patterning the gate electrode material film in a shape larger than the opening.
The semiconductor memory device of the present invention can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.

1 is a schematic cross-sectional view and an equivalent circuit diagram of a main part of a semiconductor memory device (Embodiment 1) of the present invention. It is a schematic sectional drawing of the principal part which shows the deformation | transformation of the semiconductor memory device (Embodiment 1) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 2) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 3) of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the semiconductor memory device (Embodiment 4) of this invention. It is a circuit diagram for demonstrating the function of the electric charge holding film of the semiconductor memory device (Embodiment 4) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 5) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 6) of this invention. It is a schematic sectional drawing of the principal part for demonstrating the write-in operation | movement of the semiconductor memory device (Embodiment 6) of this invention. It is a schematic sectional drawing of the principal part for demonstrating the read-out operation | movement of the semiconductor memory device (Embodiment 6) of this invention. It is a schematic sectional drawing of the principal part for demonstrating the erase operation of the semiconductor memory device (Embodiment 6) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 7) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 8) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 9) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 10) of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the semiconductor memory device (Embodiment 10) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 11) of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the semiconductor memory device (Embodiment 11) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 12) of this invention. It is a schematic sectional drawing of the principal part which shows the semiconductor memory device (Embodiment 13) of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the semiconductor memory device (Embodiment 13) of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the semiconductor memory device (Embodiment 13) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 14) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 15) of this invention. It is an expansion schematic sectional drawing of the principal part of FIG. It is an expansion schematic sectional drawing of the principal part of FIG. 41 is a graph showing electrical characteristics of the semiconductor memory device (Embodiment 15) according to the present invention. It is a schematic sectional drawing of the principal part of a deformation | transformation of the semiconductor memory device (Embodiment 15) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 16) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 17) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 18) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 19) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 20) of this invention. It is a schematic sectional drawing of the principal part of the semiconductor memory device (Embodiment 21) of this invention. It is a schematic block diagram of the portable electronic device incorporating the semiconductor memory device of this invention. It is a schematic sectional drawing of the principal part which shows the conventional semiconductor memory device.

Explanation of symbols

1, 81, 111, 919 Semiconductor substrate 2, 14, 114, 904, 1902 Gate insulating film 3, 17, 117, 903 Gate electrode 4, 15, 16, 20, 21, 22, 32, 1904 Charge holding film 5, 1905 Source / drain region 6 Region where gate electrode is formed 7 High concentration impurity diffusion region 8 Low concentration impurity diffusion region 11 Well 12 First diffusion region 13 Second diffusion region 18, 41, 43, 44, 46, 54 , 141, 143, 9061, 9063 Silicon oxide film 19, 25 Gate sidewall insulating film 23, 24 Region where charge is accumulated or trapped 26, 27 Side wall 28, 29 N-type region 30, 42, 45, 47, 51, 53, 58, 142, 142a, 9062 Silicon nitride film 31 Element isolation region 48, 55, 481, 491, 06, 1906 Insulating film 49, 481, 491 Floating gate conductive film 52 Resist pattern 56 Resist pattern 57 Polysilicon film 71 Channel region not covered with gate electrode 72 Moving direction of hot hole 82 Body region 83 Embedded oxide film 112, 113, 920 Diffusion region 142 Charge holding region 161, 162, 162a, 605, 805, 906 Memory function body 171 Offset region 181, 192 region 182-183 Electric field line 191, 603, 803 P-type diffusion region 211 Control circuit 212 Battery 213 RF (Radio Frequency) circuit 214 Display unit 215 Antenna 216 Signal line 217 Power line 410 Inversion layer 601 Glass panel 602 Semiconductor layer 604, 804, 903 N-type diffusion region 607, 807 Electrode 6 08 Refractory metal silicide film 609a, 609b Wiring 610 Interlayer insulating film 612, 918 Contact plug 622, 1903 Word line 623, 914 Bit line 631 Element 900 SOI substrate 901 Channel area 902 Variable resistance area 911 Variable resistance 912 Select transistor 913 Rewrite word Line 915 Source line 916 Selected word line 917 Metal wiring 1901 Semiconductor substrate, well region provided in semiconductor substrate or semiconductor layer located on insulator 1902 Gate insulating film 1907 Terminal connecting bit line and source / drain region

Claims (29)

  A first conductivity type region formed in the semiconductor layer; a second conductivity type region formed in contact with the first conductivity type region in the semiconductor layer; and the first and second regions on the semiconductor layer. A memory function body disposed across a boundary between two conductivity type regions, and an electrode that is in contact with the memory function body and provided on the first conductivity type region with an insulating film interposed therebetween Semiconductor memory device.   A first conductivity type region formed in the semiconductor layer; two second conductivity type regions formed on both sides of the first conductivity type region in the semiconductor layer; and the first conductivity type on the semiconductor layer. And two memory function bodies respectively disposed across the boundary of the second conductivity type region, an electrode in contact with each of the memory function bodies and provided on the first conductivity type region via an insulating film, A semiconductor memory device comprising:   3. The semiconductor memory device according to claim 2, wherein two or more bits of information are stored by accumulating electric charges independently in each of the two memory function bodies.   A channel region formed in the semiconductor layer, a variable resistance region provided on both sides of the channel region, two diffusion regions provided on both sides of the channel region via the variable resistance region, and the channel region A gate electrode provided through a gate insulating film, and two memory function bodies arranged on both sides of the gate electrode so as to straddle a variable resistance region and a part of a diffusion region. Semiconductor memory device.   5. The semiconductor memory device according to claim 4, wherein the variable resistance region is set to a conductivity type different from that of the diffusion region.   The semiconductor memory device according to claim 4, wherein the information stored in the other memory function body is read by forming a pinch-off point in a region close to one memory function body in the channel region.   A gate electrode formed on the semiconductor layer through a gate insulating film; a channel region disposed under the gate electrode; a diffusion region disposed on both sides of the channel region and having a conductivity type opposite to the channel region; A semiconductor memory device comprising: a memory function body for holding electric charges formed on both sides of the gate electrode and overlapping the diffusion region. A semiconductor substrate, a semiconductor layer disposed on a well region or an insulator provided in the semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate or the semiconductor layer disposed on the well region or insulator provided in the semiconductor substrate The gate insulating film formed, a single gate electrode formed on the gate insulating film, a channel region disposed immediately below the gate electrode, two diffusion regions disposed on both sides of the channel region, Having one or more memory cells made of sidewall insulating films formed on both sides of the gate electrode and overlapping the diffusion region;
The semiconductor memory device, wherein the sidewall insulating film has a function of holding electric charge.   The sidewall insulating film is configured to deplete at least a part of the diffusion region under the sidewall insulating film or invert the conductivity type corresponding to the amount of charge held in the sidewall insulating film. The semiconductor memory device according to claim 8.   The semiconductor memory device according to any one of claims 4 to 9, wherein four memory values are stored per memory cell by two memory function bodies.   11. The structure according to claim 4, wherein a part of the diffusion region is extended to a position higher than the surface of the channel region, and at least a part of the memory function body is sandwiched between the gate electrode and a part of the diffusion region. The semiconductor memory device according to any one of the above.   11. The electrode wiring terminal is connected to the diffusion region, and at least a part of the memory function body is sandwiched between the gate electrode and a part of the electrode wiring terminal connected to the diffusion region. The semiconductor memory device according to any one of the above.   The semiconductor memory device according to claim 4, wherein the diffusion region is arranged offset with respect to the gate electrode end.   The semiconductor memory device according to claim 4, wherein the diffusion region overlaps with the gate electrode, or an end portion of the diffusion region is arranged to coincide with the gate electrode end.   The diffusion region is made of an N-type semiconductor, and one diffusion region is set to a reference voltage, and the other diffusion region and the gate electrode are set to a voltage higher than the reference voltage, whereby electrons can be injected into the memory function body. 14. The semiconductor memory device according to any one of 14.   The diffusion region is made of an N-type semiconductor. One diffusion region is set to a reference voltage, the other diffusion region is set to a voltage higher than the reference voltage, and the gate electrode is set to a voltage lower than the reference voltage. The semiconductor memory device according to claim 4, which can be implanted.   The diffusion region is made of a P-type semiconductor, and one diffusion region is set to a reference voltage, and the other diffusion region and the gate electrode are set to a voltage lower than the reference voltage, whereby holes can be injected into the memory function body. 14. The semiconductor memory device according to any one of 14.   The diffusion region is made of a P-type semiconductor, and one diffusion region is set to a reference voltage, the other diffusion region is set to a voltage lower than the reference voltage, and the gate electrode is set to a voltage higher than the reference voltage. The semiconductor memory device according to claim 4, which can be implanted. A semiconductor substrate;
A first conductivity type well region formed in the semiconductor substrate;
A gate insulating film formed on the well region;
A plurality of word lines formed on the gate insulating film;
A plurality of second conductivity type diffusion regions respectively formed on both sides of the word line;
At least on a part of the diffusion region, or across a part of the diffusion region from a part of the well region to the word line, the well region, and the diffusion region on both sides of the plurality of word lines. A charge holding film formed directly or via an insulating film and having a function of accumulating or trapping charges;
A plurality of bit lines connected to the diffusion region and extending in a direction intersecting the word lines;
A word line has a recess at its lower end, and at least a portion of the charge retention film is embedded in the recess directly or via an insulating film.   20. The semiconductor memory device according to claim 19, wherein the semiconductor substrate is an SOI substrate having a surface semiconductor layer, and a first conductivity type well region is formed as a body region in the surface semiconductor layer.   21. The semiconductor memory device according to claim 19, wherein the charge retention film is in contact with the diffusion region and / or the well region or the body region through the insulating film in the vicinity of the end of the word line.   The semiconductor memory device according to claim 19, wherein the word line has a side wall insulating film on a side wall, and a part of the side wall insulating film is formed as a charge holding film.   The part of the diffusion region is extended to a position higher than the lower surface of the gate insulating film, and at least a part of the charge holding film is sandwiched between the word line and a part of the diffusion region. The semiconductor memory device according to any one of the above.   The memory functional body or the sidewall insulating film is a film having a function of accumulating or trapping charges or a function of maintaining a charge polarization state, and includes an insulator film including a silicon nitride film; a conductor film or a semiconductor layer inside Insulator film; insulator film containing one or more dots made of a conductor or semiconductor; or a single layer or a laminate of an insulator film including a ferroelectric film in which the internal charge is polarized by an electric field and maintained in that state 24. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a film. Forming a gate insulating film and a gate electrode on a semiconductor substrate;
An insulating film having a function of accumulating or trapping charges is deposited on the entire surface of the obtained substrate,
23. The method of manufacturing a semiconductor memory device according to claim 22, further comprising: selectively etching the insulating film to form a side wall insulating film on the side wall of the gate electrode. One gate electrode formed on a P-type semiconductor substrate, a P-type well region formed in the semiconductor substrate or a P-type semiconductor layer disposed on an insulator, and disposed below the one gate electrode For a semiconductor memory device comprising a channel region, two N-type source / drain regions located on both sides of the channel region, and a memory functional unit existing in the vicinity of the source / drain region,
The semiconductor layer formed on the semiconductor substrate, the well region formed in the semiconductor substrate, or the insulator, with one source / drain region set as a reference voltage and the gate electrode set to a voltage lower than the reference voltage Is set to a voltage higher than the reference voltage, and the other source / drain region is set to a voltage higher than the semiconductor layer, the well region formed in the semiconductor substrate, or the semiconductor layer formed on the insulator. Then, a hole is injected into the memory function body, thereby operating the semiconductor memory device. One gate electrode formed on an N-type semiconductor substrate, an N-type well region formed in the semiconductor substrate, or an N-type semiconductor layer disposed on an insulator, and a channel region below the one gate electrode, For a semiconductor memory device comprising two P-type source / drain regions located on both sides of the channel region and a memory functional unit existing in the vicinity of the source / drain region,
The semiconductor layer disposed on the semiconductor substrate, the well region or the insulator formed in the semiconductor substrate, with one source / drain region set as a reference voltage and the gate electrode set to a voltage higher than the reference voltage Is set to a voltage lower than a reference voltage, and the other source / drain region is set to a voltage lower than that of the semiconductor substrate, the well region formed in the semiconductor substrate, or the semiconductor layer disposed on the insulator. Thus, an operation method of a semiconductor memory device, wherein electrons are injected into the memory function body.   The memory function body or the sidewall insulating film is a film having a function of accumulating or trapping charges or a function of maintaining a charge polarization state, and includes an insulator film including a silicon nitride film; a conductor film or a semiconductor layer inside Insulator film; insulator film containing one or more dots made of a conductor or semiconductor; or a single layer or a laminate of an insulator film including a ferroelectric film in which the internal charge is polarized by an electric field and maintained in that state 28. The method of operating a semiconductor memory device according to claim 26 or 27, wherein the semiconductor memory device is a film.   A portable electronic apparatus comprising the semiconductor memory device according to claim 1.

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