JP2004343015A - Semiconductor memory and its operating method, and portable electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory, e.g. flash memory, which can be reduced in size easily. <P>SOLUTION: A p-type well region has a memory isolation region 1108 and an active region 1110 on the surface. A memory element capable of storing 2 bits is formed in each active region 1102. A word line 1104 serves as the gate electrode of a memory element on the same row. Source/drain diffusion region 1107 of a memory element on the same row is electrically connected in common with a bit line 1132 through a contact. With regard to two adjacent bit lines 1132, one bit line 1132 is connected electrically with one source/drain diffusion region 1107 on the same row while the other bit line 1132 is connected electrically with the other source/drain diffusion region 1107 on the same row. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００９４】
この表１から明らかなように、本実施の形態のメモリセルアレイは、ランダムアクセス（１ビット毎の読出し及び書換え動作）が可能である。このため、一括消去しなければならないデバイスに比較し、アクセス効率を上げることが可能である。また、メモリ状態の一時記憶、一括消去、書き込みといったシーケンスも不要となるため制御回路が簡単になるという効果がある。
【００９５】
上記読出し動作時によれば、あるメモリセルの２ビットの記憶を連続して読み出そうとする場合（例えば、メモリセルＭ２２のメモリ機能体ｍ１，ｍ２を連続して読み出す場合）、近傍のビット線ＢＬ１〜ＢＬ４の電位を全て反転しなければならないため、効率が悪い。そのため、後述のように、アドレスデコーダ回路などの工夫を行い、左右のメモリ機能体ｍ１，ｍ２のアクセスのためのアドレスを離すなどの対策を行うことにより連続して交互に読み出す状態を回避することが好ましい。
【００９６】
上記実施の形態では、メモリ素子のゲート電極はワード線２１０４の一部であったが、ワード線の一部でなくてもよい。つまり、上記メモリ素子のゲート電極はワード線と別体であってもよい。この場合、上記ワード線は、同一行のメモリ素子のゲート電極を接続する。
【００９７】
（実施の形態３）
本発明の実施の形態３を、図８及び図９を用いて説明する。
【００９８】
図８は本実施の形態のメモリセルアレイの概略平面図であり、図９は上記メモリセルアレイの第１層メタル配線の配置を説明する図である。ただし、図８においては、上部配線構造（ビット線及びコンタクト）は簡略のため結線図として表現している。また、図８及び図９では、３行×３列のメモリセルアレイを示しているが、行数及び列数は任意である。
【００９９】
本実施の形態のメモリセルアレイが上記実施の形態２のメモリセルアレイと異なるのは、ソース／ドレイン拡散領域３１０７とビット線３１３２（ＢＬ１，ＢＬ２，ＢＬ３，ＢＬ４）との接続パターンであり、以下で説明する。
【０１００】
上記メモリセルアレイでは、ウェル領域の表面が、素子分離領域３１０８と、帯状の複数の活性領域３１１０（Ａ１，Ａ２，Ａ３）とに区分けされている。上記ビット線ＢＬ１とビット線ＢＬ２との間に位置する活性領域Ａ１では、隣り合う２つのソース／ドレイン拡散領域３１０７の一方はビット線ＢＬ１に接続され、その２つのソース／ドレイン拡散領域３１０７の他方はビット線ＢＬ２に接続されている。また、上記ビット線ＢＬ２とビット線ＢＬ３との間に位置する活性領域Ａ２では、隣り合う２つのソース／ドレイン拡散領域３１０７の一方はビット線ＢＬ２に接続され、その２つのソース／ドレイン拡散領域３１０７の他方はビット線ＢＬ３に接続されている。そして、上記ビット線ＢＬ３とビット線ＢＬ４との間に位置する活性領域Ａ３では、隣り合う２つのソース／ドレイン拡散領域３１０７の一方はビット線ＢＬ３に接続され、その２つのソース／ドレイン拡散領域３１０７の他方はビット線ＢＬ４に接続されている。
【０１０１】
また、同一行で隣り合う２つのソース／ドレイン拡散領域３１０７は、楕円柱形状のコンタクトを介して１つのビット線３１３２（ＢＬ１，ＢＬ２，ＢＬ３，ＢＬ４）に電気的に接続されている。具体的には、上記ワード線ＷＬ１よりも図中上側の領域では、活性領域Ａ１に属するソース／ドレイン拡散領域３１０７と、活性領域Ａ２に属するソース／ドレイン拡散領域３１０７とが、楕円柱形状のコンタクト３１３１（図９参照）を介してビット線ＢＬ２に電気的に共通に接続されている。そして、上記ワード線ＷＬ１とワード線ＷＬ２との間では、活性領域Ａ２に属するソース／ドレイン拡散領域３１０７と、活性領域Ａ３に属するソース／ドレイン拡散領域３１０７とが、楕円柱形状のコンタクト３１３１を介してビット線ＢＬ３に電気的に共通に接続されている。また、上記ワード線ＷＬ２とワード線ＷＬ３との間では、活性領域Ａ１に属するソース／ドレイン拡散領域３１０７と、活性領域Ａ２に属するソース／ドレイン拡散領域３１０７とが、楕円柱形状のコンタクト３１３１を介してビット線ＢＬ２に電気的に共通に接続されている。そして、上記ワード線ＷＬ３よりも図中下側の領域では、実線の四角で部分Ｃ８において、活性領域Ａ２に属するソース／ドレイン拡散領域３１０７と、活性領域Ａ３に属するソース／ドレイン拡散領域３１０７とが、楕円柱形状のコンタクト３１３１を介してビット線ＢＬ３に電気的に共通に接続されている。
【０１０２】
言い換えると、例えば、上記ワード線ＷＬ１とワード線ＷＬ２との間において活性領域Ａ１に属するソース／ドレイン拡散領域３１０７がソース領域である場合、ワード線ＷＬ１とワード線ＷＬ２との間において活性領域Ａ２に属するソース／ドレイン拡散領域３１０７もソース領域となる。
【０１０３】
本実施の形態のメモリセルアレイによれば、図８中の左右方向（行方向）のピッチを小さくしても第１層メタル配線間のマージンを大きくとることができる。したがって、更に大幅にメモリセルの面積を縮小して製造コストを削減することができる。
【０１０４】
本実施の形態のメモリセルアレイの回路図は、図４と同じとなる。したがって、動作方法も上記実施の形態２のメモリセルアレイと同様にしてよい。
【０１０５】
本デバイスの構造について、別の言い方で述べると、半導体基板上に素子分離領域と活性領域がライン状に交互に形成され、素子分離領域と活性領域とに対して交差するようにワード線が形成されている。そして、上記活性領域において、ワード線と交差する領域がチャネル領域となり、ワード線が交差していない領域がソース／ドレイン拡散領域となっている。そして、上記素子分離領域を挟んで同一行で隣り合う２つのソースドレイン領域を、１つのコンタクトを介して１本のビット線に電気的に接続している。また、同一列の３つのチャネル領域に注目した場合、チャネル領域間の一方の素子分離領域の両側の２つのソース／ドレイン拡散領域は１つのコンタクで電気的に接続され、チャネル領域間の他方の素子分離領域の両側の２つのソース／ドレイン拡散領域は電気的に接続されていない構造と呼ぶことができる。
【０１０６】
上記実施の形態では、メモリ素子のゲート電極はワード線３１０４の一部であったが、ワード線の一部でなくてもよい。つまり、上記メモリ素子のゲート電極はワード線と別体であってもよい。この場合、上記ワード線は、同一行のメモリ素子のゲート電極を接続する。
【０１０７】
（実施の形態４）
本実施の形態のメモリセルアレイの製造方法を、図１０〜図１３を用いて説明する。
【０１０８】
図１０に、本実施の形態４メモリセルアレイのメモリセルの形成工程時の半導体基板を上方から見た概略図を示し、図１１に、上記メモリセルアレイの概略断面図を示す。
【０１０９】
以下、図１０及び図１１を用いて、上記メモリセルアレイのメモリセルの形成工程について説明する。
【０１１０】
まず、図１０に示すように、例えばｐ型で比抵抗が数Ωｃｍ程度の単結晶シリコンからなる半導体基板４１０１（図１１参照）に、素子分離領域の一例としてのトレンチ素子分離（溝型素子分離）４１０８を形成した後、ｐ型ウエル４１０２（図１１参照）を形成する。上記ｐ型ウエル４１０２は、トレンチ素子分離４１０８（溝型素子分離）で分離されている。
【０１１１】
上記トレンチ素子分離４１０８は、半導体基板をドライエッチングして溝を形成した後、この溝の内部を含む半導体基板上にＣＶＤ（化学的気相成長）法でシリコン酸化膜を堆積する。続いて、上記シリコン酸化膜を化学的機械研磨（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ；ＣＭＰ）法で研磨して溝の内部のみにシリコン酸化膜を残すことにより形成する。
【０１１２】
上記ｐ型ウエル１０１は、半導体基板にｐ型不純物、例えばＢ（ボロン）のイオン注入を行った後、アニールを行い不純物を熱拡散させることにより形成する。
【０１１３】
次に、上記半導体基板の表面を洗浄した後、酸化工程を行って膜厚１〜２０ｎｍ程度のゲート酸化膜（図示せず）を半導体基板上に形成して、ＣＶＤ法によって膜厚５０〜４００ｎｍ程度のポリシリコン膜をそのゲート酸化膜上に形成する。
【０１１４】
次に、上記ポリシリコン膜及びゲート酸化膜にに対してパターニングを行って、ゲート電極として機能するワード線４１０４（ＷＬ１，ＷＬ２，ＷＬ３）と、ゲート絶縁膜４１０３（図１１参照）とを形成する。上記パターニングは、ポリシリコン膜上に形成したフォトレジスト膜をマスクとして用いて行う。
【０１１５】
次に、上記ワード線４１０４においてゲート電極として機能する部分の上面及び側面を覆う膜厚０．８〜２００ｎｍのシリコン窒化膜４１０９（図１１参照）を形成する。このシリコン窒化膜４１０９においてワード線４１０４の両側の部分がメモリ機能体となる。
【０１１６】
次に、上記ワード線４１０４の両側のｐ型ウエル４１０２にソース／ドレイン拡散領域の一例としての拡散領域４１０７（図１１参照）を形成することにより、メモリセルを形成する。
【０１１７】
上記拡散領域４１０７は、ｎ型半導体領域であって、ｐ型ウエル４１０２にｎ型不純物、例えばＰ（リン）をイオン注入して形成する。
【０１１８】
図１２に、本実施の形態のメモリセルアレイの他の概略断面図を示し、図１３に、上記メモリセルアレイのメタル配線の配置を説明するための図を示す。
【０１１９】
以下、図１１〜図１３を用いて、上記メモリセルの形成後の工程である層間絶縁膜工程、コンタクト工程及び残りの工程について説明する。
【０１２０】
まず、図１１に示すように、ＣＶＤ法により、膜厚２０〜１００ｎｍ程度のシリコン酸化膜（図示せず）及び膜厚７０〜２００ｎｍのシリコン窒化膜４２０１を全面に堆積し、更に、層間絶縁膜４１４１を形成するための膜厚２００〜７００ｎｍシリコン酸化膜を全面に堆積する。上記シリコン窒化膜は、この後のコンタクトエッチの際にエッチングストッパーとして用いる。
【０１２１】
次に、上記シリコン酸化膜をＣＭＰ法で研磨してその表面の平坦化を行う。
【０１２２】
次に、表面が平坦化されたシリコン酸化膜上にフォトレジスト膜を形成した後、このフォトレジスト膜をマスクにして、シリコン酸化膜に異方性エッチングでコンタクトホール４２０２を形成する。このとき、上記異方性エッチングは、シリコン酸化膜のエッチングレートがシリコン窒化膜のエッチングレートに比べて速い条件で行う。また、上記コンタクトホール４２０２間には、シリコン酸化膜より成る層間絶縁膜４１４１が形成される。更に、上記シリコン窒化膜とシリコン酸化膜とのエッチングを行う。
【０１２３】
次に、上記コンタクホール４２０２内をタングステンで満たすことにより、タングステンから成る楕円柱形状のコンタクト４１３１を形成する。
【０１２４】
上記コンタクト４１３１は、例えばコンタクトホール４２０２内部におけるシリコン酸化膜に、タングステンをＣＶＤ法で堆積した後、タングステンの上部をＣＭＰ法（またはエッチバック法）で除去して、タングステンをコンタクトホール４２０２内部のみに残すことにより形成する。
【０１２５】
次に、上記コンタクト４１３１及び層間絶縁膜４１４１上にメタル膜を形成する。
【０１２６】
上記メタル配線は、例えば、スパッタ法で、合計の膜厚６００ｎｍ程度、チタンナイトライド膜／アルミ銅合金膜／チタンナイトライド膜を順次製膜で形成する。
【０１２７】
最後に、上記メタル膜に対してフォトリソグラフィ及びメタルエッチングを行うことにより、図１２及び図１３に示すようなビット線４１３２（ＢＬ１，ＢＬ２，ＢＬ３，ＢＬ４）を形成する。
【０１２８】
上記各拡散領域４１０７（ｎ型半導体領域）と各ビット線４１３２とを電気的に接続する際には、以下の規則に従って配線する。なお、以下では、上記ワード線４１０４が延びる方向（図中の左右方向）と平行なものを行と呼び、ビット線４１３２が延びる方向（図中の上下方向）と平行なものを列と呼ぶ。
【０１２９】
ある１列の複数の拡散領域４１０７に注目した場合、複数の拡散領域４１０７は近傍の１つのビット線４１３２に対して２個ごとに接続されている。この際、上記１つのビット線４１３２は１行おきに拡散領域４１０７に接続している。そして、上記１つのビット線４１３２に隣り合う他のビット線４１３２は、その１つのビット線４１３２が拡散領域４１０７に接続していない行において、拡散領域４１０７に接続している。つまり、上記１つのビット線４１３２が拡散領域４１０７に接続する行と、上記他のビット線４１３２が拡散領域４１０７に接続する行とは１行ずれている。言い換えると、上記１つのビット線４１３２と、上記他のビット線４１３２とは、同一行の拡散領域４１０７に接続していない。
【０１３０】
また、ある隣り合う２列の複数の拡散領域４１０７に注目した場合、同一行で隣り合う２つの拡散領域４１０７が、一行おきに、１つのコンタクト４１３１を介してその２列間の１つのビット線４１３２に電気的に接続している。
【０１３１】
このように接続することで、隣り合う２つのビット線４１３４と１本のワード線４１０４とを選んだ場合に、誤って２つ以上のメモリセルが選択されることがなく、メモリセルを個別に選択でき、ランダムアクセスが可能となる。
【０１３２】
また、上述したような規則に従って配線を有する構造では、ゲートと素子分離が直線に近い形のため、製造しやすいため、歩留まりがよい。
【０１３３】
上記実施の形態では、シリコン窒化膜４１０９の一部でメモリ機能体を形成していたが、これにメモリ機能体は限られない。例えば、上記ワード線４１０４の側壁酸化を行って、この側壁を覆うシリコン酸化膜を形成した後、ＣＶＤ法により、膜厚５〜２００ｎｍ程度のシリコン窒化膜と膜厚５〜２００ｎｍのシリコン酸化膜とを順次全面に堆積し、エッチバック法により、ワード線４１０４の側壁にサイドウォールスペーサ形状のメモリ機能体を形成してもよい。このメモリ機能体の一例としては、図１７に示すようなものがある。
【０１３４】
また、１本のビット線４１３２と２つの拡散領域４１０７との電気的な接続は図１４に示すようなものでもよい。つまり、１本のビット線４１３２を、コンタク４２３１及び楕円板形状の導電体４３３１を介して２つの拡散領域４１０７に電気的に接続してもよい。
【０１３５】
上記実施の形態では、メモリ素子のゲート電極はワード線４１０４の一部であったが、ワード線の一部でなくてもよい。つまり、上記メモリ素子のゲート電極はワード線と別体であってもよい。この場合、上記ワード線は、同一行のメモリ素子のゲート電極を接続する。
【０１３６】
（実施の形態５）
本実施の形態５では、図１４のメモリセルアレイの具体的な製造方法について説明する。本実施の形態５のメモリセルアレイは、高選択比の条件（シリコン酸化膜のエッチングレートがシリコン窒化膜のエッチングレートに比べて速い条件）を持つエッチング装置が使用できない場合において製造される。
【０１３７】
上記メモリセルアレイの製造方法では、以下の様にマスクを１枚追加することにより、上記実施の形態４と同様に専有面積の少ない高密度セルを製造する。
【０１３８】
すなわち、上記実施の形態４の製造方法と同様にしてメモリセルの形成工程までを行う。その後、ＣＶＤを用いて窒化シリコンの製膜を行う。製膜した窒化シリコンにパターニングを行い窓を空けた後、タングステン・シリサイドをデポしパターニングを行い、タングステン・シリサイドによるローカル配線を行う。その後、メタル工程でビット線を形成する。
【０１３９】
本実施の形態の製造方法では、上記実施の形態４に比較して、マスク枚数が増加するが、高選択比の条件（シリコン酸化膜のエッチングレートがシリコン窒化膜のエッチングレートに比べて速い条件）を持つエッチング装置が使用できない場合でも、同程度の高密度メモリセルを形成することが可能である。
【０１４０】
タングステン・シリサイドによるローカル配線以外にもポリシリコン配線を用いることもできる。また、本実施の形態では、ポリシリコン配線を行った後、シリサイド化する際に、ローカル配線を行うという方法も行える。特にシリサイド化では、自己整合的なプロセスであるため、高融点金属のドライエッチングが、不要になり、プロセスが簡略化できるメリットがある。また、ポリシリコン、チタン、チタン・シリサイド、コバルト・シリサイド等のシリサイド配線を用いてもよい。
【０１４１】
本実施の形態の製造方法でも、通常のロジックトランジスタと同様の工程で、ゲート電極までは製造することが可能であるため、信頼性のある製造方法で製造できるため歩留まりが向上する。また、メモリロジック混載プロセスを容易に実現できる。また、本実施例では実質的にメタル配線１層でメモリを製造することができるため、歩留まりが向上する。
【０１４２】
さらに、本実施の形態の説明では、メモリ機能体のシリコン窒化膜とローカル配線とを形成する際の保護膜は別の膜であったが、工程的に膜厚の整合性がある場合は、シリコン窒化膜とローカル配線との形成に１つの保護膜を兼用しても構わない。この場合、ゲート電極形成後のエッチバックの際に、レジストマスクでパターニングを行えば、サイドウオールと保護パターンが同時に形成できる。このようにすることによりさらなる工程の簡略化を行うことが可能である。
【０１４３】
本実施の形態でも上記実施の形態４でも、拡散領域とビット線とを電気的に接続する配線材料は、配線抵抗を考えた場合、構造が似ていることからほぼ等しいため、ばらつきがあまりない。その結果、センスアンプが比較的簡単に設計できるメリットがある。
【０１４４】
本実施の形態では、メモリ機能体をシリコン窒化膜と絶縁膜で作ったいわゆるＯＮＯ（Ｏｘｉｄｅ Ｎｉｔｒｉｄｅ Ｏｘｉｄｅ）膜で説明してきたが、メモリ機能体は、例えば電荷の蓄積等によって可変抵抗のように抵抗を変化させることができる膜であれば、何でも良い。例えば、フローティングゲートやシリコンドット膜の様な電荷を蓄積することのできる膜を形成することでも本発明を実施できることは、言うまでもない。
【０１４５】
（実施の形態６）
図１５に、本発明の実施の形態６の半導体記憶装置のブロック図を示す。
【０１４６】
上記半導体記憶装置は、メモリセルアレイ６３０１と、アクセス対象のメモリセルを特定するためのカラムアドレスバッファ６３０２と、ロウアドレスバッファ６３０３と、カラムデコーダの一例としてのカラムアドレスデコーダ６３０４と、ロウデコーダの一例としてのロウアドレスデコーダ６３０５と、センスアンプの一例としてのセンスアンプ６３０６と、制御回路６３０７とを備えている。
【０１４７】
上記制御回路６３０７は、メモリセルアレイ６３０１、カラムアドレスバッファ６３０２、ロウアドレスバッファ６３０３、カラムアドレスデコーダ６３０４、ロウアドレスデコーダ６３０５及びセンスアンプ６３０６を制御している。
【０１４８】
上記メモリセルアレイ６３０１として上記実施の形態１〜５のいずれかのメモリセルアレイを用いている。したがって、記憶容量の大きくすることができると共に、製造コストを低減することができる。
【０１４９】
ところで、上記のような半導体記憶装置を設計する際に、読み出し動作の効率を考えると、上記実施の形態２で述べたように、あるメモリセルの２ビットの記憶を連続して読み出そうとするのは効率が悪い。なぜなら、上記メモリセルの２ビット情報を連続して読み出そうとすれば、読み出し電流の向きを反対にする（ソースとドレインを入れ替える）必要があり、近傍のビット線の電位を全て反転しなければならないからである。それゆえ、あるメモリセルに記憶される２ビットのアドレスは、互いに離しておくのが好ましい。例えば、同一のワード線に属し互いに隣接するメモリセルの記憶ビットの一方を連続したアドレスにしておき、同一メモリセル内の記憶ビットの一方と他方のアドレスは離しておけばよい。
【０１５０】
（実施の形態７）
これまで説明してきたメモリセルアレイを、液晶ドライバに組み込むことが可能である。本発明のプロセスは、液晶ドライバの製造工程と適合性が有り、従来までは別置きであったメモリを液晶ドライバ内部に組み込むことが可能である。したがって、メモリ機能付きの液晶ドライバを容易に低コストで製造が可能である。
【０１５１】
このメモリを用いて画像の調整の値（γ値）等を、記憶することにより、多機能な液晶ドライバが実現できる。
【０１５２】
（実施の形態８）
図１６に、携帯電子機器のブロック図を示す。
【０１５３】
上記携帯電子機器は、中央演算装置８４０１、メモリ部８４０２、電源８４０３、入出力部８４０４及び画像出力部８４０５を備えている。上記メモリ部８４０２は、上記実施の形態１〜５のいずれかのメモリセルアレイを含んでいる。
【０１５４】
上記メモリ部８４０２には、メインメモリの機能の他に、書き換え可能なファームウェア記憶装置（ハードウェアの基本的なシーケンスなどを記憶する装置）としての機能、システムの設定を記憶する記憶装置としての機能を持たせることができる。
【０１５５】
上記構成の携帯電子機器によれば、上記メモリ部８４０２が上記実施の形態１〜５のいずれかのメモリセルアレイを含んでいるので、高集積化が容易であり、製造コストを削減することができる。
【０１５６】
また、上記中央演算装置１４０１などとメモリ部１４０２とを１つのチップ上に混載するのが容易であるため、更に製造コストを削減することもできる。
【０１５７】
本実施の形態の携帯電子機器の具体例としては、携帯電話、電子手帳、携帯ゲーム機器などがある。
【０１５８】
（実施の形態９）
図１７は、本発明の半導体記憶装置に使用されるメモリ素子の一例の断面構造を示す図である。
【０１５９】
上記メモリ素子は、半導体基板１０１の表面に形成されたｐ型ウェル領域１０２上に形成されている。上記ｐ型ウェル領域１０２上にゲート絶縁膜１０３を介してゲート電極１０４が形成されている。上記ゲート電極１０４の上面及び側面は、電荷を保持するトラップ準位を有して電荷保持膜となるシリコン窒化膜１０９で覆われている。このシリコン窒化膜１０９において、ゲート電極１０４の側方に位置する部分がメモリ機能体１０５ａ，１０５ｂとして機能する。すなわち、上記メモリ機能体１０５ａ，１０５ｂが、書換え動作により実際に電荷を蓄積する。
【０１６０】
また、上記ｐ型ウェル１０２の表面に形成された第１，第２の拡散領域１０７ａ，１０７ｂは、それぞれソース領域またはドレイン領域として機能し、オフセット構造を有している。すなわち、上記第１，第２の拡散領域１０７ａ，１０７ｂはゲート電極下領域１２１には存在せず、電荷保持部（メモリ機能体１０５ａ，１０５ｂ）下のオフセット領域１２０がチャネル領域１２２の一部を構成している。
【０１６１】
図１８は、上記メモリ素子の変形例を示す図である。なお、図１８において、図１７に示す構成部と同一構成部は、図１６における構成部と同一参照番号を付して説明を省略する。
【０１６２】
上記メモリ素子が、図１７のメモリ素子と異なる点は、シリコン窒化膜１０９の代わりに第１，第２のメモリ機能体１３１ａ，１３１ｂを用いている点である。図１７に示すように、上記第１，第２のメモリ機能体１３１ａ，１３１ｂは、図中左右方向（ゲート長方向）においてゲート電極１０４を挟むように配置されている。つまり、上記第１のメモリ機能体１３１ａはゲート電極１０４の一方の側方に配置され、第２のメモリ機能体１３１ｂはゲート電極１０４の他方の側方に配置されている。また、上記第１，第２のメモリ機能体１３１ａ，１３１ｂは、シリコン窒化膜１１３と、このシリコン窒化膜１１３を挟むシリコン酸化膜１１１，１１２とから成る構造を有している。このように、上記シリコン窒化膜１１３がシリコン酸化膜１１１，１１２で挟まれた構造とすることにより、書換え動作時の電荷注入効率が高くなり、より高速な動作が可能となる。
【０１６３】
なお、図１８において、シリコン窒化膜１１３を強誘電体で置き換えてもよい。更には、図１７において、シリコン窒化膜１０９の部分１０５ａ，１０５ｂを、ナノメートルサイズの導電体または半導体からなる微粒子が内部に散点状に分布する絶縁膜に置き換えてもよい。このとき、上記微粒子が１ｎｍ未満であると、量子効果が大きすぎるためにドットに電荷がトンネルするのが困難になり、１０ｎｍを超えると室温では顕著な量子効果が現れなくなる。したがって、上記微粒子の直径は１ｎｍ〜１０ｎｍの範囲にあることが好ましい。
【０１６４】
また、上記第１，第２のメモリ機能体１３１ａ，１３１ｂの形状は、サイドウォールスペーサ形状であったが、これに必ずしも限定されない。例えば、図１６のメモリ素子の場合、シリコン窒化膜１０９の部分１０５ａ，１０５ｂが形成されている領域に電荷を保持する機能もしくは分極を保持する物質が配置されていれば、シリコン窒化膜１０９の形状は特に限定されない。
【０１６５】
以下、図１９〜図２３を用いて、図１７のメモリ素子の動作方法について述べる。なお、図１９〜図２３において、ＷＬはワード線、ＢＬ１，ＢＬ２はビット線を夫々示し、半導体基板１０１の図示は省略している。
【０１６６】
まず、図１９及び図２０を用いて、上記メモリ素子の書込み動作を説明する。なお、以下では、上記第１のメモリ機能体１３１ａ，２３１ｂが電荷を保持する機能を有する場合について説明する。
【０１６７】
ここで、「書込み」とは、図１８のメモリ素子がＮチャネル型である場合には第１，第２のメモリ機能体１３１ａ，１３１ｂに電子を注入することを指すこととする。以後、図１８のメモリ素子がＮチャネル型であるとして説明する。
【０１６８】
上記第２のメモリ機能体１３１ｂに電子を注入する（書込む）ためには、図１９に示すように、ｎ型の導電型を有する第１の拡散領域１０７ａをソース領域とする一方、ｎ型の導電型を有する第２の拡散領域１０７ｂをドレイン領域とする。例えば、上記第１の拡散領域１０７ａ及びｐ型ウェル領域１０２に０Ｖ、第２の拡散領域１０７ｂに＋５Ｖ、ゲート電極１０４に＋５Ｖを印加すればよい。このような電圧条件によれば、反転層２２６は、第１の拡散領域１０７ａ（ソース領域）から第２の拡散領域１０７ｂ（ドレイン領域）に向かって伸びるが、第２の拡散領域１０７ｂ（ドレイン領域）に達することなく、ピンチオフ点が発生する。電子は、ピンチオフ点から第２の拡散領域１０７ｂ（ドレイン領域）まで高電界により加速され、いわゆるホットエレクトロン（高エネルギーの伝導電子）となる。このホットエレクトロンが第２のメモリ機能体１３１ｂに注入されることにより書込みが行なわれる。なお、上記第１のメモリ機能体１３１ａ近傍では、ホットエレクトロンが発生しないため、書込みは行なわれない。
【０１６９】
このようにして、第２のメモリ機能体１３１ｂに電子を注入して、書込みを行なうことができる。
【０１７０】
一方、上記第１のメモリ機能体１３１ａに電子を注入する（書込む）ためには、図２０に示すように、第２の拡散領域１０７ｂをソース領域に、第１の拡散領域１０７ａをドレイン領域とする。例えば、上記第２の拡散領域１０７ｂ及びｐ型ウェル領域１０２に０Ｖ、第１の拡散領域１０７ａに＋５Ｖ、ゲート電極１０４に＋５Ｖを印加すればよい。このように、上記第２のメモリ機能体１３１ｂに電子を注入する場合とは、第１のメモリ機能体１３１ａに電子を注入する場合のソース／ドレイン領域を入れ替える。これにより、上記第１のメモリ機能体１３１ａに電子を注入して、書込みを行なうことができる。
【０１７１】
次に、図２１及び図２２を用いて、上記メモリ素子の消去動作を説明する。
【０１７２】
上記第１のメモリ機能体１３１ａに記憶された情報を消去する第１の消去方法では、図２１に示すように、第１の拡散領域１０７ａに正電圧（例えば、＋５Ｖ）、ｐ型ウェル領域１０２に０Ｖを印加して、第１の拡散領域１０７ａとｐ型ウェル領域１０２とのＰＮ接合に逆方向バイアスをかけ、更にゲート電極１０４に負電圧（例えば、−５Ｖ）を印加すればよい。このとき、上記ＰＮ接合のうちゲート電極１０４付近では、負電圧が印加されたゲート電極１０４の影響により、特にポテンシャルの勾配が急になる。そのため、バンド間トンネルによりＰＮ接合のｐ型ウェル領域１０２側にホットホール（高エネルギーの正孔）が発生する。このホットホールが負の電位をもつゲート電極１０４方向に引きこまれ、その結果、第１のメモリ機能体１３１ａにホール注入が行なわれる。このようにして、第１のメモリ機能体１３１ａの消去が行なわれる。このとき第２の拡散領域１０７ｂには０Ｖを印加すればよい。
【０１７３】
上記第２のメモリ機能体１３１ｂに記憶された情報を消去する場合は、上記第１の消去方法において第１の拡散領域１０７ａと第２の拡散領域１０７ｂの電位を入れ替えればよい。つまり、上記第１の拡散領域１０７ａには０Ｖを印加すると共に、第２の拡散領域１０７ｂには５Ｖを印加する。
【０１７４】
上記第１のメモリ機能体１３１ａに記憶された情報を消去する第２の消去方法では、図２２に示すように、第１の拡散領域１０７ａに正電圧（例えば、＋４Ｖ）、第２の拡散領域１０７ｂに０Ｖ、ゲート電極１０４に負電圧（例えば、−４Ｖ）、ｐ型ウェル領域１０２に正電圧（例えば、＋０．８Ｖ）を印加すればよい。この際、上記ｐ型ウェル領域１０２と第２の拡散領域１０７ｂとの間に順方向電圧が印加され、ｐ型ウェル領域１０２に電子が注入される。注入された電子は、ｐ型ウェル領域１０２と第１の拡散領域１０７ａとのＰＮ接合まで拡散し、そこで強い電界により加速されてホットエレクトロンとなる。このホットエレクトロンは、ＰＮ接合において、電子−ホール対を発生させる。すなわち、上記ｐ型ウェル領域１０２と第２の拡散領域１０７ｂとの間に順方向電圧を印加することにより、ｐ型ウェル領域１０２に注入された電子がトリガーとなって、第２の拡散領域１０７ｂとは反対側に位置するＰＮ接合でホットホールが発生する。上記ＰＮ接合で発生したホットホールは負の電位をもつゲート電極１０４方向に引きこまれ、その結果、第１のメモリ機能体１３１ａに正孔注入が行なわれる。
【０１７５】
上記第２の消去方法によれば、ｐ型ウェル領域１０２と第１の拡散領域１０７ａとのＰＮ接合において、バンド間トンネルによりホットホールが発生するに足りない電圧しか印加されない場合においても、第２の拡散領域１０７ｂからｐ型ウェル領域１０２に注入された電子は、ＰＮ接合で電子−正孔対が発生するトリガーとなり、ホットホールを発生させることができる。したがって、消去動作時の電圧を低下させることができる。特に、図１７及び図１８で示したオフセット領域１２０が存在する場合は、負の電位が印加されたゲート電極１０４により上記ＰＮ接合が急峻となる効果が少ない。そのため、バンド間トンネルによるホットホールの発生が難しいのであるが、第２の消去方法はその欠点を補い、低電圧で消去動作を実現することができる。
【０１７６】
具体的には、上記第１のメモリ機能体１３１ａに記憶された情報を消去する場合、第１の消去方法では、第１の拡散領域１０７ａに＋５Ｖを印加しなければならなかったが、第２の消去方法では、＋４Ｖで足りた。このように、第２の消去方法によれば、消去時の電圧を低減することができるので、消費電力が低減され、ホットキャリアによるメモリ素子の劣化を抑制することができる。
【０１７７】
上記第１，第２の消去方法の何れによっても、メモリ素子は過消去が起きにくいという特徴を有している。上記過消去とは、メモリ機能体に蓄積された正孔の量が増大するにつれ、飽和することなく閾値が低下していく現象を指す。フラッシュメモリを代表とするＥＥＰＲＯＭでは大きな問題となっており、特に閾値が負になった場合にメモリセルの選択が不可能になるという致命的な動作不良を生じる。上記メモリ素子においては、メモリ機能体に大量の正孔が蓄積された場合においても、メモリ機能体下に電子が誘起されるのみで、ゲート絶縁膜下のチャネル領域のポテンシャルにはほとんど影響を与えない。消去時の閾値はゲート絶縁膜下のポテンシャルにより決まるので、過消去が起きにくいのである。
【０１７８】
次に、図２３を用いて、上記メモリ素子の読み出し動作を説明する。
【０１７９】
上記第１のメモリ機能体１３１ａに記憶された情報を読み出す場合、図２３に示すように、第１の拡散領域１０７ａをソース領域とすると共に、第２の拡散領域１０７ｂをドレイン領域として、トランジスタを飽和領域動作させる。例えば、上記第１の拡散領域１０７ａ及びｐ型ウェル領域１０２に０Ｖ、第２の拡散領域１０７ｂ及びゲート電極１０４に＋２Ｖを印加すればよい。この際、上記第１のメモリ機能体１３１ａに電子が蓄積していない場合には、ドレイン電流が流れやすい。一方、上記第１のメモリ機能体１３１ａに電子が蓄積している場合は、第１のメモリ機能体１３１ａ近傍で反転層が形成されにくいので、ドレイン電流は流れにくい。したがって、ドレイン電流を検出することにより、第１のメモリ機能体１３１ａの記憶情報を読み出すことができる。このとき、上記第２のメモリ機能体１３１ｂにおける電荷蓄積の有無は、ドレイン近傍がピンチオフしているため、ドレイン電流に影響を与えない。
【０１８０】
上記第２のメモリ機能体１３１ｂに記憶された情報を読み出す場合、第２の拡散領域１０７ｂをソース領域とすると共に、第１の拡散領域１０７ａをドレイン領域として、トランジスタを飽和領域動作させる。例えば、上記第２の拡散領域１０７ｂ及びｐ型ウェル領域１０２に０Ｖ、第１の拡散領域１０７ａに＋１．８Ｖ、ゲート電極１０４に＋２Ｖを印加すればよい。このように、上記第１のメモリ機能体１３１ａに記憶された情報を読み出す場合とは、ソース／ドレイン領域を入れ替えることにより、第２のメモリ機能体１３１ｂに記憶された情報の読出しを行なうことができる。
【０１８１】
なお、上記チャネル領域１２２においてゲート電極１０４で覆われない部分（オフセット領域１２０）が残されている場合、その部分においては、第１，第２のメモリ機能体１３１ａ，１３１ｂの余剰電荷の有無によって反転層が消失または形成される結果、大きなヒステリシス（閾値の変化）が得られる。ただし、上記オフセット領域１２０の幅があまり大きいと、ドレイン電流が大きく減少し、読出し速度が大幅に遅くなる。したがって、十分なヒステリシスと読出し速度が得られるように、オフセット領域１０２の幅を決定することが好ましい。
【０１８２】
上記拡散領域１０７ａ，１０７ｂがゲート電極１０４端に達している場合、つまり、拡散領域１０７ａ，１０７ｂとゲート電極１０４とがオーバーラップしている場合であっても、書込み動作によりトランジスタの閾値はほとんど変わらなかったが、ソース／ドレイン端での寄生抵抗が大きく変わり、ドレイン電流は大きく減少（１桁以上）した。したがって、ドレイン電流の検出により読出しが可能であり、メモリとしての機能を得ることができる。ただし、より大きなメモリヒステリシス効果を必要とする場合、拡散領域１０７ａ，１０７ｂとゲート電極１０４とがオーバーラップしていないほうが好ましい。つまり、上記オフセット領域１２０が存在するほうが好ましい。
【０１８３】
以上の動作方法により、１トランジスタ当り選択的に２ビットの書込み及び消去が可能となる。また、上記メモリ素子のゲート電極１０４にワード線ＷＬを、第１の拡散領域１０７ａにビット線ＢＬ１を、第２の拡散領域１０７ｂにビット線ＢＬ２をそれぞれ接続し、メモリ素子を配列することにより、メモリセルアレイを構成することができる。
【０１８４】
また、上記動作方法では、ソース電極とドレイン電極とを入れ替えることによって、１つのメモリ素子当り２ビットの書込み及び消去をさせているが、ソース領域とドレイン領域とを固定して１ビットメモリとして動作させてもよい。この場合、ソース／ドレイン領域の一方を共通固定電圧とすることが可能となり、ソース／ドレイン領域に接続されるビット線の本数を半減することができる。
【０１８５】
以上の説明から明らかなように、上記メモリ素子によれば、第１，第２のメモリ機能体１３１ａ，１３１ｂはゲート絶縁膜１０３と独立して形成され、ゲート電極１０４の両側に形成されている。そのため、２ビット動作が可能である。更には、上記第１のメモリ機能体１３１ａと第２のメモリ機能体１３１ｂとは、ゲート電極１０４により分離されているので、書換え時の干渉が効果的に抑制される。また、上記ゲート絶縁膜１０３は、第１，第２のメモリ機能体１３１ａ，１３１ｂと分離されているので、薄膜することができる。したがって、短チャネル効果を抑制することができると共に、メモリ素子を容易に微細化することができる。
【０１８６】
（実施の形態１０）
この実施の形態のメモリ素子は、図２４に示すように、第１，第２のメモリ機能体２６１，２６２をゲート電極２１７の両側に備えている。上記第１，第２のメモリ機能体２６１，２６２は、電荷を保持する領域（電荷を蓄える領域であって、電荷を保持する機能を有する膜であってもよい）と、電荷を逃げにくくする領域（電荷を逃げにくくする機能を有する膜であってもよい）とから構成されて、ＯＮＯ構造を有している。すなわち、上記第１，第２のメモリ機能体２６１，２６２は、シリコン窒化膜２４２と、このシリコン窒化膜２４２を挟むシリコン酸化膜２４１，２４３とで構成されている。上記第１，第２のメモリ機能体２６１，２６２では、シリコン窒化膜２４２が電荷を保持する機能を果たす。また、上記シリコン酸化膜２４１，２４３はシリコン窒化膜２４２中に蓄えられた電荷を逃げにくくする機能を有する膜の役割を果たす。
【０１８７】
また、上記第１，第２のメモリ機能体２６１，２６２における電荷を保持する領域（シリコン窒化膜２４２）は、第１，第２の拡散領域２１２，２１３とそれぞれオーバーラップしている。ここで、「オーバーラップする」とは、第１，第２の拡散領域２１２，２１３の少なくとも一部の領域上に、電荷を保持する領域（シリコン窒化膜２４２）の少なくとも一部が存在することを意味する。なお、図２４において、２１１は半導体基板、２１４はゲート絶縁膜、２１７はゲート電極、２７１はオフセット領域、２７２はチャネル領域である。上記オフセット領域２７１は、ゲート電極２１７と第１，第２の拡散領域２１２，２１３とのオフセット領域である。また、上記チャネル領域２７２は、ゲート絶縁膜２１４下であって半導体基板２１１最表面部に相当する。
【０１８８】
以下、上記第１，第２のメモリ機能体２６１，２６２における電荷を保持する領域（シリコン窒化膜２４２）と第１，第２の拡散領域２１２，２１３とがオーバーラップすることによる効果を説明する。
【０１８９】
図２５は、図２４の右側の第２のメモリ機能体２６２周辺部の拡大図である。また、図２５において、Ｗ１はゲート電極２１４と第２の拡散領域２１３とのオフセット量を示し、Ｗ２はゲート電極２１７のゲート長方向の切断面における第２のメモリ機能体２６２の幅を示している。このように、上記第２のメモリ機能体２６２の幅をＷ２と定義したのは、シリコン窒化膜２４２のゲート電極２１７と離れた側の端が、第２のメモリ機能体２６２のゲート電極２１７から離れた側の端と一致しているためである。また、上記第２のメモリ機能体２６２と第２の拡散領域２１３とのオーバーラップ量はＷ２−Ｗ１で表されることになる。ここで特に重要なことは、上記第２のメモリ機能体２６２のうちシリコン窒化膜２４２が、拡散領域２１３とオーバーラップする、つまり、Ｗ２＞Ｗ１なる関係を満たすことである。
【０１９０】
なお、図２６に示すような第２のメモリ機能体２６２ａの場合、シリコン窒化膜２４２ａのゲート電極２１７と離れた側の端が、メモリ機能体２６２ａのゲート電極２１７から離れた側の端と一致していない。この場合は、Ｗ２をゲート電極２１７の第２のメモリ機能体２６２側の端から、シリコン窒化膜１４２ａのゲート電極２１７とは反対側の端までと定義すればよい。また、図２６において、２４１ａ，２４３ａはシリコン酸化膜である。
【０１９１】
図２７は、図２５の構造において、第２のメモリ機能体２６２の幅Ｗ２を１００ｎｍに固定し、オフセット量Ｗ１を変化させたときのドレイン電流Ｉｄを示している。ここで、ドレイン電流Ｉｄは、第２のメモリ機能体２６２を消去状態（ホールが蓄積されている）とし、第１，第２の拡散領域２１２，２１３をそれぞれソース領域，ドレイン領域として、デバイスシミュレーションにより求めた。
【０１９２】
図２７から明らかなように、Ｗ１が１００ｎｍ以上（すなわち、シリコン窒化膜２４２と第２の拡散領域２１３とがオーバーラップしない状態）では、ドレイン電流Ｉｄが急速に減少している。上記ドレイン電流Ｉｄの値は、読出し動作速度にほぼ比例するので、Ｗ１が１００ｎｍ以上ではメモリの性能は急速に劣化する。一方、上記シリコン窒化膜２４２と第２の拡散領域２１３とがオーバーラップする範囲においては、ドレイン電流の減少は緩やかである。したがって、量産製造においてばらつきも考慮した場合、電荷を保持する機能を有する膜であるシリコン窒化膜２４２の少なくとも一部とソース／ドレイン領域とがオーバーラップしなければ、事実上メモリ機能を得ることが困難である。
【０１９３】
上述したデバイスシミュレーションの結果を踏まえて、Ｗ２を１００ｎｍ固定とし、Ｗ１を設計値として６０ｎｍ及び１００ｎｍとして、メモリセルアレイを作製した。Ｗ１が６０ｎｍの場合、シリコン窒化膜１４２と第１，第２の拡散領域１１２，１１３とは設計値として４０ｎｍオーバーラップし、Ｗ１が１００ｎｍの場合、設計値としてオーバーラップしない。これらのメモリセルアレイの読出し時間を測定した結果、ばらつきを考慮したワーストケースで比較して、Ｗ１を設計値として６０ｎｍとした場合の方が、読出しアクセス時間で１００倍高速であった。実用上、読み出しアクセス時間は１ビットあたり１００ナノ秒以下であることが好ましいが、Ｗ１＝Ｗ２では、この条件を到底達成できないことが分かった。また、製造ばらつきまで考慮した場合、Ｗ２−Ｗ１＞１０ｎｍであることがより好ましいことが判明した。
【０１９４】
上記第１のメモリ機能体２６１（領域２８０）に記憶された情報の読み出しは、上記実施の形態１と同様に、第１の拡散領域２１２をソース領域とし、第２の拡散領域２１３をドレイン領域としてチャネル領域中のドレイン領域に近い側にピンチオフ点を形成するのが好ましい。すなわち、２つのメモリ機能体のうち一方に記憶された情報を読み出す時に、ピンチオフ点をチャネル領域内であって、他方のメモリ機能体に近い領域に形成させるのが好ましい。これにより、第２のメモリ機能体２６２の記憶状況の如何にかかわらず、第１のメモリ機能体２６１の記憶情報を感度よく検出することができ、２ビット動作を可能にする大きな要因となる。
【０１９５】
一方、２つの第１，第２のメモリ機能体２６１，２６２の片側のみに情報を記憶させる場合、または、２つの第１，第２のメモリ機能体２６１，２６２を同じ記憶状態にして使用する場合には、読出し時に必ずしもピンチオフ点を形成しなくてもよい。
【０１９６】
なお、図２４には図示していないが、半導体基板２１１の表面にウェル領域（Ｎチャネル素子の場合はｐ型ウェル）を形成することが好ましい。ウェル領域を形成することにより、チャネル領域の不純物濃度をメモリ動作（書換え動作及び読出し動作）に最適にしつつ、その他の電気特性（耐圧、接合容量、短チャネル効果）を制御するのが容易になる。
【０１９７】
メモリ機能体は、メモリの保持特性を向上させる観点から、電荷を保持する機能を有する電荷保持膜と絶縁膜とを含んでいるのが好ましい。本実施の形態では、電荷保持膜として電荷をトラップする準位を有するシリコン窒化膜２４２、絶縁膜として電荷保持膜に蓄積された電荷の散逸を防ぐ働きのあるシリコン酸化膜２４１，２４３を用いている。メモリ機能体が電荷保持膜と絶縁膜とを含むことにより電荷の散逸を防いで保持特性を向上させることができる。さらに、メモリ機能体が電荷保持膜のみで構成される場合に比べて電荷保持膜の体積を適度に小さくすることができる。電荷保持膜の体積を適度に小さくすることにより電荷保持膜内での電荷の移動を制限し、記憶保持中に電荷移動による特性変化が起こるのを抑制することができる。
【０１９８】
また、メモリ機能体は、ゲート絶縁膜表面と略平行に配置される電荷保持膜を含むことが好ましい。言い換えると、メモリ機能体における電荷保持膜の上面が、ゲート絶縁膜上面から等しい距離に位置するように配置されることが好ましい。具体的には、図２８に示すように、第２のメモリ機能体２６２ｂの電荷保持膜２４２ｂが、ゲート絶縁膜２１４表面と略平行な面を有している。言い換えると、上記電荷保持膜２４２ｂは、ゲート絶縁膜２１４表面に対応する高さから、均一な高さに形成されることが好ましい。
【０１９９】
上記第２のメモリ機能体２６２ｂ中に、ゲート絶縁膜２１４表面と略平行な電荷保持膜２４２ｂがあることにより、電荷保持膜２４２ｂに蓄積された電荷の多寡によりオフセット領域２７１での反転層の形成されやすさを効果的に制御することができ、ひいてはメモリ効果を大きくすることができる。また、上記電荷保持膜２４２ｂをゲート絶縁膜２１４の表面と略平行とすることにより、オフセット量（Ｗ１）がばらついた場合でもメモリ効果の変化を比較的小さく保つことができ、メモリ効果のばらつきを抑制することができる。しかも、電荷保持膜２４２ａ上部方向への電荷の移動が抑制され、記憶保持中に電荷移動による特性変化が起こるのを抑制することができる。
【０２００】
さらに、上記メモリ機能体２６２は、ゲート絶縁膜２１４の表面と略平行な電荷保持膜２４２ａとチャネル領域（またはウェル領域）とを隔てる絶縁膜（例えば、シリコン酸化膜２４４ｂのうちオフセット領域２７１上の部分）を含むことが好ましい。この絶縁膜により、電荷保持膜２４２ｂに蓄積された電荷の散逸が抑制され、さらに保持特性の良いメモリ素子を得ることができる。
【０２０１】
なお、上記電荷保持膜２４２ｂの膜厚を制御すると共に、電荷保持膜２４２ｂ下の絶縁膜（シリコン酸化膜２４４のうちオフセット領域２７１上の部分）の膜厚を一定に制御することにより、半導体基板表面から電荷保持膜２４２ｂ中に蓄えられる電荷までの距離を概ね一定に保つことが可能となる。つまり、半導体基板表面から電荷保持膜２４２ｂ中に蓄えられる電荷までの距離を、電荷保持膜２４２ｂ下の絶縁膜の最小膜厚値から、電荷保持膜２４２ａ下の絶縁膜の最大膜厚値と電荷保持膜２４２ａの最大膜厚値との和までの間に制御することができる。これにより、上記電荷保持膜２４２ｂに蓄えられた電荷により発生する電気力線の密度を概ね制御することが可能となり、メモリ素子のメモリ効果の大きさばらつきを非常に小さくすることが可能となる。
【０２０２】
本実施形態で述べた第２のメモリ機能体２６２について好ましい条件が、第１のメモリ機能体２６１に対しても好ましい条件であることは言うまでもない。
【０２０３】
（実施の形態１１）
この実施の形態は、メモリ機能体２６２のシリコン窒化膜２４２が、図２９に示すように、略均一な膜厚を有する。さらに、上記電荷保持膜２４２は、ゲート絶縁膜２１４の表面と略平行に配置された第１の部分２８１と、ゲート電極２１７の側面と略平行に配置された第２の部分２８２とを有している。
【０２０４】
上記ゲート電極２１７に正電圧が印加された場合には、メモリ機能体２６２中での電気力線は矢印２８３のように、シリコン窒化膜２４２を２回通過する。つまり、上記電気力線は、第１の部分２８１と第２の部分とを通過する。なお、上記ゲート電極２１７に負電圧が印加された時は、電気力線の向きは矢印２８３の向きとは反対になる。ここで、上記シリコン窒化膜２４２の比誘電率は約６であり、シリコン酸化膜２４１，２４３の比誘電率は約４である。したがって、上記第１の部分２８１のみから成る電荷保持膜のみが存在する場合よりも、矢印２８３方向の電気力線におけるメモリ機能体２６２の実効的な比誘電率が大きくなるので、電気力線の両端での電位差をより小さくすることができる。すなわち、上記ゲート電極２１７に印加された電圧の多くの部分が、オフセット領域２７１における電界を強くするために使われることになる。
【０２０５】
書換え動作時に電荷がシリコン窒化膜２４２に注入されるのは、発生した電荷がオフセット領域２７１における電界により引き込まれるためである。したがって、上記第２の部分を電荷保持膜が含むことにより、書換え動作時にメモリ機能体２６２に注入される電荷が増加し、書換え速度が増大する。
【０２０６】
なお、上記シリコン酸化膜２４３の部分もシリコン窒化膜であった場合、つまり、電荷保持膜がゲート絶縁膜２１４の表面に対応する高さに対して均一でない場合、シリコン窒化膜の上方向への電荷の移動が顕著になって、保持特性が悪化する。
【０２０７】
電荷保持膜は、シリコン窒化膜に代えて、比誘電率が非常大きい酸化ハフニウムなどの高誘電体により形成されることがより好ましい。
【０２０８】
さらに、メモリ機能体は、ゲート絶縁膜表面と略平行な電荷保持膜とチャネル領域（またはウェル領域）とを隔てる絶縁膜（シリコン酸化膜２４１のうちオフセット領域２７１上の部分）をさらに含むことが好ましい。この絶縁膜により、電荷保持膜に蓄積された電荷の散逸が抑制され、さらに保持特性を向上させることができる。
【０２０９】
また、メモリ機能体は、ゲート電極と、ゲート電極側面に対して略平行な向きに延びた電荷保持膜とを隔てる絶縁膜（シリコン酸化膜２４１のうちゲート電極２１７に接した部分）をさらに含むことが好ましい。この絶縁膜により、ゲート電極から電荷保持膜へ電荷が注入されて電気的特性が変化することを防止し、メモリ素子の信頼性を向上させることができる。
【０２１０】
さらに、上記実施の形態２と同様に、電荷保持膜下の絶縁膜（シリコン酸化膜２４１のうちオフセット領域２７１上の部分）の膜厚を一定に制御すること、さらにゲート電極側面上に配置する絶縁膜（シリコン酸化膜２４１のうちゲート電極２１７に接した部分）の膜厚を一定に制御することが好ましい。これにより、電荷保持膜に蓄えられた電荷により発生する電気力線の密度を概ね制御することができると共に、電荷リークを防止することができる。
【０２１１】
（実施の形態１２）
本実施の形態は、ゲート電極、メモリ機能体及びソース／ドレイン領域間距離の最適化に関する。
【０２１２】
図３０に示したように、Ａはゲート長方向の切断面におけるゲート電極長、Ｂはソース／ドレイン領域間の距離（チャネル長）、Ｃは一方のメモリ機能体の端から他方のメモリ機能体の端までの距離、つまり、ゲート長方向の切断面における一方のメモリ機能体内の電荷を保持する機能を有する膜の端（ゲート電極と離れている側）から他方のメモリ機能体内の電荷を保持する機能を有する膜の端（ゲート電極と離れている側）までの距離を示す。
【０２１３】
まず、Ｂ＜Ｃであることが好ましい。チャネル領域のうちゲート電極２１７下の部分と、ソース／ドレイン領域となる第１，第２の拡散領域２１２，２１３との間にはオフセット領域２７１が存する。Ｂ＜Ｃにより、第１，第２のメモリ機能体２６１，２６２（シリコン窒化膜２４２）に蓄積された電荷により、オフセット領域２７１の全領域において、反転の容易性が効果的に変動する。したがって、メモリ効果が増大し、特に読出し動作の高速化が実現する。
【０２１４】
また、ゲート電極２１７と第１，第２の拡散領域（ソース／ドレイン領域）２１２，２１３がオフセットしている場合、つまり、Ａ＜Ｂが成立する場合には、ゲート電極２１７に電圧を印加したときのオフセット領域２７１の反転のしやすさが第１，第２のメモリ機能体２６１，２６２に蓄積された電荷量によって大きく変化し、メモリ効果が増大すると共に、短チャネル効果を低減することができる。ただし、上記メモリ効果が発現する限りにおいては、必ずしも存在する必要はない。
【０２１５】
また、上記オフセット領域２７１がない場合においても、第１，第２の拡散領域２１２，２１３の不純物濃度が十分に薄ければ、第１，第２のメモリ機能体２６１，２６２（シリコン窒化膜２４２）においてメモリ効果が発現し得る。
【０２１６】
したがって、Ａ＜Ｂ＜Ｃであるのが最も好ましい。
【０２１７】
（実施の形態１３）
この実施の形態のメモリ素子は、図３１に示すように、上記実施の形態２における半導体基板をＳＯＩ基板とする以外は、実質的に同様の構成を有する。
【０２１８】
このメモリ素子は、半導体基板２８６上に埋め込み酸化膜２８８が形成され、さらにその上にＳＯＩ層が形成されている。ＳＯＩ層内には第１，第２の拡散領域２１２，２１３が形成され、それ以外の領域はボディ領域２８７となっている。
【０２１９】
このメモリ素子によっても、上記実施の形態２のメモリ素子と同様の作用効果を奏する。さらに、上記第１，第２の拡散領域２１２，２１３とボディ領域２８７との接合容量を著しく小さくすることができるので、素子の高速化や低消費電力化が可能となる。
【０２２０】
（実施の形態１４）
この実施の形態のメモリ素子は、図３２に示すように、上記実施の形態２において、ｎ型のソース／ドレイン領域である第１，第２の拡散領域２１２，２１３のチャネル側に隣接して、ｐ型高濃度領域２９１を追加した以外は、実質的に同様の構成を有する。
【０２２１】
すなわち、上記ｐ型高濃度領域２９１におけるｐ型を与える不純物（例えばボロン）濃度が、領域２９２におけるｐ型を与える不純物濃度より高い。上記ｐ型高濃度領域２９１におけるｐ型の不純物濃度は、例えば、５×１０^１７〜１×１０^１９ｃｍ^−３程度が適当である。また、上記領域２９２のｐ型の不純物濃度は、例えば、５×１０^１６〜１×１０^１８ｃｍ^−３とすることができる。
【０２２２】
このように、上記ｐ型高濃度領域２９１を設けることにより、第１，第２の拡散領域２１２，２１３と半導体基板２１１との接合が、第１，第２のメモリ機能体２６１，２６２の直下で急峻となる。そのため、書込み及び消去動作時にホットキャリアが発生し易くなり、書込み動作及び消去動作の電圧を低下させ、あるいは書込み動作及び消去動作を高速にすることが可能となる。さらに、上記領域２９２の不純物濃度は比較的薄いので、メモリが消去状態にあるときの閾値が低く、ドレイン電流は大きくなる。そのため、読出し速度が向上する。したがって、書換え電圧が低くまたは書換え速度が高速で、かつ、読出し速度が高速なメモリ素子を得ることができる。
【０２２３】
また、図３２において、ソース／ドレイン領域近傍であってメモリ機能体の下（すなわち、ゲート電極２１７の直下ではない）において、ｐ型高濃度領域２９１を設けることにより、トランジスタ全体としての閾値は著しく上昇する。この上昇の程度は、ｐ型高濃度領域２９１がゲート電極２１７の直下にある場合に比べて著しく大きい。メモリ機能体に書込み電荷（トランジスタがＮチャネル型の場合は電子）が蓄積した場合は、この差がいっそう大きくなる。一方、メモリ機能体に十分な消去電荷（トランジスタがＮチャネル型の場合は正孔）が蓄積された場合は、トランジスタ全体としての閾値は、ゲート電極２１７下のチャネル領域（領域２９２）の不純物濃度で決まる閾値まで低下する。すなわち、消去時の閾値は、ｐ型高濃度領域２９１の不純物濃度には依存せず、一方で、書込み時の閾値は非常に大きな影響を受ける。よって、ｐ型高濃度領域２９１をメモリ機能体の下であってソース／ドレイン領域近傍に配置することにより、書込み時の閾値のみが非常に大きく変動し、メモリ効果（書込み時と消去時での閾値の差）を著しく増大させることができる
【０２２４】
（実施の形態１５）
この実施の形態のメモリ素子は、図３３に示すように、上記実施の形態２において、電荷保持膜（シリコン窒化膜２４２）とチャネル領域またはウェル領域とを隔てる絶縁膜の厚さＴ１が、ゲート絶縁膜２１４の厚さＴ２よりも薄いこと以外は、実質的に同様の構成を有する。
【０２２５】
上記ゲート絶縁膜２１４は、メモリの書換え動作時における耐圧の要請から、その厚さＴ２には下限値が存在する。しかし、上記絶縁膜の厚さＴ１は、耐圧の要請にかかわらず、Ｔ２よりも薄くすることが可能である。
【０２２６】
本実施の形態のメモリ素子において、上述のようにＴ１に対する設計の自由度が高いのは以下の理由による。本実施の形態のメモリ素子においては、電荷保持膜とチャネル領域またはウェル領域とを隔てる絶縁膜は、ゲート電極とチャネル領域またはウェル領域とに挟まれていない。そのため、上記電荷保持膜とチャネル領域またはウェル領域とを隔てる絶縁膜には、ゲート電極とチャネル領域またはウェル領域間に働く高電界が直接作用せず、ゲート電極から横方向に広がる比較的弱い電界が作用する。そのため、ゲート絶縁膜に対する耐圧の要請にかかわらず、Ｔ１をＴ２より薄くすることが可能になるのである。一方、例えば、フラッシュメモリに代表されるＥＥＰＲＯＭにおいては、フローティングゲートとチャネル領域またはウェル領域とを隔てる絶縁膜は、ゲート電極（コントロールゲート）とチャネル領域またはウェル領域に挟まれているので、ゲート電極からの高電界が直接作用する。それゆえ、ＥＥＰＲＯＭにおいては、フローティングゲートとチャネル領域またはウェル領域とを隔てる絶縁膜の厚さが制限され、メモリ素子の機能の最適化が阻害されるのである。
【０２２７】
以上より明らかなように、本実施の形態のメモリ素子において電荷保持膜とチャネル領域またはウェル領域とを隔てる絶縁膜が、ゲート電極とチャネル領域またはウェル領域とに挟まれていないことが、Ｔ１の自由度を高くする本質的な理由となっている。
【０２２８】
上記絶縁膜の厚さＴ１を薄くすることにより、第１，第２のメモリ機能体２６１，２６２への電荷の注入が容易になり、書込み動作及び消去動作の電圧を低下させ、または書込み動作及び消去動作を高速にすることが可能となり、また、シリコン窒化膜２４２に電荷が蓄積された時にチャネル領域またはウェル領域に誘起される電荷量が増えるため、メモリ効果を増大させることができる。
【０２２９】
ところで、上記第１，第２のメモリ機能体２６１，２６２中での電気力線は、図２９の矢印２８４で示すように、シリコン窒化膜２４２を通過しない短いものもある。このような短い電気力線上では比較的電界強度が大きいので、この電気力線に沿った電界は書換え動作時においては大きな役割を果たしている。上記絶縁膜の厚さＴ１を薄くすることによりシリコン窒化膜２４２が図の下側に移動し、矢印２８３で示す電気力線がシリコン窒化膜２４２を通過するようになる。それゆえ、上記矢印２８４で示す電気力線に沿った第１，第２のメモリ機能体２６１，２６２中の実効的な比誘電率が大きくなり、電気力線の両端での電位差をより小さくすることができる。したがって、上記ゲート電極２１７に印加された電圧の多くの部分が、オフセット領域における電界を強くするために使われ、書込み動作及び消去動作が高速になる。
【０２３０】
以上より明らかなように、Ｔ１＜Ｔ２とすることにより、メモリの耐圧性能を低下させることなく、書込み動作及び消去動作の電圧を低下させ、または書込み動作及び消去動作を高速にし、さらにメモリ効果を増大することが可能となる。
【０２３１】
なお、上記絶縁膜の厚さＴ１は、製造プロセスによる均一性や膜質が一定の水準を維持することが可能であり、かつ保持特性が極端に劣化しない限界となる０．８ｎｍ以上であることがより好ましい。
【０２３２】
具体的には、デザインルールの大きな高耐圧が必要とされる液晶ドライバーＬＳＩのような場合、液晶パネルＴＦＴ（薄膜トランジスタ）を駆動するために、最大１５〜１８Ｖの電圧が必要となる。このため、ゲート酸化膜を薄膜化することができない。上記液晶ドライバーＬＳＩに画像調整用として本発明の不揮発性メモリを混載する場合、本発明で用いるメモリ素子ではゲート絶縁膜厚とは独立して電荷保持膜（シリコン窒化膜２４２）とチャネル領域またはウェル領域とを隔てる絶縁膜の厚さを最適に設計できる。例えば、ゲート電極長（ワード線幅）２５０ｎｍのメモリセルに対して、Ｔ１＝２０ｎｍ、Ｔ２＝１０ｎｍで個別に設定でき、書込み効率の良いメモリセルを実現できている（Ｔ１が通常のロジックトランジスタよりも厚くても短チャネル効果が発生しない理由はゲート電極に対して、ソース・ドレイン領域がオフセットしているためである）。
【０２３３】
（実施の形態１６）
この実施の形態のメモリ素子は、図３４に示すように、上記実施の形態２において、電荷保持膜（シリコン窒化膜２４２）とチャネル領域またはウェル領域とを隔てる絶縁膜の厚さＴ１が、ゲート絶縁膜２１４の厚さＴ２よりも厚いこと以外は、実質的に同様の構成を有する。
【０２３４】
上記ゲート絶縁膜２１４は、素子の短チャネル効果防止の要請から、その厚さＴ２には上限値が存在する。しかし、上記絶縁膜の厚さＴ１は、短チャネル効果防止の要請にかわらず、ゲート絶縁膜２１４の厚さＴ２よりも厚くすることが可能である。すなわち、微細化スケーリングが進んだとき（ゲート絶縁膜２１４の薄膜化が進行したとき）にゲート絶縁膜厚とは独立して電荷保持膜（シリコン窒化膜２４２）とチャネル領域またはウェル領域とを隔てる絶縁膜（シリコン酸化膜）の厚さＴ１を最適に設計できるため、第１，第２のメモリ機能体２６１，２６２がスケーリングの障害にならないという効果を奏する。
【０２３５】
本実施の形態のメモリ素子において、上述のように絶縁膜の厚さＴ１に対する設計の自由度が高い理由は、既に述べた通り、電荷保持膜とチャネル領域またはウェル領域とを隔てる絶縁膜が、ゲート電極とチャネル領域またはウェル領域とに挟まれていないことによる。そのため、上記ゲート絶縁膜２１４に対する短チャネル効果防止の要請にかかわらず、絶縁膜の厚さＴ１をゲート絶縁膜２１４の厚さＴ２より厚くすることが可能になるのである。
【０２３６】
上記絶縁膜の厚さＴ１を厚くすることにより、第１，第２のメモリ機能体２６１，２６２に蓄積された電荷が散逸するのを防ぎ、メモリの保持特性を改善することが可能となる。
したがって、Ｔ１＞Ｔ２とすることにより、メモリの短チャネル効果を悪化させることなく保持特性を改善することが可能となる。
【０２３７】
なお、上記絶縁膜の厚さＴ１は、書換え速度の低下を考慮して、２０ｎｍ以下であることが好ましい。
【０２３８】
具体的には、フラッシュメモリに代表される従来の不揮発性メモリは、選択ゲート電極が書込み消去ゲート電極を構成し、上記書込み消去ゲート電極に対応するゲート絶縁膜（フローティングゲートを内包する）が電荷蓄積膜を兼用している。このため、微細化（短チャネル効果抑制のため薄膜化が必須）の要求と、信頼性確保（保持電荷のリーク抑制のため、フローティングゲートとチャネル領域またはウェル領域とを隔てる絶縁膜の厚さは７ｎｍ程度以下には薄膜化できない）の要求が相反するため、微細化が困難となる。実際、ＩＴＲＳ（Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｔｅｃｈｎｏｌｏｇｙ Ｒｏａｄｍａｐ ｆｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ：国際半導体技術ロードマップ）によれば、物理ゲート長の微細化は０．２ミクロン程度以下に対して目処が立っていない。本発明で用いるメモリ素子では、上述したようにＴ１とＴ２を個別に設計できることにより、微細化が可能となる。例えば、本発明では、ゲート電極長（ワード線幅）４５ｎｍのメモリセルに対して、Ｔ２＝４ｎｍ、Ｔ１＝７ｎｍで個別に設定し、短チャネル効果の発生しないメモリ素子を実現した。上記ゲート絶縁膜２１４の厚さＴ２を通常のロジックトランジスタよりも厚く設定しても短チャネル効果が発生しない理由はゲート電極に対して、ソース・ドレイン領域がオフセットしているためである。また、本発明で用いるメモリ素子はゲート電極に対して、ソース・ドレイン領域がオフセットしているため、通常のロジックトランジスタと比較しても更に微細化を容易にしている。
【０２３９】
以上要約すると、第１，第２のメモリ機能体２６１，２６２の上部に書込、消去を補助する電極が存在しないため、電荷保持膜とチャネル領域またはウェル領域とを隔てる絶縁膜には、書込、消去を補助する電極とチャネル領域またはウェル領域間に働く高電界が直接作用せず、ゲート電極２１７から横方向に広がる比較的弱い電界が作用するだけである。そのため、同じ加工世代に対してロジックトランジスタのゲート長と同程度以上に微細化されたゲート長を保有するメモリセルの実現が可能になるのである。
【０２４０】
（実施の形態１７）
この実施の形態は、メモリ素子の書換えを行ったときの電気特性の変化に関する。
【０２４１】
図３５は、Ｎチャネル型メモリ素子のメモリ機能体中の電荷量が変化したときの、ドレイン電流Ｉｄ対ゲート電圧Ｖｇの特性（実測値）を示す図である。なお、図２２において、実線は消去状態におけるドレイン電流Ｉｄとゲート電圧Ｖｇとの関係を示し、点線は書き込み状態におけるドレイン電流Ｉｄとゲート電圧Ｖｇとの関係を示している。
【０２４２】
図３５から明らかなように、消去状態（図３５中において実線で示す状態）から書込み動作を行った場合、単純に閾値が上昇するのみならず、特にサブスレッショルド領域においてグラフの傾きが顕著に減少している。そのため、上記ゲート電圧Ｖｇが比較的高い領域においても、消去状態と書込み状態でのドレイン電流比が大きくなっている。例えば、Ｖｇ＝２．５Ｖにおいても、電流比は２桁以上を保っている。この特性は、フラッシュメモリの場合（図３９）と大きく異なる。
【０２４３】
このような特性の出現は、ゲート電極と拡散領域とがオフセットし、ゲート電界がオフセット領域に及びにくいために起こる特有な現象である。メモリ素子が書込み状態にあるときには、ゲート電極に正電圧を加えてもメモリ機能体下のオフセット領域には反転層が極めてできにくい状態になっている。これが、書込み状態においてサブスレッショルド領域でのＩｄ−Ｖｇ曲線の傾きが小さくなる原因となっている。一方、メモリ素子が消去状態にあるときには、オフセット領域には高密度の電子が誘起されている。なおかつ、ゲート電極に０Ｖが印加されているとき（すなわちオフ状態にあるとき）は、ゲート電極下のチャネルには電子が誘起されない（そのためオフ電流が小さい）。これが、消去状態においてサブスレッショルド領域でのＩｄ−Ｖｇ曲線の傾きが大きく、かつ閾値以上の領域でも電流の増加率（コンダクタンス）が大きい原因となっている。
【０２４４】
以上のことから明らかなように、本発明で用いるメモリ素子は、書込み時と消去時のドレイン電流比を特に大きくすることができる。
【０２４５】
また、本発明の半導体記憶装置の一例であるメモリセルアレイが備えるメモリ素子は、２ビットの情報を記憶することが可能であり、微細化が容易であり、形成が容易である。
【０２４６】
本発明の半導体記憶装置が備えるメモリ素子は、主として、拡散領域である第１導電型の領域と、この第１導電型の領域に隣接する第２導電型の領域と、第１導電型の領域上から第２導電型の領域上に渡るメモリ機能体と、このメモリ機能体の側方に形成された電極とを有している。この電極は、第２導電型の領域上に絶縁膜を介して形成される。あるいは、上記メモリ素子は、主として、ゲート絶縁膜と、ゲート絶縁膜上に形成されたゲート電極と、ゲート電極の両側に形成されたメモリ機能体と、各メモリ機能体のゲート電極と反対側に配置されたソース／ドレイン領域（拡散領域）と、ゲート電極下に配置されたチャネル領域とを有している。
【０２４７】
本明細書において、上記第１導電型とは、ｐ型またはｎ型を意味する。また、第２導電型とは、第１導電型がｐ型の場合はｎ型、ｎ型の場合はｐ型を意味する。
【０２４８】
上記メモリ素子は、１つのメモリ機能体に２値またはそれ以上の情報を記憶することにより、４値またはそれ以上の情報を記憶するメモリ素子として機能し、また、メモリ機能体による可変抵抗効果により、選択トランジスタとメモリトランジスタとの機能を兼ね備えたメモリセルとしても機能する。
【０２４９】
上記メモリ素子は４値またはそれ以上の情報を記憶できるが、必ずしも４値またはそれ以上の情報を記憶して機能させる必要はなく、例えば、２値の情報を記憶して機能させてもよい。
【０２５０】
本発明の半導体記憶装置は、半導体基板上、好ましくは半導体基板内に形成された第１導電型（ｐ型またはｎ型）のウェル領域上に形成されることが好ましい。
【０２５１】
上記半導体基板としては、半導体装置に使用されるものであれば特に限定されるものではなく、例えば、シリコン、ゲルマニウム等の元素半導体によるバルク基板、または、シリコンゲルマニウム、ＧａＡｓ、ＩｎＧａＡｓ、ＺｎＳｅ、ＧａＮ等の化合物半導体によるバルク基板が挙げられる。また、上記半導体基板として、表面上に半導体層を有する基板を用いてもよい。上記基板としては、単層ＳＯＩ（シリコン・オン・インシュレータ）基板または複層ＳＯＩ基板等の種々の基板、表面上に半導体層を有するガラス基板やプラスチック基板等がある。上述した基板の中でも、シリコン基板、または、表面にシリコン層が形成されたＳＯＩ基板等が好ましい。上記半導体基板または半導体層は、内部を流れる電流量に多少が生ずるが、単結晶（例えば、エピタキシャル成長による）、多結晶またはアモルファスのいずれであってもよい。
【０２５２】
上記半導体基板または半導体層には、素子分離領域が形成されていることが好ましく、さらに、トランジスタ、キャパシタ及び抵抗等の素子、これらによる回路、半導体装置や層間絶縁膜が組み合わされて、シングルまたはマルチレイヤー構造で形成されていてもよい。なお、上記素子分離領域は、ＬＯＣＯＳ（シリコン局所酸化）膜、トレンチ酸化膜、ＳＴＩ膜等種々の素子分離膜により形成することができる。上記半導体基板はｐ型またはｎ型の導電型を有していてもよく、半導体基板には、少なくとも１つの第１導電型（ｐ型またはｎ型）のウェル領域が形成されていることが好ましい。上記半導体基板及びウェル領域の不純物濃度は、当該分野で公知の範囲のものが使用できる。なお、上記半導体基板としてＳＯＩ基板を用いる場合、ＳＯＩ基板は表面半導体層にウェル領域が形成されていてもよいが、チャネル領域下にボディ領域を有していてもよい。
【０２５３】
上記ゲート絶縁膜または絶縁膜としては、通常、半導体装置に使用されるものであれば特に限定されるものではなく、例えば、シリコン酸化膜やシリコン窒化膜等の絶縁膜を使用することができる。また、上記ゲート絶縁膜としては、酸化アルミニウム膜、酸化チタニウム膜、酸化タンタル膜及び酸化ハフニウム膜などの高誘電体膜の単層膜または積層膜を使用することができる。これらの膜のなかでも、シリコン酸化膜が好ましい。上記ゲート絶縁膜は、例えば、１〜２０ｎｍ程度、好ましく１〜６ｎｍ程度の膜厚とすることが適当である。また、上記ゲート絶縁膜は、ゲート電極直下にのみに形成されていてもよいし、ゲート電極よりも大きく（幅広）で形成されていてもよい。つまり、上記ゲート絶縁膜の幅は、ゲート電極の幅と同じであってもよいし、ゲート電極の幅よりも広くてもよい。
【０２５４】
上記ゲート電極は、ゲート絶縁膜上に、通常半導体装置に使用されるような形状または下端部に凹部を有した形状で形成されている。また、上記ゲート電極は単一のゲート電極であってもよい。この「単一のゲート電極」とは、単層または複層の導電膜によって分離されないように一体形状で形成されているゲート電極を意味する。また、上記ゲート電極は、側壁に側壁絶縁膜を有していてもよい。つまり、上記ゲート電極は側壁の少なくとも一部が絶縁膜で形成されていてもよい。
【０２５５】
また、上記ゲート電極は、通常、半導体装置に使用されるものであれば特に限定されるものではない。つまり、上記ゲート電極の例としては、導電膜、例えばポリシリコンから成る電極、銅やアルミニウム等の金属から成る電極、タングステン、チタン及びタンタル等の高融点金属から成る電極、高融点金属とのシリサイド等の単層膜または積層膜等から成る電極等が挙げられる。ゲート電極の膜厚は、例えば５０〜４００ｎｍ程度の膜厚で形成することが適当である。なお、上記ゲート電極の下にはチャネル領域が形成されている。
【０２５６】
上記メモリ機能体は、少なくとも、電荷を保持する機能を有するか、電荷を蓄えて保持する機能を有するか、電荷をトラップする機能を有するか、若しくは、電荷分極状態を保持する機能を有する膜または領域を含んでいる。これらの機能を果たすものとしては、シリコン窒化物、シリコン、リン、シリケートガラス、シリコンカーバイド、アルミナ、高誘電体、酸化亜鉛、強誘電体及び金属等が挙げられる。上記シリコン窒化物は、電荷をトラップする準位が多数存在するため大きなヒステリシス特性を得ることができる。また、上記シリコン窒化物は、電荷保持時間が長く、リークパスの発生による電荷漏れの問題が生じないため保持特性が良好であり、さらに、ＬＳＩ（大規模集積回路）プロセスではごく標準的に用いられる材料であるため好ましい。また、上記シリケートガラスはリン、ボロン等の不純物を含んでいる。また、上記高誘電体としては、ハフニウムオキサイド、ジルコニウムオキサイド及びタンタルオキサイド等がある。
【０２５７】
また、上記メモリ機能体は、例えば、シリコン窒化膜を含む絶縁体膜で形成してもよいし、導電膜もしくは半導体層を内部に含む絶縁体膜で形成してもよい。また、上記メモリ機能体は、導電体ドットもしくは半導体ドットを１つ以上含む絶縁体膜で形成してもよい。また、上記メモリ機能体は、電界により内部電荷が分極し、その状態が保持される強誘電体膜を含む絶縁膜等の単層または積層構造によって形成することもできる。
【０２５８】
上記シリコン窒化膜などの電荷保持機能を有する絶縁膜を内部に含む絶縁膜をメモリ機能体として用いることにより、記憶保持に関する信頼性を高めることができる。これは、上記シリコン窒化膜が絶縁体であるから、その一部に電荷のリークが生じた場合でも、直ちにシリコン窒化膜全体の電荷が失われることがないからである。更には、複数のメモリ素子を配列する場合、メモリ素子間の距離が縮まって隣接するメモリ機能体が接触しても、メモリ機能体が導電体からなる場合のように夫々のメモリ機能体に記憶された情報が失われることがないからである。また、コンタクトプラグをよりメモリ機能体と接近して配置することができ、場合によってはメモリ機能体と重なるように配置することができるので、メモリ素子の微細化が容易となる。
【０２５９】
また、記憶保持に関する信頼性をより高めるためには、電荷を保持する機能を有する領域は、必ずしも膜状である必要はなく、離散的に存在することが好ましい。具体的には、上記領域は、電荷を保持しにくい材料、例えばシリコン酸化物中にドット状に分散していることが好ましい。
【０２６０】
また、導電膜もしくは半導体層を内部に含む絶縁体膜をメモリ機能体として用いることにより、導電体もしくは半導体中への電荷の注入量を自由に制御できるため、多値化しやすい効果がある。
【０２６１】
さらに、導電体もしくは半導体ドットを１つ以上含む絶縁体膜をメモリ機能体として用いることにより、電荷の直接トンネリングによる書込・消去が行ないやすくなり、低消費電力化の効果がある。
【０２６２】
また、上記メモリ機能体は、電界により分極方向が変化するＰＺＴ（チタン酸ジルコニウム鉛）、ＰＬＺＴ（（Ｐｂ_１−ｙＬａ_ｙ）（Ｚｒ_ｘＴｉ_１−ｘ）Ｏ_３）等の強誘電体膜を含んでもよい。この場合、分極により強誘電体膜の表面に実質的に電荷が発生し、この状態で電荷が保持される。したがって、上記強誘電体膜は、膜外から供給された電荷をトラップする膜と同様なヒステリシス特性を得ることができる。且つ、上記強誘電体膜の電荷保持は、膜外からの電荷注入の必要がなく、膜内の電荷の分極のみによってヒステリシス特性を得ることができるため、高速に書込・消去ができる効果がある。
【０２６３】
上記メモリ機能体は、電荷を逃げにくくする領域、または、電荷を逃げにくくする機能を有する膜をさらに含むことが好ましい。電荷を逃げにくくする機能を果たすものとしては、シリコン酸化膜等が挙げられる。
【０２６４】
上記メモリ機能体に含まれる電荷保持膜は、直接または絶縁膜を介してゲート電極の両側に形成されている。また、上記電荷保持膜は、直接、半導体基板（ウェル領域、ボディ領域、ソース／ドレイン領域または拡散領域）上に配置している。あるいは、上記電荷保持膜はゲート絶縁膜または絶縁膜を介して半導体基板（ウェル領域、ボディ領域、ソース／ドレイン領域または拡散領域）上に配置している。ゲート電極の両側の電荷保持膜は、直接または絶縁膜を介してゲート電極の側壁の全てまたは一部を覆うように形成されていることが好ましい。応用例としては、ゲート電極が下端部に凹部を有する場合には、直接または絶縁膜を介して凹部を完全にまたは凹部の一部を埋め込むように形成されていてもよい。
【０２６５】
上記ゲート電極は、メモリ機能体の側壁のみに形成されるか、または、メモリ機能体の上部を覆わないことが好ましい。つまり、上記ゲート電極の最上部の位置は、メモリ機能体の最上部の位置より高くならないことが好ましい。このような配置により、コンタクトプラグをよりゲート電極と接近して配置することができるので、メモリ素子の微細化が容易となる。また、このような単純な配置を有するメモリ素子は製造が容易であり、歩留まりを向上することができる。
【０２６６】
上記電荷保持膜として導電膜を用いる場合には、電荷保持膜が半導体基板（ウェル領域、ボディ領域、ソース／ドレイン領域または拡散領域）やゲート電極と直接接触しないように、絶縁膜を介して配置させることが好ましい。例えば、導電膜と絶縁膜との積層構造、絶縁膜内に導電体をドット状等に分散させた構造、ゲートの側壁に形成された側壁絶縁膜内の一部に導電体を配置した構造等が挙げられる。
【０２６７】
上記ソース／ドレイン領域は、半導体基板またはウェル領域と逆の導電型の拡散領域として、電荷保持膜のゲート電極と反対側の半導体基板の表面にそれぞれに形成されている。ソース／ドレイン領域と半導体基板またはウェル領域との接合は、不純物濃度が急峻であることが好ましい。これは、上記接合の不純物濃度が急峻であると、ホットエレクトロンやホットホールが低電圧で効率良く発生し、より低電圧で高速な動作が可能となるからである。ソース／ドレイン領域の接合深さは、特に限定されるものではなく、得ようとする半導体記憶装置の性能等に応じて、適宜調整することができる。なお、半導体基板としてＳＯＩ基板を用いる場合には、ソース／ドレイン領域は、表面半導体層の膜厚よりも小さな接合深さを有していてもよいが、表面半導体層の膜厚とほぼ同程度の接合深さを有していることが好ましい。
【０２６８】
また、上記ソース／ドレイン領域は、ゲート電極端とオーバーラップするように形成してもよいし、ゲート電極端と端が一致するように形成してもよいし、ゲート電極端に対してオフセットされるように形成してもよい。特に、ソース／ドレイン領域がゲート電極端に対してオフセットされている場合には、ゲート電極に電圧を印加したとき、電荷保持膜下のオフセット領域の反転しやすさが、メモリ機能体に蓄積された電荷量によって大きく変化し、メモリ効果が増大するとともに、短チャネル効果の低減をもたらすため好ましい。ただし、あまりオフセットしすぎると、ソース・ドレイン間の駆動電流が著しく小さくなるため、ゲート長方向に対して平行方向の電荷保持膜の厚さよりもオフセット量つまり、ゲート長方向における一方のゲート電極端から近い方のソース・ドレイン領域までの距離は短い方が好ましい。特に重要なことは、メモリ機能体中の電荷蓄積領域の少なくとも一部が、拡散領域であるソース／ドレイン領域の一部とオーバーラップしていることである。本発明の半導体記憶装置を構成するメモリ素子の本質は、メモリ機能体の側壁部にのみ存在するゲート電極とソース／ドレイン領域間の電圧差によりメモリ機能体を横切る電界によって記憶を書き換えることであるためである。
【０２６９】
また、上記ソース／ドレイン領域の一部は、チャネル領域表面、つまりゲート絶縁膜下面よりも高い位置に延設されていてもよい。この場合には、半導体基板内に形成されたソース／ドレイン領域上に、このソース／ドレイン領域と一体化した導電膜が積層されて構成されていることが適当である。この導電膜としては、例えば、ポリシリコン、アモルファスシリコン等の半導体、シリサイド、上述した金属、高融点金属等が挙げられる。これらの中でも、ポリシリコンが好ましい。これは、ポリシリコンは不純物拡散速度が半導体基板に比べて非常に大きいために、半導体基板内におけるソース／ドレイン領域の接合深さを浅くするのが容易で、短チャネル効果の抑制がしやすいためである。なお、この場合には、このソース／ドレイン領域の一部は、ゲート電極とともに、メモリ機能体の少なくとも一部を挟持するように配置することが好ましい。
【０２７０】
また、上記メモリ素子は、通常の半導体プロセスによって、例えば、ゲート電極の側方に単層または積層構造のサイドウォールスペーサを形成する方法と同様の方法によって形成することができる。具体的には、上記メモリ素子の形成方法に、次の（ａ）〜（ｅ）の方法等を利用することができる。
【０２７１】
（ａ） ゲート電極を形成した後、電荷保持膜、電荷保持膜／絶縁膜、絶縁膜／電荷保持膜、絶縁膜／電荷保持膜／絶縁膜等の電荷保持膜を含む単層膜または複層膜を形成し、適当な条件下でエッチバックしてこれらの膜をサイドウォールスペーサ状に残す方法。
【０２７２】
（ｂ） 絶縁膜または電荷保持膜を形成し、適当な条件下でエッチバックしてサイドウォールスペーサ状に残し、さらに電荷保持膜または絶縁膜を形成し、同様にエッチバックしてサイドウォールスペーサ状に残す方法。
【０２７３】
（ｃ） 粒子状の電荷保持材料を分散させた絶縁膜材料をゲート電極を含む半導体基板上に塗布または堆積し、適当な条件下でエッチバックして、絶縁膜材料をサイドウォールスペーサ形状に残す方法。
【０２７４】
（ｄ） ゲート電極を形成した後、上記単層膜または複層膜を形成し、マスクを用いてパターニングする方法。
【０２７５】
（ｅ） ゲート電極または電極を形成する前に、電荷保持膜、電荷保持膜／絶縁膜、絶縁膜／電荷保持膜、絶縁膜／電荷保持膜／絶縁膜等を形成し、これらの膜のチャネル領域となる領域に開口を形成し、その上全面にゲート電極材料膜を形成し、このゲート電極材料膜を、開口を含み、開口よりも大きな形状でパターニングする方法。
【０２７６】
また、上記メモリ素子を複数用いてメモリセルアレイを構成した場合、メモリ素子の最良の形態は、次の（１）〜（１０）の要件を満たすものである。
【０２７７】
（１） 複数のメモリ素子のゲート電極がワード線と一体となって形態である。
【０２７８】
（２） 上記ワード線の両側にはメモリ機能体が形成されている。
【０２７９】
（３） メモリ機能体内で電荷を保持するのは絶縁体、特にシリコン窒化膜である。
【０２８０】
（４） メモリ機能体はＯＮＯ膜で構成されており、シリコン窒化膜はゲート絶縁膜の表面と略並行な表面を有している。
【０２８１】
（５） メモリ機能体中のシリコン窒化膜はワード線及びチャネル領域とシリコン酸化膜で隔てられている。
【０２８２】
（６） メモリ機能体内のシリコン窒化膜と拡散層とがオーバーラップしている。
【０２８３】
（７） ゲート絶縁膜の表面と略並行な表面を有するシリコン窒化膜とチャネル領域または半導体層とを隔てる絶縁膜の厚さと、ゲート絶縁膜の厚さが異なる。
【０２８４】
（８） １個のメモリ素子の書込み及び消去動作は単一のワード線により行なう。
【０２８５】
（９） メモリ機能体の上には書込み及び消去動作を補助する機能を有する電極（ワード線）がない。
【０２８６】
（１０） メモリ機能体の直下で拡散領域と接する部分に拡散領域の導電型と反対導電型の不純物濃度が濃い領域を有する。
【０２８７】
上記（１）〜（１０）の要件を全て満たす場合が最良の形態となるが、無論、必ずしも上記要件を全て満たす必要はない。
【０２８８】
上記（１）〜（１０）の要件のうち複数の要件が満される場合、特に好ましい組み合わせが存在する。例えば、（３）メモリ機能体内で電荷を保持するのが絶縁体、特にシリコン窒化膜であり、（９）メモリ機能体の上には書込み及び消去動作を補助する機能を有する電極（ワード線）がなく、（６）メモリ機能体内の絶縁膜（シリコン窒化膜）と拡散層とがオーバーラップしている、場合である。上記メモリ機能体内で電荷を保持しているのが絶縁体であり、且つ、メモリ機能体の上には書込み及び消去動作を補助する機能を有する電極がない場合には、メモリ機能体内の絶縁膜（シリコン窒化膜）と拡散層とがオーバーラップしている場合にのみ、書込み動作が良好に行なわれることを発見した。すなわち、要件（３）及び（９）を満たす場合は、要件（６）を満たすことが必須であることが判明した。一方、メモリ機能体内で電荷を保持するのが導電体である場合はメモリ機能体内の導電体と拡散層がオーバーラップしていない場合でも、書込み動作を行なうことができた（メモリ機能体内の導体が書込み電極との容量カップリングにより書込み補助を行なうため）。また、メモリ機能体の上に書込み及び消去動作を補助する機能を有する電極がある場合は、メモリ機能体内の絶縁膜と拡散層がオーバーラップしていない場合でも、書込み動作を行なうことができた。
【０２８９】
しかしながら、メモリ機能体内で電荷を保持するのが導電体ではなく絶縁体であり、且つ、メモリ機能体の上には書込み及び消去動作を補助する機能を有する電極がない場合には、以下のような非常に大きな効果を得ることができる。
【０２９０】
まず、ビット線コンタクトをワード線側壁のメモリ機能体と、より接近して配置することができ、またはメモリ素子間の距離が接近しても複数のメモリ機能体が干渉せず記憶情報を保持できるので、メモリ素子の微細化が容易となる。メモリ機能体内の電荷保持領域が導体の場合、容量カップリングによりメモリ素子間が近づくにつれて電荷保持領域間で干渉が起き、記憶情報を保持できなくなる。
【０２９１】
また、上記メモリ機能体内の電荷保持領域が絶縁体（例えばシリコン窒化膜）である場合、メモリセル毎にメモリ機能体を独立させる必要が無くなる。例えば、複数のメモリセルで共有される１本のワード線の両側に形成されたメモリ機能体は、メモリセル毎に分離する必要が無く、１本のワード線の両側に形成されたメモリ機能体を、ワード線を共有する複数のメモリセルで共有することが可能となる。そのため、メモリ機能体を分離するフォト、エッチング工程が不要となり製造工程が簡略化される。更には、フォトの位置合わせマージン、エッチングの膜減りマージンが不要となるため、メモリセル間のマージンを縮小できる。したがって、メモリ機能体内の電荷保持領域が導電体（例えば多結晶シリコン膜）である場合と比較して、同じ微細加工レベルで形成しても、メモリセル占有面積を微細化できる効果がある（メモリ機能体内の電荷保持領域が導電体である場合、メモリ機能体をメモリセル毎に分離するフォト、エッチング工程が必要となり、フォトの位置合わせマージン、エッチングの膜減りマージンが必要となる）。
【０２９２】
更に、メモリ機能体の上には書込み及び消去動作を補助する機能を有する電極がなく素子構造が単純であるから工程数が減少し、歩留まりを向上し、論理回路やアナログ回路を構成するトランジスタとの混載を容易にすることができる。
更にまた、非常に重要な設計事項として、メモリ機能体内の電荷保持領域が絶縁体であり、且つ、メモリ機能体の上に書込み及び消去動作を補助する機能を有する電極がない場合（上記２つの条件を満たすことにより、セル占有面積の縮小、製造方法の簡略化による歩留まり向上、ならびにコスト削減という非常に重要な効果が得られる）であっても、メモリ機能体内の電荷保持領域と拡散層をオーバーラップさせることにより、非常に低電圧で書込、消去が可能となることを我々は発見した。具体的には、５Ｖ以下という低電圧により書込み及び消去動作が行なわれることを確認した。この作用は回路設計上非常に大きな効果を有する。つまり、フラッシュメモリのような高電圧をチップ内で作る必要がなくなるため、莫大な占有面積が必要となるチャージポンピング回路を省略、もしくは、規模を小さくすることが可能となる。特に、小規模容量のメモリを調整用としてロジックＬＳＩに内蔵する場合、メモリ部の占有面積はメモリセルよりも、メモリセルを駆動する周辺回路の占有面積が支配的となるため、メモリセル用電圧昇圧回路を省略、もしくは、規模を小さくすることは、チップサイズを縮小させるためには最も効果的となる。
【０２９３】
以上より、要件（３）、（９）及び（６）を満たすことが特に好ましいのである。
【０２９４】
上記メモリ素子及び論理素子を組み合わせた半導体記憶装置は、電池駆動の携帯電子機器、特に携帯情報端末に用いることができる。携帯電子機器としては、携帯情報端末、携帯電話、ゲーム機器等が挙げられる。
【０２９５】
【発明の効果】
以上より明らかなように、本発明の半導体記憶装置によれば、特定のワード線及びビット線を選択することにより特定のメモリ機能体の記憶情報を書換えまたは読み出すことが可能となる。
【０２９６】
更に、記憶素子のゲート電極の側壁には、電荷を保持する機能または分極を保持する機能を有するメモリ機能体が形成されており、チャネル領域とゲート電極とを隔てるゲート絶縁体とは分離されて形成されている。そのため、上記ゲート絶縁体を薄膜化して短チャネル効果を抑制するのが容易である。したがって、上記記憶素子を微細化し、製造コストを削減することができる。
【図面の簡単な説明】
【図１】図１は本発明の実施の形態１のメモリセルアレイの概略平面図である。
【図２】図２は図１の２−２線の概略断面図である。
【図３】図３は図１の３−３線の概略断面図である。
【図４】図４は上記実施の形態１メモリセルアレイの回路図である。
【図５】図５は上記実施の形態１メモリセルアレイの変形例の概略平面図である。
【図６】図６は本発明の実施の形態２のメモリセルアレイの概略平面図である。
【図７】図７は図６の７−７線の概略断面図である。
【図８】図８は本発明の実施の形態３のメモリセルアレイの概略平面図である。
【図９】図９は上記実施の形態３メモリセルアレイの第１層メタル配線の配置を説明するための図である。
【図１０】図１０は本発明の実施の形態４のメモリセルアレイのメモリセルの形成工程を説明するための図である。
【図１１】図１１は上記実施の形態４メモリセルアレイの概略断面図である。
【図１２】図１２は上記実施の形態４のメモリセルアレイの他の概略断面図である。
【図１３】図１３は上記実施の形態４のメモリセルアレイのメタル配線の配置を説明するための図である。
【図１４】図１４は上記実施の形態４のメモリセルアレイの変形例の概略断面図である。
【図１５】図１５は本発明の実施の形態６の半導体記憶装置のブロック図である。
【図１６】図１６は携帯電子機器のブロック図である。
【図１７】図１７は本発明の実施の形態９の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図１８】図１８は図１７のメモリ素子の変形例の概略断面図である。
【図１９】図１９は本発明の半導体記憶装置に使用されるメモリ素子の書込み動作を説明するための図である。
【図２０】図２０は本発明の半導体記憶装置に使用されるメモリ素子の書込み動作を説明するための図である。
【図２１】図２１は本発明の半導体記憶装置に使用されるメモリ素子の消去動作を説明するための図である。
【図２２】図２２は本発明の半導体記憶装置に使用されるメモリ素子の消去動作を説明するための図である。
【図２３】図２３は本発明の半導体記憶装置に使用されるメモリ素子の読出し動作を説明するための図である。
【図２４】図２４は本発明の実施の形態１０の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図２５】図２５は図２４のメモリ素子の一部の拡大図である。
【図２６】図２６は図２４のメモリ素子の変形例の一部の拡大図である。
【図２７】図２７は図２４のメモリ素子の電気特性を示すグラフである。
【図２８】図２８は図２４のメモリ素子の他の変形例の一部の拡大図である。
【図２９】図２９は本発明の実施の形態１１の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３０】図３０は本発明の実施の形態１２の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３１】図３１は本発明の実施の形態１３の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３２】図３２は本発明の実施の形態１４の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３３】図３３は本発明の実施の形態１５の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３４】図３４は本発明の実施の形態１６の半導体記憶装置に使用されるメモリ素子の要部の概略断面図である。
【図３５】図３５は本発明の実施の形態１７の半導体記憶装置に使用されるメモリ素子の電気特性を示すグラフである。
【図３６】図３６は従来のフラッシュメモリのメモリセルアレイの概略平面図である。
【図３７】図３７は図３６の３７−３７線の概略断面図である。
【図３８】図３８は上記従来のフラッシュメモリの電気特性を示すグラフである。
【符号の説明】
１０１，２１１，２８６，１１０１，２１０１，３１０１，４１０１ 半導体基板
１０２，１１０２，２１０２，４１０２ ｐ型ウエル領域
１０４，２１７ ゲート電極
１０５ａ，１０５ｂ，１１０５ａ，１１０５ｂ メモリ機能体
１０７ａ，２１２，２６１ 第１の拡散領域
１０７ｂ，２１３，２６２ 第２の拡散領域
１２２，２７２，１１１１ チャネル領域
１３１ａ，２６１ 第１のメモリ機能体
１３１ｂ，２６２，２６２ａ，２６２ｂ 第２のメモリ機能体
２１４，１１０３，４１０３ ゲート絶縁膜
２８７ ボディ領域
１１０４，２１０４，３１０４，４１０４ ワード線
１１０７，２１０７，３１０７ ソース／ドレイン拡散領域
１１０８，２１０８，３１０８ 素子分離領域
１１１０，２１１０，３１１０ 活性領域
１１３１，２１３１，３１３１，４１３１，４２３１ コンタクト
１１３２，２１３２，３１３２，４１３２ ビット線
４１０７ 拡散領域
４１０８ トレンチ素子分離
Ｍ１１，Ｍ２１，…，Ｍ３３ メモリセル
ｍ１，ｍ２ メモリ機能体[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device, an operation method thereof, and a portable electronic device. More specifically, the present invention relates to a semiconductor memory device including a field effect transistor having a memory function body having a function of retaining electric charge or polarization, an operation method thereof, and a portable electronic device including such a semiconductor memory device.
[0002]
[Prior art]
A flash memory, which is one of nonvolatile memories, includes a memory cell array as a semiconductor storage device.
[0003]
Conventionally, as a memory cell array of a flash memory, there is one as shown in FIG. 36 (for example, see Patent Document 1).
[0004]
FIG. 36 is a schematic plan view of the memory cell array. FIG. 37 is a schematic sectional view taken along line 37-37 in FIG. 36 and 37, reference numeral 901 denotes a semiconductor substrate, 902 denotes a channel region, FG denotes a floating gate, WL denotes a word line, SL denotes a source line, BL denotes a bit line, 908 denotes an element isolation region, and 931 denotes an insulating film. ing.
[0005]
The memory cell array includes a plurality of memory cells arranged in a matrix. Each memory cell has a floating gate FG, as shown in FIG. 37, and retains the memory as the amount of charge in the floating gate FG.
[0006]
According to the memory cell array having the above configuration, a specific word line or bit line is selected and a predetermined voltage is applied, so that a desired memory cell can be rewritten and read.
[0007]
FIG. 38 is a diagram schematically showing a characteristic of a drain current (Id) versus a gate voltage (Vg) when the amount of charge in the floating gate FG of the memory cell changes.
[0008]
When the amount of negative charges in the floating gate FG increases, the threshold value increases, and the Id-Vg curve moves substantially in parallel in the direction in which Vg increases (the direction of the arrow in the figure).
[0009]
[Patent Document 1]
JP 05-304277 A
[0010]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional memory cell array, the floating gate FG is arranged between the word line WL also serving as a gate electrode and the channel region 902. Then, an insulating film 931 is provided between the floating gate FG and the word line WL and between the floating gate FG and the channel region 902 in order to prevent charge leakage from the floating gate FG.
[0011]
As described above, the floating gate FG and the insulating film 931 exist between the word line WL and the channel region 902, and it is difficult to reduce the thickness of the insulating film 931. As a result, the conventional memory cell array has a problem in that the memory cell cannot be miniaturized and thus cannot be miniaturized.
[0012]
Therefore, an object of the present invention is to provide a semiconductor memory device that can be easily reduced in size.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device according to a first aspect of the present invention
A semiconductor substrate having a surface divided into an element isolation region and an active region,
A storage element that is a plurality of field-effect transistors formed in the active region and arranged in a matrix,
A word line connected to the gate electrode of the storage element in the same row;
A bit line electrically connected in common to a source / drain diffusion region of the storage element in the same column via a contact;
Regarding two adjacent bit lines, one bit line is electrically connected to one of the source / drain diffusion regions in the same column, while the other bit line is electrically connected to the source / drain diffusion region in the same column. Electrically connected to the other of
The storage element is
The gate electrode formed on the semiconductor substrate via a gate insulating film,
Two memory function bodies formed on both sides of the gate electrode and having a function of retaining charge or polarization;
A channel region disposed below the gate insulating film;
The source / drain diffusion regions disposed on both sides of the channel region;
Including
The amount of current flowing from one of the source / drain diffusion regions to the other of the source / drain diffusion regions when a voltage is applied to the gate electrode changes depending on the amount of charge or polarization held in the memory function body. It is characterized by.
[0014]
According to the semiconductor memory device having the above configuration, since the two memory function bodies formed on both sides of the gate electrode are independent of the gate insulating film, the memory function performed by the memory function body and the gate insulating film play the role. It is separated from the transistor operation function. Thus, it is easy to reduce the thickness of the gate insulating film while having a sufficient memory function and to suppress the short channel effect. Therefore, since the storage element can be miniaturized, the size can be easily reduced, and the manufacturing cost can be suppressed.
[0015]
Further, since the two memory function bodies formed on both sides of the gate electrode are separated by a word line, interference at the time of rewriting is effectively suppressed. In other words, since the two memory functional units are separated by the gate electrode, the distance between the two memory functional units can be reduced. Therefore, the memory element can be further miniaturized.
[0016]
Further, since the memory function bodies are formed on both sides of the gate electrode, a memory cell array having memory cells having a structure in which the memory function bodies are physically separated can be realized.
[0017]
In addition, by selecting a specific word line and a specific bit line, it is possible to rewrite or read information stored in a specific memory function body.
[0018]
In the semiconductor memory device according to one embodiment, since at least a part of the memory function body is formed so as to overlap with a part of the source / drain diffusion region, the reading speed can be sufficiently increased. .
[0019]
In one embodiment, the contact is commonly connected to the adjacent source / drain diffusion regions in the same row.
[0020]
According to the semiconductor memory device of the above embodiment, the contacts are commonly connected to adjacent source / drain diffusion regions in the same row. That is, two adjacent source / drain diffusion regions in the same row share one bit line. Therefore, the area occupied by the element isolation region can be reduced and the shape of the element isolation can be simplified. Therefore, high integration is possible, and the manufacturing cost can be further reduced.
[0021]
Further, by sharing the source / drain diffusion regions between adjacent storage elements in the same column, the area of the memory cell can be significantly reduced.
[0022]
In one embodiment of the present invention, the memory function unit performs a rewrite operation and a read operation as independent storage units.
[0023]
According to the semiconductor memory device of the above embodiment, two or more bits of data can be stored in one memory element, so that the cost per bit unit is further reduced.
[0024]
In one embodiment, the contact has an elliptical column shape.
[0025]
According to the semiconductor memory device of the above embodiment, when the shape of the contact is an elliptical column, the formation of the contact is simplified.
[0026]
Further, since the contact has an elliptical column shape, the bit line interval can be narrowed, and a semiconductor memory device with a small occupied area can be realized.
[0027]
In one embodiment of the present invention, the contact is electrically connected to the source / drain diffusion region via an elliptical conductor.
[0028]
According to the semiconductor memory device of the above embodiment, since the contact is electrically connected to the source / drain diffusion region via the elliptical conductor, even if the etching apparatus is restricted, the high density memory can be used. Is feasible.
[0029]
In one embodiment, the memory functional unit has a surface substantially parallel to the surface of the gate insulating film and has a function of retaining charge or polarization; An insulating film formed between the active region and the active region, wherein the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more.
[0030]
According to the semiconductor memory device of the above embodiment, the thickness of the insulating film formed between the charge holding film and the active region is smaller than the thickness of the gate insulating film and is 0.8 nm or more. Thus, the reliability of the storage element can be improved.
[0031]
In addition, since the memory function body includes a charge holding film having a surface substantially parallel to the surface of the gate insulating film and having a function of holding charge or polarization, it is possible to reduce a variation in a memory effect of the storage element. it can. Therefore, variation in the read current of the storage element can be suppressed. Furthermore, since the change in the characteristics of the storage element during storage is reduced, the storage characteristics of the semiconductor memory device are improved.
[0032]
In one embodiment, the memory functional unit has a surface substantially parallel to the surface of the gate insulating film and has a function of retaining charge or polarization; An insulating film formed between the gate insulating film and the active region, wherein the thickness of the insulating film is larger than the thickness of the gate insulating film and is equal to or less than 20 nm.
[0033]
According to the semiconductor memory device of the embodiment, the thickness of the insulating film formed between the charge holding film and the active region is larger than the thickness of the gate insulating film and is equal to or less than 20 nm. The reliability of the storage element can be improved.
[0034]
Since the memory function body includes a charge holding film having a surface substantially parallel to the surface of the gate insulating film and having a function of holding charge or polarization, the operation of the storage element, for example, the rewriting operation can be performed at high speed. it can.
[0035]
In one embodiment, the memory function body has a silicon nitride film and a silicon oxide film sandwiching the silicon nitride film.
[0036]
According to the semiconductor memory device of the above embodiment, the structure in which the silicon nitride film is sandwiched between the silicon oxide films can be manufactured in almost the same process as that of the logic LSI (large-scale integrated circuit). realizable.
[0037]
Since the memory functional unit has a structure in which a silicon nitride film is sandwiched between silicon oxide films, the efficiency of charge injection into the memory functional unit during a rewrite operation is increased, and higher-speed operation is possible.
[0038]
In one embodiment, the memory function body includes an insulating film, and a plurality of dot-shaped metal bodies formed in the insulating film,
The diameter of the metal body is in the range of 0.1 nm to 20 nm.
[0039]
According to the semiconductor memory device of the embodiment, the memory function body includes the insulating film and the plurality of dot-shaped metal bodies formed in the insulating film and having a diameter of 0.1 nm or more and 20 nm or less. Operation at lower voltage is possible, and low power consumption can be achieved. Alternatively, higher-speed operation becomes possible, and a high-speed memory can be realized.
[0040]
A semiconductor memory device according to one embodiment includes a column decoder, a sense amplifier, and a row decoder, and is formed of one chip.
[0041]
Since the semiconductor memory device of the embodiment includes the column decoder, the sense amplifier, and the row decoder and is formed of one chip, a high-speed nonvolatile high-density memory can be realized.
[0042]
In addition, when a plurality of semiconductor memory devices of the present invention arranged and a column decoder, a sense amplifier, and a row decoder are used, a specific storage element can be selected to perform rewrite and read operations.
[0043]
Further, since it is easy to mix the semiconductor transistor of the present invention with normal transistors constituting logic circuits and analog circuits such as column decoders, sense amplifiers and row decoders, the manufacturing process is easy and low cost. Is provided.
[0044]
The semiconductor storage device according to one embodiment includes a liquid crystal driver.
[0045]
According to the semiconductor memory device of the embodiment, since the liquid crystal driver is provided, a high-performance liquid crystal driver can be manufactured at low cost by incorporating a memory for storing initial values of the liquid crystal driver in the liquid crystal driver. Becomes
[0046]
A method of operating a semiconductor memory device according to a second invention is the method of operating a semiconductor memory device according to the first invention, wherein the method is connected to a channel region of the storage element to which the memory function body in which information to be read is stored belongs. Before applying a potential for performing a read operation to the word line thus set, all the bit lines located on one side of the storage element are precharged to a first potential, and All the bit lines located on the other side are precharged to the second potential.
[0047]
According to the operation method of the semiconductor memory device having the above configuration, all the bit lines located on one side of the storage element to which the memory function body to be operated belongs are precharged to the first potential, and the storage element Are precharged to the second potential. After that, a potential for performing a reading operation is applied to a word line connected to a channel region of the storage element. According to such an operation method, reading, writing, and erasing operations by random access with a relatively simple control circuit can be performed, the area occupied by the memory can be further reduced, the operation efficiency can be improved, and high-speed operation can be performed. .
[0048]
Further, all the bit lines located on one side of the storage element are precharged to the first potential, and all the bit lines located on the other side of the storage element are connected to the second potential. Since the precharge is performed to the potential, a noise current in detecting a current flowing through the selected field effect transistor (memory element) can be reduced.
[0049]
A portable electronic device according to a third aspect is provided with the semiconductor memory device according to the first aspect.
[0050]
According to the portable electronic device having the above configuration, the semiconductor memory device according to the first aspect of the invention has low power consumption and is high-speed nonvolatile. Therefore, the function realized by using a plurality of components can be realized only by the semiconductor memory device of the first invention. As a result, a small-sized portable electronic device with low power consumption and a small number of components can be realized.
[0051]
By using the semiconductor memory device of the present invention in a portable electronic device, the manufacturing cost of the control circuit can be reduced, so that the cost of the portable electronic device itself can be reduced. Alternatively, the capacity of the nonvolatile memory included in the control circuit can be increased to enhance the functions of the portable electronic device.
[0052]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0053]
(Embodiment 1)
In this embodiment, a semiconductor memory device (memory cell array) configured by arranging memory elements as an example of a storage element will be described.
[0054]
FIG. 1 is a schematic plan view of the memory cell array according to the first embodiment, FIG. 2 is a schematic sectional view taken along line 2-2 in FIG. 1, and FIG. 3 is a schematic view taken along line 3-3 in FIG. It is sectional drawing. However, in FIG. 1, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplification. Although FIGS. 1 to 3 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary.
[0055]
According to the memory cell array, as shown in FIG. 2, the semiconductor substrate 1101 has the p-type well region 1102. As shown in FIG. 1, the surface of the p-type well region 1102 is divided into an element isolation region 1108 and a plurality of active regions 1110 arranged in a matrix. In each of the active regions 1110, a memory element as an example of a storage element is formed. Further, word lines 1104 (WL1, WL2, WL3) functioning as gate electrodes of memory elements are formed on the semiconductor substrate 1101 so as to extend in the horizontal direction in FIG. 1 and are arranged side by side in the vertical direction in FIG. ing.
[0056]
As shown in FIG. 2, a silicon nitride film 1109 is formed on the side and upper surfaces of the word lines 1104 (WL1, WL2, WL3). That is, the side and top surfaces of the word line 1104 are covered with the silicon nitride film 1109. In the silicon nitride film 1109, portions existing on both side walls of the word line 1104 are memory function bodies 1105a and 1105b. A gate insulating film 1103 is formed between the word line 1104 and each active region 1110. The region below the gate insulating film 1103 is a channel region 1111 of the memory element, and source / drain diffusion regions 1107 are formed on both sides of the channel region 1111. Then, as shown in FIG. 1, the source / drain diffusion regions 1107 in the same column are commonly electrically connected to the bit lines 1132 (BL1, BL2, BL3, BL4). Regarding two adjacent bit lines 1132 (for example, BL1 and BL2) among the bit lines 1131, one bit line 1132 (BL1) is electrically connected to one of the source / drain diffusion regions 1107 in the same column, while the other is connected to the other. Bit line 1132 (BL2) is electrically connected to the other of the source / drain diffusion regions 1107 in the same column. The bit line 1132 (BL1, BL2, BL3, BL4) is electrically connected to the source / drain diffusion region 1107 via a contact 1131 (see FIG. 2).
[0057]
The contact 1131 is formed by filling a conductive material in a contact hole (a hole connecting the source / drain diffusion region 1107 and the first-layer metal wiring). The contact hole needs to be sufficiently large to connect the source / drain diffusion region 1107 and the first layer metal wiring, and has a length in a direction connecting the source / drain diffusion region 1107 and the first layer metal wiring. Need to be longer. Therefore, the shape of the contact hole is an elliptical column shape. That is, in FIG. 1, for example, an elliptical column-shaped contact 1131 is formed in a part C surrounded by a practical square. Elliptical column-shaped contacts 1131 are also formed in portions other than the portion C.
[0058]
By using the above-mentioned elliptical column-shaped contact hole, a margin between metal wirings becomes unnecessary and an occupied area can be reduced, as compared with a case where connection is made by metal wiring or the like at the top, and the manufacturing process is simplified. can do. That is, the line spacing of the bit lines 1132 can be reduced, and the manufacturing process can be simplified.
[0059]
The bit line 1132 is formed on the element isolation region 1108 as shown in FIG. An interlayer insulating film 1141 exists between the bit line 1132 and the silicon nitride film 1109.
[0060]
FIG. 4 shows a circuit diagram of the memory cell array. In FIG. 4, the memory elements included in the memory array are represented by symbols representing ordinary field effect transistors for simplification. In the memory cell Mij (i = 1, 2, 3, j = 1, 2, 3) composed of the memory element, the gate electrode is connected to the word line WLi (i = 1, 2, 3) by the two sources / One of the drain diffusion regions 1107 is connected to a bit line BLj (j = 1, 2, 3), and the other of the source / drain diffusion regions 1107 is connected to a bit line BLj + 1 (j = 1, 2, 3). Each of the memory cells Mij includes two memory function bodies m1 and m2 (1105a and 1105b).
[0061]
In order to operate the memory cell array, a voltage required for an operation method of the memory cell Mij may be applied to a desired memory cell via a specific word line WLi, a bit line BLj, and a bit line BLj + 1. For example, when writing to one of the memory function bodies m1 and m2 of the memory cell M11, +5 V may be applied to the word line WL1, + 5V to the bit line BL1, and 0V to the bit line BL2. To write data to the other of the memory function bodies m1 and m2 of the memory cell M11, it is sufficient to apply +5 V to the word line WL1, 0 V to the bit line BL1, and +5 V to the bit line BL2. At this time, for example, 0 V may be applied to other unselected word lines and unselected bit lines.
[0062]
Note that a method for operating the storage element included in the memory cell Mij will be described in detail in another embodiment.
[0063]
As is apparent from the above description, the memory cell array according to the present embodiment has memory cells Mij arranged in a matrix. One memory cell Mij can store two bits, and the gate insulating film 1103 can be thinned. Therefore, since the memory cell Mij can be easily miniaturized, the size of the memory cell array can be easily reduced, and the manufacturing cost can be reduced.
[0064]
Further, as described above, the process of forming the memory element is very close to a normal CMOS (complementary metal oxide semiconductor) process, and is a conventional EEPROM (Electrically Erasable Programmable ROM: an electrically erasable read-only). It can be manufactured very easily as compared with a nonvolatile memory having a floating gate such as a memory. Therefore, it is easy to manufacture the memory cell array of the present invention, and it is also easy to mix logic circuits in the memory cell array.
[0065]
In the memory element used in the above embodiment, the side surface and the upper surface of the gate electrode (word line 1104) are covered with the silicon nitride film 1109, but only the side surface of the gate electrode (word line 1104) is covered with the silicon nitride film. You may.
[0066]
Further, instead of the silicon nitride film 1109, a memory function body having a function of retaining charge or polarization may be formed. The memory function body is formed on both sides of the word line on the active region. Such a memory function body will be described later in an eleventh embodiment.
[0067]
The memory function body may be composed of, for example, a silicon nitride film holding electric charges and a silicon oxide film sandwiching the silicon nitride film. In this case, the silicon nitride film preferably overlaps the source / drain diffusion regions. When a memory element including such a memory function body is used in the semiconductor memory device of the present embodiment, the reading speed of the semiconductor memory device can be sufficiently increased.
[0068]
Further, it is preferable that the memory function body includes a charge holding film disposed substantially in parallel with the surface of the gate insulating film. When a memory element including such a memory function body is used in the semiconductor memory device of the present embodiment, variation in the memory effect of the memory element can be reduced, so that variation in the read current of the semiconductor memory device can be suppressed. . Furthermore, since the change in the characteristics of the memory element during storage can be reduced, the storage characteristics of the semiconductor memory device are improved.
[0069]
Further, it is preferable that the charge retention film included in the memory function body has a portion having a surface substantially parallel to the surface of the gate insulating film and a portion extending substantially parallel to the side surface of the gate electrode. When such a memory function body is used in the semiconductor memory device of the present embodiment, the rewriting speed of the memory element is increased, so that the speed of the rewriting operation of the semiconductor memory device can be increased.
[0070]
In the case where an insulating film is formed between the charge holding film and the channel region or the well region, the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more. It is preferable that When a memory element including such an insulating film is used in the semiconductor memory device of this embodiment, it is possible to reduce the voltage of the write operation and the erase operation or to increase the speed of the write operation and the erase operation. Further, since the memory effect of the memory element increases, the reading speed of the semiconductor memory device can be increased.
[0071]
Further, when an insulating film is formed on the insulating film between the charge holding film and the channel region or the well region, the thickness of the insulating film is larger than the thickness of the gate insulating film and may be 20 nm or less. preferable. When a memory element including such an insulating film is used for the semiconductor memory device of this embodiment, retention characteristics can be improved without deteriorating the short-channel effect of the memory element. However, sufficient memory retention performance can be obtained.
[0072]
Further, the memory element of the present embodiment preferably includes two memory functional units each including a silicon nitride film and a silicon oxide film sandwiching the silicon nitride film. When such a memory element is used in the semiconductor memory device of this embodiment, the operation speed of the semiconductor memory device can be improved, and the reliability can be improved.
[0073]
FIG. 5 shows a modified example of the memory cell array.
[0074]
In the above modification, the distance between the contacts can be reduced in the direction in which the word lines 1104 extend, so that the distance between the bit lines can be reduced. In this case, for example, an elliptical column-shaped contact is formed at a portion C5 surrounded by a practical square in FIG. Elliptical column-shaped contacts are also formed in portions other than the portion C5. Each of the contacts is electrically connected to two adjacent source / drain diffusion regions in the same row.
[0075]
Also in the above modification, the use of the elliptical column-shaped contact eliminates the need for a margin between the metal wirings and reduces the occupied area as compared with the case where the connection is made by the upper metal wiring or the like. Is also simplified. That is, the line spacing of the bit lines 1132 can be reduced, and the manufacturing process can be simplified.
[0076]
In the above embodiment, the gate electrode of the memory element is a part of the word line 1104, but may not be a part of the word line. That is, the gate electrode of the memory element may be separate from the word line. In this case, the word lines connect the gate electrodes of the memory elements in the same row.
[0077]
(Embodiment 2)
The memory cell array according to the present embodiment will be described with reference to FIGS.
[0078]
FIG. 6 is a schematic plan view of the memory cell array according to the second embodiment of the present invention, and FIG. 7 is a schematic sectional view taken along line 7-7 in FIG. The circuit diagram of the memory cell array is the same as FIG. However, in FIG. 6, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. 6 and 77 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary.
[0079]
As can be seen from FIG. 6, the memory cell array according to the present embodiment is different from the memory cell array according to the first embodiment in that two memory elements adjacent to each other in the same column (storage elements arranged in the vertical direction on the paper of FIG. 6) are used. ) Shares one source / drain diffusion region 2107. As described above, the adjacent storage elements in the same column share one source / drain diffusion region 2107, so that the area of the source / drain diffusion region 2107 itself is reduced. That is, the number of source / drain diffusion regions 2107 required in the memory cell array is reduced. Further, a margin by the element isolation region 2108 for isolating the source / drain diffusion region 2107 itself becomes unnecessary. That is, the element isolation region 2108 does not need to be formed between storage elements adjacent to each other in the same column. Therefore, the area of the memory cell can be significantly reduced.
[0080]
In addition, since the shape of the element isolation region 2108 is simplified, manufacturing becomes easy and the yield is improved.
[0081]
Also in the memory cell array of the present embodiment, a voltage for a desired operation can be applied to a desired memory cell by the same method as in the first embodiment.
[0082]
Also in the memory cell array of the present embodiment, an elliptical column-shaped contact 2131 shown in FIG. 7 is formed in, for example, a portion C6 surrounded by a solid square in FIG. Also, elliptical column-shaped contacts 2131 are formed in portions other than the portion C6. The contact 2131 is made of a conductive material, and is designed to electrically connect the bit line 2132 (BL1, BL2, BL3, BL4) to the source / drain diffusion region 2107 of the active region 2110. I have.
[0083]
By using the contact 2131 having an elliptic column shape, a margin between the metal wires is not required, the occupied area can be reduced, and the manufacturing process can be simplified, as compared with the case where the upper metal wires are connected. . That is, the interval between the bit lines 2132 can be narrowed, and the manufacturing process can be simplified.
[0084]
Further, according to the memory cell array of the present embodiment, the pitch between word lines 2104 (WL1, WL2, WL3) can be narrower than in the memory cell array of the first embodiment. Therefore, the memory cell array according to the present embodiment can be made smaller than the memory cell array according to the first embodiment, and the manufacturing cost can be further reduced.
[0085]
When two adjacent bit lines 2104 are selected from the bit lines 2132, one active region 2110 is defined between the two bit lines 2132. The plurality of source / drain diffusion regions 2107 belonging to the specified active region 2110 are alternately connected to one of the two bit lines 2132 and the other of the two bit lines 2132. That is, one of two adjacent source / drain diffusion regions of the plurality of source / drain diffusion regions 2107 is connected to one of the two bit lines 2132, and the other of the source / drain diffusion regions is the two source / drain diffusion regions. Is connected to the other one of the bit lines 2132. Alternatively, since every other source / drain diffusion region 2107 belonging to the specified active region 2110 becomes a source region or a drain region, one of the two bit lines 2104 belongs to the specified active region 2110. Expressed as being connected to one of the source / drain diffusion regions 2107 and the other of the selected two bit lines 2104 being connected to the other of the source / drain diffusion regions 2107 belonging to the specified active region 2110 You can also.
[0086]
Hereinafter, the operation of the memory cell array will be described with reference to FIG.
[0087]
First, a method for reading the memory cell array will be described. Here, for example, it is assumed that the storage information of the memory function body m1 on the bit line BL2 side of the memory cell M22 is read.
[0088]
First, the bit lines BL1 and BL2 are precharged to a logic level L, and the bit lines BL3 and BL4 are precharged to a logic level H. After the precharge of the bit lines BL1, BL2, BL3, and BL4 is completed, the word line WL2 is set to the logic level H. The moment the word line WL2 goes to the logic level H, the memory cell M22 is turned on. At this time, a high voltage (logic level H-logic level L) is applied between the source and the drain of the memory cell M22 to cause a current to flow, but the current amount changes depending on the state of the memory function body m1. Therefore, the state of the memory function body m1 can be known by detecting the amount of current flowing through the bit line BL2 or the bit line BL3 or monitoring the potential change of the bit line BL2 or the bit line BL3.
[0089]
In the above read operation, if the bit line BL1 is not precharged to the logic level L, the memory cell M21 is turned on at the moment when the word line WL2 becomes the logic level H, and the bit line BL1 The current flows to Such a current hinders detection of a current flowing through the selected memory cell M22. Therefore, it is preferable that the bit line BL1 be precharged to the same logic level L as the bit line BL2. Similarly, it is preferable that the bit line BL4 be precharged to the same logic level H as the bit line BL3.
[0090]
On the other hand, when recalling the storage information of the memory function body m2 on the bit line BL3 side of the memory cell M22, the bit lines BL1 and BL2 are precharged to the logic level H and BL3 and BL4 are precharged to the logic level L. After charging, the word line WL2 may be set to the logic level H.
[0091]
Table 1 below shows an example of a specific voltage in each of the write, read, and erase operations of the memory cell array according to the present embodiment. In Table 1, Lbw, Hbw, Lww, and Hww are the low-level potential of the bit line, the high-level potential of the bit line, the low-level potential of the word line, and the high-level potential of the word line during writing, respectively. Lbr, Hbr, Lwr, and Hwr are the low level potential of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level potential of the word line at the time of reading, respectively. Lbe1, Lbe2, Hbe, Lwe, and Hwe are the low level potential 1 of the bit line, the low level potential 2 of the bit line, the high level potential of the bit line, the low level potential of the word line, and the low level potential of the word line at the time of erasing, respectively. High level potential. .., Lwe, and Hwe are specific examples of specific voltages in parentheses in Table 1.
[0092]
Note that the erasing method described in Table 1 uses a second erasing method described later. Therefore, at the time of erasing, Lbe2 (+0.8 V in Table 1) is applied to the p-type well region 2102 on the semiconductor substrate 2101. For example, when erasing information of the memory function body m1 of the memory cell M22, electrons injected by the forward voltage applied to the p-type well region 2102 and the bit line BL3 serve as a trigger, and the information of the memory function body m1 is erased. It will be erased. Lbe2 is applied to the bit line BL1 to prevent erroneous erasure of the memory cell M21.
[0093]
[Table 1]

[0094]
As is clear from Table 1, the memory cell array according to the present embodiment can perform random access (read and rewrite operation for each bit). For this reason, the access efficiency can be improved as compared with a device that needs to be erased all at once. In addition, there is no need to perform a sequence such as temporary storage of the memory state, batch erasing, and writing, so that the control circuit is simplified.
[0095]
According to the above-described read operation, when two-bit storage of a certain memory cell is to be continuously read (for example, when the memory function bodies m1 and m2 of the memory cell M22 are continuously read), a nearby bit line is read. Since all the potentials of BL1 to BL4 must be inverted, the efficiency is low. Therefore, as will be described later, by devising an address decoder circuit and the like, and taking measures such as separating addresses for accessing the left and right memory functional units m1 and m2, it is possible to avoid a state of continuously reading alternately. Is preferred.
[0096]
In the above embodiment, the gate electrode of the memory element is a part of the word line 2104, but may not be a part of the word line. That is, the gate electrode of the memory element may be separate from the word line. In this case, the word lines connect the gate electrodes of the memory elements in the same row.
[0097]
(Embodiment 3)
Third Embodiment A third embodiment of the present invention will be described with reference to FIGS.
[0098]
FIG. 8 is a schematic plan view of the memory cell array according to the present embodiment, and FIG. 9 is a view for explaining the arrangement of the first-layer metal wiring of the memory cell array. However, in FIG. 8, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. 8 and 9 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary.
[0099]
The memory cell array according to the present embodiment is different from the memory cell array according to the second embodiment in the connection pattern between the source / drain diffusion region 3107 and the bit lines 3132 (BL1, BL2, BL3, BL4). I do.
[0100]
In the memory cell array, the surface of the well region is divided into an element isolation region 3108 and a plurality of band-shaped active regions 3110 (A1, A2, A3). In the active region A1 located between the bit line BL1 and the bit line BL2, one of two adjacent source / drain diffusion regions 3107 is connected to the bit line BL1, and the other of the two source / drain diffusion regions 3107 Are connected to the bit line BL2. In the active region A2 located between the bit line BL2 and the bit line BL3, one of two adjacent source / drain diffusion regions 3107 is connected to the bit line BL2, and the two source / drain diffusion regions 3107 are connected. Is connected to the bit line BL3. In the active region A3 located between the bit line BL3 and the bit line BL4, one of two adjacent source / drain diffusion regions 3107 is connected to the bit line BL3, and the two source / drain diffusion regions 3107 are connected. Is connected to the bit line BL4.
[0101]
In addition, two adjacent source / drain diffusion regions 3107 in the same row are electrically connected to one bit line 3132 (BL1, BL2, BL3, BL4) via an elliptical contact. More specifically, in the region above the word line WL1 in the figure, the source / drain diffusion region 3107 belonging to the active region A1 and the source / drain diffusion region 3107 belonging to the active region A2 are formed into elliptical column-shaped contacts. It is electrically commonly connected to the bit line BL2 via 3131 (see FIG. 9). Then, between the word line WL1 and the word line WL2, the source / drain diffusion region 3107 belonging to the active region A2 and the source / drain diffusion region 3107 belonging to the active region A3 are connected via an elliptical column-shaped contact 3131. And is electrically connected to the bit line BL3 in common. Further, between the word line WL2 and the word line WL3, the source / drain diffusion region 3107 belonging to the active region A1 and the source / drain diffusion region 3107 belonging to the active region A2 are connected via an elliptical column-shaped contact 3131. And is electrically connected to the bit line BL2 in common. Then, in the region below the word line WL3 in the drawing, the source / drain diffusion region 3107 belonging to the active region A2 and the source / drain diffusion region 3107 belonging to the active region A3 are formed by a solid line in a portion C8. , And are electrically connected in common to the bit line BL3 via an elliptical column-shaped contact 3131.
[0102]
In other words, for example, when the source / drain diffusion region 3107 belonging to the active region A1 between the word line WL1 and the word line WL2 is a source region, the active region A2 is connected between the word line WL1 and the word line WL2. The source / drain diffusion region 3107 to which it belongs is also a source region.
[0103]
According to the memory cell array of the present embodiment, even if the pitch in the horizontal direction (row direction) in FIG. 8 is reduced, the margin between the first-layer metal wirings can be increased. Therefore, the area of the memory cell can be further reduced, and the manufacturing cost can be reduced.
[0104]
The circuit diagram of the memory cell array of the present embodiment is the same as FIG. Therefore, the operation method may be the same as that of the memory cell array of the second embodiment.
[0105]
Stated another way, the structure of the device is such that element isolation regions and active regions are alternately formed in a line on a semiconductor substrate, and word lines are formed so as to intersect the element isolation regions and active regions. Have been. In the active region, a region crossing the word line is a channel region, and a region not crossing the word line is a source / drain diffusion region. Then, two adjacent source / drain regions in the same row with the element isolation region interposed therebetween are electrically connected to one bit line via one contact. When attention is paid to three channel regions in the same column, two source / drain diffusion regions on both sides of one element isolation region between the channel regions are electrically connected by one contact, and the other between the channel regions. The two source / drain diffusion regions on both sides of the element isolation region can be called a structure that is not electrically connected.
[0106]
In the above embodiment, the gate electrode of the memory element is a part of the word line 3104, but may not be a part of the word line. That is, the gate electrode of the memory element may be separate from the word line. In this case, the word lines connect the gate electrodes of the memory elements in the same row.
[0107]
(Embodiment 4)
The method of manufacturing the memory cell array according to the present embodiment will be described with reference to FIGS.
[0108]
FIG. 10 is a schematic view of a semiconductor substrate viewed from above during a process of forming a memory cell of the memory cell array according to the fourth embodiment, and FIG. 11 is a schematic sectional view of the memory cell array.
[0109]
Hereinafter, a process of forming the memory cells of the memory cell array will be described with reference to FIGS.
[0110]
First, as shown in FIG. 10, for example, a p-type semiconductor substrate 4101 made of single crystal silicon having a specific resistance of about several Ωcm (see FIG. 11) is provided with a trench element isolation (trench element isolation) as an example of an element isolation region. After forming 4108), a p-type well 4102 (see FIG. 11) is formed. The p-type well 4102 is separated by a trench element isolation 4108 (groove element isolation).
[0111]
The trench element isolation 4108 forms a groove by dry etching a semiconductor substrate, and then deposits a silicon oxide film on the semiconductor substrate including the inside of the groove by a CVD (chemical vapor deposition) method. Subsequently, the silicon oxide film is formed by polishing by a chemical mechanical polishing (CMP) method so as to leave the silicon oxide film only inside the groove.
[0112]
The p-type well 101 is formed by implanting ions of a p-type impurity, for example, B (boron) into a semiconductor substrate, and then annealing to thermally diffuse the impurity.
[0113]
Next, after cleaning the surface of the semiconductor substrate, an oxidation step is performed to form a gate oxide film (not shown) having a thickness of about 1 to 20 nm on the semiconductor substrate, and a thickness of 50 to 400 nm is formed by the CVD method. A polysilicon film is formed on the gate oxide film.
[0114]
Next, the polysilicon film and the gate oxide film are patterned to form a word line 4104 (WL1, WL2, WL3) functioning as a gate electrode and a gate insulating film 4103 (see FIG. 11). . The patterning is performed using a photoresist film formed on the polysilicon film as a mask.
[0115]
Next, a silicon nitride film 4109 (see FIG. 11) with a thickness of 0.8 to 200 nm is formed to cover the upper surface and side surfaces of the portion functioning as a gate electrode in the word line 4104. In the silicon nitride film 4109, portions on both sides of the word line 4104 serve as memory function bodies.
[0116]
Next, a memory cell is formed by forming a diffusion region 4107 (see FIG. 11) as an example of a source / drain diffusion region in the p-type well 4102 on both sides of the word line 4104.
[0117]
The diffusion region 4107 is an n-type semiconductor region, and is formed by ion-implanting an n-type impurity, for example, P (phosphorus) into the p-type well 4102.
[0118]
FIG. 12 shows another schematic cross-sectional view of the memory cell array of the present embodiment, and FIG. 13 shows a diagram for explaining the arrangement of metal wirings of the memory cell array.
[0119]
Hereinafter, the interlayer insulating film process, the contact process, and the remaining processes, which are processes after the formation of the memory cell, will be described with reference to FIGS.
[0120]
First, as shown in FIG. 11, a silicon oxide film (not shown) having a thickness of about 20 to 100 nm and a silicon nitride film 4201 having a thickness of 70 to 200 nm are deposited on the entire surface by a CVD method. A 200-700 nm-thick silicon oxide film for forming 4141 is deposited on the entire surface. The silicon nitride film is used as an etching stopper in the subsequent contact etching.
[0121]
Next, the silicon oxide film is polished by a CMP method to planarize the surface.
[0122]
Next, after forming a photoresist film on the silicon oxide film whose surface is flattened, a contact hole 4202 is formed in the silicon oxide film by anisotropic etching using the photoresist film as a mask. At this time, the anisotropic etching is performed under the condition that the etching rate of the silicon oxide film is faster than the etching rate of the silicon nitride film. An interlayer insulating film 4141 made of a silicon oxide film is formed between the contact holes 4202. Further, the silicon nitride film and the silicon oxide film are etched.
[0123]
Next, the contact hole 4202 is filled with tungsten to form an elliptical column-shaped contact 4131 made of tungsten.
[0124]
The contact 4131 is formed, for example, by depositing tungsten on a silicon oxide film in the inside of the contact hole 4202 by a CVD method, removing the upper portion of the tungsten by a CMP method (or an etch-back method), and leaving tungsten only in the contact hole 4202. It is formed by leaving.
[0125]
Next, a metal film is formed on the contact 4131 and the interlayer insulating film 4141.
[0126]
For the metal wiring, for example, a titanium nitride film / aluminum copper alloy film / titanium nitride film is sequentially formed by sputtering with a total film thickness of about 600 nm.
[0127]
Finally, by performing photolithography and metal etching on the metal film, bit lines 4132 (BL1, BL2, BL3, BL4) as shown in FIGS. 12 and 13 are formed.
[0128]
When electrically connecting each diffusion region 4107 (n-type semiconductor region) and each bit line 4132, wiring is performed according to the following rules. In the following, a direction parallel to the direction in which the word line 4104 extends (the left-right direction in the figure) is referred to as a row, and a direction parallel to the direction in which the bit line 4132 extends (the vertical direction in the figure) is referred to as a column.
[0129]
When attention is paid to a plurality of diffusion regions 4107 in one column, the plurality of diffusion regions 4107 are connected to one neighboring bit line 4132 every two lines. At this time, the one bit line 4132 is connected to the diffusion region 4107 every other row. The other bit line 4132 adjacent to the one bit line 4132 is connected to the diffusion region 4107 in a row where the one bit line 4132 is not connected to the diffusion region 4107. That is, the row where the one bit line 4132 is connected to the diffusion region 4107 is shifted from the row where the other bit line 4132 is connected to the diffusion region 4107 by one row. In other words, the one bit line 4132 and the other bit line 4132 are not connected to the diffusion region 4107 in the same row.
[0130]
When attention is paid to a plurality of diffusion regions 4107 in two adjacent columns, two adjacent diffusion regions 4107 in the same row are connected every other row via one contact 4131 to one bit line between the two columns. 4132 is electrically connected.
[0131]
With such a connection, when two adjacent bit lines 4134 and one word line 4104 are selected, two or more memory cells are not erroneously selected, and the memory cells are individually selected. Selectable, random access is possible.
[0132]
Further, in a structure having a wiring in accordance with the above-described rule, since the gate and the element isolation are close to a straight line, it is easy to manufacture, and thus the yield is good.
[0133]
In the above embodiment, the memory function body is formed by a part of the silicon nitride film 4109, but the memory function body is not limited to this. For example, after performing side wall oxidation of the word line 4104 to form a silicon oxide film covering the side wall, a silicon nitride film having a thickness of about 5 to 200 nm and a silicon oxide film having a thickness of 5 to 200 nm are formed by the CVD method. May be sequentially deposited on the entire surface, and a sidewall spacer-shaped memory function body may be formed on the side wall of the word line 4104 by an etch-back method. FIG. 17 shows an example of the memory function body.
[0134]
The electrical connection between one bit line 4132 and two diffusion regions 4107 may be as shown in FIG. That is, one bit line 4132 may be electrically connected to the two diffusion regions 4107 via the contact 4231 and the conductor 4331 having an elliptic plate shape.
[0135]
In the above embodiment, the gate electrode of the memory element is a part of the word line 4104, but may not be a part of the word line. That is, the gate electrode of the memory element may be separate from the word line. In this case, the word lines connect the gate electrodes of the memory elements in the same row.
[0136]
(Embodiment 5)
In the fifth embodiment, a specific method for manufacturing the memory cell array in FIG. 14 will be described. The memory cell array of the fifth embodiment is manufactured when an etching apparatus having a condition of a high selectivity (a condition in which the etching rate of the silicon oxide film is faster than the etching rate of the silicon nitride film) cannot be used.
[0137]
In the method of manufacturing the memory cell array, a high-density cell having a small occupied area is manufactured in the same manner as in the fourth embodiment by adding one mask as described below.
[0138]
That is, the steps up to the step of forming the memory cell are performed in the same manner as in the manufacturing method of the fourth embodiment. Thereafter, a silicon nitride film is formed using CVD. After patterning the formed silicon nitride to open a window, tungsten silicide is deposited and patterned, and local wiring is formed by tungsten silicide. After that, a bit line is formed in a metal process.
[0139]
In the manufacturing method of the present embodiment, the number of masks is increased as compared with the above-described fourth embodiment, but the condition of high selectivity (the condition that the etching rate of the silicon oxide film is faster than that of the silicon nitride film) Even if an etching apparatus having the above (2) cannot be used, it is possible to form a high-density memory cell of the same level.
[0140]
Polysilicon wiring may be used in addition to the local wiring of tungsten silicide. Further, in this embodiment, a method of performing local wiring when silicidation is performed after performing polysilicon wiring can also be performed. In particular, since silicidation is a self-aligned process, there is an advantage that dry etching of a high melting point metal is not required and the process can be simplified. Further, a silicide wiring of polysilicon, titanium, titanium silicide, cobalt silicide, or the like may be used.
[0141]
Also in the manufacturing method of the present embodiment, up to the gate electrode can be manufactured in the same process as a normal logic transistor, so that the manufacturing method can be manufactured by a reliable manufacturing method, so that the yield is improved. Further, the memory logic mixed process can be easily realized. Further, in the present embodiment, since the memory can be manufactured substantially with one layer of the metal wiring, the yield is improved.
[0142]
Further, in the description of the present embodiment, the protective film for forming the silicon nitride film of the memory function body and the local wiring is another film. However, when the film thickness is consistent in the process, One protective film may be used for forming the silicon nitride film and the local wiring. In this case, if patterning is performed with a resist mask at the time of etching back after forming the gate electrode, the sidewall and the protection pattern can be formed simultaneously. By doing so, it is possible to further simplify the process.
[0143]
In both the present embodiment and the fourth embodiment, the wiring material for electrically connecting the diffusion region and the bit line has almost the same structure in view of the wiring resistance because of the similar structure. . As a result, there is an advantage that the sense amplifier can be designed relatively easily.
[0144]
In the present embodiment, the so-called ONO (Oxide Nitride Oxide) film made of a silicon nitride film and an insulating film has been used as the memory function body. However, the memory function body has a resistance such as a variable resistance due to, for example, charge accumulation. Any film can be used as long as it can change the value. For example, it goes without saying that the present invention can be implemented by forming a film capable of accumulating charges such as a floating gate or a silicon dot film.
[0145]
(Embodiment 6)
FIG. 15 shows a block diagram of a semiconductor memory device according to the sixth embodiment of the present invention.
[0146]
The semiconductor memory device includes a memory cell array 6301, a column address buffer 6302 for specifying a memory cell to be accessed, a row address buffer 6303, a column address decoder 6304 as an example of a column decoder, and an example of a row decoder. , A sense amplifier 6306 as an example of a sense amplifier, and a control circuit 6307.
[0147]
The control circuit 6307 controls the memory cell array 6301, column address buffer 6302, row address buffer 6303, column address decoder 6304, row address decoder 6305, and sense amplifier 6306.
[0148]
The memory cell array according to any one of Embodiments 1 to 5 is used as the memory cell array 6301. Therefore, the storage capacity can be increased, and the manufacturing cost can be reduced.
[0149]
By the way, when designing the semiconductor memory device as described above, considering the efficiency of the read operation, as described in the second embodiment, it is attempted to continuously read the 2-bit storage of a certain memory cell. It is inefficient to do. This is because, in order to continuously read the 2-bit information of the memory cell, it is necessary to reverse the direction of the read current (replace the source and drain), and all the potentials of the nearby bit lines must be inverted. Because it must be. Therefore, it is preferable that 2-bit addresses stored in a certain memory cell be separated from each other. For example, one of the storage bits of memory cells belonging to the same word line and adjacent to each other may be set to a continuous address, and one of the storage bits in the same memory cell may be separated from the other address.
[0150]
(Embodiment 7)
The memory cell array described so far can be incorporated in a liquid crystal driver. The process of the present invention is compatible with the manufacturing process of the liquid crystal driver, and it is possible to incorporate a memory which has been conventionally provided separately in the liquid crystal driver. Therefore, a liquid crystal driver with a memory function can be easily manufactured at low cost.
[0151]
A multifunctional liquid crystal driver can be realized by storing image adjustment values (γ values) and the like using this memory.
[0152]
(Embodiment 8)
FIG. 16 shows a block diagram of a portable electronic device.
[0153]
The portable electronic device includes a central processing unit 8401, a memory unit 8402, a power supply 8403, an input / output unit 8404, and an image output unit 8405. The memory section 8402 includes the memory cell array according to any of the first to fifth embodiments.
[0154]
The memory portion 8402 has a function as a rewritable firmware storage device (a device that stores a basic sequence of hardware) and a function as a storage device that stores system settings, in addition to the function of the main memory. Can be provided.
[0155]
According to the portable electronic device having the above configuration, since the memory section 8402 includes the memory cell array according to any of Embodiments 1 to 5, high integration can be easily performed and manufacturing cost can be reduced. .
[0156]
Further, since it is easy to mount the central processing unit 1401 and the like and the memory unit 1402 on one chip, the manufacturing cost can be further reduced.
[0157]
Specific examples of the mobile electronic device according to the present embodiment include a mobile phone, an electronic organizer, a mobile game device, and the like.
[0158]
(Embodiment 9)
FIG. 17 is a diagram showing a cross-sectional structure of an example of a memory element used in the semiconductor memory device of the present invention.
[0159]
The memory element is formed on a p-type well region 102 formed on a surface of a semiconductor substrate 101. A gate electrode 104 is formed on the p-type well region 102 via a gate insulating film 103. The top and side surfaces of the gate electrode 104 are covered with a silicon nitride film 109 having a trap level for retaining charges and serving as a charge retention film. In the silicon nitride film 109, portions located on the sides of the gate electrode 104 function as memory function bodies 105a and 105b. That is, the memory function bodies 105a and 105b actually accumulate charges by the rewriting operation.
[0160]
The first and second diffusion regions 107a and 107b formed on the surface of the p-type well 102 function as a source region or a drain region, respectively, and have an offset structure. That is, the first and second diffusion regions 107a and 107b do not exist in the lower region 121 of the gate electrode, and the offset region 120 below the charge holding unit (memory function bodies 105a and 105b) forms part of the channel region 122. Make up.
[0161]
FIG. 18 is a diagram showing a modified example of the memory element. 18, the same components as those shown in FIG. 17 are denoted by the same reference numerals as those in FIG. 16, and description thereof will be omitted.
[0162]
The memory element differs from the memory element in FIG. 17 in that first and second memory function bodies 131a and 131b are used instead of the silicon nitride film 109. As shown in FIG. 17, the first and second memory function bodies 131a and 131b are arranged so as to sandwich the gate electrode 104 in the horizontal direction (gate length direction) in the figure. That is, the first memory function body 131a is arranged on one side of the gate electrode 104, and the second memory function body 131b is arranged on the other side of the gate electrode 104. The first and second memory function bodies 131a and 131b have a structure including a silicon nitride film 113 and silicon oxide films 111 and 112 sandwiching the silicon nitride film 113. As described above, by adopting a structure in which the silicon nitride film 113 is sandwiched between the silicon oxide films 111 and 112, the charge injection efficiency at the time of the rewrite operation is increased, and a higher-speed operation can be performed.
[0163]
In FIG. 18, the silicon nitride film 113 may be replaced with a ferroelectric. Further, in FIG. 17, the portions 105a and 105b of the silicon nitride film 109 may be replaced with an insulating film in which fine particles made of a nanometer-sized conductor or semiconductor are distributed in a scattered manner. At this time, if the particle size is less than 1 nm, the quantum effect is too large, so that it is difficult for charges to tunnel through the dots. If it exceeds 10 nm, a remarkable quantum effect does not appear at room temperature. Therefore, the diameter of the fine particles is preferably in the range of 1 nm to 10 nm.
[0164]
In addition, the shape of the first and second memory function bodies 131a and 131b is a sidewall spacer shape, but is not necessarily limited to this. For example, in the case of the memory element shown in FIG. 16, if a material for retaining a charge or a substance for retaining polarization is arranged in a region where the portions 105a and 105b of the silicon nitride film 109 are formed, the shape of the silicon nitride film 109 is reduced. Is not particularly limited.
[0165]
Hereinafter, an operation method of the memory element in FIG. 17 will be described with reference to FIGS. 19 to 23, WL indicates a word line, and BL1 and BL2 indicate bit lines, respectively, and the semiconductor substrate 101 is not shown.
[0166]
First, the write operation of the memory element will be described with reference to FIGS. Hereinafter, a case will be described in which the first memory function bodies 131a and 231b have a function of retaining charges.
[0167]
Here, “writing” refers to injecting electrons into the first and second memory function bodies 131a and 131b when the memory element in FIG. 18 is an N-channel type. Hereinafter, a description will be given assuming that the memory element of FIG. 18 is of the N-channel type.
[0168]
In order to inject (write) electrons into the second memory function body 131b, as shown in FIG. 19, the first diffusion region 107a having n-type conductivity is used as a source region while n-type is used. The second diffusion region 107b having the above conductivity type is defined as a drain region. For example, 0V may be applied to the first diffusion region 107a and the p-type well region 102, + 5V may be applied to the second diffusion region 107b, and + 5V may be applied to the gate electrode 104. According to such a voltage condition, the inversion layer 226 extends from the first diffusion region 107a (source region) to the second diffusion region 107b (drain region). ), And a pinch-off point occurs. The electrons are accelerated by a high electric field from the pinch-off point to the second diffusion region 107b (drain region) and become so-called hot electrons (high-energy conduction electrons). The writing is performed by injecting the hot electrons into the second memory function body 131b. Note that no writing is performed in the vicinity of the first memory function body 131a because no hot electrons are generated.
[0169]
Thus, writing can be performed by injecting electrons into the second memory function body 131b.
[0170]
On the other hand, in order to inject (write) electrons into the first memory function body 131a, as shown in FIG. 20, the second diffusion region 107b is used as a source region and the first diffusion region 107a is used as a drain region. And For example, 0V may be applied to the second diffusion region 107b and the p-type well region 102, + 5V may be applied to the first diffusion region 107a, and + 5V may be applied to the gate electrode 104. Thus, the case where electrons are injected into the second memory function body 131b is the same as the case where the source / drain regions are used when electrons are injected into the first memory function body 131a. Thus, writing can be performed by injecting electrons into the first memory function body 131a.
[0171]
Next, an erasing operation of the memory element will be described with reference to FIGS.
[0172]
In the first erasing method for erasing information stored in the first memory function body 131a, as shown in FIG. 21, a positive voltage (for example, +5 V) is applied to the first diffusion region 107a, and the p-type well region 102 , A reverse bias is applied to the PN junction between the first diffusion region 107 a and the p-type well region 102, and a negative voltage (for example, −5 V) is applied to the gate electrode 104. At this time, in the vicinity of the gate electrode 104 of the PN junction, the gradient of the potential becomes particularly steep due to the influence of the gate electrode 104 to which the negative voltage is applied. Therefore, hot holes (high-energy holes) are generated on the p-type well region 102 side of the PN junction due to the band-to-band tunnel. The hot holes are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a. Thus, the first memory function body 131a is erased. At this time, 0 V may be applied to the second diffusion region 107b.
[0173]
When erasing the information stored in the second memory function body 131b, the potentials of the first diffusion region 107a and the second diffusion region 107b may be exchanged in the first erasing method. That is, 0V is applied to the first diffusion region 107a, and 5V is applied to the second diffusion region 107b.
[0174]
In the second erasing method for erasing information stored in the first memory function body 131a, as shown in FIG. 22, a positive voltage (for example, +4 V) is applied to the first diffusion region 107a, It suffices to apply 0 V to the gate electrode 107 b, apply a negative voltage (for example, −4 V) to the gate electrode 104, and apply a positive voltage (for example, +0.8 V) to the p-type well region 102. At this time, a forward voltage is applied between the p-type well region 102 and the second diffusion region 107b, and electrons are injected into the p-type well region 102. The injected electrons diffuse to the PN junction between the p-type well region 102 and the first diffusion region 107a, where they are accelerated by a strong electric field to become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. That is, by applying a forward voltage between the p-type well region 102 and the second diffusion region 107b, the electrons injected into the p-type well region 102 serve as a trigger, and the second diffusion region 107b Hot holes are generated at the PN junction located on the opposite side from the above. Hot holes generated at the PN junction are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a.
[0175]
According to the above-described second erasing method, the second erasing method can be applied to the case where only a voltage sufficient to generate a hot hole due to an inter-band tunnel is applied to the PN junction between the p-type well region 102 and the first diffusion region 107a. Injected from the diffusion region 107b into the p-type well region 102 serves as a trigger for generating an electron-hole pair at the PN junction, and can generate a hot hole. Therefore, the voltage at the time of the erase operation can be reduced. In particular, when the offset region 120 shown in FIG. 17 and FIG. 18 exists, the effect that the PN junction becomes sharp due to the gate electrode 104 to which the negative potential is applied is small. For this reason, it is difficult to generate hot holes due to band-to-band tunneling. However, the second erasing method can compensate for the drawback, and realize the erasing operation at a low voltage.
[0176]
Specifically, when erasing information stored in the first memory function body 131a, in the first erasing method, +5 V had to be applied to the first diffusion region 107a. In the erasing method, +4 V was sufficient. As described above, according to the second erasing method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the memory element due to hot carriers can be suppressed.
[0177]
In any of the first and second erasing methods, the memory element has a feature that over-erasing hardly occurs. The over-erase refers to a phenomenon in which the threshold value decreases without saturation as the amount of holes accumulated in the memory function body increases. This is a serious problem in an EEPROM typified by a flash memory. In particular, when the threshold value becomes negative, a fatal operation failure occurs in that a memory cell cannot be selected. In the above-mentioned memory element, even when a large amount of holes are accumulated in the memory function body, only electrons are induced under the memory function body, and this has almost no effect on the potential of the channel region below the gate insulating film. Absent. Since the threshold value at the time of erasing is determined by the potential under the gate insulating film, over-erasing hardly occurs.
[0178]
Next, a read operation of the memory element will be described with reference to FIG.
[0179]
When reading information stored in the first memory function body 131a, as shown in FIG. 23, the first diffusion region 107a is used as a source region, the second diffusion region 107b is used as a drain region, and a transistor is used. Operate in the saturation region. For example, 0V may be applied to the first diffusion region 107a and the p-type well region 102, and + 2V may be applied to the second diffusion region 107b and the gate electrode 104. At this time, when no electrons are accumulated in the first memory function body 131a, a drain current easily flows. On the other hand, when electrons are accumulated in the first memory function body 131a, a drain current does not easily flow because an inversion layer is not easily formed near the first memory function body 131a. Therefore, by detecting the drain current, information stored in the first memory function body 131a can be read. At this time, the presence or absence of charge accumulation in the second memory function body 131b does not affect the drain current because the vicinity of the drain is pinched off.
[0180]
When reading information stored in the second memory function body 131b, the transistor is operated in a saturation region using the second diffusion region 107b as a source region and the first diffusion region 107a as a drain region. For example, 0V may be applied to the second diffusion region 107b and the p-type well region 102, + 1.8V may be applied to the first diffusion region 107a, and + 2V may be applied to the gate electrode 104. As described above, when reading the information stored in the first memory function body 131a, the information stored in the second memory function body 131b can be read by exchanging the source / drain regions. it can.
[0181]
When a portion (offset region 120) that is not covered with the gate electrode 104 is left in the channel region 122, the portion depends on the presence or absence of surplus electric charges in the first and second memory function bodies 131a and 131b. As a result of the disappearance or formation of the inversion layer, a large hysteresis (change in threshold value) is obtained. However, if the width of the offset region 120 is too large, the drain current is greatly reduced, and the reading speed is significantly reduced. Therefore, it is preferable to determine the width of the offset region 102 so that sufficient hysteresis and reading speed can be obtained.
[0182]
Even when the diffusion regions 107a and 107b reach the end of the gate electrode 104, that is, even when the diffusion regions 107a and 107b and the gate electrode 104 overlap, the threshold value of the transistor hardly changes due to the writing operation. However, the parasitic resistance at the source / drain ends was greatly changed, and the drain current was greatly reduced (one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the diffusion regions 107a and 107b and the gate electrode 104 do not overlap. That is, it is preferable that the offset region 120 exists.
[0183]
With the above operation method, two bits can be selectively written and erased per transistor. The word line WL is connected to the gate electrode 104 of the memory element, the bit line BL1 is connected to the first diffusion region 107a, and the bit line BL2 is connected to the second diffusion region 107b. A memory cell array can be configured.
[0184]
Further, in the above operation method, two bits are written and erased per memory element by exchanging the source electrode and the drain electrode. However, the source region and the drain region are fixed to operate as a 1-bit memory. You may let it. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be reduced by half.
[0185]
As is clear from the above description, according to the memory element, the first and second memory function bodies 131a and 131b are formed independently of the gate insulating film 103 and formed on both sides of the gate electrode 104. . Therefore, a two-bit operation is possible. Furthermore, the first memory function body 131a and the second memory function body 131b are separated by the gate electrode 104, so that interference at the time of rewriting is effectively suppressed. Further, since the gate insulating film 103 is separated from the first and second memory function bodies 131a and 131b, it can be made thin. Therefore, the short channel effect can be suppressed, and the memory element can be easily miniaturized.
[0186]
(Embodiment 10)
As shown in FIG. 24, the memory element of this embodiment includes first and second memory function bodies 261 and 262 on both sides of the gate electrode 217. The first and second memory function bodies 261 and 262 serve as a region for retaining electric charges (a region for storing electric charges and may be a film having a function of retaining electric charges) and a region for preventing the escape of electric charges. And a region (may be a film having a function of preventing charge from escaping), and has an ONO structure. That is, the first and second memory function bodies 261 and 262 are constituted by the silicon nitride film 242 and the silicon oxide films 241 and 243 sandwiching the silicon nitride film 242. In the first and second memory function bodies 261 and 262, the silicon nitride film 242 performs a function of retaining charges. The silicon oxide films 241 and 243 function as films having a function of making it difficult for the charges stored in the silicon nitride film 242 to escape.
[0187]
In addition, the regions (silicon nitride films 242) of the first and second memory function bodies 261 and 262 that hold electric charges overlap with the first and second diffusion regions 212 and 213, respectively. Here, “overlap” means that at least a part of the charge holding region (silicon nitride film 242) exists on at least a part of the first and second diffusion regions 212 and 213. Means In FIG. 24, 211 is a semiconductor substrate, 214 is a gate insulating film, 217 is a gate electrode, 271 is an offset region, and 272 is a channel region. The offset region 271 is an offset region between the gate electrode 217 and the first and second diffusion regions 212 and 213. Further, the channel region 272 corresponds to the outermost surface portion of the semiconductor substrate 211 under the gate insulating film 214.
[0188]
Hereinafter, the effect of overlapping the charge holding regions (silicon nitride film 242) and the first and second diffusion regions 212 and 213 in the first and second memory function bodies 261 and 262 will be described. .
[0189]
FIG. 25 is an enlarged view of the periphery of the second memory function body 262 on the right side of FIG. In FIG. 25, W1 indicates an offset amount between the gate electrode 214 and the second diffusion region 213, and W2 indicates a width of the second memory function body 262 at a cross section of the gate electrode 217 in the gate length direction. I have. As described above, the width of the second memory function body 262 is defined as W2 because the end of the silicon nitride film 242 on the side remote from the gate electrode 217 is separated from the gate electrode 217 of the second memory function body 262. This is because it matches the end on the far side. The amount of overlap between the second memory function body 262 and the second diffusion region 213 is represented by W2−W1. What is particularly important here is that the silicon nitride film 242 of the second memory function body 262 overlaps with the diffusion region 213, that is, satisfies the relationship of W2> W1.
[0190]
In the case of the second memory function body 262a as shown in FIG. 26, the end of the silicon nitride film 242a on the side away from the gate electrode 217 is in line with the end on the side of the memory function body 262a on the side away from the gate electrode 217. I haven't. In this case, W2 may be defined from the end of the gate electrode 217 on the side of the second memory function body 262 to the end of the silicon nitride film 142a on the side opposite to the gate electrode 217. In FIG. 26, 241a and 243a are silicon oxide films.
[0191]
FIG. 27 shows the drain current Id when the width W2 of the second memory function body 262 is fixed to 100 nm and the offset amount W1 is changed in the structure of FIG. Here, the drain current Id is obtained by device simulation using the second memory function body 262 in an erased state (holes are accumulated) and the first and second diffusion regions 212 and 213 as a source region and a drain region, respectively. Determined by
[0192]
As is apparent from FIG. 27, when W1 is 100 nm or more (that is, the state where the silicon nitride film 242 and the second diffusion region 213 do not overlap), the drain current Id decreases rapidly. Since the value of the drain current Id is almost proportional to the read operation speed, the memory performance is rapidly deteriorated when W1 is 100 nm or more. On the other hand, in a range where the silicon nitride film 242 and the second diffusion region 213 overlap, the drain current decreases gradually. Therefore, in consideration of variations in mass production, if at least a part of the silicon nitride film 242, which is a film having a function of retaining electric charges, and the source / drain regions do not overlap, a memory function can be obtained effectively. Have difficulty.
[0193]
Based on the results of the device simulation described above, W2 was fixed at 100 nm, and W1 was set at 60 nm and 100 nm as design values, to fabricate a memory cell array. When W1 is 60 nm, the silicon nitride film 142 and the first and second diffusion regions 112 and 113 overlap by 40 nm as a design value, and when W1 is 100 nm, they do not overlap as a design value. As a result of measuring the read time of these memory cell arrays, the read access time was 100 times faster when W1 was set to 60 nm as the design value, compared with the worst case in which the variation was considered. In practice, the read access time is preferably 100 nanoseconds or less per bit, but it has been found that this condition cannot be achieved at all when W1 = W2. In addition, it has been found that W2-W1> 10 nm is more preferable in consideration of manufacturing variations.
[0194]
The reading of the information stored in the first memory function body 261 (area 280) is performed by using the first diffusion region 212 as the source region and the second diffusion region 213 as the drain region, as in the first embodiment. It is preferable to form a pinch-off point on the side closer to the drain region in the channel region. That is, when reading information stored in one of the two memory function bodies, it is preferable to form a pinch-off point in a region within the channel region and close to the other memory function body. Thus, regardless of the storage state of the second memory function body 262, the information stored in the first memory function body 261 can be detected with high sensitivity, which is a major factor that enables the 2-bit operation.
[0195]
On the other hand, when information is stored in only one side of the two first and second memory function bodies 261, 262, or when the two first and second memory function bodies 261, 262 are stored in the same storage state, they are used. In such a case, it is not always necessary to form a pinch-off point at the time of reading.
[0196]
Although not shown in FIG. 24, a well region (p-type well in the case of an N-channel element) is preferably formed on the surface of the semiconductor substrate 211. By forming the well region, it is easy to control the other electrical characteristics (breakdown voltage, junction capacitance, short channel effect) while optimizing the impurity concentration of the channel region for the memory operation (rewriting operation and reading operation). .
[0197]
It is preferable that the memory function body includes a charge holding film having a function of holding charges and an insulating film from the viewpoint of improving the holding characteristics of the memory. In this embodiment mode, a silicon nitride film 242 having a level for trapping electric charges is used as a charge holding film, and silicon oxide films 241 and 243 having a function of preventing dissipation of charges accumulated in the charge holding film are used as an insulating film. I have. Since the memory function body includes the charge holding film and the insulating film, the charge can be prevented from dissipating and the holding characteristics can be improved. Furthermore, the volume of the charge holding film can be appropriately reduced as compared with the case where the memory function body is composed of only the charge holding film. By appropriately reducing the volume of the charge holding film, the movement of charges in the charge holding film can be limited, and a change in characteristics due to the charge transfer during storage can be suppressed.
[0198]
Further, it is preferable that the memory function body includes a charge retention film disposed substantially in parallel with the gate insulating film surface. In other words, it is preferable that the upper surface of the charge retaining film in the memory function body is disposed at an equal distance from the upper surface of the gate insulating film. Specifically, as shown in FIG. 28, the charge holding film 242b of the second memory function body 262b has a surface substantially parallel to the surface of the gate insulating film 214. In other words, it is preferable that the charge retention film 242b be formed at a uniform height from the height corresponding to the surface of the gate insulating film 214.
[0199]
Since the charge holding film 242b substantially parallel to the surface of the gate insulating film 214 is provided in the second memory function body 262b, an inversion layer is formed in the offset region 271 by the amount of charge accumulated in the charge holding film 242b. It is possible to effectively control the easiness of the operation, and to increase the memory effect. Further, by making the charge retention film 242b substantially parallel to the surface of the gate insulating film 214, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and the variation in the memory effect can be reduced. Can be suppressed. In addition, the movement of charges in the upper direction of the charge holding film 242a is suppressed, so that a change in characteristics due to the movement of charges during storage can be suppressed.
[0200]
Further, the memory function body 262 is formed of an insulating film (for example, the silicon oxide film 244b on the offset region 271) separating the charge holding film 242a and the channel region (or well region) substantially parallel to the surface of the gate insulating film 214. Part). With this insulating film, dissipation of the charge accumulated in the charge holding film 242b is suppressed, and a memory element with better holding characteristics can be obtained.
[0201]
The thickness of the charge holding film 242b is controlled, and the thickness of the insulating film under the charge holding film 242b (the portion of the silicon oxide film 244 on the offset region 271) is controlled to be constant. The distance from the surface to the charges stored in the charge holding film 242b can be kept substantially constant. In other words, the distance from the surface of the semiconductor substrate to the charge stored in the charge holding film 242b is determined from the minimum thickness of the insulating film below the charge holding film 242b to the maximum thickness of the insulating film below the charge holding film 242a. Control can be performed up to the sum of the maximum thickness value of the holding film 242a. As a result, the density of lines of electric force generated by the charges stored in the charge holding film 242b can be substantially controlled, and the variation in the size of the memory effect of the memory element can be extremely reduced.
[0202]
Needless to say, the preferable conditions for the second memory function body 262 described in the present embodiment are also preferable conditions for the first memory function body 261.
[0203]
(Embodiment 11)
In this embodiment, the silicon nitride film 242 of the memory function body 262 has a substantially uniform film thickness as shown in FIG. Further, the charge retention film 242 has a first portion 281 disposed substantially parallel to the surface of the gate insulating film 214 and a second portion 282 disposed substantially parallel to the side surface of the gate electrode 217. ing.
[0204]
When a positive voltage is applied to the gate electrode 217, the lines of electric force in the memory function body 262 pass through the silicon nitride film 242 twice as indicated by an arrow 283. That is, the lines of electric force pass through the first portion 281 and the second portion. When a negative voltage is applied to the gate electrode 217, the direction of the lines of electric force is opposite to the direction of the arrow 283. Here, the relative permittivity of the silicon nitride film 242 is about 6, and the relative permittivity of the silicon oxide films 241 and 243 is about 4. Therefore, the effective relative dielectric constant of the memory function body 262 in the electric flux line in the direction of the arrow 283 becomes larger than that in the case where only the charge holding film composed only of the first portion 281 is present. The potential difference at both ends can be further reduced. That is, most of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region 271.
[0205]
The charge is injected into the silicon nitride film 242 during the rewrite operation because the generated charge is drawn by the electric field in the offset region 271. Therefore, when the charge holding film includes the second portion, the charge injected into the memory function body 262 during the rewrite operation increases, and the rewrite speed increases.
[0206]
If the silicon oxide film 243 is also a silicon nitride film, that is, if the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 214, the silicon nitride film The charge transfer becomes remarkable, and the holding characteristics deteriorate.
[0207]
It is more preferable that the charge retention film is formed of a high dielectric material such as hafnium oxide having a very large relative dielectric constant instead of the silicon nitride film.
[0208]
Further, the memory function body may further include an insulating film (a portion of the silicon oxide film 241 on the offset region 271) separating the charge holding film substantially parallel to the surface of the gate insulating film and the channel region (or well region). preferable. With this insulating film, dissipation of the charges accumulated in the charge holding film is suppressed, and the holding characteristics can be further improved.
[0209]
Further, the memory function body further includes an insulating film (a portion of silicon oxide film 241 in contact with gate electrode 217) separating the gate electrode and the charge holding film extending in a direction substantially parallel to the side surface of the gate electrode. Is preferred. With this insulating film, it is possible to prevent electric charges from being injected from the gate electrode into the charge holding film and to prevent the electrical characteristics from changing, thereby improving the reliability of the memory element.
[0210]
Further, as in the second embodiment, the thickness of the insulating film (the portion of the silicon oxide film 241 above the offset region 271) under the charge retaining film is controlled to be constant, and the insulating film is disposed on the side surface of the gate electrode. It is preferable to control the thickness of the insulating film (the portion of the silicon oxide film 241 in contact with the gate electrode 217) to be constant. Thus, the density of the lines of electric force generated by the charges stored in the charge holding film can be substantially controlled, and the charge leakage can be prevented.
[0211]
(Embodiment 12)
This embodiment relates to optimization of a distance between a gate electrode, a memory function body, and a source / drain region.
[0212]
As shown in FIG. 30, A is the gate electrode length in the cut surface in the gate length direction, B is the distance between the source / drain regions (channel length), and C is the end of one memory function body to the other memory function body. From the end of the film having the function of retaining the charge in one memory function body (the side remote from the gate electrode) on the cut surface in the gate length direction, that is, the charge in the other memory function body It shows the distance to the end of the film having the function of performing the function (the side away from the gate electrode).
[0213]
First, it is preferable that B <C. An offset region 271 exists between a portion of the channel region below the gate electrode 217 and the first and second diffusion regions 212 and 213 serving as source / drain regions. Due to B <C, the charge accumulated in the first and second memory function bodies 261 and 262 (silicon nitride film 242) effectively changes the ease of inversion in the entire region of the offset region 271. Therefore, the memory effect increases, and particularly, the speed of the read operation is increased.
[0214]
When the gate electrode 217 is offset from the first and second diffusion regions (source / drain regions) 212 and 213, that is, when A <B is satisfied, a voltage is applied to the gate electrode 217. The easiness of inversion of the offset region 271 at the time greatly changes depending on the amount of electric charge accumulated in the first and second memory function bodies 261 and 262, and the memory effect is increased and the short channel effect is reduced. it can. However, as long as the above-mentioned memory effect appears, it is not always necessary to exist.
[0215]
Even when the offset region 271 is not provided, if the impurity concentration of the first and second diffusion regions 212 and 213 is sufficiently low, the first and second memory function bodies 261 and 262 (the silicon nitride film 242) ) May exhibit a memory effect.
[0216]
Therefore, it is most preferable that A <B <C.
[0219]
(Embodiment 13)
As shown in FIG. 31, the memory element of this embodiment has substantially the same configuration except that the semiconductor substrate in the second embodiment is an SOI substrate.
[0218]
In this memory element, a buried oxide film 288 is formed on a semiconductor substrate 286, and an SOI layer is further formed thereon. First and second diffusion regions 212 and 213 are formed in the SOI layer, and the other region is a body region 287.
[0219]
With this memory element, the same operation and effect as those of the memory element according to the second embodiment can be obtained. Furthermore, since the junction capacitance between the first and second diffusion regions 212 and 213 and the body region 287 can be significantly reduced, the speed of the device and the power consumption can be reduced.
[0220]
(Embodiment 14)
As shown in FIG. 32, the memory element of this embodiment is different from that of the second embodiment in that the first and second diffusion regions 212 and 213 which are n-type source / drain regions are adjacent to the channel side. , P-type high-concentration region 291 is added.
[0221]
That is, the p-type impurity (for example, boron) concentration in the p-type high concentration region 291 is higher than the p-type impurity concentration in the region 292. The p-type impurity concentration in the p-type high concentration region 291 is, for example, 5 × 10 ¹⁷ ~ 1 × 10 ¹⁹ cm ^-3 The degree is appropriate. The p-type impurity concentration of the region 292 is, for example, 5 × 10 ¹⁶ ~ 1 × 10 ¹⁸ cm ^-3 It can be.
[0222]
By providing the p-type high-concentration region 291 as described above, the junction between the first and second diffusion regions 212 and 213 and the semiconductor substrate 211 is directly below the first and second memory function bodies 261 and 262. And becomes steep. Therefore, hot carriers are easily generated at the time of writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the speed of the writing and erasing operations can be increased. Further, since the impurity concentration of the region 292 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current increases. Therefore, the reading speed is improved. Therefore, a memory element having a low rewrite voltage or a high rewrite speed and a high read speed can be obtained.
[0223]
In FIG. 32, the p-type high-concentration region 291 is provided near the source / drain region and below the memory function body (that is, not immediately below the gate electrode 217), so that the threshold value of the entire transistor is significantly increased. To rise. The extent of this rise is significantly greater than when the p-type high concentration region 291 is immediately below the gate electrode 217. When the write charge (electrons when the transistor is an N-channel type) is accumulated in the memory function body, the difference is further increased. On the other hand, when sufficient erase charges (holes when the transistor is an N-channel type) are accumulated in the memory function body, the threshold value of the transistor as a whole depends on the impurity concentration of the channel region (region 292) below the gate electrode 217. To a threshold determined by. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the p-type high concentration region 291, while the threshold value at the time of writing is greatly affected. Therefore, by arranging the p-type high-concentration region 291 below the memory function body and in the vicinity of the source / drain region, only the threshold value at the time of writing varies greatly, and the memory effect (at the time of writing and erasing). Threshold difference) can be significantly increased
[0224]
(Embodiment 15)
In the memory element of this embodiment, as shown in FIG. 33, the thickness T1 of the insulating film separating the charge holding film (silicon nitride film 242) and the channel region or the well region in the second embodiment is different from that of the gate element in the second embodiment. It has substantially the same configuration except that it is thinner than the thickness T2 of the insulating film 214.
[0225]
The thickness T2 of the gate insulating film 214 has a lower limit due to the demand for withstand voltage during the rewriting operation of the memory. However, the thickness T1 of the insulating film can be made smaller than T2 regardless of the demand for the withstand voltage.
[0226]
In the memory element of the present embodiment, the degree of freedom in designing T1 as described above is high for the following reason. In the memory element of this embodiment, the insulating film that separates the charge retention film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region. Therefore, a high electric field acting between the gate electrode and the channel region or the well region does not directly act on the insulating film separating the charge retention film and the channel region or the well region, and a relatively weak electric field spreading laterally from the gate electrode. Acts. Therefore, it is possible to make T1 thinner than T2 regardless of the demand for the withstand voltage for the gate insulating film. On the other hand, for example, in an EEPROM typified by a flash memory, an insulating film separating a floating gate and a channel region or a well region is sandwiched between a gate electrode (control gate) and a channel region or a well region. The high electric field from directly acts. Therefore, in the EEPROM, the thickness of the insulating film separating the floating gate from the channel region or the well region is limited, and the optimization of the function of the memory element is hindered.
[0227]
As is clear from the above description, in the memory element of the present embodiment, the fact that the insulating film that separates the charge holding film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region corresponds to T1. This is the essential reason for increasing the degree of freedom.
[0228]
By reducing the thickness T1 of the insulating film, the injection of charges into the first and second memory function bodies 261 and 262 becomes easy, and the voltage of the writing operation and the erasing operation is reduced. The erasing operation can be performed at high speed, and the amount of electric charge induced in the channel region or the well region when electric charges are accumulated in the silicon nitride film 242 increases, so that the memory effect can be increased.
[0229]
By the way, the electric lines of force in the first and second memory function bodies 261 and 262 may be short as shown by an arrow 284 in FIG. 29 and do not pass through the silicon nitride film 242. Since the electric field strength is relatively large on such a short line of electric force, the electric field along the line of electric force plays a large role during the rewriting operation. By reducing the thickness T1 of the insulating film, the silicon nitride film 242 moves to the lower side in the figure, and the lines of electric force indicated by arrows 283 pass through the silicon nitride film 242. Therefore, the effective relative permittivity in the first and second memory function bodies 261 and 262 along the lines of electric force indicated by the arrow 284 increases, and the potential difference at both ends of the lines of electric force decreases. be able to. Therefore, a large part of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region, and the writing operation and the erasing operation become faster.
[0230]
As is clear from the above, by setting T1 <T2, the voltage of the write operation and the erase operation can be reduced or the write operation and the erase operation can be performed at a high speed without lowering the withstand voltage performance of the memory, and the memory effect can be further improved. It is possible to increase.
[0231]
It is to be noted that the thickness T1 of the insulating film is preferably at least 0.8 nm, which is a limit at which uniformity and film quality can be maintained at a constant level due to a manufacturing process and retention characteristics are not extremely deteriorated. More preferred.
[0232]
Specifically, in the case of a liquid crystal driver LSI that requires a high withstand voltage having a large design rule, a maximum voltage of 15 to 18 V is required to drive a liquid crystal panel TFT (thin film transistor). Therefore, the thickness of the gate oxide film cannot be reduced. When the nonvolatile memory of the present invention is mixedly mounted on the liquid crystal driver LSI for image adjustment, in the memory element used in the present invention, the charge holding film (silicon nitride film 242) and the channel region or well are independent of the gate insulating film thickness. The thickness of the insulating film separating the region can be optimally designed. For example, a memory cell having a gate electrode length (word line width) of 250 nm can be individually set at T1 = 20 nm and T2 = 10 nm, and a memory cell with high writing efficiency can be realized (T1 is larger than a normal logic transistor). The reason why the short channel effect does not occur even if the thickness is large is that the source / drain regions are offset with respect to the gate electrode.)
[0233]
(Embodiment 16)
As shown in FIG. 34, in the memory element of this embodiment, the thickness T1 of the insulating film separating the charge holding film (silicon nitride film 242) and the channel region or the well region in the second embodiment is different from that of the second embodiment. Except for being thicker than the thickness T2 of the insulating film 214, it has a substantially similar configuration.
[0234]
The thickness T2 of the gate insulating film 214 has an upper limit due to a demand for preventing a short channel effect of the device. However, the thickness T1 of the insulating film can be larger than the thickness T2 of the gate insulating film 214 regardless of the requirement for preventing the short channel effect. In other words, when the miniaturization scaling advances (when the gate insulating film 214 becomes thinner), the charge retaining film (silicon nitride film 242) is separated from the channel region or the well region independently of the gate insulating film thickness. Since the thickness T1 of the insulating film (silicon oxide film) can be optimally designed, there is an effect that the first and second memory function bodies 261 and 262 do not hinder the scaling.
[0235]
In the memory element of the present embodiment, as described above, the degree of freedom in design with respect to the thickness T1 of the insulating film is high, as described above, because the insulating film that separates the charge retention film from the channel region or the well region is The reason is that it is not sandwiched between the gate electrode and the channel region or the well region. Therefore, the thickness T1 of the insulating film can be made larger than the thickness T2 of the gate insulating film 214 regardless of the request for preventing the short channel effect on the gate insulating film 214.
[0236]
By increasing the thickness T1 of the insulating film, the charge stored in the first and second memory function bodies 261 and 262 can be prevented from being dissipated, and the retention characteristics of the memory can be improved.
Therefore, by setting T1> T2, it is possible to improve the holding characteristics without deteriorating the short channel effect of the memory.
[0237]
The thickness T1 of the insulating film is preferably 20 nm or less in consideration of a decrease in the rewriting speed.
[0238]
Specifically, in a conventional nonvolatile memory represented by a flash memory, a select gate electrode forms a write / erase gate electrode, and a gate insulating film (including a floating gate) corresponding to the write / erase gate electrode has a charge. The storage film is also used. For this reason, the demand for miniaturization (it is necessary to reduce the film thickness to suppress the short channel effect) and the securing of reliability (the thickness of the insulating film that separates the floating gate from the channel region or the well region in order to suppress the leakage of the retained charges, Since the requirement of being less than about 7 nm cannot be achieved, miniaturization becomes difficult. In fact, according to the ITRS (International Technology Roadmap for Semiconductors), the miniaturization of the physical gate length is not expected to be about 0.2 μm or less. In the memory element used in the present invention, since T1 and T2 can be individually designed as described above, miniaturization becomes possible. For example, in the present invention, for a memory cell having a gate electrode length (word line width) of 45 nm, T2 = 4 nm and T1 = 7 nm are individually set to realize a memory element in which a short channel effect does not occur. Even if the thickness T2 of the gate insulating film 214 is set to be larger than that of a normal logic transistor, the short channel effect does not occur because the source / drain region is offset with respect to the gate electrode. Further, in the memory element used in the present invention, since the source / drain regions are offset with respect to the gate electrode, miniaturization is further facilitated as compared with a normal logic transistor.
[0239]
In summary, since there is no electrode for assisting writing and erasing above the first and second memory function bodies 261 and 262, the insulating film separating the charge holding film and the channel region or the well region has a write operation. The high electric field acting between the electrode for assisting read / erase and the channel region or the well region does not directly act, but only a relatively weak electric field spreading laterally from the gate electrode 217 acts. Therefore, it is possible to realize a memory cell having a gate length that is reduced to be equal to or more than the gate length of the logic transistor for the same processing generation.
[0240]
(Embodiment 17)
This embodiment relates to a change in electrical characteristics when a memory element is rewritten.
[0241]
FIG. 35 is a diagram showing characteristics (actually measured values) of the drain current Id versus the gate voltage Vg when the amount of charge in the memory function body of the N-channel type memory element changes. In FIG. 22, the solid line shows the relationship between the drain current Id and the gate voltage Vg in the erased state, and the dotted line shows the relationship between the drain current Id and the gate voltage Vg in the written state.
[0242]
As is clear from FIG. 35, when the writing operation is performed from the erased state (the state indicated by the solid line in FIG. 35), not only the threshold value simply rises, but also the inclination of the graph is significantly reduced particularly in the sub-threshold region. are doing. Therefore, even in a region where the gate voltage Vg is relatively high, the drain current ratio between the erased state and the written state is large. For example, even at Vg = 2.5 V, the current ratio maintains two digits or more. This characteristic is significantly different from the case of the flash memory (FIG. 39).
[0243]
The appearance of such characteristics is a peculiar phenomenon that occurs because the gate electrode and the diffusion region are offset and the gate electric field is hard to reach the offset region. When the memory element is in the written state, even if a positive voltage is applied to the gate electrode, it is extremely difficult to form an inversion layer in the offset region below the memory function body. This causes the slope of the Id-Vg curve in the sub-threshold region to decrease in the writing state. On the other hand, when the memory element is in the erased state, high-density electrons are induced in the offset region. When 0 V is applied to the gate electrode (that is, when the gate electrode is off), no electrons are induced in the channel below the gate electrode (therefore, the off-state current is small). This causes a large slope of the Id-Vg curve in the sub-threshold region in the erased state, and a large current increase rate (conductance) even in the region above the threshold.
[0244]
As is apparent from the above, the memory element used in the present invention can particularly increase the drain current ratio between the time of writing and the time of erasing.
[0245]
A memory element included in a memory cell array which is an example of the semiconductor memory device of the present invention can store 2-bit information, is easily miniaturized, and is easy to form.
[0246]
The memory element included in the semiconductor memory device of the present invention mainly includes a first conductivity type region that is a diffusion region, a second conductivity type region adjacent to the first conductivity type region, and a first conductivity type region. It has a memory function body extending over the region of the second conductivity type from above, and an electrode formed on a side of the memory function body. This electrode is formed on the region of the second conductivity type via an insulating film. Alternatively, the memory element mainly includes a gate insulating film, a gate electrode formed on the gate insulating film, a memory function body formed on both sides of the gate electrode, and a memory function body on a side opposite to the gate electrode. It has a source / drain region (diffusion region) arranged and a channel region arranged below the gate electrode.
[0247]
In this specification, the first conductivity type means p-type or n-type. The second conductivity type means n-type when the first conductivity type is p-type and p-type when the first conductivity type is n-type.
[0248]
The memory element functions as a memory element for storing quaternary or more information by storing binary or more information in one memory function body, and also by a variable resistance effect by the memory function body. , Also functions as a memory cell having both functions of a selection transistor and a memory transistor.
[0249]
The memory element can store quaternary or more information, but it is not necessary to store and function quaternary or more information. For example, the memory element may store and function binary information.
[0250]
The semiconductor memory device of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type (p-type or n-type) well region formed in the semiconductor substrate.
[0251]
The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. For example, a bulk substrate made of an elemental semiconductor such as silicon and germanium, or silicon germanium, GaAs, InGaAs, ZnSe, GaN, etc. And a bulk substrate made of the compound semiconductor. Further, a substrate having a semiconductor layer on a surface may be used as the semiconductor substrate. Examples of the substrate include various substrates such as a single-layer SOI (silicon-on-insulator) substrate and a multi-layer SOI substrate, and a glass substrate and a plastic substrate having a semiconductor layer on the surface. Among the above-described substrates, a silicon substrate, an SOI substrate having a silicon layer formed on a surface, or the like is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystal, or amorphous.
[0252]
An element isolation region is preferably formed in the semiconductor substrate or the semiconductor layer. Further, elements such as a transistor, a capacitor, and a resistor, a circuit including the elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multiple element. It may be formed in a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS (local silicon oxide) film, a trench oxide film, and an STI film. The semiconductor substrate may have a p-type or n-type conductivity type, and the semiconductor substrate preferably has at least one first conductivity type (p-type or n-type) well region formed therein. . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, the SOI substrate may have a well region formed in a surface semiconductor layer, or may have a body region below a channel region.
[0253]
The gate insulating film or the insulating film is not particularly limited as long as it is generally used for a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film can be used. In addition, as the gate insulating film, a single-layer film or a stacked film of a high dielectric film such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film can be used. Among these films, a silicon oxide film is preferable. The gate insulating film has a thickness of, for example, about 1 to 20 nm, preferably about 1 to 6 nm. Further, the gate insulating film may be formed only immediately below the gate electrode, or may be formed to be larger (wider) than the gate electrode. That is, the width of the gate insulating film may be the same as the width of the gate electrode, or may be larger than the width of the gate electrode.
[0254]
The gate electrode is formed on the gate insulating film in a shape that is usually used for a semiconductor device or in a shape having a concave portion at a lower end. Further, the gate electrode may be a single gate electrode. The “single gate electrode” means a gate electrode formed in an integral shape so as not to be separated by a single-layer or multiple-layer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. That is, at least a part of the side wall of the gate electrode may be formed of an insulating film.
[0255]
The gate electrode is not particularly limited as long as it is generally used for a semiconductor device. That is, examples of the gate electrode include a conductive film, for example, an electrode made of polysilicon, an electrode made of a metal such as copper and aluminum, an electrode made of a high melting point metal such as tungsten, titanium, and tantalum, and a silicide with a high melting point metal. And the like made of a single-layer film or a laminated film. The gate electrode is preferably formed to have a thickness of, for example, about 50 to 400 nm. Note that a channel region is formed below the gate electrode.
[0256]
The memory function body has at least a function of retaining charge, a function of storing and retaining charge, a function of trapping charge, or a film having a function of retaining a charge polarization state or Contains the area. Those that fulfill these functions include silicon nitride, silicon, phosphorus, silicate glass, silicon carbide, alumina, high dielectric, zinc oxide, ferroelectric, and metal. Since the silicon nitride has a large number of levels for trapping charges, a large hysteresis characteristic can be obtained. In addition, the silicon nitride has a long charge retention time, does not cause a problem of charge leakage due to generation of a leak path, and has good retention characteristics, and is used as a standard in LSI (Large Scale Integrated Circuit) processes. It is preferable because it is a material. Further, the silicate glass contains impurities such as phosphorus and boron. Examples of the high dielectric include hafnium oxide, zirconium oxide, and tantalum oxide.
[0257]
Further, the memory function body may be formed of, for example, an insulating film including a silicon nitride film, or may be formed of an insulating film including a conductive film or a semiconductor layer therein. Further, the memory function body may be formed of an insulator film including one or more conductive dots or semiconductor dots. Further, the memory function body may be formed by a single layer or a laminated structure of an insulating film or the like including a ferroelectric film in which internal charges are polarized by an electric field and the state is maintained.
[0258]
By using an insulating film including an insulating film having a charge retaining function such as the silicon nitride film therein as a memory function body, reliability of storage retention can be improved. This is because since the silicon nitride film is an insulator, even if a part of the silicon nitride film leaks electric charge, the electric charge of the entire silicon nitride film is not immediately lost. Furthermore, when a plurality of memory elements are arranged, even if the distance between the memory elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of a conductor. This is because the information that has been given will not be lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the memory element.
[0259]
Further, in order to further increase the reliability of memory retention, the region having the function of retaining charges does not necessarily have to be in the form of a film, but preferably exists discretely. Specifically, it is preferable that the above-mentioned region is dispersed in a dot shape in a material that does not easily retain electric charge, for example, silicon oxide.
[0260]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0261]
Further, by using an insulator film containing one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0262]
Further, the memory function body includes PZT (lead zirconium titanate) and PLZT ((Pb _1-y La _y ) (Zr _x Ti _1-x ) O ₃ ) May be included. In this case, electric charge is substantially generated on the surface of the ferroelectric film by the polarization, and the electric charge is held in this state. Therefore, the ferroelectric film can have the same hysteresis characteristics as a film that traps electric charges supplied from outside the film. In addition, the charge retention of the ferroelectric film does not require charge injection from outside the film, and the hysteresis characteristic can be obtained only by the polarization of the charge in the film. is there.
[0263]
It is preferable that the memory function body further includes a region which makes it difficult for the charge to escape, or a film having a function of making the charge hard to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0264]
The charge retaining film included in the memory function body is formed on both sides of the gate electrode directly or via an insulating film. Further, the charge retention film is disposed directly on the semiconductor substrate (well region, body region, source / drain region or diffusion region). Alternatively, the charge retention film is disposed on a semiconductor substrate (well region, body region, source / drain region, or diffusion region) via a gate insulating film or an insulating film. It is preferable that the charge holding films on both sides of the gate electrode are formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed to completely or partially fill the concave portion directly or via an insulating film.
[0265]
Preferably, the gate electrode is formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. That is, it is preferable that the uppermost position of the gate electrode is not higher than the uppermost position of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the memory element is facilitated. Further, a memory element having such a simple arrangement is easy to manufacture and can improve the yield.
[0266]
In the case where a conductive film is used as the charge holding film, the charge holding film is arranged via an insulating film so as not to come into direct contact with the semiconductor substrate (well region, body region, source / drain region or diffusion region) or the gate electrode. Preferably. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductor is dispersed in a dot shape or the like in an insulating film, a structure in which a conductor is arranged in a part of a sidewall insulating film formed on a side wall of a gate, and the like. Is mentioned.
[0267]
The source / drain regions are formed on the surface of the semiconductor substrate opposite to the gate electrode of the charge holding film, respectively, as diffusion regions of a conductivity type opposite to that of the semiconductor substrate or the well region. The junction between the source / drain region and the semiconductor substrate or well region preferably has a steep impurity concentration. This is because if the impurity concentration at the junction is steep, hot electrons and hot holes are efficiently generated at a low voltage, and high-speed operation at a lower voltage is possible. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that in the case where an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have the following junction depth.
[0268]
Further, the source / drain region may be formed so as to overlap with the gate electrode end, may be formed so that the gate electrode end may coincide with the end, or may be offset with respect to the gate electrode end. You may form so that it may be. In particular, when the source / drain region is offset with respect to the gate electrode end, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region below the charge retaining film is accumulated in the memory function body. This is preferable because it greatly changes depending on the amount of electric charge, which increases the memory effect and reduces the short channel effect. However, if the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset amount is larger than the thickness of the charge holding film in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the nearer source / drain region is shorter. What is particularly important is that at least a part of the charge storage region in the memory function body overlaps with a part of the source / drain region which is a diffusion region. The essence of the memory element constituting the semiconductor memory device of the present invention is that the memory is rewritten by the electric field crossing the memory function body due to the voltage difference between the gate electrode and the source / drain region existing only on the side wall of the memory function body. That's why.
[0269]
Further, a part of the source / drain region may be extended to a position higher than the surface of the channel region, that is, a lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high melting point metals. Among them, polysilicon is preferable. This is because polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate, and it is easy to suppress the short channel effect. It is. In this case, it is preferable that a part of the source / drain region is disposed so as to sandwich at least a part of the memory function body together with the gate electrode.
[0270]
Further, the memory element can be formed by a normal semiconductor process, for example, by a method similar to a method of forming a single-layer or stacked-layer side wall spacer on a side of a gate electrode. Specifically, the following methods (a) to (e) and the like can be used as the method for forming the memory element.
[0271]
(A) After forming the gate electrode, a single layer film or a multilayer film including a charge holding film such as a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, etc. A method in which films are formed and etched back under appropriate conditions to leave these films in the form of sidewall spacers.
[0272]
(B) An insulating film or a charge retaining film is formed and etched back under appropriate conditions to leave a sidewall spacer shape. Further, a charge retaining film or an insulating film is formed and similarly etched back to form a sidewall spacer shape. How to leave on.
[0273]
(C) An insulating film material in which a particulate charge holding material is dispersed is applied or deposited on a semiconductor substrate including a gate electrode, and is etched back under appropriate conditions to leave the insulating film material in a sidewall spacer shape. Method.
[0274]
(D) A method of forming the single-layer film or the multi-layer film after forming the gate electrode, and patterning using a mask.
[0275]
(E) Before forming a gate electrode or an electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, etc. are formed, and a channel of these films is formed. A method in which an opening is formed in a region to be a region, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
[0276]
When a memory cell array is configured by using a plurality of the memory elements, the best mode of the memory element satisfies the following requirements (1) to (10).
[0277]
(1) The gate electrodes of a plurality of memory elements are integrated with a word line.
[0278]
(2) A memory function body is formed on both sides of the word line.
[0279]
(3) It is an insulator, particularly a silicon nitride film, that holds charges in the memory function body.
[0280]
(4) The memory function body is composed of an ONO film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulating film.
[0281]
(5) The silicon nitride film in the memory function body is separated from the word line and the channel region by the silicon oxide film.
[0282]
(6) The silicon nitride film and the diffusion layer in the memory function body overlap.
[0283]
(7) The thickness of the insulating film that separates the silicon nitride film having a surface substantially parallel to the surface of the gate insulating film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film.
[0284]
(8) Write and erase operations of one memory element are performed by a single word line.
[0285]
(9) There is no electrode (word line) having the function of assisting the writing and erasing operations on the memory function body.
[0286]
(10) A region having a high impurity concentration of a conductivity type opposite to the conductivity type of the diffusion region is provided immediately below the memory function body in contact with the diffusion region.
[0287]
The best mode is the case where all of the above requirements (1) to (10) are satisfied, but, needless to say, it is not always necessary to satisfy all of the above requirements.
[0288]
When a plurality of requirements among the requirements (1) to (10) are satisfied, a particularly preferable combination exists. For example, (3) an insulator, particularly a silicon nitride film, holds electric charges in the memory function body, and (9) an electrode (word line) having a function of assisting a write and erase operation on the memory function body. (6) The case where the insulating film (silicon nitride film) in the memory function body and the diffusion layer overlap. When the insulator holds the electric charge in the memory function body and there is no electrode having the function of assisting the writing and erasing operations on the memory function body, the insulating film in the memory function body It has been found that the writing operation is performed favorably only when the (silicon nitride film) and the diffusion layer overlap. That is, it has been found that when the requirements (3) and (9) are satisfied, the requirement (6) must be satisfied. On the other hand, when the electric charge is held in the memory function body by the conductor, the writing operation can be performed even when the conductor in the memory function body and the diffusion layer do not overlap (the conductor in the memory function body). Is to assist writing by capacitive coupling with the writing electrode). In addition, when there was an electrode having a function of assisting the writing and erasing operations on the memory function body, the writing operation could be performed even when the insulating film and the diffusion layer in the memory function body did not overlap. .
[0289]
However, in the case where it is an insulator, not a conductor, that retains electric charge in the memory function body, and there is no electrode on the memory function body having a function of assisting writing and erasing operations, A very large effect can be obtained.
[0290]
First, the bit line contact can be arranged closer to the memory function body on the side wall of the word line, or even if the distance between the memory elements is short, a plurality of memory function bodies can hold the stored information without interference. This facilitates miniaturization of the memory element. When the charge holding region in the memory function body is a conductor, interference occurs between the charge holding regions as the memory elements approach each other due to capacitive coupling, and storage information cannot be held.
[0291]
When the charge holding region in the memory function body is an insulator (for example, a silicon nitride film), it is not necessary to make the memory function body independent for each memory cell. For example, memory function bodies formed on both sides of one word line shared by a plurality of memory cells do not need to be separated for each memory cell, and memory function bodies formed on both sides of one word line. Can be shared by a plurality of memory cells sharing a word line. Therefore, a photo and etching process for separating the memory function body is not required, and the manufacturing process is simplified. Further, a margin for alignment of a photo and a margin for reducing the thickness of an etching film are not required, so that a margin between memory cells can be reduced. Therefore, as compared with the case where the charge holding region in the memory function body is a conductor (for example, a polycrystalline silicon film), even if formed at the same fine processing level, there is an effect that the memory cell occupation area can be reduced (memory If the charge holding region in the functional body is a conductor, a photo and etching step for separating the memory functional body for each memory cell is required, and a photo alignment margin and an etching film reduction margin are required.
[0292]
Furthermore, since there is no electrode having the function of assisting the writing and erasing operations on the memory function body and the element structure is simple, the number of steps is reduced, the yield is improved, and the transistors forming the logic circuit and the analog circuit are formed. Can be easily combined.
Further, as a very important design matter, the case where the charge holding region in the memory function body is an insulator and there is no electrode having a function of assisting the writing and erasing operations on the memory function body (the above two cases). By satisfying the conditions, a very important effect of reducing the cell occupation area, improving the yield by simplifying the manufacturing method, and reducing the cost can be obtained). We have found that overlapping allows writing and erasing at very low voltages. Specifically, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less. This function has a very large effect on circuit design. That is, since it is not necessary to generate a high voltage in a chip as in a flash memory, it is possible to omit a charge pumping circuit requiring an enormous occupation area or to reduce the scale. In particular, when a small-capacity memory is incorporated in a logic LSI for adjustment, the occupied area of the memory section is dominated by the occupied area of the peripheral circuit that drives the memory cell rather than the memory cell. Eliminating or reducing the scale of the booster circuit is most effective for reducing the chip size.
[0293]
As described above, it is particularly preferable to satisfy the requirements (3), (9), and (6).
[0294]
The semiconductor memory device in which the memory element and the logic element are combined can be used for a battery-driven portable electronic device, particularly, a portable information terminal. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.
[0295]
【The invention's effect】
As is clear from the above, according to the semiconductor memory device of the present invention, it is possible to rewrite or read the storage information of a specific memory function by selecting a specific word line and a specific bit line.
[0296]
Further, a memory function body having a function of retaining charge or a function of retaining polarization is formed on a side wall of the gate electrode of the storage element, and is separated from a gate insulator separating the channel region and the gate electrode. Is formed. Therefore, it is easy to suppress the short channel effect by reducing the thickness of the gate insulator. Therefore, the memory element can be miniaturized, and the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a memory cell array according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view taken along line 2-2 of FIG.
FIG. 3 is a schematic sectional view taken along line 3-3 in FIG. 1;
FIG. 4 is a circuit diagram of the memory cell array according to the first embodiment.
FIG. 5 is a schematic plan view of a modified example of the memory cell array according to the first embodiment.
FIG. 6 is a schematic plan view of a memory cell array according to a second embodiment of the present invention.
FIG. 7 is a schematic sectional view taken along line 7-7 in FIG. 6;
FIG. 8 is a schematic plan view of a memory cell array according to a third embodiment of the present invention.
FIG. 9 is a diagram for explaining an arrangement of a first-layer metal wiring of the memory cell array according to the third embodiment;
FIG. 10 is a diagram illustrating a process of forming a memory cell of a memory cell array according to a fourth embodiment of the present invention.
FIG. 11 is a schematic sectional view of the memory cell array according to the fourth embodiment.
FIG. 12 is another schematic cross-sectional view of the memory cell array according to the fourth embodiment.
FIG. 13 is a diagram for explaining an arrangement of metal wires of the memory cell array according to the fourth embodiment.
FIG. 14 is a schematic sectional view of a modification of the memory cell array according to the fourth embodiment.
FIG. 15 is a block diagram of a semiconductor memory device according to a sixth embodiment of the present invention.
FIG. 16 is a block diagram of a portable electronic device.
FIG. 17 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a ninth embodiment of the present invention;
FIG. 18 is a schematic sectional view of a modified example of the memory element of FIG. 17;
FIG. 19 is a diagram for explaining a write operation of a memory element used in the semiconductor memory device of the present invention.
FIG. 20 is a diagram for explaining a write operation of a memory element used in the semiconductor memory device of the present invention.
FIG. 21 is a diagram for explaining an erase operation of a memory element used in the semiconductor memory device of the present invention.
FIG. 22 is a diagram for explaining an erase operation of a memory element used in the semiconductor memory device of the present invention.
FIG. 23 is a diagram illustrating a read operation of a memory element used in the semiconductor memory device of the present invention.
FIG. 24 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a tenth embodiment of the present invention;
FIG. 25 is an enlarged view of a part of the memory device of FIG. 24;
FIG. 26 is an enlarged view of a part of a modification of the memory element of FIG. 24;
FIG. 27 is a graph showing electric characteristics of the memory device of FIG. 24;
FIG. 28 is an enlarged view of a part of another modification of the memory device of FIG. 24;
FIG. 29 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to an eleventh embodiment of the present invention;
FIG. 30 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a twelfth embodiment of the present invention.
FIG. 31 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a thirteenth embodiment of the present invention;
FIG. 32 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a fourteenth embodiment of the present invention;
FIG. 33 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a fifteenth embodiment of the present invention;
FIG. 34 is a schematic sectional view of a main part of a memory element used in a semiconductor memory device according to a sixteenth embodiment of the present invention.
FIG. 35 is a graph showing electric characteristics of a memory element used in the semiconductor memory device according to Embodiment 17 of the present invention;
FIG. 36 is a schematic plan view of a memory cell array of a conventional flash memory.
FIG. 37 is a schematic sectional view taken along line 37-37 of FIG. 36;
FIG. 38 is a graph showing electric characteristics of the conventional flash memory.
[Explanation of symbols]
101, 211, 286, 1101, 101, 3101, 4101 Semiconductor substrate
102, 1102, 2102, 4102 p-type well region
104,217 Gate electrode
105a, 105b, 1105a, 1105b Memory function body
107a, 212, 261 First diffusion region
107b, 213, 262 Second diffusion region
122,272,1111 Channel area
131a, 261 First memory function body
131b, 262, 262a, 262b Second memory function body
214, 1103, 4103 Gate insulating film
287 body region
1104, 2104, 3104, 4104 Word line
1107, 2107, 3107 Source / drain diffusion regions
1108, 2108, 3108 Element isolation region
1110, 2110, 3110 Active area
1131, 1311, 3131, 4131, 4231 contacts
1132, 2132, 3132, 4132 Bit line
4107 Diffusion area
4108 Trench element isolation
M11, M21, ..., M33 memory cells
m1, m2 memory function body

Claims (13)

A semiconductor substrate having an element isolation region and an active region on its surface,
A storage element that is a plurality of field-effect transistors formed in the active region and arranged in a matrix,
A word line connected to the gate electrode of the storage element in the same row;
A bit line electrically connected in common to a source / drain diffusion region of the storage element in the same column via a contact;
Regarding two adjacent bit lines, one bit line is electrically connected to one of the source / drain diffusion regions in the same column, while the other bit line is electrically connected to the source / drain diffusion region in the same column. Electrically connected to the other of
The storage element is
The gate electrode formed on the semiconductor substrate via a gate insulating film,
Two memory function bodies formed on both sides of the gate electrode and having a function of retaining charge or polarization;
A channel region disposed below the gate insulating film;
The source / drain diffusion regions disposed on both sides of the channel region.
The amount of current flowing from one of the source / drain diffusion regions to the other of the source / drain diffusion regions when a voltage is applied to the gate electrode changes depending on the amount of charge or polarization held in the memory function body. A semiconductor memory device characterized by the following. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the contacts are commonly connected to the adjacent source / drain diffusion regions in the same row. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein the memory function unit performs a rewrite operation and a read operation as independent storage units. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the contact has an elliptical column shape. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the contact is electrically connected to the source / drain diffusion region via an elliptical conductor. The semiconductor memory device according to claim 1,
The memory function body,
A charge holding film having a function of holding charge or polarization by having a surface substantially parallel to the surface of the gate insulating film,
Having an insulating film formed between the charge retention film and the active region,
A semiconductor memory device wherein the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more. The semiconductor memory device according to claim 1,
The memory function body,
A charge holding film having a function of holding charge or polarization by having a surface substantially parallel to the surface of the gate insulating film,
Having an insulating film formed between the charge retention film and the active region,
A semiconductor memory device, wherein the thickness of the insulating film is larger than the thickness of the gate insulating film and is equal to or less than 20 nm. The semiconductor memory device according to claim 1,
The semiconductor memory device according to claim 1, wherein the memory function body includes a silicon nitride film and a silicon oxide film sandwiching the silicon nitride film. The semiconductor memory device according to claim 1,
The memory function body has an insulating film, and a plurality of dot-shaped metal bodies formed in the insulating film,
A semiconductor memory device, wherein the diameter of the metal body is in a range of 0.1 nm or more and 20 nm or less. The semiconductor memory device according to claim 1,
A semiconductor memory device including a column decoder, a sense amplifier, and a row decoder, and comprising one chip. The semiconductor memory device according to claim 1,
A semiconductor memory device comprising a liquid crystal driver. 2. The operation method of the semiconductor memory device according to claim 1, wherein:
Before applying a potential for performing a read operation to the word line connected to the channel region of the storage element to which the memory function body to be operated belongs,
All the bit lines located on one side of the storage element are precharged to a first potential, and all the bit lines located on the other side of the storage element are precharged to a second potential. A method for operating a semiconductor memory device, comprising charging. A portable electronic device comprising the semiconductor storage device according to claim 1.

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