JP2004349353A - Semiconductor storage device, its operating method, and portable electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which a storage element can be miniaturized and, at the same time, which can be reduced in manufacturing cost, because an insulator separating a channel region and a word electrode from each other is formed in a separated state and a short channel effect can be suppressed easily by reducing the thickness of the insulator. <P>SOLUTION: In the semiconductor storage device, a plurality of memory elements which are composed of field effect transistors are formed in an active region and disposed in a matrix-like state. The memory elements are formed on parts of word lines 1104 formed as gate electrodes on a semiconductor substrate 1101 through gate insulating films 1103 and on the lateral sides of the gate electrodes; and contain memory function groups 1105a and 1105b having charge holding functions, channel regions 1110 disposed under the gate insulating films 1103, and diffusion regions 1107 disposed on both sides of the channel regions 1110. In addition, two memory elements adjoining each other in the same row own jointly the diffusion region 1107 disposed in the area between the gate electrodes of the memory elements. Moreover, two memory elements adjoining each other in the same column also own jointly the diffusion region 1107 disposed in the area between the gate electrodes of the memory elements. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０１７７】
上記表１から明らかなように、本実施の形態のメモリセルアレイは、ランダムアクセス（１ビット毎の読出し及び書換え動作）が可能である。このため、一括消去しなければならないデバイスに比較し、アクセス効率を上げることが可能である。また、メモリ状態の一時記憶、一括消去、書込みといったシーケンスも不要となるため制御回路が簡単になるという効果がある。なお、上述の第１の消去方法を用いた場合は、表１においてＬｂｅ２をＬｂｅ１と同じ（０Ｖ）にし、Ｈｂｅを適切な電圧値（例えば＋６Ｖ）にすればよい。この場合、消去動作は少なくとも２ビットが一括に行われることとなる。
【０１７８】
上記読出し動作時によれば、あるメモリセルの２ビットの記憶を連続して読み出そうとする場合（例えば、メモリセルＭ２３のメモリ機能体ｍ１、ｍ２を連続して読み出すなど）、近傍のビット線の電位を全て反転しなければならない（上の例ではビット線ＢＬ２〜ＢＬ５の電位を全て反転する）ため、効率が悪い。そのため、アドレスデコーダー回路などの工夫を行い、左右のメモリ機能体のアドレスを互いに離すなどの対策を行なうことにより連続して交互に読み出す状態を回避することが好ましい。
【０１７９】
以上の説明より明らかなように、本実施の形態のメモリセルアレイは、上記メモリ素子を配列して構成されている。上述のように、上記メモリ素子は、１つの素子で２ビットの記憶が可能であり、ゲート絶縁膜の薄膜化が可能であるから、微細化が容易である。したがって、上記メモリ素子を配列して構成する本実施の形態のメモリセルアレイも、面積の縮小（もしくは高密度化）が容易となり、製造コストが削減される。
【０１８０】
また、本実施の形態のメモリセルアレイにおいては、１つの拡散領域が、４個のメモリ素子（電界効果トランジスタ）によって共有されているため、ビット線数及びビット線と拡散領域とを接続するコンタクト孔数が少なくなる。したがって、ビット線及びコンタクト孔に纏わるマージンが小さいのでメモリセルアレイの更なる縮小（もしくは高密度化）及び製造コストの低減が可能となる。
【０１８１】
また、上述のように、上記メモリ素子を形成するプロセスは、通常のＣＭＯＳ（相補型金属酸化膜半導体）プロセスに非常に近く、従来のＥＥＰＲＯＭなどフローティングゲートを有する不揮発性メモリに比べて非常に簡単に製造することが可能である。したがって、本発明のメモリセルアレイの製造が容易であり、更には論理回路との混載も容易となる。
【０１８２】
本実施の形態に用いるメモリ素子は、上記実施の形態２に記載するように、メモリ機能体２６１、２６２における電荷を保持する領域（シリコン窒化膜２４２）は、拡散領域２１２、２１３とそれぞれオーバーラップするのが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、半導体記憶装置の読出し速度を十分に高速にすることができる。
【０１８３】
また、本実施の形態に用いるメモリ素子は、実施の形態２に記載するように、メモリ機能体は、ゲート絶縁膜表面と略平行に配置されるな電荷保持膜を含むことが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、メモリ素子のメモリ効果のばらつきを小さくすることができるので、半導体記憶装置の読出し電流ばらつきを抑えることができる。更には、記憶保持中のメモリ素子の特性変化を小さくすることができるので、半導体記憶装置の記憶保持特性が向上する。
【０１８４】
また、本実施の形態に用いるメモリ素子は、上記実施の形態３に記載するように、メモリ機能体は、ゲート絶縁膜表面と略平行に配置されるな電荷保持膜を含み、かつ、ゲート電極側面と略並行に延びた部分を含むことが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、メモリ素子の書換え速度が増大するので、半導体記憶装置の書換え動作を高速にすることができる。
【０１８５】
また、本実施の形態に用いるメモリ素子は、上記実施の形態７のメモリ素子を用いることが好ましい。すなわち、電荷保持膜（シリコン窒化膜２４２）とチャネル領域又はウェル領域とを隔てる絶縁膜の厚さ（Ｔ１）が、ゲート絶縁膜の厚さ（Ｔ２）よりも薄く、０．８ｎｍ以上であることが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、書込み動作及び消去動作の電圧を低下させ、又は書込み動作及び消去動作を高速にすることが可能となる。更には、メモリ素子のメモリ効果が増大するので、半導体記憶装置の読出し速度を高速にすることが可能となる。
【０１８６】
また、本実施の形態に用いるメモリ素子は、上記実施の形態８のメモリ素子を用いることが好ましい。すなわち、電荷保持膜（シリコン窒化膜２４２）とチャネル領域又はウェル領域とを隔てる絶縁膜の厚さ（Ｔ１）が、ゲート絶縁膜の厚さ（Ｔ２）よりも厚く、２０ｎｍ以下であることが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、メモリ素子の短チャネル効果を悪化させることなく保持特性を改善することができるから、半導体記憶装置を高集積化しても十分な記憶保持性能を得ることができる。
【０１８７】
また、本実施の形態に用いるメモリ素子は、例えば上記実施の形態２（図７）のように、シリコン窒化膜がシリコン酸化膜で挟まれた構造を有するメモリ機能体を備えていることが好ましい。このようなメモリ素子を本実施の形態の半導体記憶装置に用いれば、半導体記憶装置の動作速度を向上し、信頼性を向上させることが可能となる。
【０１８８】
また、本実施の形態に用いるメモリ素子は、既に述べた最良の形態のメモリ素子を用いるのが、最も好ましい。それにより、半導体記憶装置の性能を最良のものにすることができる。
【０１８９】
（実施の形態１１）
本発明の実施の形態１１を、図２５を用いて説明する。本実施の形態の半導体記憶装置は、上記実施の形態１０の半導体記憶装置において、ワード線１１０４（ＷＬ１、ＷＬ２、ＷＬ３、ＷＬ４）を蛇行させることによりメモリセル面積を縮小したものである。また、図２５において、図２０に示した構成部と同一構成部は、図２０における構成部と同一参照番号を付して説明を省略する。
【０１９０】
ワード線１１０４（ＷＬ１、ＷＬ２、ＷＬ３、ＷＬ４）は、素子分離領域１１０８が並ぶ周期と同期して蛇行している。互いに隣接するワード線１１０４の蛇行は、逆位相となっている（１８０度ずれている）。そのため、互いに隣り合う２本のワード線１１０４において、ワード線１１０４が延びる方向と垂直な方向（図２５における紙面上下方向）における距離は、素子分離領域１０８が並ぶ周期と同期して変化している。具体的には、上記隣り合う２本のワード線１１０４間において、ビット線１１３２が延在する方向に平行な方向の距離は、活性領域上よりも素子分離領域１１０８上の方が短くなっている。具体的には、互いに隣り合うワード線１１０４間に第１又は第２の拡散領域Ｄ１、Ｄ２が挟持される部分においては上記距離は長く、互いに隣接するワード線が１つの素子分離領域１１０８上を通過する部分においては上記距離は短い。
【０１９１】
上記のようにワード線１１０４（ＷＬ１、ＷＬ２、ＷＬ３、ＷＬ４）を蛇行させることにより、ワード線１１０４とコンタクトＣＨとのマージンを保ったまま、素子分離領域１１０８の長さを短くすることができる。図２０と図２５とを比較すれば明らかなように、本実施の形態の半導体記憶装置のメモリセルの大きさは、図２５における紙面上下方向の長さにおいて縮小される。したがって、メモリセルアレイの更なる縮小（もしくは高密度化）及び製造コストの低減が可能となる。
【０１９２】
（実施の形態１２）
本発明の実施の形態１２を、図２６及び図２７を用いて説明する。本実施の形態の半導体記憶装置は、上記実施の形態１又は上記実施の形態２のメモリセルアレイと論理回路部とを含み、１つのチップから成っている。
【０１９３】
図２６は、メモリセルアレイを構成する記憶素子１３と、論理回路部を構成するスイッチング素子１４との概略の断面図を並べて比較した図である。ここでは、既出の符号については説明を省略する。記憶素子１３と、スイッチング素子１４との構造上の違いは、スイッチング素子１４においては、拡散領域１２０７ａ、１２０７ｂがゲート端に達しているという点のみである。すなわち、スイッチング素子１４はオフセット領域１１２０をもたない。拡散領域１２０７ａ、１２０７ｂは、例えばＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造を有している。なお、スイッチング素子１４のサイドウォールスペーサ１２０５は、記憶素子１３のメモリ機能体１１０５ａ、１１０５ｂと全く同じ構造を有している。
【０１９４】
記憶素子１３を形成するための手順は、通常の標準ロジック（論理）トランジスタ形成プロセスと非常に親和性の高いものとなっている。上述のように論理回路部を構成するスイッチング素子１４は、記憶素子１３の構成に近い構成を有している。上記スイッチング素子１４と上記記憶素子１３との相違点は、スイッチング素子１４においてはサイドウォールスペーサ１２０５をメモリ機能体としては使用しない点と、スイッチング素子４はＬＤＤ領域を持つという点とである。シリコン酸化膜１１１１、１１１２、シリコン窒化膜１１１３の膜厚構成比は記憶素子１３が適切な動作をするように選べばよい。上記スイッチング素子１４のサイドウォールスペーサの膜構成が記憶素子１３と同様な構造であったとしても、サイドウォールスペーサ幅（すなわちシリコン酸化膜１１１１、１１１２とシリコン窒化膜１１１３のトータル膜厚）が適切であって、書換え動作が起こらない電圧範囲で動作させる限り、トランジスタ性能を損なうことがない。
【０１９５】
なお、図２６の参照番号に関して、１１０７ａおよび１１０７ｂはソース・ドレイン拡散領域の一例としての拡散領域、１１２１はゲート電極下領域である。
【０１９６】
これまでの説明で明らかなように、上記論理回路部を構成するスイッチング素子１４と上記メモリセルアレイを構成する記憶素子１３とを混載させるためには、スイッチング素子１４にのみＬＤＤ構造を形成する必要がある。ＬＤＤ構造を形成するためには、上記ゲート電極を形成した後であって上記メモリ機能体（サイドウォールスペーサ）を形成する前に、ＬＤＤ形成のための不純物注入を行なえばよい。したがって、上記ＬＤＤ形成のための不純物注入を行なう際に、上記記憶素子１３のみフォトレジストでマスクするだけで、記憶素子１３と上記論理回路部を構成するスイッチング素子１４とを容易に混載することが可能となる。更に、スイッチング素子１４によってＳＲＡＭ（スタティック・ランダム・アクセス・メモリ）を構成すれば、不揮発性メモリ、ロジック回路、ＳＲＡＭを容易に混載することができる。
【０１９７】
なお、スイッチング素子１４は必ずしもＬＤＤ構造を有する必要はなく、記憶素子３は必ずしもＬＤＤ構造を有してはならないわけではない。しかしながら、スイッチング素子１４はＬＤＤ構造を有し、記憶素子１３は必ずしもＬＤＤ構造を有しないのが好ましい。これにより、スイッチング素子１４の駆動電流を大きくしつつ、記憶素子３のメモリ効果を大きくすることができる。したがって、スイッチング素子１４で構成される上記論理回路部は高速で動作し、かつ記憶素子１３で構成されるメモリセルアレイからは良好なメモリ特性を得ることができる。
【０１９８】
図２７は、本実施の形態である半導体記憶装置の構成図である。半導体記憶装置１５は、記憶素子１３から構成されるメモリセルアレイ１３０１を含んでいる。半導体記憶装置１５は、更に、それぞれスイッチング素子１４から構成されるアクセス対象のメモリセルを特定するためのカラムアドレスバッファ１３０２、ロウアドレスバッファ１３０３、カラムアドレスデコーダー１３０４、ロウアドレスデコーダー１３０５、センスアンプ１３０６、これらの各部を制御する制御回路１３０７、ＭＰＵ（マイクロ・プロセッサ・ユニット）１３０８を含んでいる。
【０１９９】
上記実施の形態１０又は上記実施の形態１１のメモリセルアレイと、論理回路部を１つのチップ上に混載することにより、大容量の不揮発性メモリを搭載し、製造が容易で低コストなＬＳＩチップが提供される。
【０２００】
ところで、上記のような半導体記憶装置を設計する際に、読み出し動作の効率を考えると、前述したように、あるメモリセルの２ビットの記憶を連続して読み出そうとするのは効率が悪い。なぜなら、前述のように、メモリセルの２ビット情報を連続して読み出そうとすれば、読み出し電流の向きを反対にする（ソースとドレインを入れ替える）必要があり、近傍のビット線の電位を全て反転しなければならないからである。それゆえ、あるメモリセルに記憶される２ビットのアドレスは、互いに離しておくのが好ましい。例えば、同一のワード線に属し互いに隣接するメモリセルの記憶ビットの一方を連続したアドレスにしておき、同一メモリセル内の記憶ビットの一方と他方のアドレスは離しておけばよい。
【０２０１】
（実施の形態１３）
上記実施の形態１０乃至１２の半導体記憶装置を、電池駆動の携帯電子機器、特に携帯情報端末に用いることができる。携帯電子機器としては、携帯情報端末、携帯電話、ゲーム機器などが挙げられる。
【０２０２】
図２８は、携帯電話の例を示している。この携帯電話の制御回路１４１１には、本発明の半導体記憶装置又は半導体装置が組み込まれている。また、図２８の参照番号に関して、１４１２は電池、１４１３はＲＦ（無線周波数）回路部、１４１４は表示部、１４１５はアンテナ部、１４１６は信号線、１４１７は電源線である。
【０２０３】
本発明の半導体記憶装置又は半導体装置を携帯電子機器に用いることにより、制御回路の製造コストが削減されるから、携帯電子機器自体のコストを削減することができる。もしくは、制御回路に含まれる不揮発性メモリを大容量化して、携帯電子機器の機能を高度化することができる。
【０２０４】
【発明の効果】
以上より明らかなように、第１の発明の半導体記憶装置によれば、ワード線の側壁には、電荷を保持する機能又は分極を保持する機能を有するメモリ機能体が形成されており、チャネル領域とワード電極とを隔てる絶縁体は分離されて形成されている。その結果、上記絶縁体を薄膜化して短チャネル効果を抑制するのが容易になるから、記憶素子を微細化できると共に、製造コストを削減することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図２】本発明の実施の形態１の半導体記憶装置の他のメモリ素子の要部の概略断面図である。
【図３】上記実施の形態１のメモリ素子の書込み動作を説明する図である。
【図４】上記実施の形態１のメモリ素子の書込み動作を説明する図である。
【図５】上記実施の形態１のメモリ素子のの去動作を説明する図である。
【図６】上記実施の形態１のメモリ素子の消去動作を説明する図である。
【図７】上記実施の形態１のメモリ素子の読出し動作を説明する図である。
【図８】本発明の実施の形態２の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図９】図８の要部の拡大概略断面図である。
【図１０】図８の要部の変形例の拡大概略断面図である。
【図１１】上記実施の形態２のメモリ素子の電気特性を示すグラフである。
【図１２】上記実施の形態２のメモリ素子の変形例の要部の概略断面図である。
【図１３】本発明の実施の形態３の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１４】本発明の実施の形態４の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１５】本発明の実施の形態５の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１６】本発明の実施の形態６の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１７】本発明の実施の形態７の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１８】本発明の実施の形態８の半導体記憶装置のメモリ素子の要部の概略断面図である。
【図１９】本発明の実施の形態９の半導体記憶装置のメモリ素子の電気特性を示すグラフである。
【図２０】本発明の実施の形態１０の半導体記憶装置の概略平面図である。
【図２１】図２０の２１−２１線の概略断面図である。
【図２２】図２０の２２−２２線の概略断面図である。
【図２３】図２０の２３−２３線の概略断面図である。
【図２４】上記実施の形態１０の半導体記憶装置の回路図である。
【図２５】本発明の実施の形態１１の半導体記憶装置の概略平面図である。
【図２６】本発明の実施の形態１２の半導体記憶装置を説明するための図であり、メモリセルアレイを構成する記憶素子と、論理回路部を構成するスイッチング素子の概略の断面図を並べて比較した図である。
【図２７】上記実施の形態１２の半導体記憶装置のブロック図である。
【図２８】本発明の実施の形態１３の携帯電子機器のブロック図である。
【図２９】従来のフラッシュメモリのメモリセルアレイの概略平面図である。
【図３０】図２９の３０−３０線の概略断面図である。
【図３１】上記従来のフラッシュメモリの電気特性を示すグラフである。
【符号の説明】
１ メモリ素子
２ メモリ素子
１３ 記憶素子
１５ 半導体記憶装置
１０１ 半導体基板
１０４ ゲート電極
１０５ａ，１０５ｂ メモリ機能体
１０７ａ，１０７ｂ 拡散領域
１２２ チャネル領域
１３１ａ，１３１ｂ メモリ機能体
２１１ 半導体基板
２１２，２１３ 拡散領域
２１４ ゲート絶縁膜
２１７ ゲート電極
２６１，２６２ メモリ機能体
２６２ａ メモリ機能体
２７２ チャネル領域
１１０１ 半導体基板
１１０３ ゲート絶縁膜
１１０４ ワード線
１１０５ａ，１１０５ｂ メモリ機能体
１１０７ａ，１１０７ｂ 拡散領域
１１０８ 素子分離領域
１１１０ チャネル領域
１１３２ ビット線
１３０１ メモリセルアレイ
Ｍ１１，Ｍ１２，…，Ｍ４１ メモリセル
ｍ１，ｍ２ メモリ機能体
ＷＬ，ＷＬ１，ＷＬ２，…，ＷＬ４ ワード線
ＢＬ１，ＢＬ２，…，ＢＬ６ ビット線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device, an operation method thereof, and a portable electronic device. More specifically, a semiconductor memory device in which a field effect transistor having a memory function body having a function of retaining electric charge or polarization is arranged, an operation method thereof, and a portable electronic device having such a semiconductor memory device Equipment related.
[0002]
[Prior art]
A flash memory, which is one of nonvolatile memories, includes a memory cell array as a semiconductor storage device.
[0003]
Conventionally, as a memory cell array of a flash memory, there is one as shown in FIG. 29 (for example, see Patent Document 1).
[0004]
FIG. 29 is a schematic plan view of the memory cell array. FIG. 30 is a schematic sectional view taken along line 30-30 of FIG. 29 and 30, 901 is a semiconductor substrate, 902 is a channel region, FG is a floating gate, WL is a word line, SL is a source line, BL is a bit line, 908 is an element isolation region, and 931 is an insulating film. ing.
[0005]
The memory cell array includes a plurality of memory cells arranged in a matrix. Each memory cell has a floating gate FG, as shown in FIG. 30, and retains the memory as the amount of charge in the floating gate FG.
[0006]
According to the memory cell array having the above-described configuration, a desired memory cell can be rewritten and read by selecting a specific word line WL and bit line BL and applying a predetermined voltage.
[0007]
FIG. 31 is a diagram schematically showing a characteristic of a drain current (Id) versus a gate voltage (Vg) when the amount of charge in the floating gate FG of the memory cell changes.
[0008]
When the amount of negative charges in the floating gate FG increases, the threshold value increases, and the Id-Vg curve moves substantially parallel to the direction in which Vg increases (the direction of the arrow in the figure).
[0009]
[Patent Document 1]
JP 05-304277 A
[0010]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional memory cell array, the floating gate FG is arranged between the word line WL also serving as a gate electrode and the channel region 902. Then, an insulating film 931 is provided between the floating gate FG and the word line WL and between the floating gate FG and the channel region 902 in order to prevent charge leakage from the floating gate FG.
[0011]
As described above, the floating gate FG and the insulating film 931 exist between the word line WL and the channel region 902, and it is difficult to reduce the thickness of the insulating film 931. As a result, the conventional memory cell array has a problem that the memory cell cannot be miniaturized.
[0012]
Therefore, an object of the present invention is to provide a semiconductor memory device that can be easily miniaturized.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention comprises:
A semiconductor substrate having an element isolation region and an active region on its surface,
A storage element that is a plurality of field-effect transistors formed in the active region and arranged in a matrix,
A word line connected to a gate electrode of the storage element;
A bit line connected to the source / drain diffusion region of the storage element;
Regarding two adjacent bit lines, one bit line is electrically connected to one of the source / drain diffusion regions in the same column, while the other bit line is electrically connected to the source / drain diffusion region in the same column. Electrically connected to the other of
The storage elements adjacent in the same row share one of the source / drain diffusion regions,
The storage elements adjacent in the same column share one of the source / drain diffusion regions,
The storage element is
The gate electrode formed on the semiconductor substrate via a gate insulating film,
A memory function body formed on the side of the gate electrode and having a function of retaining charge or polarization;
A channel region disposed below the gate insulating film;
The source / drain diffusion regions arranged on both sides of the channel region;
Including
The amount of current flowing from one of the source / drain diffusion regions to the other of the source / drain diffusion regions when a voltage is applied to the gate electrode changes depending on the amount of charge or polarization held in the memory function body. It is characterized by.
[0014]
According to the semiconductor memory device having the above configuration, a memory function body having a function of retaining charges or a function of retaining polarization is formed on the side wall of the word line. This memory function body is formed separately from an insulator (gate insulating film) separating the channel region and the word electrode. Accordingly, it is easy to reduce the thickness of the insulator to suppress the short channel effect. Therefore, the memory element can be miniaturized, and the manufacturing cost can be reduced.
[0015]
Further, adjacent storage elements in the same row share one of the source / drain diffusion regions, and adjacent storage elements in the same column share one of the source / drain diffusion regions. That is, one source / drain diffusion region is shared by four field effect transistors. Therefore, the number of the bit lines is reduced, and the number of contact holes for connecting the bit lines and the source / drain diffusion regions is also reduced. Therefore, the margin associated with the bit line and the contact hole is small, so that the semiconductor memory device can be further reduced and the manufacturing cost can be reduced.
[0016]
In one embodiment of the present invention, the word lines extend in a meandering manner, and a distance in a direction parallel to a direction in which the bit lines extend between two adjacent word lines is equal to or less than the distance. The element isolation region is shorter than the active region.
[0017]
According to the semiconductor memory device of the above embodiment, each of the word lines extends in a meandering manner. Between two adjacent word lines in such a plurality of word lines, the distance in the direction parallel to the direction in which the bit lines extend is shorter on the element isolation region than on the active region. Thus, the length of the element isolation region can be reduced while keeping the margin between the word line and the connection between the bit line and the source / drain diffusion region. That is, the surface area of the element isolation region can be reduced while securing the margin of the word line with respect to the connection portion. Therefore, when the storage element is used as a memory cell of a memory cell array, it is possible to further reduce (or increase the density of) the memory cell array and reduce the manufacturing cost.
[0018]
In one embodiment of the present invention, the memory function body is formed on both sides of the word line, and a rewrite operation and a read operation are performed as independent storage units.
[0019]
According to the semiconductor memory device of the above embodiment, the memory rewrite operation and the read operation are independently performed on each of the two memory function bodies formed on the side walls on both sides of the word line. Is easily realized. Therefore, when the storage element is used as a memory cell of a memory cell array, multi-leveling of one memory cell is easily realized. As a result, the capacity of the memory cell array can be further increased, and the manufacturing cost can be reduced.
[0020]
In one embodiment, at least a part of the memory function body overlaps a part of the source / drain diffusion region.
[0021]
According to the semiconductor memory device of the embodiment, at least a part of the memory function body overlaps a part of the source / drain diffusion region, so that the read speed of the storage element can be sufficiently increased.
[0022]
In one embodiment, the memory function body includes a charge holding film having a surface substantially parallel to a surface of the gate insulating film and having a function of holding charges.
[0023]
According to the semiconductor memory device of the above embodiment, the memory function body includes the charge holding film having a surface substantially parallel to the surface of the gate insulating film and having a function of holding charge, so that the memory of the storage element Variations in the effect can be reduced. As a result, variations in the read current of the storage element can be suppressed. Further, the change in characteristics of the storage element during storage can be reduced, so that the storage characteristics of the storage element are improved.
[0024]
In one embodiment, the charge storage film has a surface substantially parallel to a side surface of the gate electrode.
[0025]
According to the semiconductor memory device of the embodiment, the charge retaining film has a surface substantially parallel to the side surface of the gate electrode, so that the rewriting operation of the memory element can be performed at high speed.
[0026]
In one embodiment, the memory function body includes an insulating film formed between the charge holding film and the active region, and the thickness of the insulating film is equal to the thickness of the gate insulating film. It is thinner and 0.8 nm or more.
[0027]
According to the semiconductor memory device of the above embodiment, the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more. And the speed of the write operation and the erase operation can be increased. Further, since the memory effect of the storage element is increased, the read speed of the storage element can be increased.
[0028]
In one embodiment, the memory function body includes an insulating film formed between the charge holding film and the active region, and the thickness of the insulating film is equal to the thickness of the gate insulating film. It is thicker and not more than 20 nm.
[0029]
According to the semiconductor memory device of the above embodiment, since the thickness of the insulating film is larger than the thickness of the gate insulating film and is equal to or less than 20 nm, the holding characteristics can be improved without deteriorating the short channel effect of the memory element. Can be improved. Therefore, even when the storage element is highly integrated, sufficient storage retention performance can be obtained in the storage element.
[0030]
In one embodiment, the memory function body includes a silicon nitride film and a silicon oxide film sandwiching the silicon nitride film.
[0031]
According to the semiconductor memory device of the embodiment, since the memory function body has a structure in which the silicon nitride film is sandwiched between the silicon oxide films, the efficiency of charge injection into the memory function body during a rewrite operation increases, High-speed operation becomes possible.
[0032]
A semiconductor memory device according to one embodiment includes a column decoder, a sense amplifier, and a row decoder, and is formed of one chip.
[0033]
According to the semiconductor memory device of the above embodiment, since the semiconductor memory device includes the column decoder, the sense amplifier, and the row decoder, a specific memory element can be selected to perform the rewrite and read operations.
[0034]
Further, since it is easy to mount the normal transistors constituting the logic circuits and analog circuits such as the column decoder, the sense amplifier and the row decoder, and the semiconductor memory device of the present invention, the manufacturing process is facilitated. Costs can be reduced.
[0035]
The operation method of the semiconductor memory device according to the second invention is the operation method of the semiconductor memory device according to the first invention, wherein the method is connected to the gate electrode of the storage element to which the memory function body to be operated belongs. Before applying a potential for operating the memory function body to the word line, all of the bit lines located on one side of the storage element are precharged to a first potential, and All the bit lines located on the other side of the element are precharged to a second potential.
[0036]
According to the operation method of the semiconductor memory device having the above configuration, all the bit lines located on one side of the storage element to which the memory function body to be operated belongs are precharged to the first potential, and the storage element Are precharged to the second potential. Thereafter, a potential for operating the memory function body is applied to the word line connected to the gate electrode of the storage element. According to such an operation method, reading, writing, and erasing operations by random access with a relatively simple control circuit can be performed, the area occupied by the memory can be further reduced, the operation efficiency can be improved, and high-speed operation can be performed. . For example, when reading information from the storage element, the information in the storage element can be read immediately after a potential for performing a reading operation is applied to a word line connected to a gate electrode of the storage element.
[0037]
Further, all the bit lines located on one side of the storage element are precharged to the first potential, and all the bit lines located on the other side of the storage element are connected to the second potential. Since the precharge is performed to the potential, a noise current in detecting a current flowing through the selected field effect transistor (memory element) can be reduced.
[0038]
According to a third aspect of the invention, a portable electronic device includes the semiconductor memory device according to the first aspect.
[0039]
According to the portable electronic device having the above configuration, since the manufacturing cost of the control circuit is reduced by providing the semiconductor memory device of the first aspect, the cost of the portable electronic device itself can be reduced. Alternatively, the capacity of the nonvolatile memory included in the control circuit can be increased to enhance the functions of the portable electronic device.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor memory device of the present invention will be described in detail with reference to the illustrated embodiments.
[0041]
In the semiconductor memory device (memory cell array) of the present invention, memory elements as storage elements that can store 2-bit information, are easy to miniaturize, and are easy to form are arranged.
[0042]
The memory element as a storage element included in the semiconductor memory device of the present invention mainly includes a first conductivity type region as a source / drain diffusion region, a second conductivity type region, and first and second conductivity type regions. Including a memory functional body disposed over the boundary of the semiconductor device and an electrode provided via an insulating film, or mainly including a gate insulating film, a gate electrode formed on the gate insulating film, and a gate electrode. , A memory function body formed on both sides of the memory function body, a source / drain diffusion region arranged on each side of the memory function body opposite to the gate electrode, and a channel region arranged below the gate electrode.
[0043]
In this specification, the first conductivity type means P-type or N-type. The second conductivity type means N-type when the first conductivity type is P-type and P-type when the first conductivity type is N-type.
[0044]
The memory element functions as a memory element for storing quaternary or more information by storing binary or more information in one charge holding film, and also has a variable resistance effect by a memory function body. , Also functions as a memory cell having both functions of a selection transistor and a memory transistor. However, this memory element does not necessarily need to store and function quaternary information or more, and may function by storing binary information, for example.
[0045]
The semiconductor storage device of the present invention is preferably formed using a semiconductor substrate, preferably a first conductivity type well region formed in the semiconductor substrate.
[0046]
The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. For example, a bulk made of an element semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN is used. A substrate. In addition, as a substrate having a semiconductor layer on its surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer over a glass or plastic substrate may be used. Among them, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.
[0047]
An element isolation region is preferably formed on the semiconductor substrate or the semiconductor layer, and elements such as a transistor, a capacitor, and a resistor, a circuit including the elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multiple element. It may be formed in a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS (local silicon oxide) film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and the semiconductor substrate preferably has at least one well region of a first conductivity type (P-type or N-type). . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, or a body region may be provided below the channel region.
[0048]
The gate insulating film or the insulating film is not particularly limited as long as it is generally used for a semiconductor memory device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film Or a high-dielectric film such as a tantalum oxide film and a hafnium oxide film. Among them, a silicon oxide film is preferable. The thickness of the gate insulating film is, for example, about 1 to 20 nm, preferably about 1 to 6 nm. The gate insulating film may be formed only immediately below the gate electrode, or may be formed larger (wider) than the gate electrode.
[0049]
The gate electrode or the electrode is formed on the gate insulating film in a shape as used for a normal semiconductor memory device or in a shape having a concave portion at a lower end. Further, the gate electrode may be a single gate electrode. Note that a single gate electrode means a gate electrode which is formed as an integral shape without being separated by a single-layer or multilayer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. The gate electrode is not particularly limited as long as it is generally used for a semiconductor memory device. A conductive film, for example, a metal such as polysilicon: copper and aluminum: a high melting point metal such as tungsten, titanium, and tantalum A single-layer film or a laminated film of silicide with a high melting point metal, etc. The gate electrode is preferably formed to have a thickness of, for example, about 50 to 400 nm. Note that a channel region is formed below the gate electrode.
[0050]
The memory function body is configured to include at least a film or a region having a function of retaining charges, having a function of storing and retaining charges, trapping charges, or retaining a charge polarization state. Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectric substances such as hafnium oxide, zirconium oxide, and tantalum oxide; zinc oxide; Body; metal and the like. The memory function body includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer therein; an insulator film including one or more conductors or semiconductor dots; It can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. Above all, the silicon nitride film has a large hysteresis characteristic due to the presence of many levels for trapping electric charges, and has a long charge retention time and does not cause a problem of charge leakage due to generation of a leak path. Is preferable, and is a material used as a standard in the LSI process.
[0051]
By using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability regarding storage and holding can be improved. This is because, since the silicon nitride film is an insulator, even if a charge leaks to a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. Furthermore, when a plurality of memory elements are arranged, even if the distance between the memory elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of a conductor. No lost information is lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the memory element.
[0052]
In order to further increase the reliability of memory retention, the insulating film having a function of retaining charges does not necessarily have to be in the form of a film, and insulators having a function of retaining charges are discretely present in the insulating film. Is preferred. Specifically, it is preferable that the material is dispersed in a dot shape in a material that does not easily retain charge, for example, silicon oxide.
[0053]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0054]
Further, by using an insulator film containing one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0055]
Further, a ferroelectric film such as PZT or PLZT whose polarization direction changes by an electric field may be used as the memory function body. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to the polarization, and are maintained in that state. Therefore, a hysteresis characteristic similar to that of a film that is supplied with electric charge from outside the film having a memory function and traps electric charge can be obtained, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since the hysteresis characteristic can be obtained only by the polarization of the electric charge in the film, there is an effect that writing / erasing can be performed at high speed.
[0056]
That is, it is preferable that the memory function body further include a region that makes it difficult for the charge to escape or a film that has a function of making the charge hard to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0057]
The charge retaining film included in the memory function body is formed directly or on both sides of the gate electrode via an insulating film, and also directly on the semiconductor substrate (well region, body region, or via the gate insulating film or the insulating film). (Source / drain region or diffusion region). The charge retention films on both sides of the gate electrode are preferably formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed so as to completely or partially fill the concave portion directly or via an insulating film.
[0058]
The gate electrode is preferably formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the memory element is facilitated. Further, a memory element having such a simple arrangement is easy to manufacture and can improve the yield.
[0059]
In the case where a conductive film is used as the charge holding film, the charge holding film is provided with an insulating film interposed therebetween so as not to directly contact the semiconductor substrate (the well region, the body region, the source / drain region, or the diffusion region) or the gate electrode. Is preferred. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in an insulating film, a structure in which a part is arranged in a side wall insulating film formed on a side wall of a gate, and the like are given. .
[0060]
The source / drain diffusion regions are arranged on the opposite side of the gate electrode of the charge holding film as diffusion regions of a conductivity type opposite to that of the semiconductor substrate or the well region. The junction between the source / drain diffusion region and the semiconductor substrate or well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain diffusion region is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that when an SOI substrate is used as the semiconductor substrate, the source / drain diffusion region may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have a bonding depth of the order.
[0061]
The source / drain diffusion region may be arranged so as to overlap with the gate electrode end, may be arranged so as to coincide with the gate electrode end, or may be arranged so as to be offset with respect to the gate electrode end. May be. In particular, in the case of offset, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region below the charge retaining film greatly changes depending on the amount of charge accumulated in the memory function body, and the memory effect is reduced. It is preferred because it increases and brings about a reduction in the short channel effect. However, if the offset is too large, the drive current between the source and the drain becomes extremely small. It is preferable that the distance from the source / drain diffusion region to the closer one is shorter. What is particularly important is that at least a part of the charge accumulation region in the memory function body overlaps with a part of the source / drain diffusion region which is a diffusion region. The essence of the memory element constituting the semiconductor memory device of the present invention is that the memory is rewritten by an electric field crossing the memory function body due to a voltage difference between the gate electrode and the source / drain diffusion region existing only on the side wall of the memory function body. Because there is.
[0062]
The source / drain diffusion region may partially extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain diffusion region is laminated on the source / drain diffusion region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high-melting point metals. Among them, polysilicon is preferable. Polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so it is easy to reduce the junction depth of the source / drain diffusion region in the semiconductor substrate, and it is easy to suppress the short channel effect. is there. In this case, it is preferable that a part of the source / drain diffusion region is disposed so as to sandwich at least a part of the memory function body together with the gate electrode.
[0063]
The memory element of the present invention can be formed by a normal semiconductor process, for example, by a method similar to the method of forming a single-layer or stacked-layer sidewall spacer on the side wall of a gate electrode. Specifically, after forming a gate electrode or an electrode, a single layer including a charge holding film such as a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, and an insulating film / charge holding film / insulating film. A method of forming a film or a laminated film, etching back under appropriate conditions to leave these films in the form of sidewall spacers; forming an insulating film or a charge retaining film, and etching back under appropriate conditions to form a sidewall. A method in which a charge retaining film or an insulating film is formed in the form of a spacer, and then etched back in the same manner to leave a sidewall spacer; a semiconductor substrate including a gate electrode formed of an insulating film material in which a particulate charge retaining material is dispersed A method of applying or depositing on the upper surface and etching back under appropriate conditions to leave the insulating film material in a side wall spacer shape; after forming a gate electrode, forming the single-layer film or the laminated film and forming a mask A method in which patterning and the like using. Before forming a gate electrode or an electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, and the like are formed, and a channel region of these films is formed. An opening is formed in a region to be formed, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
[0064]
An example of a method for forming the memory element will be described.
[0065]
First, a gate insulating film and a gate electrode are formed on a semiconductor substrate by a known procedure. Subsequently, a silicon oxide film having a thickness of 0.8 to 20 nm, more preferably 3 to 10 nm is formed on the entire surface of the semiconductor substrate by a thermal oxidation method or deposited by a CVD (Chemical Vapor Deposition) method. . Next, a silicon nitride film having a thickness of 2 to 15 nm, more preferably 3 to 10 nm is deposited on the entire surface of the silicon oxide film by a CVD method. Further, a silicon oxide film of 20 to 70 nm is deposited on the entire surface of the silicon nitride film by a CVD method.
[0066]
Subsequently, the silicon oxide film / silicon nitride film / silicon oxide film is etched back by anisotropic etching to form a memory functional body optimal for storage in the form of a sidewall spacer on the side wall of the gate electrode.
[0067]
Thereafter, diffusion layers (source / drain regions) are formed by ion implantation using the gate electrode and the sidewall spacer-shaped memory function body as a mask. After that, the silicide process and the upper wiring process may be performed by a known procedure.
[0068]
When a memory cell array is configured by arranging the memory elements of the present invention, the memory element is in the best mode when all of the following requirements (1) to (10) are satisfied.
(1) The gate electrodes of a plurality of memory elements have a word line function integrally.
(2) A memory function body is formed on both sides of the word line.
(3) It is an insulator, particularly a silicon nitride film, that holds charges in the memory function body.
(4) The memory function body is composed of an ONO (Oxide Nitride Oxide) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulating film.
(5) The silicon nitride film in the memory function body is separated from the word line and the channel region by the silicon oxide film.
(6) The silicon nitride film and the diffusion layer in the memory function body overlap.
(7) The thickness of the insulating film that separates the silicon nitride film having a surface substantially parallel to the surface of the gate insulating film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film.
(8) Write and erase operations of one memory element are performed by a single word line.
(9) There is no electrode (word line) having the function of assisting the writing and erasing operations on the memory function body.
(10) A region having a high impurity concentration of a conductivity type opposite to the conductivity type of the diffusion region is provided immediately below the memory function body in contact with the diffusion region.
[0069]
Needless to say, the memory element of the present invention does not necessarily need to satisfy all of the above requirements (1) to (10).
[0070]
When a plurality of the above requirements (1) to (10) are satisfied, a particularly preferable combination exists. For example, (3) an insulator, particularly a silicon nitride film, holds electric charges in the memory function body, and (9) an electrode (word line) having a function of assisting a write and erase operation on the memory function body. (6) The case where the insulating film (silicon nitride film) in the memory function body and the diffusion layer overlap. If the insulator holds the electric charge in the memory function body and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film ( It has been found that only when the silicon nitride film) and the diffusion layer overlap, the writing operation is performed favorably. That is, it has been found that, when the requirements (3) and (9) are satisfied, the requirement (6) must be satisfied. On the other hand, when the electric charge is held in the memory function body by the conductor, the writing operation can be performed even when the conductor in the memory function body and the diffusion layer do not overlap (the conductor in the memory function body). Is to assist writing by capacitive coupling with the writing electrode). In addition, when there was an electrode having a function of assisting the writing and erasing operations on the memory function body, the writing operation could be performed even when the insulating film and the diffusion layer in the memory function body did not overlap. .
[0071]
However, in the case where it is an insulator, not a conductor, that retains electric charges in the memory function body, and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, A very large effect can be obtained.
[0072]
First, the bit line contact can be arranged closer to the memory function body on the side wall of the word line, or even if the distance between the memory elements is short, a plurality of memory function bodies do not interfere with each other and can hold the stored information. This facilitates miniaturization of the memory element. When the charge holding region in the memory function body is a conductor, interference occurs between the charge holding regions as the memory elements approach each other due to capacitive coupling, and storage information cannot be held.
[0073]
When the charge holding region in the memory function body is an insulator (for example, a silicon nitride film), it is not necessary to make the memory function body independent for each memory cell. For example, memory function bodies formed on both sides of one word line shared by a plurality of memory cells do not need to be separated for each memory cell, and memory function bodies formed on both sides of one word line. Can be shared by a plurality of memory cells sharing a word line. Therefore, a photo and etching process for separating the memory function body is not required, and the manufacturing process is simplified. Further, a margin for alignment of a photo and a margin for reducing the thickness of an etching film are not required, so that a margin between memory cells can be reduced. Therefore, as compared with the case where the charge holding region in the memory function body is a conductor (for example, a polycrystalline silicon film), even if formed at the same fine processing level, there is an effect that the memory cell occupation area can be reduced (memory If the charge holding region in the functional body is a conductor, a photo and etching step for separating the memory functional body for each memory cell is required, and a photo alignment margin and an etching film reduction margin are required.
[0074]
Furthermore, since there is no electrode having the function of assisting the writing and erasing operations on the memory function body and the element structure is simple, the number of steps is reduced, the yield is improved, and the transistors forming the logic circuit and the analog circuit are formed. Can be easily combined.
[0075]
Further, as a very important design matter, the case where the charge holding region in the memory function body is an insulator and there is no electrode having a function of assisting the writing and erasing operations on the memory function body (the above two conditions) Is very effective in reducing the cell occupation area, improving the yield by simplifying the manufacturing method, and reducing the cost.) We have found that wrapping allows writing and erasing at very low voltages. Specifically, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less. This function has a very large effect on circuit design. That is, since it is not necessary to generate a high voltage in a chip as in a flash memory, it is possible to omit a charge pumping circuit requiring an enormous occupation area or to reduce the scale. In particular, when a small-capacity memory is incorporated in a logic LSI for adjustment, the occupied area of the memory section is dominated by the occupied area of the peripheral circuit that drives the memory cell rather than the memory cell. Eliminating or reducing the scale of the booster circuit is most effective for reducing the chip size.
[0076]
From the above, it is particularly preferable to satisfy the above requirements (3), (9) and (6).
[0077]
The semiconductor memory device of the present invention can be used with a personal computer, a notebook, a laptop, a personal assistant / transmitter, a minicomputer, a workstation, a mainframe, a multiprocessor computer or other Data processing systems such as computer systems of all types; electronic components constituting data processing systems such as CPUs, memories, and data storage devices; communication devices such as telephones, PHSs, modems, and routers; image displays such as display panels and projectors Equipment; office equipment such as printers, scanners, and copiers; imaging equipment such as video cameras and digital cameras; entertainment equipment such as game machines and music players; information equipment such as portable information terminals, clocks, and electronic dictionaries; Car ode E. In-vehicle devices such as e .; AV devices for recording and reproducing information such as moving images, still images, and music; appliances such as washing machines, microwave ovens, refrigerators, rice cookers, dishwashers, vacuum cleaners, air conditioners, etc .; , A wide range of applications to health management devices such as weight scales and blood pressure monitors; and electronic devices such as portable storage devices such as IC cards and memory cards. In particular, application to portable electronic devices such as mobile phones, portable information terminals, IC cards, memory cards, portable computers, portable game machines, digital cameras, portable video players, portable music players, electronic dictionaries, watches and the like is effective. is there. Note that the semiconductor storage device of the present invention may be incorporated as at least a part of a control circuit or a data storage circuit of an electronic device, or may be removably incorporated as needed.
[0078]
In the following embodiments, a case is described in which an N-channel element is used as a memory, but a P-channel element may be used as a memory. In this case, the conductivity types of the impurities may be all reversed.
[0079]
In the following description of the drawings, portions using the same material and substance are denoted by the same reference numerals, and do not necessarily indicate the same shape.
[0080]
Also, it should be noted that the following drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness and size of each layer and each part, and the like are different from actual ones. Therefore, the specific dimensions of the thickness and size should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.
[0081]
(Embodiment 1)
FIG. 1 shows a cross-sectional structure of a memory element as an example of a storage element included in a semiconductor memory device of the present invention.
[0082]
As shown in FIG. 1, the memory element 1 is formed on a P-type well region 102 formed on a surface of a semiconductor substrate 101. A gate electrode 104 is formed on the P-type well region 102 via a gate insulating film 103. On both sides of the gate electrode 104, memory function bodies 105a and 105b are formed. Here, the memory function body refers to a portion of the memory function body or the charge holding film in which charges are actually accumulated by the rewriting operation. In the example shown in FIG. 1, the upper surface and the side surface of the gate electrode 104 are covered with a silicon nitride film 109 having a trap level for retaining charges and serving as a charge retaining film. Both side wall portions of the electrode 104 serve as memory function bodies 105a and 105b, respectively, which actually hold electric charges. The diffusion regions 107a and 107b as an example of the source / drain diffusion regions function as a source region or a drain region, respectively. The diffusion region of the memory element 1 has an offset structure. That is, the diffusion regions 107 a and 107 b do not reach the region 121 below the gate electrode, and the offset region 120 below the charge holding portion forms a part of the channel region 122.
[0083]
FIG. 2 shows another example of a memory element as a storage element included in the semiconductor memory device of the present invention.
[0084]
The memory element 2 of FIG. 2 is different from the memory element 1 of FIG. 1 in that each of the memory function bodies 131a and 131b has a trap level for holding a charge, and a silicon nitride film 113 as an example of a charge holding film. Has a structure sandwiched between a silicon oxide film 111 and a silicon oxide film 112 as an example of an insulating film. By adopting a structure in which the silicon nitride film 113 is sandwiched between the silicon oxide films 111 and 112, the charge injection efficiency at the time of rewriting operation of the memory element is increased, and higher-speed operation can be performed.
[0085]
In FIG. 2, the silicon nitride film 113 may be replaced with a ferroelectric. Further, in FIG. 1, the memory function bodies 105a and 105b may have a structure in which fine particles made of a nanometer-sized conductor or semiconductor are distributed in an insulating film in a scattered manner. At this time, if the particle size is less than 1 nm, the quantum effect is too large, so that it is difficult for charges to tunnel through the dots. If it exceeds 10 nm, a remarkable quantum effect does not appear at room temperature. Therefore, the diameter of the fine particles is preferably in the range of 1 nm to 10 nm. Further, the memory function bodies 131a and 131b do not necessarily have to be in the shape of a sidewall spacer as in the memory element 2 (FIG. 2). For example, in the memory element 1 (FIG. 1), the silicon nitride film 109 having a trap level for retaining charges covers the side surface and the upper surface of the gate electrode 104. These are both side wall portions (105a, 105b) of the gate electrode. That is, it is only necessary that a substance that retains the function of retaining electric charge or the polarization is disposed in these regions.
[0086]
The principle of the write operation of the memory element will be described with reference to FIGS. Here, a case where the memory function bodies 131a and 131b have a function of holding electric charges will be described.
[0087]
Here, writing refers to injecting electrons into the memory function bodies 131a and 131b when the memory elements 1 and 2 are of the N-channel type. Hereinafter, description will be made on the assumption that the memory elements 1 and 2 are of the N-channel type.
[0088]
In order to inject (write) electrons into the second memory function body 131b, as shown in FIG. 3, the first diffusion region 107a (having N-type conductivity) is used as a source electrode and the second diffusion region 107a is used as a second electrode. The diffusion region 107b (having N-type conductivity) is used as a drain electrode. For example, 0V may be applied to the first diffusion region 107a and the P-type well region 102, + 5V may be applied to the second diffusion region 107b, and + 5V may be applied to the gate electrode 104. According to such a voltage condition, the inversion layer 226 extends from the first diffusion region 107a (source electrode) but does not reach the second diffusion region 107b (drain electrode), and a pinch-off point occurs. The electrons are accelerated by a high electric field from the pinch-off point to the second diffusion region 107b (drain electrode), and become so-called hot electrons (high-energy conduction electrons). The writing is performed by injecting the hot electrons into the second memory function body 131b. Note that no writing is performed in the vicinity of the first memory function body 131a because hot electrons do not occur.
[0089]
Thus, writing can be performed by injecting electrons into the second memory function body 131b.
[0090]
On the other hand, in order to inject (write) electrons into the first memory function body 131a, as shown in FIG. 4, the second diffusion region 107b is used as a source electrode, and the first diffusion region 107a is used as a drain electrode. I do. For example, 0V may be applied to the second diffusion region 107b and the P-type well region 102, + 5V may be applied to the first diffusion region 107a, and + 5V may be applied to the gate electrode 104. As described above, when electrons are injected into the second memory function body 131b, writing can be performed by injecting electrons into the first memory function body 131a by exchanging the source / drain regions.
[0091]
Next, the erasing operation principle of the memory element will be described with reference to FIGS.
[0092]
In the first method of erasing information stored in the first memory function body 131a, as shown in FIG. 5, a positive voltage (for example, + 5V) is applied to the first diffusion region 107a, and 0V is applied to the P-type well region 102. , A reverse bias is applied to the PN junction between the first diffusion region 107 a and the P-type well region 102, and a negative voltage (for example, −5 V) is applied to the gate electrode 104. At this time, in the vicinity of the gate electrode 104 of the PN junction, the potential gradient becomes particularly steep due to the influence of the gate electrode to which the negative voltage is applied. Therefore, hot holes (high-energy holes) are generated on the P-type well region 102 side of the PN junction due to the band-to-band tunnel. The hot holes are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a. Thus, the first memory function body 131a is erased. At this time, 0 V may be applied to the second diffusion region 107b.
[0093]
When erasing information stored in the second memory function body 131b, the potentials of the first diffusion region and the second diffusion region may be exchanged in the above.
[0094]
In the second method for erasing information stored in the first memory function body 131a, as shown in FIG. 6, a positive voltage (for example, +4 V) is applied to the first diffusion region 107a and a voltage is applied to the second diffusion region 107b. 0 V, a negative voltage (for example, −4 V) to the gate electrode 104, and a positive voltage (for example, +0.8 V) to the P-type well region 102 may be applied. At this time, a forward voltage is applied between the P-type well region 102 and the second diffusion region 107b, and electrons are injected into the P-type well region 102. The injected electrons diffuse to the PN junction between the P-type well region 102 and the first diffusion region 107a, where they are accelerated by a strong electric field to become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. That is, when a forward voltage is applied between the P-type well region 102 and the second diffusion region 107b, electrons injected into the P-type well region 102 serve as a trigger, and the PN junction located on the opposite side is triggered. Causes hot holes. Hot holes generated at the PN junction are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a.
[0095]
According to the second method, even when only a voltage sufficient to generate a hot hole due to an interband tunnel is applied to the PN junction between the P-type well region and the first diffusion region 107a, the second diffusion is performed. The electrons injected from the region 107b serve as a trigger for generating an electron-hole pair at the PN junction, and can generate a hot hole. Therefore, the voltage at the time of the erase operation can be reduced. In particular, when the offset region 120 (see FIGS. 1 and 2) exists, the effect that the PN junction is sharpened by the gate electrode to which the negative potential is applied is small. Therefore, it is difficult to generate a hot hole due to the band-to-band tunnel. However, the second method can compensate for the disadvantage and realize the erasing operation at a low voltage.
[0096]
When erasing information stored in the first memory function body 131a, in the first erasing method, +5 V had to be applied to the first diffusion region 107a, but in the second erasing method, , + 4V was sufficient. As described above, according to the second method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the memory element due to hot carriers can be suppressed.
[0097]
Regardless of the erasing method, the memory element of the present invention has a feature that over-erasing hardly occurs. Over-erasing is a phenomenon in which the threshold value decreases without saturation as the amount of holes stored in the memory function body increases. An EEPROM (Electrically Erasable Programmable ROM: an electrically erasable read-only memory) represented by a flash memory is a serious problem. In particular, it becomes impossible to select a memory cell when the threshold value becomes negative. Causes fatal malfunction. In the memory element of the present invention, even when a large amount of holes are accumulated in the memory function body, only electrons are induced under the memory function body, and the potential of the channel region under the gate insulating film is hardly affected. Do not give. Since the threshold value at the time of erasing is determined by the potential under the gate insulating film, over-erasing hardly occurs.
[0098]
Next, the principle of the read operation of the memory element will be described with reference to FIG.
[0099]
When reading the information stored in the first memory function body 131a, as shown in FIG. 7, the transistor is operated by using the first diffusion region 107a as a source electrode and the second diffusion region 107b as a drain electrode. For example, 0V may be applied to the first diffusion region 107a and the P-type well region 102, + 2V may be applied to the second diffusion region 107b, and + 2V may be applied to the gate electrode 104. At this time, when electrons are not accumulated in the first memory function body 131a, a drain current easily flows. On the other hand, when electrons are accumulated in the first memory function body 131a, an inversion layer is not easily formed near the first memory function body 131a, so that a drain current does not easily flow. Therefore, by detecting the drain current, information stored in the first memory function body 131a can be read. In particular, when reading is performed by applying a voltage that causes a pinch-off operation, the state of charge accumulation in the first memory function body 131a can be more accurately determined without being affected by the presence or absence of charge accumulation in the second memory function body 131b. Can be determined.
[0100]
When reading information stored in the second memory function body 131b, the transistor is operated in a saturation region using the second diffusion region 107b as a source electrode and the first diffusion region 107a as a drain electrode. For example, 0V may be applied to the second diffusion region 107b and the P-type well region 102, + 2V may be applied to the first diffusion region 107a, and + 2V may be applied to the gate electrode 104. As described above, when the information stored in the first memory function body 131a is read, the information stored in the second memory function body 131b can be read by exchanging the source / drain regions. .
[0101]
Note that in the case where a channel region (offset region 120) not covered by the gate electrode 104 is left, an inversion layer is formed in the channel region not covered by the gate electrode 104 depending on the presence or absence of excess charge of the memory function bodies 131a and 131b. It disappears or forms, resulting in a large hysteresis (change in threshold). However, if the width of the offset region 120 is too large, the drain current is greatly reduced, and the reading speed is significantly reduced. Therefore, it is preferable to determine the width of the offset region 102 so that sufficient hysteresis and reading speed can be obtained.
[0102]
Even when the diffusion regions 107a and 107b reach the end of the gate electrode 104, that is, even when the diffusion regions 107a and 107b and the gate electrode 104 overlap, the threshold value of the transistor hardly changes due to the writing operation. However, the parasitic resistance at the source / drain ends was greatly changed, and the drain current was greatly reduced (by one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the diffusion regions 107a and 107b do not overlap with the gate electrode 104 (the offset region 120 exists).
[0103]
With the above operation method, two bits can be selectively written and erased per transistor. The word line WL is connected to the gate electrode 104 of the memory element, the first bit line BL1 is connected to the first diffusion region 107a, and the second bit line BL2 is connected to the second diffusion region 107b. By arranging, a memory cell array can be formed.
[0104]
Further, in the above operation method, writing and erasing of two bits per transistor are performed by exchanging the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed to operate as a one-bit memory. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be reduced by half.
[0105]
As is clear from the above description, according to the memory element, the memory function body is formed independently of the gate insulating film and formed on both sides of the gate electrode. Therefore, a two-bit operation is possible. Further, since each memory function body is separated by the gate electrode, interference at the time of rewriting is effectively suppressed. Further, since the gate insulating film is separated from the memory function body, the short channel effect can be suppressed by reducing the thickness of the gate insulating film. Therefore, miniaturization of the memory element is facilitated.
[0106]
(Embodiment 2)
The memory element of this embodiment makes it difficult for the memory functional bodies 261 and 262 to escape the charge and the area where the charge is held (the area may store the charge and may be a film having the function of holding the charge). (A film having a function of preventing charge from escaping). For example, as shown in FIG. 8, it has an ONO structure. That is, the silicon nitride film 242 is interposed between the silicon oxide film 241 and the silicon oxide film 243 to form the memory function bodies 261 and 262. Here, the silicon nitride film has a function of retaining electric charges. In addition, the silicon oxide films 241 and 243 play a role of a film having a function of making it difficult for the charges stored in the silicon nitride film to escape.
[0107]
Further, the regions (silicon nitride films 242) of the memory function bodies 261 and 262 which hold the charges overlap with the diffusion regions 212 and 213 as an example of the source / drain diffusion regions. Here, the term “overlap” means that at least a part of the charge holding region (silicon nitride film 242) exists on at least a part of the diffusion regions 212 and 213. 8, reference numeral 211 denotes a semiconductor substrate, 214 denotes a gate insulating film, 217 denotes a gate electrode, and 271 denotes an offset region (between the gate electrode and the diffusion region). In addition, below the gate insulating film 214, the outermost surface portion of the semiconductor substrate 211 is a channel region 272.
[0108]
The effect of overlapping the charge holding region 242 and the diffusion regions 212 and 213 in the memory function bodies 261 and 262 will be described.
[0109]
FIG. 9 is an enlarged view of the periphery of the memory function body 262 on the right side of FIG. In FIG. 9, W1 indicates an offset amount between the gate electrode 217 and the diffusion region 213. Also, W2 indicates the width of the memory function body 262 at the cut surface of the gate electrode in the channel length direction, and the end of the memory function body 262 on the side of the silicon nitride film 242 remote from the gate electrode 217 is the gate electrode. The width of the memory function body 262 is defined as W2 because it coincides with the end of the memory function body 262 on the side away from the memory function body 217. W2-W1 is the amount of overlap between the memory function body 262 and the diffusion region 213. The amount of overlap between the memory function body 262 and the diffusion region 213 is represented by W2-W1. What is particularly important is that the memory function body 262 formed of the silicon nitride film 242 among the memory function bodies 262 overlaps with the diffusion region 213, that is, satisfies the relationship of W2> W1.
[0110]
As shown in FIG. 10, the end of the silicon nitride film 242a of the memory function body 262a on the side remote from the gate electrode 217 does not coincide with the end of the memory function body 262a on the side remote from the gate electrode 217. In this case, W2 may be defined as the distance from the end of the gate electrode to the end of the silicon nitride film 242a on the far side from the gate electrode 217a.
[0111]
FIG. 11 shows the drain current Id when the width W2 of the memory function body 262 is fixed to 100 nm and the offset amount W1 is changed in the structure of FIG. Here, the drain current was obtained by device simulation using the memory function body 262 in an erased state (having holes stored therein) and using the diffusion regions 212 and 213 as a source electrode and a drain electrode, respectively.
[0112]
As is clear from FIG. 11, when W1 is 100 nm or more (that is, the silicon nitride film 242 and the diffusion region 213 do not overlap), the drain current decreases rapidly. Since the drain current value is substantially proportional to the read operation speed, when W1 is 100 nm or more, the performance of the memory rapidly deteriorates. On the other hand, in a range where the silicon nitride film 242 and the diffusion region 213 overlap, the drain current decreases slowly. Therefore, in consideration of variations in mass production, if at least a part of the silicon nitride film 242, which is a film having a function of retaining electric charges, and the source / drain regions do not overlap, a memory function can be obtained effectively. Have difficulty.
[0113]
Based on the results of the device simulation described above, W2 was fixed at 100 nm, and W1 was set at 60 nm and 100 nm as design values, to fabricate a memory cell array. When W1 is 60 nm, the silicon nitride film 142 and the diffusion regions 112 and 113 overlap by 40 nm as a design value, and when W1 is 100 nm, they do not overlap as a design value. As a result of measuring the read time of these memory cell arrays, the read access time was 100 times faster when W1 was set to 60 nm as the design value, compared with the worst case in which the variation was considered. In practice, the read access time is preferably 100 nanoseconds or less per bit, but it has been found that this condition cannot be achieved at all when W1 = W2. In addition, it has been found that W2-W1> 10 nm is more preferable in consideration of manufacturing variations.
[0114]
As in the first embodiment, reading of information stored in the memory function body 261 (region 281) is performed by using the diffusion region 212 as a source electrode and the diffusion region 213 as a drain region on the side closer to the drain region in the channel region. Preferably, a pinch-off point is formed. That is, when reading information stored in one of the two memory function bodies, it is preferable to form a pinch-off point in a region within the channel region and close to the other memory function body. Thereby, regardless of the storage state of the memory function body 262, the storage information of the memory function body 261 can be detected with high sensitivity, which is a major factor that enables the 2-bit operation.
[0115]
On the other hand, when information is stored in only one side of the two memory function bodies or when the two memory function bodies are used in the same storage state, it is not always necessary to form a pinch-off point at the time of reading.
[0116]
Although not shown in FIG. 8, it is preferable to form a well region (a P-type well in the case of an N-channel element) on the surface of the semiconductor substrate 211. By forming the well region, it is easy to control the other electrical characteristics (breakdown voltage, junction capacitance, short channel effect) while optimizing the impurity concentration of the channel region for the memory operation (rewriting operation and reading operation). .
[0117]
It is preferable that the memory function body includes a charge holding film having a function of holding charges and an insulating film from the viewpoint of improving the holding characteristics of the memory. In this embodiment, a silicon nitride film 242 having a level for trapping charges is used as a charge holding film, and silicon oxide films 241 and 243 having a function of preventing dissipation of charges accumulated in the charge holding film are used as insulating films. I have. Since the memory function body includes the charge holding film and the insulating film, the charge can be prevented from dissipating and the holding characteristics can be improved. Furthermore, the volume of the charge holding film can be appropriately reduced as compared with the case where the memory function body is composed of only the charge holding film. By appropriately reducing the volume of the charge holding film, the movement of charges in the charge holding film can be limited, and a change in characteristics due to the charge transfer during storage can be suppressed.
[0118]
Further, it is preferable that the memory function body includes a charge retaining film that is disposed substantially in parallel with the surface of the gate insulating film. In other words, it is preferable that the upper surface of the charge retaining film in the memory function body is disposed at an equal distance from the upper surface of the gate insulating film. Specifically, as shown in FIG. 12, the charge holding film 242a of the memory function body 262 has a surface substantially parallel to the surface of the gate insulating film 214. In other words, it is preferable that the charge holding film 242a be formed at a uniform height from the height corresponding to the surface of the gate insulating film 214. The presence of the charge holding film 242a substantially parallel to the surface of the gate insulating film 214 in the memory function body 262 reduces the possibility of forming an inversion layer in the offset region 271 due to the amount of charge accumulated in the charge holding film 242a. Effective control can be achieved, and the memory effect can be increased. Further, by making the charge holding film 242a substantially parallel to the surface of the gate insulating film 214, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and the variation in the memory effect can be suppressed. can do. In addition, the movement of charges in the upper direction of the charge holding film 242a is suppressed, so that a change in characteristics due to the movement of charges during storage can be suppressed.
[0119]
Further, the memory function body 262 is formed of an insulating film (for example, a portion of the silicon oxide film 244 on the offset region 271) separating the charge holding film 242 a and the channel region (or well region) substantially parallel to the surface of the gate insulating film 214. ) Is preferable. With this insulating film, dissipation of the charge accumulated in the charge holding film is suppressed, and a memory element with better holding characteristics can be obtained.
[0120]
The thickness of the charge holding film 242a is controlled, and the thickness of the insulating film below the charge holding film 242a (the portion of the silicon oxide film 244 on the offset region 271) is controlled to be constant, so that the surface of the semiconductor substrate is controlled. It is possible to keep the distance from to the charge stored in the charge holding film approximately constant. That is, the distance from the surface of the semiconductor substrate to the charge stored in the charge holding film is determined from the minimum film thickness of the insulating film below the charge holding film 242a to the maximum film thickness of the insulating film below the charge holding film 242a. The control can be performed up to the sum of the maximum thickness value of the film 242a. As a result, the density of lines of electric force generated by the electric charges stored in the charge holding film 242a can be substantially controlled, and the variation in the memory effect of the memory element can be greatly reduced.
[0121]
(Embodiment 3)
In this embodiment, as shown in FIG. 13, the charge holding film 242 of the memory function body 262 has a substantially uniform film thickness, a region 281 arranged substantially parallel to the surface of the gate insulating film 214, and It has a region 282 arranged substantially parallel to the side surface of the gate electrode 217. That is, the charge retention film 242 includes a region 281 having a surface substantially parallel to the surface of the gate insulating film 214, and also includes a region 282 having a surface substantially parallel to the side surface of the gate electrode 217.
[0122]
When a positive voltage is applied to the gate electrode 217, lines of electric force in the memory function body 262 pass through the silicon nitride film 242 twice (the region 282 and the region 281) as indicated by an arrow 283. When a negative voltage is applied to the gate electrode 217, the direction of the lines of electric force is on the opposite side. Here, the relative permittivity of the silicon nitride film 242 is about 6, and the relative permittivity of the silicon oxide films 241 and 243 is about 4. Therefore, the effective relative permittivity of the memory function body 262 in the direction of the electric force line in the direction of the arrow 283 becomes larger than in the case of the charge holding film having only the region 281, and the potential difference at both ends of the electric force line becomes smaller. can do. That is, most of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region 271.
[0123]
The charge is injected into the silicon nitride film 242 during the rewrite operation because the generated charge is drawn by the electric field in the offset region 271. Therefore, by including the charge holding film indicated by the arrow 282, the charge injected into the memory function body 262 during the rewriting operation increases, and the rewriting speed increases.
[0124]
If the silicon oxide film 243 is also a silicon nitride film, that is, if the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 214, the charge in the upward direction of the silicon nitride film is Movement becomes conspicuous, and the holding characteristics deteriorate.
[0125]
It is more preferable that the charge retention film is formed of a high dielectric material such as hafnium oxide having a very large relative dielectric constant instead of the silicon nitride film.
[0126]
Further, the memory function body may further include an insulating film (a portion of the silicon oxide film 241 on the offset region 271) separating the charge holding film substantially parallel to the gate insulating film surface and the channel region (or well region). preferable. With this insulating film, dissipation of the charges accumulated in the charge holding film is suppressed, and the holding characteristics can be further improved.
[0127]
In addition, the memory function body may further include an insulating film (a portion of the silicon oxide film 241 that is in contact with the gate electrode 217) separating the gate electrode and the charge holding film extending in a direction substantially parallel to the side surface of the gate electrode. preferable. With this insulating film, it is possible to prevent electric charges from being injected from the gate electrode into the charge holding film and to prevent the electrical characteristics from changing, thereby improving the reliability of the memory element.
[0128]
Further, as in the second embodiment, the thickness of the insulating film (the portion of the silicon oxide film 241 on the offset region 271) under the charge holding film 242 is controlled to be constant, and furthermore, it is disposed on the side surface of the gate electrode. It is preferable that the thickness of the insulating film to be formed (the portion of the silicon oxide film 241 in contact with the gate electrode 217) be controlled to be constant. Thus, the density of lines of electric force generated by the electric charges stored in the electric charge holding film 242 can be substantially controlled, and electric charge leakage can be prevented.
[0129]
(Embodiment 4)
This embodiment relates to optimization of a distance between a gate electrode, a memory function body, and a source / drain region.
[0130]
As shown in FIG. 14, A is the gate electrode length in the cut surface in the channel length direction, B is the distance between the source and drain regions (channel length), and C is the end of one memory function body to the other memory function body. , That is, the charge in the other memory function body from the end of the film having the function of holding the charge in one memory function body (the side away from the gate electrode) in the cut surface in the channel length direction. It shows the distance to the end of the film having the function of performing the function (the side away from the gate electrode).
[0131]
First, it is preferable that B <C. An offset region 271 exists between a portion of the channel region below the gate electrode 217 and the source / drain regions 212 and 213. Due to B <C, the charge accumulated in the memory function bodies 261 and 262 (silicon nitride film 242) effectively changes the ease of inversion in the entire offset region 271. Therefore, the memory effect increases, and particularly, the speed of the read operation is increased.
[0132]
In addition, when the gate electrode 217 is offset from the source / drain regions 212 and 213, that is, when A <B is satisfied, it is difficult to invert the offset region when a voltage is applied to the gate electrode. It changes greatly depending on the amount of electric charge stored in the memory function body, so that the memory effect increases and the short channel effect can be reduced. However, as long as the memory effect appears, it is not always necessary to exist. Even when there is no offset region 271, if the impurity concentration of the source / drain regions 212 and 213 is sufficiently low, a memory effect can be exhibited in the memory function bodies 261 and 262 (silicon nitride film 242).
Therefore, it is most preferable that A <B <C.
[0133]
(Embodiment 5)
As shown in FIG. 15, the memory element of this embodiment has substantially the same configuration except that the semiconductor substrate in the second embodiment is an SOI substrate.
[0134]
In this memory element, a buried oxide film 288 is formed on a semiconductor substrate 286, and an SOI layer is further formed thereon. Diffusion regions 212 and 213 are formed in the SOI layer, and the other regions are body regions 287.
[0135]
With this memory element, the same operation and effect as those of the memory element according to the second embodiment can be obtained. Further, the junction capacitance between the diffusion regions 212 and 213 and the body region 287 can be significantly reduced, so that the speed of the element can be increased and the power consumption can be reduced.
[0136]
(Embodiment 6)
The memory element of this embodiment is different from the second embodiment in that a P-type high concentration region 291 is added adjacent to the channel side of N-type source / drain regions 212 and 213 as shown in FIG. Has a substantially similar configuration.
[0137]
That is, the P-type impurity (for example, boron) concentration in the P-type high concentration region 291 is higher than the P-type impurity concentration in the region 292. The P-type impurity concentration in the P-type high concentration region 291 is, for example, 5 × 10 ¹⁷ ~ 1 × 10 ¹⁹ cm ^-3 The degree is appropriate. The P-type impurity concentration of the region 292 is, for example, 5 × 10 ¹⁶ ~ 1 × 10 ¹⁸ cm ^-3 It can be.
[0138]
As described above, by providing the P-type high-concentration region 291, the junction between the diffusion regions 212 and 213 and the semiconductor substrate 211 becomes steep immediately below the memory function bodies 261 and 262. Therefore, hot carriers are easily generated at the time of writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the speed of the writing and erasing operations can be increased. Further, since the impurity concentration of region 292 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current is large. Therefore, the reading speed is improved. Therefore, a memory element having a low rewrite voltage or a high rewrite speed and a high read speed can be obtained.
[0139]
In FIG. 16, the P-type high-concentration region 291 is provided near the source / drain region and below the memory function body (that is, not immediately below the gate electrode), so that the threshold value of the entire transistor is significantly increased. I do. The degree of this increase is significantly greater than when the P-type high concentration region 291 is immediately below the gate electrode. When the write charge (electrons when the transistor is an N-channel type) is accumulated in the memory function body, the difference is further increased. On the other hand, when sufficient erase charge (holes when the transistor is an N-channel type) is accumulated in the memory function body, the threshold value of the transistor as a whole is determined by the impurity concentration of the channel region (region 292) below the gate electrode. It falls to the determined threshold. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the P-type high concentration region 291, while the threshold value at the time of writing is greatly affected. Therefore, by arranging the P-type high-concentration region 291 below the memory function body and near the source / drain region, only the threshold value at the time of writing greatly varies, and the memory effect (at the time of writing and erasing). Threshold difference) can be significantly increased.
[0140]
(Embodiment 7)
In the memory element of this embodiment, as shown in FIG. 17, the thickness (T1) of the insulating film separating the charge holding film (silicon nitride film 242) and the channel region or the well region in the second embodiment is different from that of the second embodiment. Except that the thickness is smaller than the thickness (T2) of the gate insulating film.
[0141]
The thickness T2 of the gate insulating film 214 has a lower limit due to demand for withstand voltage at the time of a memory rewrite operation. However, the thickness T1 of the insulating film can be made smaller than T2 regardless of the demand for the withstand voltage.
[0142]
In the memory element of the present embodiment, the degree of freedom in designing T1 as described above is high for the following reason. In the memory element of this embodiment, the insulating film that separates the charge retention film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region. Therefore, a high electric field acting between the gate electrode and the channel region or the well region does not directly act on the insulating film separating the charge retention film and the channel region or the well region, and a relatively weak electric field spreading laterally from the gate electrode. Works. Therefore, it is possible to make T1 thinner than T2 regardless of the demand for the withstand voltage for the gate insulating film. On the other hand, for example, in an EEPROM typified by a flash memory, an insulating film separating a floating gate and a channel region or a well region is sandwiched between a gate electrode (control gate) and a channel region or a well region. The high electric field from directly acts. Therefore, in the EEPROM, the thickness of the insulating film separating the floating gate and the channel region or the well region is limited, and the optimization of the function of the memory element is hindered. As is clear from the above, in the memory element of the present embodiment, the fact that the insulating film that separates the charge retention film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region is a factor of T1. This is an essential reason for increasing the degree of freedom.
[0143]
By making T1 thinner, it becomes easier to inject electric charges into the memory function body, it is possible to lower the voltage of the write operation and the erase operation, or to increase the speed of the write operation and the erase operation. Since the amount of charges induced in the channel region or the well region when charges are accumulated in the film 242, the memory effect can be increased.
[0144]
By the way, as shown by an arrow 284 in FIG. 13, there are short lines of electric force in the memory function body that do not pass through the silicon nitride film 242. Since the electric field strength is relatively large on such a short line of electric force, the electric field along the line of electric force plays a large role during the rewriting operation. By reducing the thickness of T1, the silicon nitride film 242 moves to the lower side in the figure, and the lines of electric force indicated by arrows 283 pass through the silicon nitride film. Therefore, the effective line of electric force in the memory function body along the arrow 284 increases, and the potential difference at both ends of the line of electric force can be further reduced. Therefore, much of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region, and the writing operation and the erasing operation are performed at high speed.
[0145]
As is clear from the above, by setting T1 <T2, the voltage of the writing operation and the erasing operation can be reduced or the writing operation and the erasing operation can be speeded up without lowering the withstand voltage performance of the memory, and the memory effect can be further improved. It is possible to increase.
The thickness T1 of the insulating film is preferably at least 0.8 nm, which is a limit at which uniformity and film quality due to the manufacturing process can be maintained at a certain level and holding characteristics are not extremely deteriorated. preferable.
[0146]
Specifically, in the case of a liquid crystal driver LSI which requires a high withstand voltage having a large design rule, a maximum voltage of 15 to 18 V is required to drive the liquid crystal panel TFT. Therefore, the thickness of the gate oxide film cannot be reduced. When the nonvolatile memory of the present invention is mixedly mounted on the liquid crystal driver LSI for image adjustment, in the memory element of the present invention, the charge holding film (silicon nitride film 242) and the channel region or the well region are independent of the gate insulating film thickness. The thickness of the insulating film that separates the above can be optimally designed. For example, for a memory cell having a gate electrode length (word line width) of 250 nm, T1 = 20 nm and T2 = 10 nm can be individually set, thereby realizing a memory cell with high writing efficiency. (The reason that the short channel effect does not occur even if T1 is thicker than a normal logic transistor is because the source / drain regions are offset with respect to the gate electrode).
[0147]
(Embodiment 8)
In the memory element of this embodiment, as shown in FIG. 18, in the second embodiment, the thickness (T1) of the insulating film separating the charge holding film (silicon nitride film 242) from the channel region or the well region is It has substantially the same configuration except that it is thicker than the thickness (T2) of the gate insulating film.
[0148]
The thickness T2 of the gate insulating film 214 has an upper limit due to a demand for preventing a short channel effect of the device. However, the thickness T1 of the insulating film can be made larger than T2 irrespective of the need to prevent the short channel effect. That is, when the miniaturization scaling advances (when the gate insulating film becomes thinner), the insulation separating the charge retaining film (silicon nitride film 242) from the channel region or the well region is independent of the gate insulating film thickness. Since the thickness of the film can be optimally designed, there is an effect that the memory function body does not hinder the scaling.
[0149]
As described above, the reason why the memory element of the present embodiment has a high degree of design freedom for T1 is that the insulating film that separates the charge retention film from the channel region or the well region includes the gate electrode and the channel region. Or, it is not sandwiched between the well region. Therefore, T1 can be made thicker than T2 irrespective of the request for preventing the short channel effect on the gate insulating film.
[0150]
By increasing T1, it is possible to prevent the charge accumulated in the memory function body from dissipating, and to improve the retention characteristics of the memory.
Therefore, by setting T1> T2, it is possible to improve the holding characteristics without deteriorating the short channel effect of the memory.
[0151]
Note that the thickness T1 of the insulating film is preferably 20 nm or less in consideration of a decrease in the rewriting speed.
[0152]
Specifically, in a conventional nonvolatile memory represented by a flash memory, a select gate electrode forms a write / erase gate electrode, and a gate insulating film (including a floating gate) corresponding to the write / erase gate electrode has a charge. The storage film is also used. For this reason, the demand for miniaturization (it is necessary to reduce the film thickness to suppress the short channel effect) and the securing of reliability (the thickness of the insulating film that separates the floating gate from the channel region or the well region in order to suppress the leakage of the retained charge is Since the requirement of being less than about 7 nm cannot be achieved, miniaturization becomes difficult. In fact, according to the ITRS (International Technology Roadmap for Semiconductors), the miniaturization of the physical gate length has not been remarkable for about 0.2 μm or less. In the memory element of the present invention, T1 and T2 can be individually designed as described above, so that miniaturization is possible. For example, in the present invention, for a memory cell having a gate electrode length (word line width) of 45 nm, T2 = 4 nm and T1 = 7 nm are individually set to realize a memory element in which a short channel effect does not occur. The reason that the short channel effect does not occur even when T2 is set to be thicker than a normal logic transistor is because the source / drain region is offset with respect to the gate electrode. Further, in the memory cell of the present invention, since the source / drain regions are offset with respect to the gate electrode, miniaturization is further facilitated as compared with a normal logic transistor.
[0153]
In summary, since there is no electrode for assisting writing and erasing above the memory function body, the electrode and the channel for assisting writing and erasing are formed on the insulating film separating the charge holding film and the channel region or the well region. The high electric field acting between the regions or the well regions does not act directly, only the relatively weak electric field spreading laterally from the gate electrode acts. Therefore, it is possible to realize a memory cell having a gate length that is reduced to be equal to or more than the gate length of the logic transistor for the same processing generation.
[0154]
(Embodiment 9)
This embodiment relates to a change in electrical characteristics when a memory element is rewritten.
[0155]
FIG. 19 shows characteristics (actually measured values) of the drain current (Id) versus the gate voltage (Vg) when the amount of charge in the memory function body of the N-channel type memory element changes. In FIG. 19, the solid line shows the relationship between the drain current Id and the gate voltage Vg in the erased state, and the dotted line shows the relationship between the drain current Id and the gate voltage Vg in the written state.
[0156]
As is clear from FIG. 19, when the writing operation is performed from the erased state (solid line), not only the threshold value simply rises, but also the inclination of the graph is remarkably reduced particularly in the sub-threshold region. Therefore, even in a region where the gate voltage (Vg) is relatively high, the drain current ratio between the erased state and the written state is large. For example, even at Vg = 2.5 V, the current ratio maintains two digits or more. This characteristic is significantly different from the characteristics of the flash memory shown in FIG.
[0157]
The appearance of such characteristics is a peculiar phenomenon that occurs because the gate electrode and the diffusion region are offset and the gate electric field is hard to reach the offset region. When the memory element is in the written state, even if a positive voltage is applied to the gate electrode, it is extremely difficult to form an inversion layer in the offset region below the memory function body. This causes the slope of the Id-Vg curve in the sub-threshold region to decrease in the writing state. On the other hand, when the memory element is in the erased state, high-density electrons are induced in the offset region. When 0 V is applied to the gate electrode (that is, when the gate electrode is off), no electrons are induced in the channel below the gate electrode (therefore, the off-state current is small). This causes a large slope of the Id-Vg curve in the sub-threshold region in the erased state, and a large current increase rate (conductance) even in the region above the threshold.
[0158]
As is clear from the above, the memory element constituting the semiconductor memory element of the present invention can have a particularly large drain current ratio at the time of writing and erasing.
[0159]
(Embodiment 10)
In this embodiment, a memory cell array having the memory elements of Embodiments 1 to 8 as memory cells will be described.
[0160]
20 is a schematic plan view of the memory cell array according to the tenth embodiment. FIG. 21 is a schematic sectional view taken along line 21-21 of FIG. 20, and FIG. 22 is a sectional view taken along line 22-22 of FIG. FIG. 23 is a schematic sectional view taken along line 23-23 of FIG. 20. However, in FIG. 20, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. Although FIGS. 20 to 22 show a memory cell array of 4 rows × 5 columns, the number of rows and the number of columns are arbitrary.
[0161]
As shown in FIGS. 22 and 23, a P-type well region 1102 is formed on a semiconductor substrate 1101. An element isolation region 1108 is formed on the surface of the P-type well region 1102. A region on the surface of the semiconductor substrate where the element isolation region 1108 is not formed is an active region. The word lines WL1, WL2, WL3, WL4 (1104) extend in the horizontal direction of the paper of FIG. 20, and are formed side by side in the vertical direction of the paper of FIG.
[0162]
As shown in FIG. 21, word lines 1104 (WL1, WL2, WL3, WL4) pass through each active region via a gate insulating film 1103. That is, the gate insulating film 1103 is formed between the word line 1104 and each active region. A diffusion region 1107 as an example of a source / drain diffusion region is formed on both sides (regions which are active regions and are not covered by the word lines 1104) of each word line 1104 (WL1, WL2, WL3, WL4). Have been. The region between the diffusion regions 1107 is the channel region 1110 of the memory element.
[0163]
As described above, the word line 1104 (gate electrode) and the diffusion region 1107 (source region or drain region) formed on both sides of the word line 1104 include a memory element which is one field-effect transistor.
[0164]
Here, in FIG. 20, three adjacent word lines 1104 (for example, WL1, WL2, WL3) are selected, and the first word line (WL1), the second word line (WL2), and the third word line Line (WL3). At this time, between the first word line and the second word line, one of the source / drain regions surrounded by the first and second word lines and the element isolation region 1108 (T1) is formed. The first diffusion regions (denoted by D1 in FIG. 20) are arranged in the direction in which the word lines 1 and 2 extend. Similarly, between the second word line (WL2) and the third word line (WL3), a source surrounded by the second and third word lines and the element isolation region 1108 (T2) is provided. The second diffusion regions (denoted by D2 in FIG. 20) which are the other of the drain regions are arranged in the direction in which the second and third word lines extend. The first diffusion region (D1) shares one channel region with each of the two second diffusion regions (D2), and each constitutes one field effect transistor. Similarly, the second diffusion region (D2) shares one channel region with each of the two first diffusion regions (D1), and constitutes one field effect transistor. Therefore, one diffusion region is shared by four field effect transistors.
[0165]
That is, the plurality of memory elements as the memory cells of the memory cell array are arranged in a matrix. In the plurality of memory elements, two memory elements adjacent to each other in the same row supply a diffusion region arranged below a region between gate electrodes of the two memory elements. Further, two memory elements adjacent to each other in the same column also share a diffusion region arranged below a region between the gate electrodes of the two memory elements.
[0166]
The above description regarding the arrangement of the element isolation region 1108 and the diffusion region 1107 can be paraphrased as follows. In FIG. 20, a first element isolation region (T1) disposed over a first word line (WL1) and a second word line (WL2), a second word line (WL2) and a third Second element isolation regions (T2) arranged over the word line (WL3) are alternately arranged in the direction in which the word line extends. A first diffusion region (D1) which is one of a source / drain region and defined by the two first element isolation regions (T1) and the first and second word lines is defined. Similarly, a second diffusion region (D2) which is the other of the source / drain regions and is surrounded by the two second element isolation regions (T2) and the second and third word lines is defined. You. The arrangement of the element isolation region and the diffusion region can be paraphrased as described above.
[0167]
As shown in FIG. 21, a silicon nitride film 1109 is formed on the side walls and the upper surface of the word lines 1104 (WL1, WL2, WL3, WL4). That is, the side and top surfaces of the word line 1104 are covered with the silicon nitride film 1109. In the silicon nitride film 1109, portions existing on both side walls of the word line 1104 are memory function bodies 1105a and 1105b. Note that an interlayer insulating film 1141 is stacked on the silicon nitride film 1109.
[0168]
One of the source / drain regions (D1) is connected to a bit line 1132 (BL2, BL4, BL6) formed of a first-layer metal wiring, and the other (D2) of the source / drain region is connected to the bit line 1132. Is connected to the adjacent bit line 1132 (BL1, BL3, BL5). The bit line extends in a direction perpendicular to the direction in which the word line extends. In this embodiment, the bit line 1132 is connected to the diffusion region 1107 by a contact 1131 (shown by CH in FIG. 20) made of a conductive material.
[0169]
FIG. 24 shows a circuit diagram of the memory cell array. For simplicity, the memory element is represented by a symbol representing a normal field effect transistor. In the memory cell Mij (i = 1, 2, 3, 4, j = 1, 2, 3, 4, 5), the gate electrode is connected to the word line WLi (i = 1, 2, 3, 4) and the diffusion region One is connected to a bit line BLj (j = 1, 2, 3, 4, 5), and the other of the diffusion regions is connected to a bit line BLj + 1 (j = 2, 3, 4, 5). Each of the memory cells Mij includes two memory function bodies m1 and m2 (1105a and 1105b).
[0170]
Next, an operation method of the memory cell array will be described.
[0171]
First, a reading method will be described. Here, it is assumed that the storage information of the memory function body (m1) on the bit line BL3 side of the memory cell M23 is read. First, the bit line BL3 is precharged to a logic level L and the bit line BL4 is precharged to a logic level H. Here, the bit line BL2 adjacent to the left side of the bit line BL3 in the figure (opposite to the bit line 4) is precharged to the logic level L, and the right side of the bit line BL4 in the figure (the opposite side to the bit line 3). ), It is preferable to precharge the adjacent bit line BL5 to the logic level H. After the precharge is completed, the word line WL2 is set to the logic level H. At the moment when the word line WL2 goes to the logic level H, the memory cells M22 and M23 are turned on. At this time, a high voltage (logic level H-logic level L) is applied between the source and the drain of the memory cell M23 and a current flows, but the current amount changes depending on the state of the memory function body m1. Therefore, the state of the memory function body m1 can be known by detecting the amount of current flowing through the bit line BL3 or BL4 or monitoring the potential change of the bit line BL3 or BL4.
[0172]
In the above operation, if the bit line BL2 has not been precharged to the logic level L, the memory cell M22 is turned on at the moment when the word line WL2 goes to the logic level H, and the bit line BL2 is switched to the bit line BL3. Electric current flows. Such a current hinders detection of a current flowing through the selected memory cell M23. Therefore, it is preferable that the bit line BL2 be precharged to the same logic level L as the bit line BL3. Similarly, it is preferable that the bit line BL5 be precharged to the same logic level H as the bit line BL4.
[0173]
When the storage information of the memory function unit (m2) on the bit line BL4 side of the memory cell M23 is called, the bit lines BL2 and BL3 are precharged to the logic level H, and the bit lines BL4 and BL5 are precharged to the logic level L. . After the precharge is completed, the word line WL2 may be set to the logic level H.
[0174]
Table 1 shows an example of specific voltages in each operation of writing, reading, and erasing in the memory cell array of the present embodiment. Lbw, Hbw, Lww, and Hww are the low-level potential of the bit line, the high-level potential of the bit line, the low-level potential of the word line, and the high-level potential of the word line during writing, respectively. Lbr, Hbr, Lwr, and Hwr are the low level potential of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level potential of the word line at the time of reading, respectively. Lbe1, Lbe2, Hbe, Lwe, and Hwe are the low level potential 1 of the bit line, the low level potential 2 of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level of the word line at the time of erasing, respectively. Potential. In each case, an example of a specific voltage is shown in parentheses.
[0175]
The erasing method described in Table 1 below uses the second erasing method described above. Therefore, at the time of erasing, Lbe2 (+0.8 V in Table 1) is applied to the P-type well region. When erasing the memory function body m1 of the memory cell M23, electrons injected by a forward voltage applied to the P-type well region and the bit line BL4 serve as a trigger to perform erasing. Lbe2 is applied to the bit line BL2 to prevent erroneous erasure of the memory cell M21.
[0176]
[Table 1]

[0177]
As is clear from Table 1, the memory cell array according to the present embodiment is capable of random access (read and rewrite operation for each bit). For this reason, the access efficiency can be improved as compared with a device that needs to be erased all at once. In addition, there is no need to perform a sequence such as temporary storage of the memory state, batch erasing, and writing, so that the control circuit is simplified. When the first erasing method described above is used, Lbe2 in Table 1 may be set to the same value (0 V) as Lbe1, and Hbe may be set to an appropriate voltage value (for example, +6 V). In this case, at least two bits are collectively performed in the erasing operation.
[0178]
According to the above-described read operation, when two-bit storage of a certain memory cell is to be continuously read (for example, the memory function bodies m1 and m2 of the memory cell M23 are continuously read), a nearby bit line is read. Must be inverted (in the above example, the potentials of the bit lines BL2 to BL5 are all inverted), which is inefficient. Therefore, it is preferable to devise an address decoder circuit and the like, and to take measures such as separating the addresses of the left and right memory functional units from each other, thereby avoiding a state in which the addresses are continuously and alternately read.
[0179]
As is clear from the above description, the memory cell array according to the present embodiment is configured by arranging the above memory elements. As described above, the memory element can store two bits with one element and can reduce the thickness of the gate insulating film, so that miniaturization is easy. Therefore, in the memory cell array according to the present embodiment in which the memory elements are arranged, the area can be easily reduced (or the density can be increased), and the manufacturing cost can be reduced.
[0180]
Further, in the memory cell array of the present embodiment, since one diffusion region is shared by four memory elements (field effect transistors), the number of bit lines and contact holes for connecting the bit lines and the diffusion region are set. Fewer numbers. Therefore, the margin for the bit line and the contact hole is small, so that the memory cell array can be further reduced (or increased in density) and the manufacturing cost can be reduced.
[0181]
Further, as described above, the process of forming the memory element is very similar to a normal CMOS (complementary metal oxide semiconductor) process, and is much simpler than a conventional nonvolatile memory having a floating gate such as an EEPROM. It is possible to manufacture. Therefore, the memory cell array of the present invention can be easily manufactured, and can be easily mounted together with a logic circuit.
[0182]
In the memory element used in this embodiment, as described in Embodiment Mode 2, the regions (silicon nitride films 242) of the memory function bodies 261 and 262 which retain electric charges overlap with the diffusion regions 212 and 213, respectively. Is preferred. When such a memory element is used in the semiconductor memory device of this embodiment, the reading speed of the semiconductor memory device can be sufficiently increased.
[0183]
Further, in the memory element used in this embodiment, as described in Embodiment 2, the memory function body preferably includes a charge retention film that is arranged substantially in parallel with the surface of the gate insulating film. When such a memory element is used in the semiconductor memory device of this embodiment, variation in the memory effect of the memory element can be reduced, so that variation in the read current of the semiconductor memory device can be suppressed. Furthermore, since the change in the characteristics of the memory element during storage can be reduced, the storage characteristics of the semiconductor memory device are improved.
[0184]
Further, in the memory element used in this embodiment, as described in Embodiment Mode 3, the memory function body includes a charge holding film which is arranged substantially in parallel with the surface of the gate insulating film, and further includes a gate electrode. It is preferable to include a portion extending substantially parallel to the side surface. When such a memory element is used in the semiconductor memory device of this embodiment, the rewriting speed of the memory element increases, so that the rewriting operation of the semiconductor memory device can be performed at high speed.
[0185]
Further, as the memory element used in this embodiment, the memory element in Embodiment 7 is preferably used. That is, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 242) from the channel region or the well region is smaller than the thickness (T2) of the gate insulating film and is 0.8 nm or more. Is preferred. When such a memory element is used in the semiconductor memory device of this embodiment, it is possible to lower the voltage of the write operation and the erase operation or to increase the speed of the write operation and the erase operation. Further, since the memory effect of the memory element increases, the reading speed of the semiconductor memory device can be increased.
[0186]
In addition, as the memory element used in this embodiment, the memory element in Embodiment 8 is preferably used. That is, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 242) from the channel region or the well region is preferably larger than the thickness (T2) of the gate insulating film and equal to or less than 20 nm. . When such a memory element is used in the semiconductor memory device of this embodiment, the holding characteristics can be improved without deteriorating the short channel effect of the memory element. Memory retention performance can be obtained.
[0187]
Further, the memory element used in this embodiment preferably includes a memory function body having a structure in which a silicon nitride film is sandwiched between silicon oxide films as in Embodiment 2 (FIG. 7), for example. . When such a memory element is used in the semiconductor memory device of this embodiment, the operation speed of the semiconductor memory device can be improved, and the reliability can be improved.
[0188]
Further, as the memory element used in this embodiment, it is most preferable to use the memory element of the best mode described above. Thereby, the performance of the semiconductor memory device can be optimized.
[0189]
(Embodiment 11)
Embodiment 11 of the present invention will be described with reference to FIG. The semiconductor memory device of the present embodiment is obtained by reducing the memory cell area by meandering the word lines 1104 (WL1, WL2, WL3, WL4) in the semiconductor memory device of the tenth embodiment. In FIG. 25, the same components as those shown in FIG. 20 are denoted by the same reference numerals as the components in FIG. 20, and description thereof is omitted.
[0190]
The word lines 1104 (WL1, WL2, WL3, WL4) meander in synchronization with the cycle in which the element isolation regions 1108 are arranged. The meandering of the word lines 1104 adjacent to each other are in opposite phases (shifted by 180 degrees). Therefore, in two adjacent word lines 1104, the distance in the direction perpendicular to the direction in which the word lines 1104 extend (the vertical direction in FIG. 25) changes in synchronization with the cycle in which the element isolation regions 108 are arranged. . Specifically, the distance in the direction parallel to the direction in which the bit line 1132 extends between the two adjacent word lines 1104 is shorter on the element isolation region 1108 than on the active region. . Specifically, in a portion where the first or second diffusion region D1 or D2 is sandwiched between the adjacent word lines 1104, the distance is long, and the adjacent word lines extend over one element isolation region 1108. The distance is short in the passing portion.
[0191]
By meandering the word lines 1104 (WL1, WL2, WL3, WL4) as described above, the length of the element isolation region 1108 can be shortened while keeping the margin between the word lines 1104 and the contacts CH. As is apparent from a comparison between FIG. 20 and FIG. 25, the size of the memory cell of the semiconductor memory device of the present embodiment is reduced in the vertical direction in FIG. Therefore, it is possible to further reduce the memory cell array (or increase the density) and reduce the manufacturing cost.
[0192]
(Embodiment 12)
Embodiment 12 of the invention will be described with reference to FIGS. 26 and 27. The semiconductor memory device according to the present embodiment includes the memory cell array and the logic circuit unit according to the first or second embodiment, and is formed of one chip.
[0193]
FIG. 26 is a side-by-side comparison of schematic cross-sectional views of the storage element 13 forming the memory cell array and the switching element 14 forming the logic circuit portion. Here, the description of the already described reference numerals is omitted. The only structural difference between the storage element 13 and the switching element 14 is that in the switching element 14, the diffusion regions 1207a and 1207b reach the gate ends. That is, the switching element 14 does not have the offset region 1120. The diffusion regions 1207a and 1207b have, for example, an LDD (Lightly Doped Drain) structure. Note that the side wall spacer 1205 of the switching element 14 has exactly the same structure as the memory function bodies 1105a and 1105b of the storage element 13.
[0194]
The procedure for forming the storage element 13 is very compatible with a normal standard logic (logic) transistor formation process. As described above, the switching element 14 configuring the logic circuit unit has a configuration close to the configuration of the storage element 13. The switching element 14 differs from the storage element 13 in that the switching element 14 does not use the sidewall spacer 1205 as a memory function body and that the switching element 4 has an LDD region. The thickness composition ratio of the silicon oxide films 1111 and 1112 and the silicon nitride film 1113 may be selected so that the storage element 13 operates properly. Even if the film configuration of the sidewall spacer of the switching element 14 is the same as that of the storage element 13, the width of the sidewall spacer (that is, the total thickness of the silicon oxide films 1111 and 1112 and the silicon nitride film 1113) is appropriate. Therefore, as long as the transistor is operated in a voltage range in which the rewriting operation does not occur, the transistor performance is not impaired.
[0195]
26, reference numerals 1107a and 1107b denote diffusion regions as examples of source / drain diffusion regions, and 1121 denotes a region under the gate electrode.
[0196]
As is apparent from the above description, it is necessary to form the LDD structure only on the switching element 14 in order to mount the switching element 14 constituting the logic circuit section and the storage element 13 constituting the memory cell array together. is there. In order to form an LDD structure, impurities may be implanted for forming an LDD after forming the gate electrode and before forming the memory function body (sidewall spacer). Therefore, when the impurities are implanted for forming the LDD, only the storage element 13 is masked with a photoresist, so that the storage element 13 and the switching element 14 constituting the logic circuit section can be easily mounted together. It becomes possible. Furthermore, if an SRAM (Static Random Access Memory) is configured by the switching element 14, the nonvolatile memory, the logic circuit, and the SRAM can be easily mounted.
[0197]
Note that the switching element 14 does not necessarily have to have the LDD structure, and the storage element 3 does not necessarily have to have the LDD structure. However, it is preferable that the switching element 14 has the LDD structure and the storage element 13 does not necessarily have the LDD structure. This makes it possible to increase the memory effect of the storage element 3 while increasing the drive current of the switching element 14. Therefore, the logic circuit section including the switching elements 14 operates at high speed, and good memory characteristics can be obtained from the memory cell array including the storage elements 13.
[0198]
FIG. 27 is a configuration diagram of the semiconductor memory device according to the present embodiment. The semiconductor storage device 15 includes a memory cell array 1301 including the storage elements 13. The semiconductor storage device 15 further includes a column address buffer 1302, a row address buffer 1303, a column address decoder 1304, a row address decoder 1305, a sense amplifier 1306, and A control circuit 1307 for controlling these units and an MPU (microprocessor unit) 1308 are included.
[0199]
By embedding the memory cell array of Embodiment 10 or Embodiment 11 and the logic circuit unit on one chip, a large-capacity nonvolatile memory is mounted, and an LSI chip that is easy to manufacture and low in cost is realized. Provided.
[0200]
By the way, when designing the semiconductor memory device as described above, considering the efficiency of the read operation, as described above, it is inefficient to try to read the 2-bit storage of a certain memory cell continuously. . This is because, as described above, in order to continuously read 2-bit information of a memory cell, it is necessary to reverse the direction of the read current (replace the source and drain), and change the potential of the nearby bit line. All must be inverted. Therefore, it is preferable that 2-bit addresses stored in a certain memory cell be separated from each other. For example, one of the storage bits of memory cells belonging to the same word line and adjacent to each other may be set to a continuous address, and one of the storage bits in the same memory cell may be separated from the other address.
[0201]
(Embodiment 13)
The semiconductor storage devices of Embodiments 10 to 12 can be used for a battery-driven portable electronic device, particularly, a portable information terminal. Examples of the portable electronic device include a portable information terminal, a mobile phone, and a game device.
[0202]
FIG. 28 illustrates an example of a mobile phone. The semiconductor memory device or the semiconductor device of the present invention is incorporated in the control circuit 1411 of the mobile phone. 28, reference numeral 1412 denotes a battery, 1413 denotes an RF (radio frequency) circuit portion, 1414 denotes a display portion, 1415 denotes an antenna portion, 1416 denotes a signal line, and 1417 denotes a power line.
[0203]
By using the semiconductor memory device or the semiconductor device of the present invention for a portable electronic device, the manufacturing cost of the control circuit can be reduced, so that the cost of the portable electronic device itself can be reduced. Alternatively, the capacity of the nonvolatile memory included in the control circuit can be increased to enhance the functions of the portable electronic device.
[0204]
【The invention's effect】
As is clear from the above, according to the semiconductor memory device of the first invention, the memory function body having the function of retaining electric charge or the function of retaining polarization is formed on the side wall of the word line, and the channel region is formed. The insulator separating the word electrode and the word electrode is formed separately. As a result, it is easy to suppress the short channel effect by reducing the thickness of the insulator, so that the memory element can be miniaturized and the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view of a main part of another memory element of the semiconductor memory device according to the first embodiment of the present invention;
FIG. 3 is a diagram illustrating a write operation of the memory element according to the first embodiment.
FIG. 4 is a diagram illustrating a write operation of the memory element according to the first embodiment.
FIG. 5 is a diagram illustrating an operation of removing the memory element according to the first embodiment.
FIG. 6 is a diagram illustrating an erase operation of the memory element according to the first embodiment.
FIG. 7 is a diagram illustrating a read operation of the memory element according to the first embodiment.
FIG. 8 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 9 is an enlarged schematic sectional view of a main part of FIG.
FIG. 10 is an enlarged schematic cross-sectional view of a modification of the main part of FIG.
FIG. 11 is a graph showing electric characteristics of the memory element according to the second embodiment.
FIG. 12 is a schematic sectional view of a main part of a modified example of the memory element of the second embodiment.
FIG. 13 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 14 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 15 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a fifth embodiment of the present invention.
FIG. 16 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a sixth embodiment of the present invention.
FIG. 17 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to a seventh embodiment of the present invention.
FIG. 18 is a schematic sectional view of a main part of a memory element of a semiconductor memory device according to an eighth embodiment of the present invention.
FIG. 19 is a graph showing electrical characteristics of a memory element of a semiconductor memory device according to a ninth embodiment of the present invention.
FIG. 20 is a schematic plan view of a semiconductor memory device according to a tenth embodiment of the present invention.
FIG. 21 is a schematic sectional view taken along line 21-21 of FIG. 20;
FIG. 22 is a schematic sectional view taken along line 22-22 of FIG. 20;
FIG. 23 is a schematic sectional view taken along line 23-23 of FIG. 20;
FIG. 24 is a circuit diagram of the semiconductor memory device according to the tenth embodiment.
FIG. 25 is a schematic plan view of a semiconductor memory device according to an eleventh embodiment of the present invention.
FIG. 26 is a diagram illustrating a semiconductor memory device according to a twelfth embodiment of the present invention, in which side sectional schematic views of a memory element forming a memory cell array and a switching element forming a logic circuit portion are compared. FIG.
FIG. 27 is a block diagram of a semiconductor memory device according to the twelfth embodiment.
FIG. 28 is a block diagram of a portable electronic device according to Embodiment 13 of the present invention.
FIG. 29 is a schematic plan view of a memory cell array of a conventional flash memory.
FIG. 30 is a schematic sectional view taken along line 30-30 in FIG. 29;
FIG. 31 is a graph showing electric characteristics of the conventional flash memory.
[Explanation of symbols]
1 Memory element
2 Memory element
13 Memory element
15 Semiconductor storage device
101 semiconductor substrate
104 Gate electrode
105a, 105b Memory function body
107a, 107b diffusion region
122 channel area
131a, 131b Memory function body
211 Semiconductor substrate
212,213 Diffusion area
214 Gate insulating film
217 Gate electrode
261,262 Memory Function
262a Memory function body
272 channel area
1101 Semiconductor substrate
1103 Gate insulating film
1104 word line
1105a, 1105b Memory function body
1107a, 1107b Diffusion area
1108 Element isolation region
1110 channel region
1132 bit line
1301 Memory cell array
M11, M12, ..., M41 memory cells
m1, m2 memory function body
WL, WL1, WL2,..., WL4 Word line
BL1, BL2, ..., BL6 bit lines

Claims (12)

A semiconductor substrate having an element isolation region and an active region on its surface,
A storage element that is a plurality of field-effect transistors formed in the active region and arranged in a matrix,
A word line connected to a gate electrode of the storage element;
A bit line connected to the source / drain diffusion region of the storage element;
Regarding two adjacent bit lines, one bit line is electrically connected to one of the source / drain diffusion regions in the same column, while the other bit line is electrically connected to the source / drain diffusion region in the same column. Electrically connected to the other of
The storage elements adjacent in the same row share one of the source / drain diffusion regions,
The storage elements adjacent in the same column share one of the source / drain diffusion regions,
The storage element is
The gate electrode formed on the semiconductor substrate via a gate insulating film,
A memory function body formed on the side of the gate electrode and having a function of retaining charge or polarization;
A channel region disposed below the gate insulating film;
Including the source / drain diffusion regions arranged on both sides of the channel region,
The amount of current flowing from one of the source / drain diffusion regions to the other of the source / drain diffusion regions when a voltage is applied to the gate electrode changes depending on the amount of charge or polarization held in the memory function body. A semiconductor memory device characterized by the above-mentioned. The semiconductor memory device according to claim 1,
Each of the word lines extends in a meandering manner,
A semiconductor memory device wherein a distance in a direction parallel to a direction in which the bit line extends between two adjacent word lines is shorter on the element isolation region than on the active region. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the memory functional unit is formed on both sides of the word line, and performs a rewrite operation and a read operation as independent storage units. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein at least a part of the memory function body overlaps a part of the source / drain diffusion region. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the memory functional unit includes a charge holding film having a surface substantially parallel to a surface of the gate insulating film and having a function of holding charges. 6. The semiconductor memory device according to claim 5,
The semiconductor memory device, wherein the charge holding film has a surface substantially parallel to a side surface of the gate electrode. 6. The semiconductor memory device according to claim 5,
The memory functional unit includes an insulating film formed between the charge holding film and the active region,
A semiconductor memory device wherein the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more. 6. The semiconductor memory device according to claim 5,
The memory functional unit includes an insulating film formed between the charge holding film and the active region,
A semiconductor memory device, wherein the thickness of the insulating film is larger than the thickness of the gate insulating film and is equal to or less than 20 nm. The semiconductor memory device according to claim 1,
The semiconductor memory device according to claim 1, wherein the memory function body includes a silicon nitride film and a silicon oxide film sandwiching the silicon nitride film. The semiconductor memory device according to claim 1,
A semiconductor memory device including a column decoder, a sense amplifier, and a row decoder, and comprising one chip. 2. The operation method of the semiconductor memory device according to claim 1, wherein:
Before applying a potential for operating the memory function body to the word line connected to the gate electrode of the storage element to which the memory function body to be operated belongs,
All the bit lines located on one side of the storage element are precharged to a first potential, and all the bit lines located on the other side of the storage element are precharged to a second potential. A method for operating a semiconductor memory device, comprising charging. A portable electronic device comprising the semiconductor storage device according to claim 1.

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