JP2007109954A - Semiconductor storage device, manufacturing method thereof and operating method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of executing storage of a plurality of bits in one cell with more reliability than a conventional device. <P>SOLUTION: The device is provided with a charge holding film formed on a semiconductor layer and having a function of locally accumulating electric charges; a gate electrode formed on one part of the charge holding film; and a diffusion region formed on the semiconductor layers of both sides of the gate electrode. In the semiconductor device, the end of the gate electrode side of the diffusion region is positioned on the outside rather than an immediately below the gate electrode, and the charge holding film extends to at least a portion on an end of the gate electrode side of the diffusion region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, a manufacturing method thereof, and an operation method thereof. More specifically, the present invention relates to a semiconductor memory device having an insulating film having a function of accumulating charges under a gate electrode and capable of storing a plurality of bits in one cell with higher reliability than before, a manufacturing method thereof, and It relates to the operation method.

  Various devices have been reported as semiconductor memory devices. Among them, NROM (Nitride-containing programmable read-only memory) is reported in Japanese Patent Laid-Open No. 2001-156189 (Patent Document 1). The NROM described in this publication will be described below with reference to FIGS.

  FIG. 16 is a schematic sectional view of a conventional NROM. This NROM is formed according to the formation of the NMOSFET. This NROM has a first insulating film 202, a charge storage insulating film 203, a second insulating film 204, and a gate electrode 205 on a p-type semiconductor substrate 201. In general, the semiconductor substrate 201 is a silicon substrate, the first insulating film 202 and the second insulating film 204 are silicon oxide films, the charge storage insulating film 203 is a silicon nitride film, and the gate electrode 205 is a polysilicon film. Is used.

  These can be formed by a known method. That is, the first insulating film 202 is formed by thermal oxidation of the surface of the semiconductor substrate 201, and the charge storage insulating film 203, the second insulating film 204, and the gate electrode 205 are formed by chemical vapor deposition (CVD). The film can be formed by processing by lithography and dry etching.

  On both sides of the gate electrode 205, there are n-type diffusion regions 206 and 207 formed by ion implantation and activation annealing so as to partially overlap the gate electrode 205.

  By applying a positive voltage to the gate electrode 205 in a state where a potential difference is provided between the diffusion regions 206 and 207, a current flows between the diffusion regions 206 and 207 through the channel region 208 under the gate electrode 205.

  Often, halo regions (pocket implantation regions) 209 and 210 having a p-type impurity concentration higher than that of the well are provided at the boundary between the diffusion regions 206 and 207 and the channel region 208. The halo regions 209 and 210 generally function to suppress a short channel effect and suppress off-leakage in a fine MOSFET. In addition, as described later, particularly in the NROM, it is described in the above-mentioned publication that there is an effect of preventing the deterioration of the device characteristics even when writing and erasing many times.

NROM writing and reading operations will be described with reference to FIGS.
FIG. 17 is a schematic explanatory diagram of the writing mechanism. At the time of writing, a positive high programming voltage is applied to the diffusion region 207 and the gate electrode 205. At this time, similarly to the normal MOSFET operation, the inversion layer 211 is formed in the channel region 208, and electrons flow from the source to the drain using the diffusion region 206 as the source and the diffusion region 207 as the drain. In this case, since the inversion layer 211 is pinched off in the vicinity of the diffusion region 207, electrons are accelerated in the vicinity of the diffusion region 207 by a high electric field, and hot electrons are generated. A part of the hot electrons are pulled by the gate electrode 205 to which a high positive voltage is applied, run upward in the drawing, and trapped in the charge storage insulating film 203. Since this film is an insulating film, the trapped electrons (charges) 212 hardly move in the film and are localized near the end of the diffusion region 207.

  FIG. 18 is a schematic explanatory diagram of the read mechanism. When writing, a positive voltage is applied to the diffusion region 207 as described above. However, when reading, a positive read voltage is applied to the diffusion region 206, and the potentials of the diffusion region 207 and the semiconductor substrate 201 are Ground. Here, when a positive voltage is applied to the gate electrode 205, electrons flow from the source to the drain, using the diffusion region 206 as the drain and the diffusion region 207 as the source. In this case, as shown in FIG. 18, when the electrons 212 trapped in the charge storage insulating film 203 near the end of the diffusion region 207 (source) exist, the current is smaller than the case where the electrons 212 do not exist due to the influence of the potential. 213 becomes small. In other words, the presence or absence of electrons 212 or the number of electrons 212 can be detected by the magnitude of the drain current of the MOSFET. Here, 213 means a read current.

  On the other hand, FIG. 19 shows a case where the same charge accumulation state is read using the diffusion region 206 as a source and the diffusion region 207 as a drain. In a state where the inversion layer is pinched off, that is, in a so-called saturation region, the inversion layer is not formed immediately below the electrons 212, so that the read current 214 is not easily affected by the potential of the electrons 212. That is, information by the writing method (FIG. 17) that generates electrons 212 near the end of the diffusion region 207 is detected by the method of FIG. 18 using the diffusion region 207 as a source. However, it is hardly detected by the method of FIG. 19 using the diffusion region 206 as a source.

Further, in accordance with the writing method of FIG. 17, if a programming voltage is applied to the diffusion region 206 instead of the diffusion region 207, electrons can be stored in the charge storage insulating film 203 near the end of the diffusion region 206. In this case, detection is possible when the diffusion region 206 is used as a source.
By such a method, the NROM can store 2-bit information with one transistor.

20 and 21 show an outline of the erasing mechanism. 20 is a schematic sectional view of the NROM, and FIG. 21 is a schematic band diagram of FIG.
At the time of erasing on the end portion of the diffusion region 207, a negative high erasing voltage is applied to the gate electrode 205 and a positive high erasing voltage is applied to the diffusion region 207, and the semiconductor substrate 201 is set to a ground potential, for example. In particular, when the p-type halo region 210 exists at the junction between the diffusion region 207 and the semiconductor substrate 201, the PN junction between the diffusion region 207 and the halo region 210 has a steep profile, and a higher reverse bias is applied. Applied. Therefore, as shown in the band diagram of FIG. 21, some electrons flow from the valence band of the halo region 210 to the conduction band of the diffusion region 207 by the interband tunnel. The tunnel electrons 215 are accelerated by the electric field, collide with silicon atoms on the substrate, and generate hot hole 216 and hot electron 217 pairs. Among these, a part of the hot hole 216 is pulled to the gate electrode 205 to which a negative bias is applied and enters the charge storage insulating film 203, so that it recombines with the already stored electrons and the stored electrons disappear. Let As a result, only the electrons on the right side of the paper near the end of the diffusion region 207 can be erased. In the same way, it is possible to erase only the electrons on the left side of the paper near the end of the diffusion region 206.

By providing the above-described halo regions 209 and 210, a high-level electric field at the time of writing / erasing can be generated only in the vicinity of the diffusion region. At this time, in the charge storage insulating film 203, a region where electrons are injected at the time of writing and a region where holes are injected at the time of erasing can be matched, and electrons that cannot be erased by the erasing operation are charged on the channel region. It does not remain in the storage insulating film 203. Therefore, it is described in the above-mentioned publication that there is an effect that it is possible to prevent deterioration of device characteristics due to accumulation of unerased electrons when repeated writing and erasing is performed.
JP 2001-156189 A

The conventional NROM has a problem that miniaturization is difficult.
That is, in a fine device having a small gate length, when used as a 2-bit memory as described above, the positions of the accumulated charges of each bit are excessively close to each other. This approach adversely affects the reliability of the memory function. For example, when writing is performed only on one bit, if the accumulated charge positions are sufficiently separated from each other, when reading the other bit in the erased state, as described above, the influence of the accumulated charge on the write side bit Hardly receive. Therefore, the difference between the “erased state” and the “written state” can be clearly obtained.

  However, when the charge storage positions approach each other due to miniaturization, the read bit is easily affected by the information of the reverse bit. As a result, a difference occurs in the read current of the read side bit not only depending on the information on the read side bit but also whether the reverse bit is “written state” or “erased state”. Due to this difference, the read margin between the “written state” and the “erased state” becomes small, and the reliability of the memory is lowered.

  Also, from the viewpoint of long-term retention, it is not preferable that the charge storage positions of both bits are too close. Since the electric charges are trapped in the insulating film, the electric charges hardly move and are localized in the short term. However, at a finite temperature, part of the stored charge moves little by little in the charge storage insulating film, and there is a risk that both bits of information will gradually mix in the long term. It causes a decrease.

  In particular, since a large amount of information is handled in the modern information society, it is desired to increase the storage capacity per unit area for a semiconductor memory device. For this reason, there is a demand not only for two stages of presence / absence of accumulated charges, but also for multi-biting, which is used for information storage in a step-by-step manner. However, the reliability problem as described above can be an obstacle to the number of bits.

  Furthermore, there is a problem of an increase in off-leakage accompanying miniaturization. The insulating film having a charge storage function under the gate electrode also serves as a gate insulating film and has a layer structure including a first insulating film, a charge storage insulating film, and a second insulating film. The first insulating film and the second insulating film prevent the stored charge from flowing out from the charge storage insulating film. In order to hold the charge for a long period of time, the first and second insulating films need to be thick enough to prevent the charge outflow due to the tunnel phenomenon as much as possible. This hinders the thinning of the gate insulating film. Therefore, in a fine device, it causes an increase in off-leakage.

Thus, according to the present invention, a charge retention film having a function of locally accumulating charges formed on the semiconductor layer,
A gate electrode formed on a part of the charge retention film having a function of locally accumulating the charge;
A diffusion region formed in the semiconductor layer on both sides of the gate electrode,
The end of the diffusion region on the gate electrode side is located outside the area directly below the gate electrode,
A semiconductor memory device is provided in which the charge retention film having a function of locally accumulating charges extends to at least the end of the diffusion region on the gate electrode side.

According to the present invention, there is also provided a method for manufacturing the above semiconductor memory device,
Forming a charge holding film having a function of locally accumulating the charge; depositing a conductor film on the charge holding film; and processing the conductor film by lithography and etching to form a gate Forming an electrode;
Forming a sidewall spacer made of an insulator on a side surface of the gate electrode;
And a step of forming the diffusion region by implanting impurities and annealing. A method of manufacturing a semiconductor memory device is provided.

Furthermore, according to the present invention, there is provided a method for operating the semiconductor memory device,
A charge having a function of locally accumulating the charge by applying a voltage so that the potential of the gate electrode and the potential of the diffusion region are opposite to each other with respect to the potential of the semiconductor layer. There is provided a method for operating a semiconductor memory device, wherein only a part of electric charges in a holding film is erased.

  The semiconductor memory device of the present invention has a so-called offset structure in which the end of the diffusion region on the gate electrode side is outside the area directly below the gate electrode, and has a function of storing charges locally. The film extends to the gate electrode side end of the diffusion region outside the gate electrode. When this device is used as a 2-bit memory cell, the charge storage portions of the left and right bits can be separated from each other. As a result, even in a fine device, both bits of information can be clearly extracted, the read margin in the written state and the erased state is increased, and the reliability of the memory can be improved. Further, the offset structure in which the distance between the diffusion regions is larger than the gate length, the short channel effect can be suppressed as compared with the conventional semiconductor memory device, and the off-leakage can be further reduced. Therefore, a semiconductor memory device with low power consumption can be provided.

  Furthermore, the portion of the charge holding film where charge is accumulated is from the vicinity of the gate electrode end to the offset portion outside the gate electrode. There are three states: accumulated charge at both the gate electrode end and the offset portion (written state), charged only on one side (intermediate state), and no charge on both (erased state). By using it for information storage, the amount of information that can be stored per cell can be increased, and a device having a storage capacity of 2 bits or more per cell can be realized.

  In addition, at least part of the charge retention film having a function of accumulating charges locally, in order from the semiconductor layer side, a first insulating film, an insulator having a charge accumulating function, and a second insulating film In the case of having a structure consisting of, the following effects are obtained.

  That is, the charge accumulated in the insulator having a charge accumulation function is prevented from flowing out to the gate electrode, the semiconductor layer, or the like by the first insulating film and the second insulating film. As a result, it is possible to improve the reliability particularly during long-term holding.

  In addition, when the thickness of the first insulating film is different between the portion below the gate electrode and the portion outside the gate electrode, the following effects are obtained. The charge erasing speed strongly depends on the thickness of the first insulating film. Therefore, the charge erasure from the insulator having the charge storage function at the end of the gate electrode and the charge erasure speed from the insulator having the charge storage function in the offset portion can be greatly changed. As a result, an intermediate state in which accumulated charges exist only in one of the gate electrode end portion and the offset portion can be formed with good control and relatively easily. Increased controllability is a merit that leads to improved device reliability and faster device operation.

  Further, when the thickness of the first insulating film is thinner in the portion outside the gate electrode than in the lower portion of the gate electrode, the following effects are obtained. That is, the charge in the offset portion can be erased more effectively and more efficiently than in the vicinity of the gate electrode end, and the formation of the intermediate state can be realized with better control.

  Further, when the band gap of the first insulating film is different between the portion below the gate electrode and the portion outside the gate electrode, the following effects are obtained. That is, it is possible to change the charge erasing speed from the end portion of the gate electrode and the charge erasing speed at the offset portion. As a result, the intermediate state in which the accumulated charge exists only in one of the gate electrode end portion and the offset portion can be formed with good control and relatively easily. Increased controllability is a merit that leads to improved device reliability and faster device operation.

  Further, when the band gap of the first insulating film is smaller in the portion outside the gate electrode than in the lower portion of the gate electrode, the following effects are obtained. That is, the charge in the offset portion can be erased more effectively and more efficiently than in the vicinity of the gate electrode end, and the formation of the intermediate state can be realized with better control.

  Further, according to the method for manufacturing a semiconductor memory device of the present invention, the semiconductor memory device of the present invention can be manufactured at a relatively low cost without using a normal semiconductor process device and without a complicated process. There is.

  Further, the sidewall spacer can be formed by thermally oxidizing the surface of the gate electrode. Therefore, the sidewall spacer can be formed easily and inexpensively.

  Further, a sidewall spacer can be formed on the side surface of the gate electrode by a step of depositing an insulating film on the surface and a step of etching back the insulating film using an anisotropic etching method. This forming method is a relatively low-temperature process that does not depend on thermal oxidation. Therefore, even if the impurity implantation for forming the halo region is performed on the semiconductor layer before forming the sidewall spacer, the influence of the sidewall spacer forming process on the impurity profile can be reduced. Therefore, controllability of profile design can be improved. As a result, the degree of freedom in design for realizing desired device characteristics is increased, and there is an effect of increasing the yield by suppressing variations in the device characteristics.

  Further, the manufacturing method has a function of locally accumulating the first charge by removing the material film for forming the charge holding film having a function of locally accumulating the charge other than the portion below the gate electrode. A step of forming a charge retention film having a function, a step of forming a material film for forming a charge retention film having a function of locally accumulating the second charge on the surface, and an anisotropic etching method. The following effects are achieved by including a step of forming a charge retention film having a function of locally accumulating the second charge by etching back the second material film.

  In other words, a semiconductor memory device in which the thickness of the charge retention film having a function of locally accumulating charges is different between a portion below the gate electrode and a portion outside the gate electrode can be obtained without using a special process. It can manufacture using a manufacturing apparatus (line apparatus).

  In addition, a compound film of a refractory metal and a semiconductor is provided on at least a part of the upper surface of the gate electrode and / or the diffusion region. Since the compound film has low resistance, the sheet resistance can be reduced, and a semiconductor memory device with lower power consumption can be realized.

  In addition, a step of depositing a refractory metal after forming a diffusion region, a step of reacting at least a semiconductor on the surface of the diffusion region with a refractory metal by heat treatment, and a step of removing unreacted refractory metal And can be formed. Therefore, the compound film can be easily formed in a self-aligning manner, and an electrical short circuit between the compound films can be prevented.

  Further, in the operation method of the semiconductor memory device of the present invention, the charge is localized by applying a voltage so that the potential of the gate electrode and the potential of the diffusion region are opposite to each other with respect to the potential of the semiconductor layer. Only a part of the charges in the charge holding film having a function of accumulating in nature can be erased. Therefore, an intermediate state between the written state and the erased state can be stably obtained with good control. Therefore, the reliability of operation and the speed of operation can be improved.

The semiconductor memory device of the present invention has a semiconductor layer, an insulating film, a gate electrode, and a diffusion region.
The semiconductor layer is not particularly limited as long as it is used in a semiconductor device. The semiconductor layer includes not only a semiconductor layer formed on the substrate but also a semiconductor substrate. For example, a bulk substrate made of an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN; an SOI substrate, an SOS substrate, or a multilayer SOI substrate; a semiconductor layer formed on a glass or plastic substrate ( A layer made of the above element semiconductor or compound semiconductor). Among these, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor layer may be single crystal, polycrystalline, or amorphous.

  The charge holding film formed on the semiconductor layer is not particularly limited as long as it has a function of locally accumulating charges, and any insulating film used in a semiconductor device can be used. For example, an insulating film in which a first insulating film, a charge storage insulator film, and a second insulating film are stacked in this order from the semiconductor layer side, an insulating film containing a plurality of fine dots capable of storing charge, and the like can be given. In addition, in this specification, an electric charge means an electron or a hole. Further, “locally” means that the charges injected into the charge holding film are held at the injected position and do not move to other portions.

  In the above examples, as the first insulating film and the second insulating film of the former insulating film, a silicon oxide film, a silicon oxynitride film, a high dielectric material film (for example, aluminum oxide, hafnium oxide, hafnium oxide-silicon oxide mixture, Zirconium oxide, zirconium oxide-silicon oxide mixture, yttrium oxide, lanthanum oxide, lanthanum oxide-silicon oxide mixture, praseodymium oxide, cerium oxide) and the like. Examples of the charge storage insulator film include a silicon nitride film, a titanium oxide film, a tantalum oxide film, and a hafnium oxide film. The first insulating film and the second insulating film may be made of the same kind of film or different kinds of films, and in particular, the first insulating film is a material having a low trap level density in the film. It is preferable to use this film. Examples of the film made of a material having a low trap level density include a silicon oxide film and an aluminum oxide film. As an example of the structure, an aluminum oxide film is used for all of the first insulating film, the charge storage insulator film, and the second insulating film, and only the charge storage insulator film has an aluminum-rich composition with a high trap state density. In this case, there is an advantage that all the three layers can be formed by the same process apparatus.

  The latter fine dots include nitrides such as silicon nitride; oxides such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide and zinc oxide; silicon; silicate glass containing impurities such as phosphorus and boron; silicon Carbide; Ferroelectric; Dot of metal or the like. The shape and size of the dots can be appropriately set according to the desired amount of accumulated charge. Examples of the insulating film containing dots include a silicon oxide film, a silicon oxynitride film, and a high dielectric material film.

  The charge retention film having a function of locally accumulating charges is an easy-to-manufacture manufacturing of an insulating film in which a first insulating film, a charge storage insulating film, and a second insulating film are stacked in this order. To preferred.

  A gate electrode is formed on a part of the charge holding film having a function of accumulating charges locally. The gate electrode is not particularly limited as long as it is usually used in a semiconductor device. For example, polysilicon: metal such as copper and aluminum: refractory metal such as tungsten, titanium and tantalum: single layer film or laminated film such as silicide with refractory metal. Note that a channel region is located in the semiconductor layer under the gate electrode.

  Diffusion regions are formed in the semiconductor layer on both sides of the gate electrode. This diffusion region is located on both sides of the channel region in the semiconductor layer and functions as a source / drain region. The conductivity type and impurity concentration of the diffusion region can be set as appropriate according to the performance of the semiconductor memory device. A surface layer of the diffusion region may be provided with a refractory metal silicide layer.

  The diffusion region may be located in a well region formed in the semiconductor layer. The well region preferably has a conductivity type different from that of the diffusion region. In this case, the conductivity type of the diffusion region is the first conductivity type, and the conductivity type of the well region is the second conductivity type.

  Furthermore, in the semiconductor memory device of the present invention, the end of the diffusion region on the gate electrode side is located outside the region directly below the gate electrode in the channel length direction. This structure is referred to as an offset structure, and a semiconductor layer where the gate electrode and the diffusion region do not exist between the gate electrode and the diffusion region is referred to as an offset portion. The length of the offset portion in the gate length (channel length) direction can be appropriately set according to the performance of the semiconductor memory device.

The offset portion is located on at least one end side of the gate electrode. The offset portions are preferably located on both sides of the gate electrode. When offset portions are provided on both sides, the lengths of the offset portions in the gate length direction may be the same or different, and are preferably the same.
When the offset portion is on both sides, the width between the diffusion regions is preferably 1.05 to 1.5 times the gate length.

  In the present invention, the charge retention film having a function of locally accumulating charges extends at least over the end of the diffusion region on the gate electrode side. A charge holding film having a function of locally accumulating charges extends from below the gate electrode to the end of the diffusion area on the gate electrode side, thereby injecting charge from the diffusion area into the insulating film. And can be easily released.

  The end of the diffusion region on the gate electrode side preferably overlaps with a charge retention film having a function of locally accumulating charges. Although there is no particular upper limit to the overlap width, from the viewpoint of long-term charge retention, it is possible to further prevent long-term retention capability by preventing the diffusion of charges in the charge retention film having a function of locally accumulating charges. In order to lead to improvement, for example, it is more preferable that the overlap width is about 0 to 70 nm.

Furthermore, in the present invention, the following configuration may be provided.
First, an impurity region having the same or different conductivity type as that of the diffusion region may be further provided at the end of the diffusion region on the gate electrode side in order to suppress off-leakage and prevent a decrease in read current. The gate electrode side end of the impurity region may or may not have an offset structure with respect to the gate electrode.

  Next, in the charge retention film having a function of locally accumulating charges, it is preferable that the portion having the charge accumulation function exists at least in the extending portion. Furthermore, it is preferable that the portion having the charge storage function exists at the gate electrode end portion and directly below. The presence of this portion at and immediately below the end of the gate electrode makes it possible to change the ease of injecting and releasing the accumulated charge between the lower portion of the gate electrode and the extending portion. Utilizing this ease of injection and release, the types of charge accumulation states can be increased. Therefore, a larger number of bits can be realized.

  Further, the portion having the charge storage function may exist on the entire surface directly under the gate electrode, or may have a structure in which the portion exists only in the vicinity of the end of the gate electrode divided into right and left. The former has an advantage that it can be easily formed without going through a complicated process. The latter has a merit that the retention characteristics can be further improved because it is possible to more effectively prevent the accumulated charges from moving gradually along the charge retention film and mixing left and right information during long-term retention. . Either structure can be selected according to the purpose.

  In the case where the charge holding film having a function of locally accumulating charges is an insulating film in which the first insulating film, the charge storage insulating film, and the second insulating film are stacked in this order, the first insulating film The film may have a different film thickness and / or band gap between the lower portion of the gate electrode and the extending portion. This makes it possible to change the ease of injecting and releasing the accumulated charge between the lower portion of the gate electrode and the extending portion. Therefore, a larger number of bits can be realized. Further, by reducing the thickness of the first insulating film in the extending portion and / or reducing the band gap, it is possible to improve the ease of charge injection and emission in this portion from the lower part of the gate electrode. Can do.

  It should be noted that the thickness of the first insulating film in the extending portion is preferably 10% or more smaller than the lower portion of the gate electrode in order to effectively realize the above-described advantages, while on the other hand, to the outside of the accumulated charge It is more preferable to have a film thickness of 3 nm or more from the viewpoint of preventing the outflow of water and realizing long-term retention.

  Further, the band gap of the first insulating film in the extending portion is preferably 10% or more smaller than the lower part of the gate electrode in order to effectively realize the above-mentioned advantage, while on the other hand, to the outside of the accumulated charge It is more preferable that the first insulating film has a barrier of 1 eV or more with respect to the semiconductor layer from the viewpoint of preventing the outflow of the semiconductor layer and realizing long-term holding.

In addition, by changing the type of the charge storage insulator film between the lower portion of the gate electrode and the extending portion, the ease of injecting and releasing the stored charge can be changed.
In this specification, the charge holding film having a function of locally accumulating charges located under the gate electrode is used as the first charge holding film, and the charge holding film located in the extending portion is used as the second charge holding film. Also referred to as a charge retention film.

(Operation method)
The semiconductor memory device can be operated as follows, for example.

  That is, the voltage is applied so that the potential of the gate electrode and the potential of the diffusion region are opposite to each other with respect to the potential of the semiconductor layer. By applying this voltage, the charges in the charge holding film having a function of locally accumulating charges can be erased. Information can be written and erased using charge erasure and non-erasure. Further, the charge to be erased may be all or a part of the charge in the charge holding film.

(Production method)
The semiconductor memory device can be manufactured as follows, for example.
That is, first, a charge holding film having a function of locally accumulating charges is formed on the semiconductor layer. Next, a conductor film is deposited on the charge retention film. Further, the gate electrode is formed by processing the conductor film by lithography and etching. Thereafter, sidewall spacers made of an insulator are formed on the side surfaces of the gate electrode so that the gate electrode is positioned on a part of the charge retention film. Next, a semiconductor memory device can be manufactured by performing impurity implantation and annealing to form the diffusion region.

  The sidewall spacer can be formed by, for example, a method of thermally oxidizing the side surface of the gate electrode, a method of stacking a sidewall spacer forming film on the entire surface, and etching back by anisotropic etching.

  When a refractory metal compound film is provided on the surface layer of the diffusion region, this compound film can be obtained, for example, by the following method. First, after forming the diffusion region, a refractory metal layer is laminated on the front surface. Next, the compound film is formed by subjecting the semiconductor layer and the refractory metal layer to heat treatment. Furthermore, the compound film can be formed only on the surface layer of the diffusion region by removing the unreacted refractory metal layer.

When the charge retention film having a function of locally accumulating charges includes the first charge retention film and the second charge retention film, for example, these films can be formed as follows.
First, after the formation of the gate electrode, the first charge retention film is formed by removing the charge retention film forming material film having a function of locally accumulating charges other than directly under the gate electrode. Next, a material film for forming a second charge retention film is formed so as to cover at least the side surface of the gate electrode. Furthermore, the second charge retention film can be formed by etching back the second material film using an anisotropic etching method.

(Embodiment)
Hereinafter, the present invention will be described in more detail with reference to the drawings. In the following, an n-type device (a device in which the diffusion region is an n-type) will be described. However, a p-type device can also be formed by reversing the impurity conductivity type and the bias. Here, the charge is defined as an electron, and a state where electrons are accumulated in the charge holding film is defined as a written state, and a case where no electrons are accumulated is defined as an erased state.

First Embodiment A configuration of a semiconductor memory device in a first embodiment will be described with reference to FIGS. FIG. 1A is a schematic cross-sectional view of the semiconductor device of the first embodiment. A first insulating film 102, a charge storage insulating film 103, and a second insulating film 104 are provided over the p-type semiconductor layer 101. Further, a gate electrode 105 made of polysilicon or the like is formed on the upper portion, and side wall spacers 106 and 107 made of an insulator are provided on the side surface of the gate electrode 105. N-type diffusion regions 109 and 110 are formed in the left and right semiconductor layers 101 of the gate electrode 105. For example, a p-type silicon substrate is used as the semiconductor layer 101. Here, the diffusion regions 109 and 110 and the gate electrode 105 do not overlap and are in an offset positional relationship (in the figure, 111 and 112 are offset portions). In addition, the first insulating film 102 and the charge storage insulating film 103 extend at least above the positions of the diffusion regions 109 and 110 near the gate electrodes. A channel region 108 is located in the semiconductor layer 101 below the gate electrode 105.

  As described above, the charge storage insulating film 103 has a structure in which the lower part is sandwiched between the first insulating film 102 and the upper part is sandwiched between the second insulating film 104 or the side wall spacers 106 and 107, and this functions as a memory function body. Have. The first insulating film 102 and the second insulating film 104 serve as a barrier for charges accumulated in the charge storage insulating film 103 and have a function of preventing the charges from easily flowing out to the semiconductor layer 101 and the gate electrode 105. .

  Here, an element isolation band, an interlayer insulating film, an electrode, a contact plug, and the like provided on the semiconductor layer are not shown. Although not shown, a halo region having a high boron concentration may be formed in the substrate of the offset portions 111 and 112.

  In the semiconductor memory device of this embodiment, the gate electrode 105 and the diffusion regions 109 and 110 are offset. For this reason, the distance between the diffusion regions 109 to 110 is larger than that of the conventional semiconductor memory device, and even in a fine device, there is an advantage that off-leak due to the short channel effect can be further reduced.

  The writing, erasing, and reading operations of the semiconductor memory device of this embodiment may be performed according to the writing, erasing, and reading methods in the above background art. That is, for example, when writing is performed, a positive write voltage of about 6V is applied to the diffusion region 110, a positive write voltage of about 6V is applied to the gate electrode, and the p-type semiconductor layer and the diffusion region 109 are set to 0V. At this time, as shown in FIG. 1B, the inversion layer 113 is formed under the gate electrode, and electrons flow from the diffusion regions 109 to 110. However, since the inversion layer 113 is pinched off in the vicinity of the diffusion region 110, electrons are accelerated in the vicinity of the diffusion region 110 by a high electric field, and hot electrons are generated. A part of the hot electrons are pulled by the electric field of the gate electrode 105 and run upward in the drawing, and are trapped by the charge storage insulating film 103 to become stored charges 114. The accumulated charge 114 is trapped in the charge accumulation insulating film 103 at a portion from the lower portion of the sidewall spacer 107 to the lower portion of the gate electrode 105 near the diffusion region 110.

  Reading of this charge (charge accumulated on the right side of the sheet with respect to the apparatus by the above writing operation) is performed as follows. That is, the diffusion region 110 is set to 0V, and a positive read voltage of about 2V is applied to the diffusion region 109. Further, a positive read voltage of about 3 V is applied to the gate electrode 105. As a result, electrons flow from the diffusion region 110 to the diffusion region 109. Depending on the amount of the stored charge 114, the magnitude of the electron flow is also affected by the potential. In other words, the amount of accumulated charge 114 can be read as the magnitude of the current, and this can be used as information storage.

  On the other hand, at the time of writing, when a positive voltage is applied to the diffusion region 109 and 0 V is applied to the diffusion region 110 contrary to the above, conversely to the above, the diffusion region Charges are trapped in the charge storage insulating film 103 at a portion of the gate electrode 105 near the lower portion 109.

  The charge on the left side is read by applying a positive voltage of 0 V to the diffusion region 109, a positive voltage of 2 V, for example, to the diffusion region 110, and a positive voltage of 3 V, for example, to the gate electrode. This can be done by detecting. In this case, the amount of charge accumulated on the left side greatly affects the magnitude of the current, but the amount of charge accumulated on the right side does not significantly affect the magnitude of the current. This is because the inversion layer in the vicinity is pinched off by the positive voltage applied to the diffusion region 110 on the right side of the paper at the time of reading as described in the above-mentioned section of the prior art.

  Conversely, when reading the right charge amount information, by applying a positive voltage to the left diffusion region 109, the left charge amount information is ignored and the right charge amount information is mainly reflected in the current amount. In other words, according to the background art method described above, by reversing the reading directions, the presence or absence of the accumulated charge on the left side and the presence or absence of the accumulated charge on the right side can be individually taken out, and 2-bit information is stored in one device. Can be stored.

  In the present embodiment, the charge storage insulating film 103 extends to the outside rather than below the gate electrode 105. For this reason, charges are accumulated in the charge storage insulating film 103 at a portion from the lower portion of the sidewall spacer 107 (106) to the lower portion of the gate electrode 105 near the diffusion region 110 (109). As a result, the charge accumulation positions of the left and right bits are separated from each other. For this reason, both bits of information can be clearly separated, and the reliability during long-term storage is also increased.

  In the case of erasing, for example, a negative erasing voltage of about −6V is applied to the gate electrode 105 and a positive erasing voltage of about 6V is applied to the right diffusion region 110, and the semiconductor layer 101 is set to 0V. To do. At this time, some electrons flow from the valence band of the semiconductor layer to the conduction band of the diffusion region 110 by the interband tunnel, and further, the electric field is accelerated to collide with silicon atoms in the semiconductor layer 101 to cause hot holes and hot electrons. Generate a pair. Part of the hot hole is pulled by the electric field of the gate electrode 105, enters the charge storage insulating film 103, recombines with the stored charge 114, and extinguishes the charge. As a result, only the charge accumulated on the right side can be erased. In the case of erasing the left accumulated charge, a positive voltage is applied to the left diffusion region 109.

  As described above, the same method as the background art can be used for writing / reading / erasing. Here, in the case of the present embodiment, the left and right charge accumulation positions are from the end of the gate electrode 105 to the offset portions 111 and 112, and can be further separated from each other than the background art. For this reason, it is easy to separate both information. In particular, when one of the left and right bits is held for a long time while being in the written state and one in the erased state, the accumulated charge gradually moves laterally from the write side bit via the trap level in the charge accumulation insulating film 103. . When the accumulated charge reaches the erasure side bit, the difference between the write side read and the erase side read becomes small, and the discrimination becomes difficult. In the present embodiment in which the left and right charge storage positions are separated from each other, such information mixing is less likely to occur, which is advantageous for long-term information retention.

Next, a method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS.
First, as shown in FIG. 2, a gate insulating film composed of a first insulating film 102, a charge storage insulating film 103, and a second insulating film 104 and a gate electrode 105 are sequentially formed on the p-type semiconductor layer 101. To do.

  Although a general silicon substrate having an element isolation region is used as the semiconductor layer 101 here, a silicon-germanium substrate or the like may be used. Further, a semiconductor layer (eg, a silicon layer) provided over a glass substrate may be used.

  The first insulating film 102 was obtained by thermally oxidizing the surface of the silicon substrate 101. The film thickness is preferably about 1 nm to 10 nm, and is 5 nm here. As the material of the film, in addition to the thermal oxide film, a CVD oxide film, a high dielectric material film, an oxide film obtained by radical oxidation, or the like may be used. Also, a combination of these films may be used.

  As the charge storage insulating film 103, a silicon nitride film is used. However, other materials such as aluminum oxide and hafnium oxide may be used, or an insulating film containing a plurality of fine dots capable of storing charge (silicon oxide film). Etc.) can also be used. A combination of these films may also be used. In this embodiment using a silicon nitride film, the film thickness is 1 nm to 15 nm, for example, 5 nm. In particular, when the film is thinned, there is an advantage that the stored charge is suppressed by suppressing the lateral diffusion of the accumulated charge.

  Here, the second insulating film 104 is a CVD oxide film, and has a thickness of 8 nm, for example. In addition to the CVD oxide film, the surface of the silicon nitride film can be thermally oxidized to obtain an oxide film, or a high dielectric material film can be used. A combination of these films may be used. When the silicon nitride film surface is thermally oxidized, a part of the surface of the silicon nitride film is consumed as an oxide film. Therefore, the consumption by oxidation is reduced so that a silicon nitride film having a desired film thickness remains finally. An overlaid silicon nitride film is formed.

  Polysilicon was used for the gate electrode 105. As the gate electrode, a polysilicon film can be formed by well-known lithography and dry etching. Here, the gate length was 130 nm and the gate width was 200 nm.

  However, in this embodiment, the etching is stopped at the second insulating film 104 to leave a film below this. Further, the second insulating film other than just under the gate electrode 105 is removed by wet etching. Although this step is not essential, the surface of the second insulating film may be damaged by plasma of the etching species during gate etching. Therefore, in order to improve the reliability as a memory device, it is preferable to remove the second insulating film other than just below the gate electrode 105. In this way, the shape of FIG. 3 is obtained.

  Next, sidewall spacers 106 and 107 made of an insulator having a thickness of about 20 nm to 150 nm are formed on the side surface of the gate electrode 105. This can also be formed by etching back after an insulating film such as a silicon oxide film is formed by CVD on the entire surface of the substrate. It can also be obtained by thermally oxidizing the surface of the gate electrode (FIG. 4). In particular, the latter method is simple and has the advantage of reducing the manufacturing cost. Here, the latter method is adopted (the advantage of the former method is mentioned in the second embodiment described later). Here, the width of the sidewall spacers 106 and 107 in the gate length direction is set to 50 nm.

  Next, a diffusion region forming step is performed. In the diffusion region forming step of this embodiment, the first insulating film 102 and the charge storage insulating film 103 remaining on the silicon layer surface are used as they are as an injection protective film. Further, a CVD oxide film or the like may be deposited thereon to adjust the implantation protective film thickness. Further, after removing the charge storage insulating film 103 exposed on the surface and the first insulating film 102 therebelow, a new implantation protective film may be formed by thermal oxidation or deposition of a CVD oxide film.

Thereafter, for example, arsenic ions whose energy is controlled to 30 keV are implanted at an area density of 5 × 10 ¹⁵ cm ⁻² , and the surface of the silicon substrate 101 and the gate electrode 105 are doped with arsenic ions as n-type impurities. To do. At this time, arsenic ions are not doped under the channel region 108 under the gate and under the side wall spacers 106 and 107.

  Thereafter, the implanted ions are activated by annealing in a nitrogen atmosphere, for example, RTA treatment at 1050 ° C. for 10 seconds. In this way, as shown in FIG. 5, n-type diffusion regions 109 and 110 as an example of the second conductivity type are formed in the silicon substrate 101 so as to be approximately bilaterally symmetrical about the gate electrode 105 on the paper surface. . During the annealing, arsenic ions diffuse into the silicon due to diffusion of arsenic ions into the lower portions of the side wall spacers 106 and 107, and part of the diffusion regions 109 and 110 extend under the side wall spacers 106 and 107. . By appropriately setting the annealing conditions, the ends of the diffusion regions 109 and 110 (the junction with the well region) are positioned under the side wall spacers 106 and 107, and the diffusion regions 106 and 107, the gate electrode 105, Offset portions 111 and 112 can be formed between the two.

  Here, the overlap width in the gate length direction between the diffusion regions 106 and 107 and the charge storage insulating film 103 is 40 nm. The width of the offset portions 111 and 112 in the gate length direction was 10 nm.

Note that halo implantation may be performed before the annealing step. The halo implantation is performed before or after the arsenic ion implantation step. In the halo implantation, boron, which is a p-type impurity, is implanted at an energy of 20 to 60 keV and has an area density of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^−2, which is smaller than the area density of arsenic. This means implantation at the bottom of the sidewall spacers 106 and 107 at an angle between 15 ° and 45 °. After the halo implantation, annealing is performed to form a halo region having a high concentration of boron, which is a p-type impurity, in the offset portions 111 and 112 near the end portions of the diffusion regions 109 and 110 (not shown). By forming the halo region, the diffusion regions 109 and 110 can be prevented from diffusing under the gate electrode 105, and the offset portions 111 and 112 can be stably formed.

  Prior to the formation of the above-mentioned various constituent members, the p-type well region which is the first conductivity type was initially the entire silicon substrate 101. Since the diffusion regions 109 and 110 are formed in the silicon substrate 101, the p-type well region of the first conductivity type is naturally reduced to the region where the diffusion regions 109 and 110 are not formed in the silicon substrate 101. It is.

  Through the above steps, the device structure of the first embodiment shown in FIG. 1 is obtained. Here, if necessary, the insulating film on the gate electrode 105 or the charge storage insulating film 103 exposed on the surface may be removed by etching.

Second Embodiment A second embodiment will be described with reference to FIGS. In the second embodiment, before the formation of the sidewall spacers 106 and 107, halo implantation and repetitive implantation with n-type impurities for reducing the halo concentration in the vicinity of the surface are performed. That is, after processing the gate electrode as shown in FIG. 3 according to the first embodiment, an implantation protective film (not shown) is formed on the surface as necessary. Thereafter, boron, which is a p-type impurity, is implanted with an energy of 15 to 20 keV and an area density of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² at an angle of 10 ° or less with respect to the vertical direction. Furthermore, in the present embodiment, arsenic, which is an n-type impurity whose energy is set to 20 to 40 keV, is implanted at an angle of 10 ° or less with respect to the vertical direction and below the area density of boron (FIG. 6).

  Thereafter, sidewall spacers 106 and 107 are formed. Here, rather than a method in which the surface of the gate electrode 105 is directly thermally oxidized, there is a method in which an insulating film is deposited on the entire surface by a CVD method, and then a sidewall spacer is formed by etch back using reactive ion etching (RIE). preferable. Since this method is a lower temperature method than the thermal oxidation method, it is possible to suppress thermal diffusion in the semiconductor layer of boron and arsenic implanted earlier.

Thereafter, for example, arsenic ions whose energy is controlled to 30 keV are implanted at an area density of 5 × 10 ¹⁵ cm ⁻² . Next, by performing an annealing process such as RTA, diffusion regions 109 and 110 extending to a part below the sidewall spacers 106 and 107, and a halo region 115 having a high p-type concentration under the sidewall spacers 106 and 107, 116, and further on top thereof, near the boundary with the first insulating film 102, halo return regions 117 and 118 in which the halo concentration is lowered by arsenic return are formed. Since this halo return region is not essential, the formation process may be omitted. However, by providing this, there is an advantage that the halo concentration under the side wall spacers 106 and 107 is prevented from becoming too high and the read current can be reduced.

In the present embodiment, halo implantation is performed before the sidewall spacers 106 and 107 are formed. Therefore, halo implantation can be performed on the lower regions of the sidewall spacers 106 and 107 at a relatively low energy at an angle close to vertical. As a result, it can be accurately injected to a desired depth. The same applies to the halo reversal injection. Further, when forming the sidewall spacers 106 and 107 after these implantations, it is preferable to form them by deposition and etchback of the CVD film rather than by thermal oxidation. The latter method has an advantage that the impurity profile can be controlled with high accuracy because the processing temperature is low and the influence on the implantation profile is small.
Thereafter, the semiconductor memory device of the second embodiment is manufactured by appropriately forming an interlayer insulating film, a contact plug, and the like.

Third Embodiment The third embodiment relates to a method for erasing a semiconductor memory device according to the present invention. According to this embodiment, the amount of information that can be stored in one cell can be further increased.

  In the first embodiment, the charges accumulated in the charge storage insulating film are erased by using hot holes generated by interband tunneling electrons. However, in this embodiment, FN tunneling (Fowler-Nordheim tunneling) by an electric field is performed. ) Is used to extract the accumulated charge. In this method, only a part of the accumulated charge can be extracted. This will be described with reference to FIGS. 8 (a) and 8 (b).

  FIG. 8A shows a state where charges are accumulated by writing to the bit on the right side of the drawing according to FIG. 1B of the first embodiment. Charges are accumulated in the charge storage insulating film 103 from under the right end of the gate electrode 105 to under the sidewall spacer 107. Here, for the sake of convenience, among these charges, the charge that exists approximately near the lower portion of the gate electrode end is represented as 114a, and the charge that exists approximately near the lower portion of the sidewall spacer is represented as 114b. In this state, when reading is performed using the left diffusion region 109 as the drain and the right diffusion region 110 as the source, the read current decreases due to the potential of both the stored charges 114a and 114b of the right bit, and is recognized as the “write state”. (If both the stored charges 114a and 114b are absent, the read current increases and is recognized as an “erased state”).

  Here, a high negative voltage, for example, −14 V is applied to the gate electrode 105, and a positive voltage of about 4 V is applied to the right diffusion region 110. The potential of the semiconductor layer 101 is 0V. At this time, due to the strong electric field between the gate electrode 105 and the right diffusion region 110, only a part of the accumulated charge, that is, the accumulated charge 114 b near the end of the diffusion region 110 under the side wall spacer 107 becomes FN tunnel. Is extracted into the diffusion region 110. On the other hand, the accumulated charge 114 a at a part away from the end of the diffusion region 110 remains in the charge accumulation insulating film 103 as it is.

  In this way, as shown in FIG. 8B, a state in which a part of the right bit charge is extracted is obtained. In this state, the right bit is read using the left diffusion region 109 as the drain and the right diffusion region 110 as the source. In this case, the read current 119 is larger than the read current for the state of FIG. 8A before the charge 114b is extracted and smaller than the read current for the erased state. That is, it can be recognized as an intermediate state between the state of FIG. That is, the three states of the erased state, the intermediate state, and the written state can be used for information storage, and the amount of information that can be stored in one cell can be increased. Thereby, a high-density storage capacity memory cell array having a high storage capacity per unit area can be realized.

  When erasing the remaining accumulated charges or erasing all accumulated charges at once, hot hole generation by band-to-band tunneling can be used as in the first embodiment, or by FN tunneling. It is also possible to erase the charge.

  When performing charge erasure by FN tunneling, for example, a high negative voltage of about −18 V is applied to the gate electrode 105, and 0 V is applied to the semiconductor layer 101 and the diffusion region 110. As a result, a strong electric field in the vertical direction is applied to the entire surface of the charge storage insulating film, and all the stored charge can be erased.

The above description has been made with respect to the erasure of the accumulated charge on the right side of the paper. However, the erase of the accumulated charge on the left side of the paper can be similarly performed by reversing the left and right sides.
Note that if the first insulating film 102, the charge storage insulating film 103, and the second insulating film 104 are made thinner, each voltage at the time of erasing can be lowered. Therefore, the film thickness may be set as appropriate within a range that does not impair the charge retention capability according to the purpose.

Fourth Embodiment A fourth embodiment will be described with reference to FIGS. First, as shown in FIG. 3 of the first embodiment, a gate electrode is formed using a lithography technique and an etching technique. In this embodiment, the second insulating film 104 and the charge storage insulating film 103 other than the lower part of the gate electrode 105 are also removed after the gate etching. Further, the first insulating film 102 other than the lower portion of the gate electrode 105 is also removed by a method such as etching using a hydrofluoric acid solution (FIG. 9). As a result, a first charge retention film is formed below the gate electrode 105.

  Further, after that, thermal oxidation may be performed on the exposed surface of the semiconductor layer 101, and so-called sacrificial oxidation treatment may be performed in which the surface is wet-etched with a hydrofluoric acid solution or the like. By performing this sacrificial oxidation treatment, even if the surface of the semiconductor layer 101 is damaged by plasma in the etching process or the charge storage insulating film removing process, this damage can be removed, and the reliability of the memory is further increased. Can be increased.

  Next, as illustrated in FIG. 10, the insulating film 121 is provided on the exposed surface of the semiconductor layer 101, and the insulating film 122 is provided on the side surfaces and the upper surface of the gate electrode 105 by performing thermal oxidation on the surface. Subsequently, a charge storage insulating film 123 such as a silicon nitride film and an insulating film 124 such as a silicon oxide film are sequentially deposited by CVD. Here, the thickness of the insulating film 121 on the semiconductor layer 101 is smaller than that of the first insulating film 102 in this embodiment. For example, the thickness of the first insulating film is 5 nm, and the thickness of the insulating film 121 over the semiconductor layer 101 is 4 nm. The film thickness of the charge storage insulating film 123 may be approximately the same as that of the charge storage insulating film 103 under the gate electrode, and is, for example, 5 nm. The thickness of the insulating film 124 is about 20 nm to 150 nm.

  Subsequently, by etching back the entire surface using RIE, sidewall spacers made of the insulating film 122, the charge storage insulating film 123, and the insulating film 124 are formed on the side surfaces of the gate electrode 105 as shown in FIG. Is done. This sidewall spacer has a structure similar to that of the memory function body under the gate electrode 105, and functions as a second charge retention film. That is, under the gate electrode 105, there is a gate insulating film composed of three layers of the first insulating film 102, the charge storage insulating film 103, and the second insulating film 104 in order from the bottom of the drawing. Have the work of On the other hand, the side wall spacer portion similarly has a memory function body composed of three portions of the insulating films 120 and 121, the charge storage insulating film 123, and the insulating film 124. In particular, a portion of the charge storage insulating film 123 is opposed to the semiconductor layer 101 with the insulating films 120 and 121 interposed therebetween, as is the case under the gate electrode 105, below the side wall spacer.

  By the way, in the etch back of this embodiment, first, the insulating film 124 other than the gate electrode side wall is removed using the charge storage insulating film 123 as an etching stopper, and subsequently, the charges other than the gate electrode side wall using the insulating films 120 and 121 as an etching stopper. A method of removing the storage insulating film 123 is used. However, it is not always necessary to remove these films. It is possible to leave an appropriate film thickness and use it as an implantation protective film in a later implantation process.

However, removing these films once and forming the implantation protective film again has higher controllability of the film thickness of the sidewall spacer portion, so in this embodiment, all the films other than the sidewall spacer portion are removed. I decided to. That is, first, the insulating film 124 and the charge storage insulating film 123 other than the side surface portion of the gate electrode 105 are removed by etch back. Further, the insulating films 120 and 121 exposed on the surface of the semiconductor layer 101 are also removed by wet etching with hydrofluoric acid or the like. Thereafter, an implantation protective film (not shown) is appropriately formed by thermal oxidation or CVD. Thereafter, for example, arsenic ions whose energy is controlled to 30 keV are implanted at an area density of 5 × 10 ¹⁵ cm ⁻² , and annealing treatment such as RTA is performed. As a result, diffusion regions 109 and 110 are formed (FIG. 12).

  Through the above steps, a structure in which the gate electrode and the diffusion region are offset and the memory function body extends from the bottom of the gate electrode to the end of the diffusion region can be obtained as in FIG. 1 of the first embodiment.

  In this embodiment, the insulating film provided between the charge storage insulating films 103 and 123 and the semiconductor layer 101, that is, the first insulating film 102 under the gate electrode 105, and the insulating films 120 and 121 under the side wall spacer are formed. Since they are formed in different steps, they can be made relatively different from each other.

  Note that a halo region or a halo hitting region may be formed according to the method of the second embodiment. In this case, after depositing the charge storage insulating film 123 and before depositing the insulating film 124, halo implantation or halo return implantation may be performed in accordance with the second embodiment. At this time, the charge storage insulating film 123 can be used as it is as an injection protective film. In addition, after performing these implantations, an insulating film 124 is deposited and etched back to form sidewalls, whereby implantation species can be introduced under the sidewall spacers (FIG. 6, FIG. 6 of the second embodiment). 7).

  Writing to the semiconductor memory device of this embodiment is performed by the same method as that of the first embodiment. That is, for example, when electrons are injected into the charge storage insulator on the right side of the paper, 0 V is applied to the semiconductor layer 101 and the diffusion region 109, a positive write voltage is applied to the diffusion region 110, and a positive write voltage is applied to the gate electrode 105. As a result, electrons flow from the diffusion region 109 to the diffusion region 110 and are accelerated by a high electric field in the vicinity of the diffusion region 110 to generate hot electrons. The hot electrons are trapped in the charge storage insulating film. At this time, as shown in FIG. 13, in the present embodiment, charges are accumulated in the right side portion (accumulated charge 125) of the charge storage insulating film 103 below the gate electrode 105 and in the right side wall spacer. This is the lower part of the charge storage insulating film 123 (stored charge 126). Reading is also performed according to the first embodiment.

Erasing is also performed according to the first embodiment, but in this embodiment, the amount of stored information per cell can be increased by adjusting the erasing time.
In the case of erasing the accumulated charge on the right side of the drawing, a negative erase voltage is applied to the gate electrode 105, a positive erase voltage is applied to the diffusion region 110, and 0V is applied to the semiconductor layer 101, as in the first embodiment. As a result, a band-to-band tunnel current 127 is generated between the diffusion region 110 and the semiconductor layer 101, and the electrons are further accelerated by an electric field to generate a hot hole 128. Part of the charge disappears in the charge storage insulating film. This process is as described in the first embodiment.

  Here, the feature of this embodiment is that the thickness of the insulating film 121 under the sidewall spacer is set to be thinner than that of the first insulating film 102 under the gate electrode. The number of hot holes that reach the charge storage insulating film over the insulating film per unit time at the time of erasure depends particularly sensitively on the insulating film thickness, and therefore hot holes that enter the charge storage insulating film 123 beyond the thin insulating film 121. The number of hot holes increases beyond the number of hot holes that enter the charge storage insulating film 103 beyond the first insulating film 102, and the charge in the charge storage insulating film 123 is preferentially erased. By utilizing this fact and applying an erase pulse of an appropriate time, the charge in the charge storage insulating film 123 of the sidewall spacer portion can be erased while leaving the charge 125 in the charge storage insulating film 103 as much as possible. The state of FIG. 14 is an intermediate state between writing and erasing. As described in the third embodiment, the amount of information that can be stored per cell can be increased by using this intermediate state as one state of stored information. In the present embodiment, this intermediate state can be realized with good control while using an erasing method using a band-to-band tunnel, and there is an advantage that this can be realized at high speed.

  In order to change from the intermediate state to a more complete erase state, the above-described band-to-band tunnel erase may be performed for a longer time, or an electric field may be extracted by the FN tunnel by applying an electric field to the gate electrode 105 and the semiconductor layer 101. Good. This is as described in the third embodiment.

  In this embodiment, erasing by band-to-band tunneling is used. However, it is also possible to create an intermediate state by preferentially extracting sidewall charges by FN tunneling by the same method as in the third embodiment. is there. In particular, by setting the thickness of the insulating film 121 in the sidewall spacer portion to be thin, the charge 126 (FIG. 13) in the sidewall spacer can be more easily extracted. Therefore, the intermediate state can be created with better control. In particular, erasing using an FN tunnel is effective in realizing a low power consumption device because almost no current flows.

  Furthermore, in this embodiment, the thickness of the insulating films 120 and 121 below the sidewall spacer is set to be smaller than the thickness of the first insulating film 102 under the gate electrode 105, but this may be reversed. Is possible. In this case, the accumulated charge 125 under the gate electrode 105 is preferentially erased when erasing. Therefore, the intermediate state can be realized by erasing until the charge 125 is erased and the charge 126 of the sidewall spacer portion remains.

  However, there is an advantage that higher controllability can be realized by setting the insulating film 121 below the side wall spacer thinner as in the above-described embodiment. That is, at the time of erasing, when a negative voltage is applied to the gate electrode 105, a positive voltage is applied to the diffusion region 110, and 0 V is applied to the semiconductor layer 101, the gate electrode 105 to the diffusion region 110 is stronger than between the gate electrode 105 to the semiconductor layer 101. An electric field is applied. Further, at this time, if the insulating films 120 and 121 under the sidewall spacer are thin, the charge 126 in the sidewall spacer portion can be erased at a higher speed by the synergistic effect of the strong electric field and the thin film thickness.

  Thereby, the difference between the erase speed of the side wall spacer portion charge 126 and the erase speed of the charge 125 under the gate electrode 105 can be further increased. Therefore, an intermediate state in which only the charge 125 under the gate electrode 105 remains can be stably generated at high speed.

Fifth Embodiment The semiconductor memory device according to the fifth embodiment is also fabricated according to the fourth embodiment. In FIG. 12, the first insulating film 102 under the gate electrode and the insulating film under the side wall spacer are provided. 120 and 121 are made of different materials and have different band gaps. For example, a silicon oxide film is used as the first insulating film 102, and a silicon oxynitride film having a smaller band gap is used as the sidewall spacer lower insulating films 120 and 121. In this way, by making the two materials different and making the different band gaps, it is possible to make a difference in the height of the electrical barrier for the hot carrier.

This method also makes a difference between the charge erasing speed in the charge storage insulating film 103 under the gate electrode and the charge erasing speed under the charge storage insulating film 123 in the side wall spacer, as described in the fourth embodiment. be able to. As a result, an intermediate state between writing and erasing can be created with good control.
Note that the first insulating film 102 and the insulating films 120 and 121 can be formed by a CVD method or the like, and films of materials other than the above may be used.

  Contrary to the above-described embodiment, the first insulating film 102 under the gate electrode 105 is made of a material having a smaller band gap and a lower electrical barrier than the sidewall spacer lower insulating films 120 and 121. Is also possible. However, for the same reason as described in the fourth embodiment, when the material having a smaller band gap is used for the insulating films 120 and 121 under the side wall spacer, the charge 125 under the gate electrode 105 is reduced during erasing. A large difference can be made between the speed at which the charge is erased and the speed at which the charge 126 in the sidewall spacer portion is erased. Therefore, an intermediate state in which the side wall spacer lower charge 126 is erased and the charge 125 under the gate electrode 105 remains can be created more easily.

Sixth Embodiment A sixth embodiment will be described with reference to FIGS. 15 (a) and 15 (b). The sixth embodiment relates to electrode formation of a semiconductor memory device, and can improve the performance of the semiconductor memory device.

  First, with respect to the structure shown in FIG. 1A obtained according to the description of the first embodiment, natural oxide films on the diffusion regions 109 and 110 and the gate electrode 105 are removed as much as possible with a hydrofluoric acid solution. Thereafter, as shown in FIG. 15A, a refractory metal film 129 is deposited on the entire upper surface. Examples of the material of the refractory metal film 129 include metals such as titanium, cobalt, and nickel. In this deposition step, a sputtering method is generally used, but a CVD method or the like may be used in addition, and any means is not particularly limited. The high melting point metal 129 is deposited with a film thickness of about 10 to 50 nm by an appropriate means.

  Next, first and second two-stage heat treatments are performed. First, as the first heat treatment, RTA treatment is performed for about 10 seconds to 30 seconds in a temperature range of about 400 ° C. to 700 ° C. By this first heat treatment, silicon and the refractory metal are formed in the portion where the upper surfaces of the diffusion regions 109 and 110 are in contact with the refractory metal film 129 and in the portion where the upper surface of the gate electrode 105 is in contact with the refractory metal film 129. React to form a refractory metal silicide film. On the other hand, at a relatively low temperature as described above, the reaction between the refractory metal film 129 and the insulating film 106 made of a silicon oxide film or the like is suppressed, and the refractory metal silicide film is not formed. Although not specifically shown in this specification, the refractory metal silicide film is not formed on the element isolation region for the same reason. For this reason, a refractory metal silicide film can be selectively formed only in a portion where silicon is in contact with a refractory metal.

  Subsequently, the unreacted refractory metal film is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. As a result, as shown in FIG. 15B, the refractory metal silicide films 131 and 132 are formed on the diffusion regions 109 and 110, and the refractory metal silicide film 130 is formed on the gate electrode 105. Can be obtained that are electrically insulated from each other.

  Thereafter, as the second heat treatment, the resistance of the refractory metal silicide films 130, 131, and 132 is further reduced by performing RTA treatment for about 10 seconds to 30 seconds in a temperature range of about 800 ° C. to 1000 ° C. be able to. Through the above steps, a low-resistance refractory metal silicide film can be formed on the gate electrode 105 and the diffusion regions 109 and 110 in a self-aligning manner. As a result, the sheet resistance of the gate electrode 105 and the diffusion regions 109 and 110 is reduced, so that low power consumption and high speed operation of the semiconductor memory device can be realized.

  The technique described in this embodiment is based on the so-called salicide technique, but this technique is possible because the semiconductor memory device of the present invention has the insulator sidewall spacer on the side surface of the gate electrode. It has become. That is, the example in which the present technique is applied to the semiconductor memory device of the first embodiment has been described here, but the same technique can be applied to the other embodiments described above.

1A is a schematic cross-sectional view of a main part of a semiconductor memory device according to a first embodiment of the present invention, and FIG. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 2nd Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 2nd Embodiment of this invention. It is a schematic sectional drawing explaining the operation | movement for forming the intermediate state of the write state and the erased state, and the read operation of an intermediate state in the semiconductor memory device of 3rd Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 4th Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 4th Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 4th Embodiment of this invention. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 4th Embodiment of this invention. It is a schematic sectional drawing explaining the write-in state of the semiconductor memory device of 4th Embodiment of this invention. In the semiconductor memory device of 4th Embodiment of this invention, it is a schematic sectional drawing explaining the operation | movement for forming the intermediate state of a write state and an erase state. It is a schematic sectional drawing explaining the manufacturing method of the semiconductor memory device of 6th Embodiment of this invention. It is a schematic sectional drawing of the principal part of the conventional semiconductor memory device. It is a schematic sectional drawing explaining the write-in operation | movement of the conventional semiconductor memory device. 18 is a schematic cross-sectional view illustrating a read operation for reading a portion written by the write operation of FIG. 17 in a conventional semiconductor memory device. FIG. 18 is a schematic cross-sectional view illustrating a read operation for reading a portion opposite to a portion written by the write operation of FIG. 17 in a conventional semiconductor memory device. It is a schematic sectional drawing explaining the erasing operation | movement of the conventional semiconductor memory device. It is the band schematic diagram of the PN junction part explaining the erase operation of the conventional semiconductor memory device.

Explanation of symbols

101 Semiconductor layer 102, 202 First insulating film 103, 123, 203 Charge storage insulating film 104, 204 Second insulating film 105, 205 Gate electrode 106, 107 Side wall spacer 108, 208 Channel region 109, 110, 206, 207 Diffusion region 111, 112 Offset portion 113, 211 Inversion layer 114 Accumulated charge 114a Accumulated charge near the gate electrode end 114b Accumulated charge under the side wall spacer 115, 116, 209, 210 Halo region 117, 118 Halo return region 119, 214 Read current 120, 121, 122, 124 Insulating film 125 Accumulated charge in charge accumulating insulating film 126 126 Accumulated charge in charge accumulating insulating film 123 127 Band-to-band tunnel current 128, 216 Hot hole 129 High Melting point metal film 130, 131, 132 Compound film 201 Semiconductor substrate 212 Electron 213, 214 Read current 215 Tunnel electron 217 Hot electron

Claims (16)

A charge retention film formed on the semiconductor layer and having a function of locally accumulating charges;
A gate electrode formed on a part of the charge retention film having a function of locally accumulating the charge;
A diffusion region formed in the semiconductor layer on both sides of the gate electrode,
The end of the diffusion region on the gate electrode side is located outside the area directly below the gate electrode,
A semiconductor memory device, wherein the charge retention film having a function of locally accumulating charges extends at least to an end of the diffusion region on the gate electrode side.   The semiconductor memory device according to claim 1, wherein the semiconductor layer includes a well region of a first conductivity type, the diffusion region is located in the well region, and is of a second conductivity type.   The charge retention film having a function of locally accumulating charge is at least partially in order from the first insulating film, the insulator having the charge accumulation function, and the second insulating film in order from the semiconductor layer side. The semiconductor memory device according to claim 1, having a structure as follows.   4. The semiconductor memory device according to claim 3, wherein the first insulating film has different film thicknesses immediately below the gate electrode and from the end of the gate electrode to the diffusion region side.   5. The semiconductor memory device according to claim 4, wherein the first insulating film has a film thickness that is thinner on the diffusion region side from an end of the gate electrode than immediately below the gate electrode.   4. The semiconductor memory device according to claim 3, wherein the first insulating film has mutually different band gaps immediately below the gate electrode and from the end of the gate electrode to the diffusion region side.   The semiconductor memory device according to claim 6, wherein the first insulating film has a smaller band gap on the diffusion region side from an end portion of the gate electrode than directly below the gate electrode.   A charge holding film having a function of locally accumulating charges, a charge holding film having a function of locally accumulating a first charge located immediately below the gate electrode, and an end of the gate electrode; 2. The semiconductor memory device according to claim 1, comprising a charge holding film having a function of locally accumulating the second charge extending toward the diffusion region.   The semiconductor memory device according to claim 1, wherein the gate electrode, the diffusion region, or the gate electrode and the diffusion region have a refractory metal compound film on at least a part of their upper surfaces.   2. The semiconductor memory device according to claim 1, wherein an end portion of the gate electrode of the diffusion region overlaps with a charge retention film having a function of locally accumulating charges with a width larger than 0 nm. A method of manufacturing a semiconductor memory device according to claim 1,
Forming a charge holding film having a function of locally accumulating the charge; depositing a conductor film on the charge holding film having a function of locally accumulating the charge; lithography and etching; Forming the gate electrode by processing the conductor film by:
Forming a sidewall spacer made of an insulator on a side surface of the gate electrode;
And a step of forming the diffusion region by performing impurity implantation and annealing.   The method of manufacturing a semiconductor memory device according to claim 11, wherein the sidewall spacer is formed by thermal oxidation of a surface of the gate electrode. The sidewall spacer is
Depositing a charge retention film having a function of locally accumulating the charge and a sidewall spacer forming material film covering the gate electrode;
The method of manufacturing a semiconductor memory device according to claim 11, wherein the method is formed by performing a process of etching back the material film by an anisotropic etching method. A method for manufacturing a semiconductor memory device according to claim 8, comprising:
Forming a charge retention film forming material film having a function of locally accumulating the first charge; depositing a conductor film on the first material film; and lithography and etching. Forming a gate electrode by processing the conductor film;
Forming a charge retention film having a function of locally accumulating the first charge by removing the first material film other than directly under the gate electrode;
Forming a charge retention film forming material film having a function of locally accumulating the second charge so as to cover at least the side surface of the gate electrode;
Forming a charge retention film having a function of locally accumulating the second charge by etching back the second material film using an anisotropic etching method;
And a step of forming the diffusion region by performing impurity implantation and annealing. After the step of forming the diffusion region,
Depositing a refractory metal so as to cover at least part of the upper surface of the diffusion region;
Forming a refractory metal compound film by reacting the semiconductor on the surface of the diffusion region with the refractory metal by heat treatment;
The method for manufacturing a semiconductor memory device according to claim 11, further comprising a step of removing unreacted refractory metal. An operation method of the semiconductor memory device according to claim 1,
A charge having a function of locally accumulating the charge by applying a voltage so that the potential of the gate electrode and the potential of the diffusion region are opposite to each other with respect to the potential of the semiconductor layer. A method for operating a semiconductor memory device, wherein only a part of electric charges in a holding film is erased.

Images