JP2003188288A - Non-volatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and the manufacturing method of the same capable of realizing the improvement of a writing efficiency and an operational speed. <P>SOLUTION: An SiGe layer 10 is formed on a silicon substrate 9. A tunnel insulation film 3 is directly formed on the surface of the SiGe layer 10 and a floating gate 2 is formed on the tunnel insulation film 3. A gate insulation film 4 is formed on the floating gate 2. A control gate 1 is formed on the gate insulation film 4. A source region 7 and a drain region 8 are formed in the SiGe layer 10 and the silicon substrate 9 at positions pinching a channel region below the tunnel insulation film 3. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as a storage medium used in digital cameras, mobile phones, portable audio equipment and the like, demand for non-volatile semiconductor storage devices such as flash memories is rapidly expanding.

At present, these portable devices are made smaller and lighter,
The demand for higher functionality is becoming more and more strict, and accordingly, miniaturization, high integration, and low power supply voltage of nonvolatile semiconductor memory devices are also increasingly demanded.

In particular, lowering the power supply voltage of the non-volatile semiconductor memory device is indispensable from the viewpoint of reducing power consumption and improving reliability such as preventing element destruction. However, simply lowering the power supply voltage reduces the speed for writing to the nonvolatile semiconductor memory device, and is not desirable from the viewpoint of speeding up.

[0005]

As described above, in the nonvolatile semiconductor memory device, lowering the power supply voltage has a problem that the writing speed is lowered.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of simultaneously improving the writing speed even when the power supply voltage is lowered, and a manufacturing method thereof.

[0007]

To achieve the above object, the present invention provides a SiGe (silicon-germanium) layer, a source region and a drain region formed in the SiGe layer at a distance from each other, and the source. A tunnel insulating film formed directly on the surface of the SiGe layer between the region and the drain region, a charge storage region formed on the tunnel insulating film, and a control electrode formed on the charge storage region. Provided is a non-volatile semiconductor memory device characterized by being provided.

The present invention also provides a SiGe layer and the Si
A source region and a drain region formed separately in the Ge layer, an insulating film directly formed on the surface of the SiGe layer including the source region and the drain region, and a charge formed on the insulating film. A storage region and a control electrode formed on the charge storage region, wherein a portion of the insulating film formed on the drain region is a tunnel insulating film which is thinner than other portions. Provided is a non-volatile semiconductor memory device.

At this time, it is preferable that a gate insulating film is formed between the charge storage region and the control electrode.

The charge storage region may be made of silicon nitride.

The thickness of the SiGe layer is preferably at least the depth of the inversion layer.

The present invention also provides a SiGe on a semiconductor substrate.
A step of forming a layer, a step of oxidizing the surface of the SiGe layer to form an oxide film, and a step of removing the oxide film and then performing the S
forming a tunnel insulating film on the surface of the iGe layer, forming a charge storage region on the tunnel insulating film, forming a gate insulating film on the charge storage region, and controlling on the gate insulating film A step of forming an electrode, and a step of forming an insulating film so as to cover a laminated structure composed of the charge storage region, the gate insulating film and the control electrode,
And a step of forming a source region and a drain region in the SiGe layer by implanting an impurity using the laminated structure as a mask, and a method for manufacturing a non-volatile semiconductor memory device.

The present invention also provides a SiGe on a semiconductor substrate.
A step of forming a layer, a step of oxidizing the surface of the SiGe layer to form an oxide film, a step of separately forming a source region and a drain region in the SiGe layer, and removing an oxide film on the drain region. And forming a tunnel insulating film by oxidizing the surface of the drain region, forming a charge storage region on the tunnel insulating film, and forming a control electrode on the charge storage region. A method for manufacturing a nonvolatile semiconductor memory device is provided.

According to the present invention, the tunnel insulating film is formed directly on the surface of the SiGe layer, and the charges are injected from this SiGe layer into the charge storage region through the tunnel insulating film.

As shown in FIG. 1, the conduction band Ec of SiGe hardly changes from the conduction band Ec of Si, but the valence band Ev 'of SiGe shifts higher than the valence band Ev of Si.

In the present invention, the valence band E of the SiGe layer is
By utilizing the fact that v ′ is shifted, the number of electrons tunneling from the valence band of the SiGe layer to the charge storage region is increased by the amount that the band gap is narrowed, and the writing speed is improved.

Here, the tunnel insulating film refers to a film that allows charges such as electrons and holes to pass through the insulating film when an electric field is applied.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiments and can be variously devised and used.

(First Embodiment) FIG. 2 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a nonvolatile semiconductor memory device related to the above. Although the structure of one cell portion is shown here, this cell structure can be applied to various memory cell units of NAND type, NOR type, OR type, and AND type.

As shown in FIG. 2, in this nonvolatile semiconductor memory device, a SiGe layer 10 is formed on a p-type silicon substrate 9. The tunnel insulating film 3 is directly formed on the surface of the SiGe layer 10. Examples of the tunnel insulating film 3 include a silicon oxide film, but in addition, a silicon nitride film, a silicon oxynitride film, TiO ₂ , T
A high dielectric constant insulating film such as aO ₂ , HfO ₂ , Al ₂ O ₃ , and ZrO ₂ can be used.

A charge storage region 2 is formed on the tunnel insulating film 3. As the charge storage region 2, a conductive film such as a polycrystalline silicon layer or a metal film can be used.

A gate insulating film 4 is formed on the charge storage region 2. SiO ₂ as the gate insulating film 4
A film or the like can be used.

A control electrode 1 is formed on the gate insulating film 4. A conductive film such as a polycrystalline silicon layer or a metal film can be used as the control electrode 1.

The laminated structure composed of the charge storage region 2, the gate insulating film 4 and the control electrode 1 is covered with an insulating film 5 made of silicon oxide for coating. A side wall insulating film 6 made of silicon nitride is formed on the side surface of this laminated structure with an insulating film 5 interposed therebetween.

The SiGe layer 10 located below the charge storage region 2 and below the tunnel insulating film 3 is a channel region.
A source region 7 and a drain region 9 made of an n-type impurity diffusion layer are formed in the SiGe layer 10 and the silicon substrate 9 so as to sandwich the channel region.

In order to write data in this nonvolatile semiconductor memory device, a gate voltage is applied to the control electrode 1 so that charges are accumulated from the SiGe layer 10 to the charge accumulation region 2 through the tunnel insulating film 3. Done by. Reading can be performed by changing the threshold value of the current flowing between the source region 7 and the drain region 8 depending on whether the charge is stored in the charge storage region 2 or not.

This non-volatile semiconductor memory device is characterized in that the SiGe layer 10 is formed on the silicon substrate 9.

As shown in FIG. 3, in SiGe, the conduction band Ec is the same as that of silicon, and the valence band Ev 'is shifted upward from the valence band Ev of silicon, so that the band gap is narrower than that of silicon. . Therefore, when a high electric field is applied to the control electrode 1, the SiGe layer 1
Electrons existing in an energy width Ev′-Ev in which the valence band Ev ′ of 0 is shifted upward are FN (Fowler
Since the electrons are injected into the charge storage region 2 by the −Nordheim) tunnel, the number of electrons injected from the SiGe layer 10 is significantly larger than the number of electrons injected from silicon. Intuitively, this is FN from within the band gap.
It can be understood that the number of electrons contributing to the FN tunnel increases because the band gap becomes narrow because there are no electrons contributing to the tunnel.

FIG. 4 shows the result of calculation of the relationship between the gate current and the gate voltage for the structure shown in FIG. 2 by simulation.

Specifically, the composition of the SiGe layer 10 is changed to Si.
_The thickness was _0.7 Ge _0.3 and the thickness was 10 nm. Also,
The impurities of the silicon substrate 9 were set to 5 × 10 ¹⁷ cm ⁻³ . The depth of the source region 7 and the drain region 8 is 0.1 μm.
m. The tunnel insulating film 3 is made of SiO ₂ and has a thickness of 9
nm. The width of the charge storage region 2 was 0.2 μm.
In this simulation, the gate voltage is applied directly to the charge storage region 2 for the sake of simplicity.

The curve indicated by the solid line in FIG. 4 is the Si _0.7 Ge
_It is a simulation result when there is a _0.3 layer 10, the curve shown by a broken line is Si _0.7 Ge _0.3 for comparison.
This is shown as a simulation result when the tunnel insulating film 10 is formed directly on the silicon substrate 9 without the layer 10.

It can be seen from FIG. 4 that the gate current in the case with the SiGe layer 10 (solid line) is larger than that in the case without the SiGe layer 10 (broken line) at the same gate voltage. Especially when the gate voltage is 19V, SiGe
With layer 10, the gate current is about 0.98 x 10
⁻⁶ A and gate current without SiGe layer 10 0.8
It can be seen that it is improved by about 23% as compared with × 10 ⁻⁶ A.

As described above, since the gate current by the FN tunnel injected from the SiGe layer 10 is larger than the current injected from silicon, the writing speed is improved. In addition, the increase in the gate current can maintain a sufficient writing speed even at a lower gate voltage, and is therefore excellent from the viewpoint of improving the reliability of preventing the dielectric breakdown of the tunnel insulating film 10. I know that

(Embodiment 2) Next, referring to FIG.
A method of manufacturing the nonvolatile semiconductor memory device shown in will be described.

First, as shown in FIG. 5A, the SiGe layer 10 is formed on the p-type silicon substrate 9. Examples of the method for forming the SiGe layer 10 include a method such as a selective epitaxial growth method, a chemical vapor deposition method, or a molecular beam epitaxial method. When using the chemical vapor deposition method, SiH is used as the silicon source gas.
₄ gas, SiH ₂ Cl ₂ gas, SiCl ₄ gas, or the like can be used. Further, as the germanium source gas, for example, GeH ₄ gas can be used. Of course, a gas other than these gases may be used.

In order to increase the gate current sufficiently,
The thickness of the SiGe layer 10 needs to be equal to or greater than the depth of the inversion layer. The depth of the inversion layer varies depending on the amount of impurities in the SiGe layer 10 and the charge storage region 2, but if it is 1 nm or more, it has an effect of increasing the gate current.

Next, as shown in FIG. 5B, SiGe
An insulating film 11 is formed on the layer 10. As the insulating film 11, for example, silicon oxide may be used. Next, impurities are introduced into the SiGe layer 10 by ion implantation through the insulating film 11. At this time, the amount of impurities in the inversion layer is SiG.
The thickness of the e-layer 10 should not be exceeded.

Next, as shown in FIG. 5C, the insulating film 1
1 is removed by etching.

Next, as shown in FIG. 5D, SiGe
The surface of the layer 10 is oxidized to form the insulating film 12. By forming this insulating film 12, dangling bonds and residual defects on the surface of the SiGe layer 10 can be reduced, and the tunnel insulating film described in the next step can be brought into a good state.

Next, as shown in FIG.
After removing the insulating film 12 shown in (d) by etching, the surface of the SiGe layer 10 is oxidized again to form the tunnel insulating film 3.

Next, as shown in FIG. 5F, the charge storage region 2, the gate insulating film 4, and the control electrode 1 are formed on the tunnel insulating film 3, and the gate laminated structure is processed by etching.

The tunnel insulating film 3 and the gate insulating film 4 are
For example, a silicon oxide film may be used. Further, the charge storage region 2 and the control electrode 1 can be formed by, for example, a method of vapor-phase growing polycrystalline silicon. As a method of processing the gate laminated structure, patterning using a mask or shaping by selective growth may be performed.

Next, as shown in FIG. 5G, the surface of the gate laminated structure composed of the charge storage region 2, the gate insulating film 4 and the control electrode 1 is covered with the insulating film 5 composed of silicon oxide. Further, the gate laminated structure covered with the insulating film 5 is covered with the insulating film 6 made of silicon nitride. Next, by implanting ions through the insulating film 6 and the insulating film 5,
SiGe layer 10 positioned so as to sandwich the charge storage region 2
Then, a source region 7 and a drain region 8 which are n-type impurity diffusion regions are formed. At this time, the source region 7 and the drain region 8 are formed so as to reach the silicon substrate 9, but may be up to the SiGe layer 10. The ion implantation may be performed at the stage when the insulating film 5 is formed.

Next, as shown in FIG. 5H, the insulating film 6
By etching the insulating film 5 and the insulating film 5, the nonvolatile semiconductor memory device shown in FIG. 2 can be formed. (Third Embodiment) Next, another method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 2 will be described with reference to FIG.

First, as shown in FIG. 6A, the SiGe layer 10 is formed on the p-type silicon substrate 9. Examples of the method for forming the SiGe layer 10 include a method such as a selective epitaxial growth method, a chemical vapor deposition method, or a molecular beam epitaxial method. When using the chemical vapor deposition method, SiH is used as the silicon source gas.
₄ gas, SiH ₂ Cl ₂ gas, SiCl ₄ gas, or the like can be used. Further, as the germanium source gas, for example, GeH ₄ gas can be used. Of course, a gas other than these gases may be used.

In order to increase the gate current sufficiently,
The thickness of the SiGe layer 10 needs to be equal to or greater than the depth of the inversion layer. The depth of the inversion layer varies depending on the amount of impurities in the SiGe layer 10 and the charge storage region 2, but if it is 1 nm or more, it has an effect of increasing the gate current.

Next, as shown in FIG. 6B, SiGe
An insulating film 11 is formed on the layer 10. As the insulating film 11, for example, silicon oxide may be used. Next, impurities are introduced into the SiGe layer 10 by ion implantation through the insulating film 11. At this time, the amount of impurities in the inversion layer is SiG.
The thickness of the e-layer 10 should not be exceeded.

Next, as shown in FIG. 6C, the insulating film 1
1 is removed by etching.

Next, as shown in FIG. 6D, SiGe
The tunnel insulating film 3 is formed on the layer 10 by depositing an insulating film. The tunnel insulating film 3 is made of, for example, C
VD (Chemical Vapor Deposition)
ion) method. in this case,
As the tunnel insulating film 3, for example, silicon oxide may be used, or TiO ₂ , TaO ₂ , HfO ₂ , Al may be used.
_A high dielectric constant gate insulating film such as ₂ O ₃ or ZrO ₂ may be used.

Next, as shown in FIG. 6E, the charge storage region 2, the gate insulating film 4, and the control electrode 1 are formed on the tunnel insulating film 3, and the gate laminated structure is processed by etching. As the gate insulating film 4, for example, a silicon oxide film may be used. Further, the charge storage region 2 and the control electrode 1 are
For example, it can be formed by a method of vapor-depositing polycrystalline silicon. As a method of processing the gate laminated structure, patterning using a mask or shaping by selective growth may be performed.

Next, as shown in FIG. 6F, the surface of the gate laminated structure composed of the charge storage region 2, the gate insulating film 4 and the control electrode 1 is covered with the insulating film 5 composed of silicon oxide. Further, the gate laminated structure covered with the insulating film 5 is covered with the insulating film 6 made of silicon nitride. Next, by implanting ions through the insulating film 6 and the insulating film 5,
SiGe layer 10 positioned so as to sandwich the charge storage region 2
Then, a source region 7 and a drain region 8 which are n-type impurity diffusion regions are formed. At this time, the source region 7 and the drain region 8 are formed so as to reach the silicon substrate 9, but may be up to the SiGe layer 10. The ion implantation may be performed at the stage when the insulating film 5 is formed.

Next, as shown in FIG. 6G, the insulating film 6
By etching the insulating film 5 and the insulating film 5, the nonvolatile semiconductor memory device shown in FIG. 2 can be formed.

In the present embodiment, the tunnel insulating film 3 is CV
It is directly formed on the surface of the SiGe layer 10 by the D method. In this way, the surface of the SiGe layer 10 described in the second embodiment can be temporarily oxidized to omit the oxidation step of reducing dangling bonds and residual defects.

(Embodiment 4) FIG. 7 is a sectional view showing another element structure according to the nonvolatile semiconductor memory device of the present invention.
Here, the structure of the cell portion is shown, but this cell structure is N
It can be applied to an AND type memory cell unit.

As shown in FIG. 7, this nonvolatile semiconductor memory device has a SiGe layer 10 on a p-type silicon substrate 9.
Are formed. A source region 18 and a drain region 19 which are n-type impurity diffusion regions are formed in the SiGe layer 10. Insulating films 14 and 13 are formed on the SiGe layer 10. In particular, the insulating film 13 formed on the drain region 19 is thinner than the insulating film 14 because it is used as a tunnel insulating film. The insulating films 13 and 14 are formed of a silicon oxide film or the like.

A charge storage region 15 is formed on the insulating films 13 and 14. The charge storage region 15 can be formed of a conductive film such as a polycrystalline silicon layer or a metal film, or an insulating film such as a silicon nitride film having a trap level capable of storing charges.

The gate insulating film 1 is formed on the charge storage region 15.
7 are formed. The gate insulating film 17 is formed of, for example, a silicon oxide film.

A control electrode 16 is formed on the gate insulating film 15. The control electrode 16 is formed of a conductive film such as a polycrystalline silicon layer or a metal film.

In FIG. 7, reference numeral 20 is an element isolation region made of a silicon oxide film.

The non-volatile semiconductor memory device having such a structure has a Floating-gate (Floating-gate tu) structure.
nnel oxide).

As shown in FIG. 7, this float is
A region having a thin tunnel insulating film 13 is provided on the drain, and in this portion, electrons are injected from the drain region 19 into the charge storage region 15 by the FN tunnel for writing. In addition, from the charge accumulation region 15 to the drain region 1
It is erased when the electrons escape to 9 through the FN tunnel.

Specifically, when a positive voltage is applied to the control electrode 16 to set the drain voltage to 0 V, the charge storage region 15 has a positive potential due to capacitive coupling, so that electrons are transferred from the drain region 19 to the charge storage region 15. Is injected. On the contrary, when the drain positive voltage is applied and the control electrode 16 is set to 0V, electrons escape from the charge storage region 15 to the drain region 19.

In this structure as well, similar to the nonvolatile semiconductor memory device shown in FIG. 2, SiG is formed on the silicon substrate 9.
Since the e-layer 10 is formed, the amount of current injected from the drain region 19 made of SiGe is larger than that of silicon.

As described above, also in the Flotox type nonvolatile semiconductor memory device, the writing speed can be improved and the gate voltage can be reduced as in the first embodiment.

(Fifth Embodiment) Next, referring to FIG.
A method of manufacturing the float type nonvolatile semiconductor memory device shown in FIG.

First, as shown in FIG. 8A, the SiGe layer 10 is formed on the p-type silicon substrate 9. Examples of the method for forming the SiGe layer 10 include a method such as a selective epitaxial growth method, a chemical vapor deposition method, or a molecular beam epitaxial method. When using the chemical vapor deposition method, SiH is used as the silicon source gas.
₄ gas, SiH ₂ Cl ₂ gas, SiCl ₄ gas, or the like can be used. Further, as the germanium source gas, for example, GeH ₄ gas can be used. Of course, a gas other than these gases may be used.

In order to increase the gate current sufficiently,
The thickness of the SiGe layer 10 needs to be equal to or greater than the depth of the inversion layer. The depth of the inversion layer varies depending on the amount of impurities in the SiGe layer 10 and the charge storage region 2, but if it is 1 nm or more, it has an effect of increasing the gate current.

Next, the insulating film 21 is formed on the SiGe layer 10. As the insulating film 21, for example, silicon oxide may be used. Examples of the forming method include a method of oxidizing the surface of the SiGe layer 10 and a method of depositing a silicon oxide film.

Next, a silicon nitride film 22 is formed on the insulating film 21 by depositing and patterning.

Next, as shown in FIG. 8B, the element isolation region 20 is formed by oxidizing the substrate to thicken the oxide film in the region where the silicon nitride film 22 is not formed.

Next, as shown in FIG. 8C, the silicon nitride layer 22 is removed by etching, and impurities are introduced into the SiGe layer 10 by ion implantation through the insulating film 21. Further, impurities are introduced by using a mask to form the source region 18 and the drain region 19.

Next, as shown in FIG. 8D, the insulating film on the drain region 19 is removed by etching by mask patterning, and the other insulating film 14 is left.

Next, as shown in FIG. 8E, the tunnel insulating film 13 thinner than the insulating film 14 is formed on the drain region 19.
To form. The tunnel insulating film 13 is the SiGe layer 1
It may be formed by direct oxidation of the 0 surface or may be formed by depositing a silicon oxide film.

However, when the tunnel insulating film 13 is formed by the direct oxidation of the surface of the SiGe layer 10, the step of oxidizing the surface of the SiGe layer 10 and removing the formed oxide film by etching is performed before the direct oxidation. In addition, it is necessary to remove residual defects and dangling bonds existing on the surface of the SiGe layer 10.

Next, as shown in FIG. 8F, the charge storage region 15, the gate insulating film 17 and the control electrode 16 are formed. As the charge storage region 15, a conductive film such as a polycrystalline silicon layer or a metal film, or an insulating film having a trap level capable of storing charges such as a silicon nitride film can be used. A silicon oxide film or the like can be used as the gate insulating film 17. Moreover, as the control electrode 16, a conductive film such as polycrystalline silicon or a metal film can be used.

Next, as shown in FIG. 8G, the insulating film 14, the charge storage region 15, the gate insulating film 17, and the control electrode 16 are etched by mask patterning, and the nonvolatile semiconductor shown in FIG. A storage device can be formed.

(Sixth Embodiment) FIGS. 9A and 9B are sectional views showing another element structure of a nonvolatile semiconductor memory device according to the present invention. Although the structure of the cell portion is shown here, this cell structure can be applied to various memory cell units of NAND type, NOR type, OR type, and AND type.

As shown in FIG. 9A, this non-volatile semiconductor memory device has SiGe on a p-type silicon substrate 9.
The layer 10 is formed. The tunnel insulating film 3 made of silicon oxide is formed on the SiGe layer 10.
A charge storage region 23 made of silicon nitride is formed on the tunnel insulating film 3. A gate insulating film 24 made of silicon oxide is formed on the charge storage region 23 made of silicon nitride. On the gate insulating film 24,
A control electrode 1 made of polycrystalline silicon is formed.

A channel region is formed in the SiGe layer 10 below the tunnel insulating film 3, and the SiG in the position sandwiching the channel region is formed.
In the e layer 10 and the silicon substrate 9, a source region 7 and a drain region 8 which are n-type impurity diffusion regions are formed.

In the nonvolatile semiconductor memory device shown in FIG. 9B, the control electrode 1 is further covered with a silicon oxide film 26 in the structure shown in FIG. 9A. In addition, the SiGe layer 1
An insulating film layer 25 made of silicon oxide is formed on the insulating film 0. Further, the laminated structure including the control electrode 1, the insulating film 24, and the insulating film 3 is covered with the interlayer insulating film 27. Further, the side wall insulating film 6 made of silicon nitride is formed on the side surface of the control electrode 1 with the interlayer insulating film 27 interposed therebetween.

The nonvolatile semiconductor memory device shown in FIGS. 9A and 9B has a MONOS (Metal-Oxide-Ni) structure.
It is called a "tride-oxide silicon" structure. In the nonvolatile semiconductor memory device having this structure, when electrons are injected into the silicon nitride film 23, the electrons can be trapped in the SiN trap level existing inside,
Writing is performed by using this as a charge storage region.

In the nonvolatile semiconductor memory device shown in FIGS. 9A and 9B, the SiGe layer 10 is formed on the silicon substrate 9 and the amount of gate current is the same as that of the first embodiment. Is increased, the writing speed is improved, and the gate voltage is reduced, so that reliability can be improved.

(Embodiment 7) Next, referring to FIG.
A method of manufacturing the semiconductor memory device shown in (a) will be described.

First, as shown in FIG. 10A, the SiGe layer 10 is formed on the p-type silicon substrate 9. SiGe
Examples of the method for forming the layer 10 include a method such as a selective epitaxial growth method, a chemical vapor deposition method, or a molecular beam epitaxial method. When the chemical vapor deposition method is used, Si is used as a silicon source gas.
H ₄ gas, SiH ₂ Cl ₂ gas, SiCl ₄ gas, or the like can be used. Further, as the germanium source gas, for example, GeH ₄ gas can be used. Of course, a gas other than these gases may be used.

In order to increase the gate current sufficiently,
The thickness of the SiGe layer 10 needs to be equal to or greater than the depth of the inversion layer. The depth of the inversion layer varies depending on the amount of impurities in the SiGe layer 10, but if it is 1 nm or more, it has the effect of increasing the gate current.

Next, as shown in FIG. 10B, SiG
The insulating film 11 is formed on the e layer 10. As the insulating film 11, for example, silicon oxide may be used. Next, impurities are introduced into the SiGe layer 10 by ion implantation through the insulating film 11.

Next, as shown in FIG. 10C, the insulating film 11 is removed by etching.

Next, as shown in FIG. 10D, SiG
The surface of the e layer 10 is oxidized to form the insulating film 12. By forming the insulating film 12, dangling bonds and residual defects on the surface of the SiGe layer 10 can be reduced, and the surface of the SiGe layer 10 can be directly oxidized.

Then, as shown in FIG. 10E, the tunnel insulating film 3 is formed by removing the insulating film 12 by etching and then oxidizing the surface of the SiGe layer 10.

Next, as shown in FIG. 10F, the charge storage region 2 made of silicon nitride is formed on the tunnel insulating film 3.
3, the gate insulating film 24 and the control electrode 1 are formed respectively. For the tunnel insulating film 3 and the gate insulating film 24, for example, silicon oxide may be used. The charge storage region 23 made of silicon nitride may be formed by, for example, depositing by the CVD method. For the control electrode 1, for example, polycrystalline silicon may be used.

Next, the tunnel insulating film 3 and the charge storage region 2
3, a gate laminated structure including the gate insulating film 24 and the control electrode 1 is formed by etching. Further, this gate laminated structure may be shaped by using selective growth.

Next, as shown in FIG. 10G, by ion implantation, the source region 7 and the drain region 8 made of the n-type impurity diffusion regions are formed at the positions sandwiching the charge storage region 23 made of silicon nitride. Form. In this way, the nonvolatile semiconductor memory device shown in FIG. 9A can be formed.

In the structure shown in FIG. 10G, insulating films 26 and 25 made of silicon oxide are formed on the surfaces of the control electrode 1, the source region 7 and the drain region 8.
Control electrode 1 each covered with an insulating film 26
The laminated structure composed of the silicon nitride film 23 and the silicon nitride film 23 is covered with the interlayer insulating film 27 and then further covered with the silicon nitride film 6 to obtain the structure shown in FIG. 9B.

(Embodiment 8) Next, referring to FIG.
Another method of manufacturing the nonvolatile semiconductor memory device shown in (a) will be described.

As shown in FIG. 11A, the SiGe layer 10 is formed on the p-type silicon substrate 9. SiGe layer 10
Examples of the method for forming the film include a method such as a selective epitaxial growth method, a chemical vapor deposition method, or a molecular beam epitaxial method. When using the chemical vapor deposition method, SiH ₄ is used as the silicon source gas.
Gas, SiH ₂ Cl ₂ gas, SiCl ₄ gas, or the like can be used. Further, as the germanium source gas, for example, GeH ₄ gas can be used. Of course, a gas other than these gases may be used.

To increase the gate current sufficiently,
The thickness of the SiGe layer 10 needs to be equal to or greater than the depth of the inversion layer. The depth of the inversion layer varies depending on the amount of impurities in the SiGe layer 10 and the charge storage region 2, but if it is 1 nm or more, it has an effect of increasing the gate current.

Next, as shown in FIG. 11B, SiG
The insulating film 11 is formed on the e layer 10. As the insulating film 11, for example, silicon oxide may be used. Next, impurities are introduced into the SiGe layer 10 by ion implantation through the insulating film 11.

Next, as shown in FIG. 11C, the insulating film 11 is removed by etching.

Next, as shown in FIG. 11D, SiG
The tunnel insulating film 3 is deposited on the surface of the e layer 10. The tunnel insulating film 3 may be deposited by using, for example, the CVD method. In this case, the tunnel insulating film 3 may be, for example, silicon oxide, or TiO ₂ , Ta.
A high dielectric constant gate insulating film such as O ₂ , HfO ₂ , Al ₂ O ₃ , and ZrO ₂ may be used.

Next, as shown in FIG. 11E, the charge storage region 2 made of silicon nitride is formed on the tunnel insulating film 3.
3, the gate insulating film 24 and the control electrode 1 are formed, and the gate laminated structure is shaped by etching. Tunnel insulating film 3
The gate insulating film 4 may be made of silicon oxide, for example. The charge storage region 23 made of silicon nitride may be formed by, for example, depositing by the CVD method.
For the control electrode 1, for example, polycrystalline silicon may be used.
In addition, the gate stacked structure may be shaped by using selective growth.

Next, as shown in FIG. 11F, by ion implantation, the source region 7 and the drain region 8 made of the n-type impurity diffusion regions are formed at the positions sandwiching the charge storage region 23 made of silicon nitride. Form. In this way, the nonvolatile semiconductor memory device shown in FIG. 9A can be formed.

In the structure shown in FIG. 11F, the surfaces of the control electrode 1, the source region 7 and the drain region 8 are covered with insulating films 26 and 25 made of silicon oxide.
Control electrode 1 each covered with an insulating film 26
The laminated structure composed of the silicon nitride film 23 and the silicon nitride film 23 is covered with the interlayer insulating film 27 and then further covered with the silicon nitride film 6 to obtain the structure shown in FIG. 9B.

[0103]

The present invention has been made in consideration of the above circumstances, and can provide a non-volatile semiconductor memory device and its manufacturing method capable of simultaneously improving the writing speed even when the power supply voltage is lowered.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a conduction band and a valence band of silicon and SiGe.

FIG. 2 is a sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing the effect of the present invention, SiGe
The figure which showed a mode that an electron passes through from a layer by an FN tunnel.

FIG. 4 is a diagram showing a relationship between a gate voltage and a gate current showing a simulation result of an FN tunnel current.

5A and 5B are cross-sectional views for explaining main processes of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

6A and 6B are cross-sectional views for explaining main steps of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 7 is a sectional view of a nonvolatile semiconductor memory device according to Embodiment 4 of the present invention.

FIG. 8 is a cross-sectional view for explaining main processes of the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 9 is a sectional view of a nonvolatile semiconductor memory device according to Embodiment 6 of the present invention.

FIG. 10 is a cross-sectional view for explaining main processes of the nonvolatile semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining main processes of the nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

[Explanation of symbols]

1, 16 ... Control electrodes 2, 15 ... Charge storage area 3, 13 ... Tunnel insulating film 4, 24, 17 ... Gate insulating film 5, 14, 25, 26 ... Insulating film 6 ... Sidewall insulating film 7, 18 ... Source area 8, 19 ... Drain region 9 ... Silicon substrate 10 ... SiGe layer 20: Element isolation region 23 ... Silicon nitride film 27 ... Interlayer insulating film

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 EP02 EP18 EP23 EP48 EP76                       EP77 EP79 ER03 ER05 ER15                       ER22 HA07 JA06 PR21 PR25                 5F101 BA24 BA26 BA34 BA35 BA45                       BB02 BB05 BC02 BD02 BD34                       BD39 BE05 BE07 BH11 BH12

Claims (7)

[Claims] 1. A SiGe layer, a source region and a drain region formed separately in the SiGe layer, and the SiGe between the source region and the drain region.
A nonvolatile insulating film, comprising: a tunnel insulating film formed directly on the surface of the layer; a charge storage region formed on the tunnel insulating film; and a control electrode formed on the charge storage region. Semiconductor memory device. 2. A SiGe layer, a source region and a drain region formed separately in the SiGe layer, and the SiG including the source region and the drain region.
an insulating film formed directly on the surface of the e layer; a charge storage region formed on the insulating film; and a control electrode formed on the charge storage region, wherein the drain of the insulating film is provided. A non-volatile semiconductor memory device, wherein a portion formed on the region is a tunnel insulating film thinner than other portions. 3. A gate insulating film is formed between the charge storage region and the control electrode.
Alternatively, the nonvolatile semiconductor memory device according to claim 2. 4. The non-volatile semiconductor memory device according to claim 1, wherein the charge storage region is formed of silicon nitride. 5. The non-volatile semiconductor memory device according to claim 1, wherein the thickness of the SiGe layer is at least equal to or greater than the depth of the inversion layer. 6. A step of forming a SiGe layer on a semiconductor substrate, a step of oxidizing the surface of the SiGe layer to form an oxide film, and a step of removing the oxide film and then forming a tunnel insulating film on the surface of the SiGe layer. A step of forming a charge storage region on the tunnel insulating film, a step of forming a gate insulating film on the charge storage region, a step of forming a control electrode on the gate insulating film, A step of forming an insulating film so as to cover a laminated structure composed of a storage region, the gate insulating film and the control electrode; and a source region and a drain in the SiGe layer by implanting impurities using the laminated structure as a mask. A method of manufacturing a nonvolatile semiconductor memory device, comprising the step of forming a region. 7. A step of forming a SiGe layer on a semiconductor substrate, a step of oxidizing the surface of the SiGe layer to form an oxide film, and a step of separately forming a source region and a drain region in the SiGe layer. Removing the oxide film on the drain region, oxidizing the surface of the drain region to form a tunnel insulating film, forming a charge storage region on the tunnel insulating film, and forming a charge storage region on the charge storage region. And a step of forming a control electrode on the substrate.