JP5351274B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  Memory cells and transistors used in NAND flash memories are becoming more and more miniaturized with generations. However, since the thinning of the insulating film is delayed with the progress of miniaturization of the transistor gate length, there is a problem in the characteristics when data is written / erased and read using the miniaturized memory cell / transistor. Occurs.

  That is, there is a reciprocal relationship between the short channel effect at the time of reading the memory cell transistor and the erroneous writing of the unselected memory cell at the time of writing to the NAND string. Here, the “short channel effect” means that when the gate length of the MIS transistor becomes small, the gate electrode cannot control the channel region, and clear ON / OFF characteristics of the transistor cannot be obtained. In order to suppress the short channel effect, it is necessary to increase the substrate impurity concentration of the transistor. However, increasing the substrate impurity concentration makes it difficult to increase the channel potential in the non-selected memory cell at the time of writing. In that case, a large electric field is applied to the insulating film of the non-selected cell, and erroneous writing is likely to occur.

  On the other hand, when the substrate impurity concentration of the transistor is reduced, erroneous writing is reduced, but the short channel effect is noticeable at the time of reading. As described above, there is a conflicting relationship that it is impossible to achieve both short channel effect suppression and erroneous write suppression, which becomes more serious as the gate length becomes finer.

  In particular, the present invention relates to a MONOS type memory cell that uses an insulating film (silicon nitride film) as a charge storage layer. However, when writing / erasing is repeated in the MONOS memory, a defect occurs at the substrate interface on the side where charge injection is performed. There is a problem that the Id-Vg characteristic (transfer characteristic) of the cell transistor deteriorates. Here, the charge storage layer is generally a conductive layer such as a floating gate electrode, a discrete conductive layer such as a nanodot memory, or silicon in MONOS (metal-oxide-nitride-oxide-silicon). It refers to an insulating film layer including a trap such as a nitride film.

  As a known technique, in order to avoid this deterioration, a p-channel MONOS transistor is formed, carriers are injected from the gate electrode side, and writing / erasing is performed, and the channel on the opposite substrate side interface is used. There is a method of reading data.

  In the invention described in Patent Document 1, the region where charge injection and data reading are performed are different, but the gate electrode for performing charge injection is formed of polycrystalline silicon or metal having a high dopant impurity concentration. That is, a transistor having a channel region on the gate side is not formed. Therefore, by controlling the charge supply by the select gate transistor, an inversion layer is formed on the gate side at the time of data reading, but a depletion layer is formed on the gate side in the non-selected cell at the time of writing (no inversion layer is formed), etc. It is impossible to control the depletion layer on the gate side. Therefore, in the invention described in Patent Document 1, the depletion layer that exists only on the substrate side is the extension of the depletion layer in the non-selected cell at the time of writing and the suppression of the short channel effect due to the reduction of the width of the depletion layer at the time of reading. There is a drawback of having to take on two roles. This contradiction becomes more and more apparent with the miniaturization of memory cells.

US Patent Application Publication No. 2007/0029625

  Accordingly, an object of the present invention is to realize both suppression of a short channel effect and prevention of erroneous writing in a memory cell, and furthermore, in a MONOS type memory cell, characteristic deterioration due to interface defects can be avoided. A non-volatile semiconductor memory device is provided.

The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device configured by arranging a plurality of nonvolatile memory cells, and the nonvolatile memory cells are formed separately from the first semiconductor layer. A first source / drain region; a first channel region formed between the first source region and the first drain region; the first source region and the first drain region; A block insulating film formed on the first semiconductor layer, a charge storage layer formed on the block insulating film, a tunnel insulating film formed on the charge storage layer, and the tunnel A second channel region formed in a second semiconductor layer formed on the insulating film;
A second source / drain region formed in the second semiconductor layer so as to face each other with the second channel region interposed therebetween, and the dopant impurity concentration of the first channel region is The dopant impurity concentration in the second channel region is higher than the second channel region.

  Note that the tunnel insulating film is an insulating film that is introduced for the purpose of passing charges by applying a high electric field and guiding charges to the charge storage layer. The block insulating film is an insulating film introduced for the purpose of interrupting a current that attempts to pass through the memory cell, and means an insulating film in which current does not flow more easily than a tunnel insulating film in a high electric field region. Usually, the block insulating film has a larger capacity than the tunnel insulating film. This is because if the capacity of the block insulating film is increased, the ratio of the voltage applied to the tunnel insulating film is increased. In order to make the capacity of the block insulating film larger than that of the tunnel insulating film, methods such as (1) increasing the area, (2) increasing the dielectric constant, and (3) reducing the film thickness are employed.

  According to the present invention, it is possible to realize a memory cell which can suppress erroneous writing of unselected memory cells and can simultaneously read data with a short channel effect suppressed. Further, in the MONOS type memory cell, it is possible to prevent the occurrence of defects during writing / erasing from affecting the data reading.

1 is a diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. Diagram showing the basic principle of a conventional memory cell The figure of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. FIG. 5 is a diagram showing a NAND memory cell unit according to a second embodiment of the present invention. The figure of the memory cell array concerning a 2nd embodiment of the present invention. The figure of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. The figure which shows the modification of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. The figure which shows the non-volatile semiconductor memory device which concerns on the 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings to be described below, the same reference numerals indicate the same parts, and duplicate descriptions are omitted.

(First embodiment)
FIG. 1 is a schematic diagram of a memory cell according to the present invention. The nonvolatile semiconductor memory device is composed of a plurality of nonvolatile memory cells.

  The memory cells constituting the nonvolatile semiconductor memory device of the present embodiment are formed on the semiconductor substrate 10, and the first source / drain regions 30 are formed separately in the semiconductor layer constituting the semiconductor substrate 10. A block insulating film 60 formed on the first channel region 20 existing between the first source / drain regions 30, a charge storage layer 50 formed on the block insulating film 60, and a charge storage A tunnel insulating film 40 formed on the layer 50, a second channel region 90 formed on the tunnel insulating film 40 and formed in the semiconductor layer 70, and a second channel formed in the semiconductor layer 70. A second source / drain region 80 sandwiching the region 90 is formed.

  Here, the channel region refers to a region where a channel can be formed in a state where a potential is applied. As described in the prior art, the charge storage layer is generally a conductive layer such as a floating gate electrode, a discrete conductive layer such as a nanodot memory, or a MONOS (metal-oxide-nitride). This means an insulating film layer including a trap such as a silicon nitride film in (-oxide-silicon). As described in the prior art, the block insulating film is also an insulating film that is introduced for the purpose of blocking the current passing through the memory cell, and the insulating film is less likely to flow current than the tunnel insulating film in a high electric field region. Say that. Usually, the block insulating film has a larger capacity than the tunnel insulating film. This is because if the capacity of the block insulating film is increased, the ratio of the voltage applied to the tunnel insulating film is increased. In order to make the capacity of the block insulating film larger than that of the tunnel insulating film, methods such as (1) increasing the area, (2) increasing the dielectric constant, and (3) reducing the film thickness are employed.

  The semiconductor substrate 10 and the semiconductor layer 70 are generally single crystal Si, but other examples include polycrystalline Si, amorphous Si, Ge, compound semiconductors, SOI (Silicon On Insulator), and organic polymers.

  As the tunnel insulating film 40, a single layer film or a laminated film containing an oxide of Si is generally used. Further, in order to improve the performance and reliability of the tunnel insulating film, nitrogen may be added to the film.

The charge storage layer 50 is generally made of silicon nitride (Si ₃ N ₄ ), but in addition, silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON) ), Hafnia (HfO ₂ ), hafnium aluminate (HfAlO ₃ ), nitrided hafnia (HfON), nitrided hafnium aluminate (HfAlON), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), lanthanum oxide ( La ₂ O ₃ ) and lanthanum aluminate (LaAlO ₃ ) can be used.

The block insulating film 60 includes silicon oxide SiO ₂ , aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), hafnia (HfO ₂ ), hafnium-aluminate (HfAlO ₃ ), hafnia nitride (HfON), and hafnium nitride. Aluminate (HfAlON), hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO ₃ ), and the like can be used.

  In FIG. 1, the tunnel insulating film 40 is arranged on the gate side and carriers are injected from the gate side (in the direction of the arrow 100), but the tunnel insulating film 40 is arranged on the semiconductor substrate 10 side upside down. However, a configuration in which carrier injection is performed from the semiconductor substrate 10 side is also possible, and an essential part of the concept of the present embodiment is not changed.

  That is, in the present embodiment, the tunnel insulating film 40 is disposed on the gate side and the block insulating film 60 is disposed on the substrate side. Conversely, the tunnel insulating film 40 is disposed on the substrate side and the block insulating film 60 is disposed on the gate side. A configuration arranged in the above is also possible.

  Next, the operation principle of this embodiment will be described.

  FIG. 2 is a diagram showing the basic principle of a conventional memory cell.

  FIG. 2 schematically shows the structure of a conventional memory cell and its operation. The memory cell performs writing / erasing by injecting charge from the first channel region 20 on the semiconductor substrate 10 side (in the direction of arrow 110), and data is written using the first channel region 20 on the side where writing / erasing is performed. Is read out.

  In this case, as described in the background section, it is impossible to achieve both suppression of the short channel effect at the time of reading and suppression of erroneous writing in the non-selected memory cell at the time of writing. This is because the depletion layer of the first channel region 20 plays two contradictory roles. One of the roles is extension of a depletion layer in a non-selected cell at the time of writing. Another role is suppression of the depletion layer width at the time of data reading. In the conventional memory cell structure shown in FIG. 2, the smaller the memory cell is, the more inconsistent the two roles of the depletion layer of the first channel region 20 are. Therefore, it is difficult to miniaturize the memory cell with the conventional memory cell structure.

  In the present embodiment (FIG. 1) for solving such a problem, in order to eliminate the contradiction imposed on the depletion layer width (or dopant impurity concentration) of the channel region, a depletion layer is formed in a non-selected cell at the time of writing. The role of stretching and the role of suppressing the short channel effect by suppressing the width of the depletion layer at the time of data reading are arranged in different places.

  That is, as shown in FIG. 1, the present embodiment is characterized in that the two roles of the depletion layer are separated by providing the second channel region 90. Specifically, the dopant impurity concentration in the semiconductor region on the tunnel insulating film 40 side is decreased, and the dopant impurity concentration in the semiconductor region on the block insulating film 60 side is increased. Data reading is performed using the first channel region 20 of the transistor formed in the semiconductor region on the block insulating film 60 side.

  According to such a configuration of the present embodiment, the following effects can be obtained. First, the depletion layer can be extended in the non-selected memory cell at the time of writing by setting the dopant impurity concentration at the interface between the tunnel insulating film 40 on the side where the charge is injected at the time of writing and the semiconductor layer 70 to be low. As a result, the voltage applied to the tunnel insulating film 40 can be reduced to prevent erroneous writing. In the memory cell at the time of writing, since the suppression of the short channel effect is not required in either the selected cell or the non-selected cell, the dopant impurity concentration in the channel region can be set low.

  On the other hand, in the present embodiment, the dopant impurity on the surface of the semiconductor substrate 10 on the data reading side is increased to suppress the short channel effect of the transistor on the data reading side (block insulating film 60 side). Therefore, it is possible to read data without error.

  In addition, the following two effects can be obtained by reading data at the interface between the semiconductor substrate 10 and the block insulating film 60 on the side opposite to the side on which the charge injection is performed.

  The first effect is that it is possible to avoid the occurrence of a defect at the interface due to repeated writing / erasing and fluctuation of the threshold voltage. This is because, in the case of the structure of this embodiment, the interface between the semiconductor substrate 10 on the data reading side and the block insulating film 60 has almost no charge passing, so that the occurrence of defects can be suppressed. The second effect is that the “proximity effect” (inter-cell interference) can be suppressed in the MONOS type memory cell. This is because in the MONOS type memory cell, charges are trapped at the interface between the charge storage layer 50 and the block insulating film 60 close to the interface on the data reading side.

  In contrast, as shown in FIG. 2, in a normal MONOS type memory cell, the electrical relationship between the first channel region 20 for performing carrier injection and data reading and the interface between the charge storage layer 50 and the block insulating film 60 is shown. Since the distance is long, the interference effect between adjacent memory cells cannot be ignored.

  On the other hand, in the memory cell of this embodiment, as shown in FIG. 1, since data is read on the semiconductor surface (first channel region 20) opposite to the charge injection, the first channel region 20 and the charge storage layer are read. The electrical distance to the 50 / block insulating film 60 interface is reduced, and the interference effect between adjacent memory cells is reduced.

  Here, if the distance between the semiconductor layer 20 from which data is read and the charge storage layer 50 / block insulating film 60 interface where trapped charges exist is short, the interference effect between adjacent memory cells is reduced for the following reason. . If there is a trapped charge of the memory cell near the semiconductor layer 20, the rate at which electric lines of force extending from the charge are terminated at the semiconductor layer 20 increases, and the charge storage layer 50 (or charge storage layer 50 / It is difficult to terminate at the interface of the block insulating film 60). On the other hand, if there is a charge far from the semiconductor layer 20, the electric lines of force are difficult to reach the semiconductor layer 20 and are terminated at the charge storage layer 50 (or the charge storage layer 50 / block insulating film 60 interface) of the adjacent cell. The proportion increases. From the above, the interference effect between adjacent cells is smaller when the charge is present at a position close to the semiconductor layer 20.

  In the present embodiment, two roles of the depletion layer are separated by providing a second channel region 90 that performs charge injection and a first channel region 20 that performs data reading above and below the insulating film stack of the memory cell, respectively. There is a special feature. That is, the extension of the depletion layer in the non-selected cell at the time of writing corresponds to the second channel region 90, and the high dopant impurity concentration necessary for the transistor operation at the time of data reading corresponds to the first channel region 20. In this way, by separating the role of the depletion layer spatially, it is possible to eliminate contradictions in requirements for the depletion layer that becomes apparent as the transistor is miniaturized. Therefore, when the structure of this embodiment is used, it is possible to further promote the miniaturization of the memory cell.

(Second Embodiment)
FIG. 3 is a schematic view of a memory cell of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. In the present embodiment, the second channel region 90 is disposed in the semiconductor substrate 15. 3A is a cross-sectional view of the second channel region 90 along the channel length direction, and FIG. 3B is a cross-sectional view of the second channel region 90 along the channel width direction. In these figures, the channel length direction is the column direction in which the bit lines extend, and the channel width direction is the row in which the word lines (the first channel region 20 and the first source / drain region 30) extend. It is a direction.

On the surface portion of the p-type silicon substrate (semiconductor substrate 15), n ⁺ -type source / drain diffusion layers (second source / drain regions 80) are arranged apart from each other. A second channel region 90 is between the source diffusion layer and the drain diffusion layer. When the nonvolatile memory cell is turned on, a channel for electrically conducting the second source / drain region 80 is formed in the second channel region 90.

The second source / drain region 80 is usually composed of an n ⁺ type diffusion layer, but when a plurality of such memory cells are connected in series to constitute a NAND type memory cell unit, The n ⁺ -type diffusion layer is not necessarily formed in the second source / drain region 80.

This is because an inversion layer in which a fringe electric field from the gate of an adjacent memory cell induces on the surface of the semiconductor substrate 15 can be used as a source / drain electrode. In this case, the n ⁺ -type silicon diffusion layer is not formed in the second source / drain region 80, and the second source / drain region 80 may be a p-type semiconductor.

  When configuring a NAND type memory cell unit, for example, as shown in FIG. 4, a plurality of memory cells 105 are connected in series, and select gate transistors 301 and 303 are connected to both ends of this series connection part. A memory cell unit can be constructed. The plurality of memory cells 105 constitute a cell / transistor row 302. The selection gate transistors 301 and 303 preferably have a MOS (Metal Oxide Semiconductor) structure.

Next, the configuration of the gate stack disposed on the semiconductor substrate 15 will be described. A silicon oxynitride film (SiON) having a thickness of, for example, 5 nm is disposed on the second channel region 90 as the tunnel insulating film 40. The average composition of this silicon oxynitride film is, for example, (SiO ₂ ) _0.8 (Si ₃ N ₄ ) _0.2 . On the tunnel insulating film 40, a silicon nitride film (Si ₃ N ₄ ) having a thickness of 5 nm is disposed as the charge storage layer 50. On the charge storage layer 50, for example, an alumina (Al ₂ O ₃ ) film having a thickness of 15 nm is disposed as the block insulating film 60. On the block insulating film 60, an n-type semiconductor layer 75 to be the first channel region 20 is disposed. As can be seen from FIG. 3B, the p ⁺ -type first source / drain region 30 is disposed adjacent to the first channel region 20.

A plurality of tunnel insulating films 40 and charge storage layers 50 are formed in the row direction, and these are separated from each other by an element isolation insulating layer 120 having an STI (Shallow Trench Isolation) structure. The block insulating film 60 disposed on the charge storage layer 50 extends in the row direction. A plurality of first channel regions 20 and p ⁺ -type first source / drain regions 30 are arranged in the row direction, and these function as control gate electrodes (word lines), or Or function as transistors arranged in series.

  In this embodiment, the block insulating film 60 is extended in the word line direction. With such a structure, the escape of the electric field due to the fringe electric field in the word line direction is reduced, and the electric field from the first channel region 20 can be efficiently transmitted to the tunnel insulating film 40 even if the memory cell transistor is miniaturized. The advantage is obtained.

Here, the p-type dopant impurity concentration in the second channel region 90 of the semiconductor substrate 15 is set to 1 × 10 ¹⁸ cm ^{−3 in} this embodiment. In addition, the n-type dopant impurity concentration in the first channel region 20 functioning as the control gate electrode was set to 1 × 10 ¹⁹ cm ⁻³ .

As described above, the dopant impurity concentration in the first channel region 20 is higher than the dopant impurity concentration in the second channel region 90. The dopant impurity concentration in the first channel region 20 is preferably about one digit (about 5 to 50 times) higher than the dopant impurity concentration in the second channel region 90. This can be seen from simple CV characteristic calculations. When the combination of dopant impurity concentrations of this embodiment is used, the operating voltage can be set so as to obtain an effective electric field of 5 MV / cm in the non-selected memory cell and 15 MV / cm in the selected memory cell at the time of writing. . That is, the distinction between the write cell and the non-write cell can be clearly made. This is because the threshold electric field for writing of a normal tunnel insulating film (SiO ₂ ) is an effective electric field of about 7 MV / cm.

Note that the "effective electric field" is a value obtained by dividing the electric flux density in the dielectric constant of SiO _2, also referred to as "terms of SiO ₂ field".

  On the other hand, if the same calculation is performed for the case where the dopant impurity concentration in the first channel region 20 and the dopant impurity concentration in the second channel region 90 are different by about two digits, it can be seen that it is difficult to find an appropriate electric field condition. Therefore, it is appropriate that the dopant impurity concentration of the first channel region 20 is about one digit (about 5 to 50 times) higher than the dopant impurity concentration of the second channel region 90.

Note that the dopant impurity concentration of the first channel region 20 from which data is read out needs to be approximately 10 ¹⁷ to 10 ¹⁸ cm ⁻³ or more with reference to ITRS (International Technology Roadmap for Semiconductors). In addition, if the dopant impurity concentration of the first channel region 20 is extremely high and a degenerate semiconductor is formed, it is difficult to form a depletion layer. Therefore, the dopant impurity concentration of the first channel region 20 should be 10 ²⁰ cm ⁻³ or less. From the above, the desirable range of the dopant impurity concentration of the first channel region 20 is 10 ¹⁷ cm ⁻³ or more and 10 ²⁰ cm ⁻³ or less.

In addition, the thickness of the tunnel insulating film 40 used in this embodiment is desirably about 2 to 8 nm. In the present embodiment, a silicon oxynitride film is used as the tunnel insulating film 40. From the viewpoint of reducing defects in the film, the average composition of the silicon oxynitride film is (SiO ₂ ) _x (Si ₃ N ₄ ) _1-x . It is desirable that 0.75 <x <1. Of course, a silicon oxide film (SiO ₂ ) corresponding to the limit composition of x = 1 may be used for the tunnel insulating film 40. If a silicon oxynitride film is used as the tunnel insulating film 40, the potential barrier against holes is reduced, so that the effect of speeding up the erase operation of the memory cell can be obtained. Similarly, a laminated tunnel insulating film such as a silicon oxide film / silicon nitride film / silicon oxide film (ONO tunnel insulating film) may be used as the tunnel insulating film 40. In this case, the erasing operation is accelerated.

The thickness of the silicon nitride film as the charge storage layer 50 used in this embodiment is desirably about 2 to 10 nm. Further, this silicon nitride film does not necessarily need to be Si ₃ N ₄ having a stoichiometric composition, and may have a Si-rich composition in order to increase the trap density in the film, or deepen the trap level. Therefore, a nitrogen-rich composition may be used. Further, the silicon nitride film as the charge storage layer 50 may contain oxygen. Furthermore, the silicon nitride film does not necessarily have a uniform composition, and the composition may change in the film thickness direction.

  Further, the film thickness of alumina as the block insulating film 60 used in the present embodiment is desirably about 5 to 20 nm. Further, alumina as the block insulating film 60 may contain some nitrogen in the film in order to reduce defects in the film. Further, the block insulating film 60 is not necessarily composed of a single layer alumina film, and a laminated block insulating film such as an alumina film / silicon oxide film / alumina film (AOA film) may be used.

The first channel region 20 and the p ⁺ -type first source / drain region 30 adjacent to the first channel region 20 used in the present embodiment are formed of polycrystalline silicon, but may be formed of amorphous silicon or single crystal silicon. I do not care. A Schottky barrier source / drain in which the p ⁺ -type first source / drain region 30 is replaced with metal or silicide may be used. At that time, a method of increasing the Schottky barrier by segregating dopant impurities at the interface between the first channel region 20 and the p ⁺ -type first source / drain region 30 may be used.

  FIG. 5 is a schematic view of the memory array of this embodiment as viewed from above. A gate stack composed of the tunnel insulating film 40, the charge storage layer 50, and the block insulating film 60 exists at the intersection of the word line (WL) and the bit line (BL). As is clear from this structure, since the transistors are arranged above and below the gate stack, the functions of the word line (WL) and the bit line (BL) are symmetrical to each other and can be interchanged. That is, when data is read using the word line (WL), the word line (WL) functions as a bit line. Therefore, as a circuit configuration, it is necessary to connect a read circuit not only to the bit line side but also to the word line side.

  As a method of driving this memory cell, a write / erase operation is performed by injecting charges from the surface of the semiconductor substrate 15 into the silicon nitride film (charge storage layer 50) through the tunnel insulating film 40, and the first Data reading is performed with or without a channel current flowing through the channel region 20.

  Next, a method for manufacturing the memory cell of FIG. 3 will be described.

  7 to 13, (a) is a cross-sectional view taken along the channel length direction of the second channel region 90, and (b) is a cross-sectional view taken along the channel width direction of the second channel region 90.

  First, as shown in FIGS. 7A and 7B, after cleaning the surface of a silicon substrate doped with a p-type impurity (semiconductor substrate 15: including the case of a well in the substrate), 800 ° C. to 1000 ° C. A silicon oxide film having a thickness of about 5 nm is formed by a thermal oxidation method in a temperature range of 5 nm. Subsequently, the silicon oxide film is nitrided by using a plasma nitriding method to form a silicon oxynitride film as the tunnel insulating film 40.

Subsequently, charges are accumulated on the tunnel insulating film 40 by LPCVD (low pressure chemical vapor deposition) using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as source gases in a temperature range of 600 ° C. to 800 ° C. A silicon nitride film having a thickness of 5 nm is formed as the layer 50.

  Then, a mask material 130 for processing the element isolation region is formed on the silicon nitride film (charge storage layer 50). A photoresist is formed on the mask material 130, and the photoresist is exposed and developed. Then, the photoresist pattern is transferred to the mask material 130 by RIE (reactive ion etching). Thereafter, the photoresist is removed.

  In this state, using the mask material 130 as a mask, the charge storage layer 50 and the tunnel insulating film 40 are sequentially etched by the RIE method to form slits 140 that separate memory cells adjacent in the row direction. Further, the semiconductor substrate 15 is etched by RIE, and an element isolation trench 150 having a depth of about 100 nm is formed in the semiconductor substrate 15.

  Next, as shown in FIGS. 8A and 8B, a silicon oxide film (element isolation insulating film 120) that is a buried oxide film that completely fills the groove formed by the slit 140 and the element isolation trench 150 is formed by CVD. Form. Subsequently, the silicon oxide film (element isolation insulating film 120) is polished by CMP (Chemical Mechanical Polishing) until the mask material 130 is exposed, and the surface of the silicon oxide film (element isolation insulating film 120) is planarized.

  Next, the buried oxide film (element isolation insulating film 120) is etched back by wet etching. By this etch back, the height of the bottom surface of the mask material 130 is made to coincide with the height of the surface of the buried oxide film (element isolation insulating film 120). Subsequently, the mask material 130 is selectively removed.

Next, as shown in FIGS. 9A and 9B, ALD (atomic layer) using TMA (Al (CH ₃ ) ₃ ) and H ₂ O or O ₃ as raw materials in a temperature range of 200 ° C. to 400 ° C. An alumina film having a thickness of about 15 nm is formed as the block insulating film 60 by a deposition method. Subsequently, the semiconductor layer 75 (polycrystalline silicon) to be the first channel region 20 is formed on the block insulating film 60 by using a CVD method using silane SiH ₄ as a source gas in a temperature range of 550 ° C. to 650 ° C., for example. Or amorphous silicon).

  Next, as shown in FIGS. 10A and 10B, a mask material 130 is formed on the semiconductor layer 75 to be the first channel region 20. The mask material 130 is formed, for example, by depositing a silicon nitride film. A photoresist is formed on the mask material 130, and the photoresist is exposed and developed. Then, the photoresist pattern is transferred to the mask material 130 by the RIE method. Thereafter, the photoresist is removed. As a result, a line pattern of the mask material 130 extending in the column direction is formed.

Next, as shown in FIGS. 11A and 11B, a p-type dopant impurity (for example, boron) is implanted by ion implantation using the mask material 130 as a mask. Then, p ⁺ type source / drain electrodes are formed by activation annealing. It should be noted that the conditions for the activation annealing are required so that the p-type dopant impurity does not diffuse excessively in the lateral direction.

  Next, after the mask material 130 is peeled off, another mask material 130 (typically a silicon nitride film) is deposited, and this time, a line pattern extending in the row direction is formed.

  12A and 12B, the semiconductor layer 75, the block insulating film 60, the charge storage layer 50, and the first channel region 20 are formed by the RIE method using the mask material 130 as a mask. The tunnel insulating film 40 is sequentially etched to form the shape of the MONOS gate stack.

Thereafter, a process (not shown) for forming a thin silicon oxide film on the side surface of the MONOS gate stack is performed by the CVD method. Next, as shown in FIGS. 13A and 13B, a second channel region on the semiconductor substrate 15 is formed by introducing phosphorus (or arsenic or antimony) by self-alignment by an ion implantation method and performing a thermal process. An n ⁺ -type source / drain diffusion layer 80 adjacent to 90 is formed to complete the memory cell. Finally, an electrode sidewall oxide film 160 and an interlayer insulating film 170 covering the memory cell are formed by CVD.

  Note that the above-described manufacturing method is merely an example, and the memory cell of FIG. 3 may be formed by other manufacturing methods.

For example, the n ⁺ -type source / drain 80 of the second channel region 90 and the p ⁺ -type source / drain 30 of the first channel region 20 are deposited by impurity-doped polycrystalline silicon in addition to the ion implantation method. It may be formed by a method or a solid phase diffusion method.

Moreover, the following modifications are possible as a method of manufacturing the MONOS gate stack insulating film disposed on the semiconductor substrate 15. Among the steps of forming the tunnel insulating film 40, the thermal oxidation method uses various methods such as wet oxidation (hydrogen combustion oxidation), plasma oxidation using O ₂ or H ₂ O as a source gas in addition to dry O ₂ oxidation. be able to. Further, the step of nitriding the silicon oxide film may be replaced with a heat treatment step in an atmosphere of NO gas or NH ₃ gas instead of the step of nitrogen plasma.

The composition of the silicon nitride film used as the charge storage layer 50 can be changed by adjusting the flow ratio of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ), which are LPCVD source gases.

Alumina (Al ₂ O ₃ ) as the block insulating film 60 is formed by ALD, and TMA (Al (CH ₃ ) ₃ ) and H ₂ O are used as source gases in the temperature range of 500 ° C. to 800 ° C. It may be formed by MOCVD (Metal Organic Chemical Vapor Deposition) method.

  Furthermore, the source gas used in the CVD method (or ALD method) may be replaced with another gas for each film constituting the above-described substrate structure and MONOS gate stack structure. Further, the CVD method can be replaced by a sputtering method. In addition, the above-described layers may be formed by a method other than the CVD method or the sputtering method, such as a vapor deposition method, a laser ablation method, or an MBE method, or a method combining these methods.

(Modification 1)
FIG. 14 is a diagram showing a modification of the memory cell of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. 14A is a cross-sectional view along the bit line direction, and FIG. 14B is a cross-sectional view along the word line direction. The same parts as those shown in FIGS. 6A and 6B are denoted by the same reference numerals, and detailed description thereof is omitted.

  This embodiment is different from the above-described second embodiment in that the configuration of the insulating film layer of the MONOS type memory cell transistor is turned upside down. Below, it demonstrates centering on a different point from 2nd Embodiment.

On the surface portion of the n-type silicon substrate (semiconductor substrate 200), p ⁺ -type second source / drain regions 210 are arranged apart from each other. A first channel region 20 is disposed between the source diffusion layer and the drain diffusion layer.

As in the case of the second embodiment, the second source / drain region 210 is usually composed of a p ⁺ -type diffusion layer. However, a plurality of such memory cells are connected in series to form a NAND. when configuring the type memory cell unit omits placing the p ⁺ -type diffusion layer, using the inversion layer fringe electric field is induced on the substrate surface from the gate electrodes of adjacent memory cells as the source and drain electrodes It is also possible.

Next, the configuration of the gate stack disposed on the n-type silicon substrate (semiconductor substrate 200) will be described. On the first channel region 20, for example, an alumina (Al ₂ O ₃ ) film having a thickness of 15 nm is disposed as the block insulating film 60. On the block insulating film 60, a silicon nitride film (Si ₃ N ₄ ) having a thickness of 5 nm is disposed as the charge storage layer 50. On the silicon nitride film (charge storage layer 50), a silicon oxynitride film (SiON) having a thickness of, for example, 5 nm is disposed as the tunnel insulating film 40. A p-type semiconductor layer 230 to be the second channel region 90 is disposed on the tunnel insulating film 40. As can be seen from FIG. 14B, n ⁺ -type source / drain regions 80 are disposed adjacent to the second channel region 90.

  In this embodiment, a plurality of block insulating films 60, charge storage layers 50, and tunnel insulating films 40 are formed in the row direction, and these are separated from each other by an element isolation insulating layer 120 having an STI (Shallow Trench Isolation) structure. The

Here, the n-type dopant impurity concentration of the first channel region 20 arranged on the silicon substrate surface (or the dopant impurity concentration of the semiconductor substrate 200) is 1 × 10 ¹⁹ cm ^{−3 in} this embodiment. In addition, the p-type dopant impurity concentration in the second channel region 90 that also functions as the control gate electrode is 1 × 10 ¹⁸ cm ⁻³ . That is, the dopant impurity concentration in the first channel region 20 is higher than the dopant impurity concentration in the second channel region 90.

  As a driving method of this memory cell, writing / erasing is performed by injecting charges from the semiconductor layer 230 constituting the second channel region 90 into the silicon nitride film (charge storage layer 50) through the tunnel insulating film 40. The operation is performed, and data is read depending on the presence or absence of a channel current flowing through the first channel region 20 on the surface of the silicon substrate (semiconductor substrate 200).

  The manufacturing method of these devices is within a range that can be realized by modifying the case of the second embodiment, and can be manufactured by using a normal apparatus and tool in an LSI process. Since this process is not difficult for those skilled in the art, a detailed description is omitted.

(Third embodiment)
FIG. 15 is a diagram illustrating a schematic structure of a memory cell of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. FIG. 15A is a cross-sectional view along the bit line direction, and FIG. 15B is a cross-sectional view along the word line direction. The same parts as those shown in FIGS. 6A and 6B are denoted by the same reference numerals, and detailed description thereof is omitted.

  This embodiment is different from the first embodiment described above in that the charge storage layer is made of phosphorus-doped silicon, which is a conductive semiconductor, instead of a silicon nitride film. Below, it demonstrates centering on a different point from 1st Embodiment.

In the present embodiment, the configuration of the gate stack disposed on the p-type silicon substrate (semiconductor substrate 15) is different from that in the first embodiment. For example, a silicon oxynitride film (SiON) having a thickness of 5 nm is disposed as the tunnel insulating film 40 on the second channel region 90 disposed on the surface of the p-type silicon substrate (semiconductor substrate 15). This is the same as in the first embodiment. On the tunnel insulating film 40, a phosphorus-doped polycrystalline silicon film having a thickness of 5 nm is disposed as the charge storage layer 300. The phosphorus concentration in this silicon film is about 1 × 10 ²⁰ cm ⁻³ . On the charge storage layer 300 (phosphorus-doped polycrystalline silicon), for example, an alumina (Al ₂ O ₃ ) film having a thickness of 15 nm is disposed as an interpoly insulating film (block insulating film 60). On the block insulating film 60, an n-type semiconductor layer 75 to be the first channel region 20 is disposed. As shown in FIG. 15B, ap ⁺ type first source / drain region 30 is disposed adjacent to the first channel region 20.

Here, the p-type dopant impurity concentration in the second channel region 90 on the p-type silicon substrate (semiconductor substrate 15) is set to 5 × 10 ¹⁷ cm ^{−3 in} this embodiment. The n-type dopant impurity concentration in the first channel region 20 functioning as the control gate electrode was set to 5 × 10 ¹⁸ cm ⁻³ . That is, the dopant impurity concentration in the first channel region 20 is higher than the dopant impurity concentration in the second channel region 90.

  The memory cell driving method is similar to that in the first embodiment. That is, a write / erase operation is performed by injecting charges from the surface of the semiconductor substrate 15 into the charge storage layer 300 (phosphorus-doped polycrystalline silicon) through the tunnel insulating film 40, and the channel current flowing through the first channel region 20 is reduced. Data reading is performed with or without presence.

  Note that the manufacturing method of these devices is within a range that can be realized by modifying the case of the first embodiment, and can be manufactured using a normal apparatus and tool in an LSI process. Since it is not difficult for those skilled in the art, a detailed description is omitted.

  In this embodiment, the charge storage layer is made of polycrystalline silicon containing a dopant impurity, but the charge storage layer is not necessarily limited thereto, and a conductive metal, metal nitride, metal carbide, A wide range of metal silicides can be used. For example, TiN or the like may be used instead of phosphorus-doped polycrystalline silicon.

  The present invention is not limited to the embodiments described above. The charge storage layer in the present invention may have various forms such as an insulating film, a conductive floating gate electrode, or conductive fine particles. Further, the forms of the tunnel insulating film and the block insulating film in the present invention are also various. The tunnel insulating film is generally a silicon oxynitride film containing nitrogen in the film or a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film, but is not limited thereto. For example, a high dielectric (high-k) insulating film or a tunnel insulating film made of a laminated film of different high-k insulating films may be used. On the other hand, the block insulating film (or interpoly insulating film) may have a structure of alumina / silicon oxide film / alumina other than alumina. Lanthanum aluminum, lanthanum aluminate, lanthanum aluminum silicate, or the like can also be used as the block insulating film (or interpoly insulating film). The block insulating film (or interpoly insulating film) may be a conventionally used laminated film of silicon oxide film / silicon nitride film / silicon oxide film, or silicon nitride film / silicon oxide film / silicon nitride film / silicon oxide film. / A laminated film of silicon nitride film may be used.

  The block insulating film (or interpoly insulating film) generally has a larger capacity than the tunnel insulating film. In addition to the fact that the block dielectric film (interpoly insulation film) has a higher average dielectric constant as a material than the tunnel insulation film, the capacity of the block insulation film (interpoly insulation film) is increased by devising the element structure. May be increased. For example, if a block insulating film (interpoly insulating film) is also arranged on the side surface of the floating gate electrode 300 and a control gate electrode is also arranged thereon, the capacity of the block insulating film (interpoly insulating film) is increased. Can do.

  The gate stack structure of the memory cell of the present invention may be formed in a well region formed near the surface of the silicon substrate. Further, instead of a silicon substrate, a SiGe substrate, a Ge substrate, a SiGeC substrate, or the like may be used, and a memory cell structure may be formed in a well region in these substrates. Furthermore, the memory element of the present invention may be formed on an SOI (silicon on insulator) substrate.

  In the present invention, the first channel region 20 and the second channel region 90 are preferably semiconductors of different conductivity types. This is because it can be formed and operated on a normal silicon substrate. That is, if the same conductivity type is used, the inversion layer cannot be formed simultaneously in the first channel region 20 and the second channel region 90, and one of them becomes a storage layer. However, assuming that the memory element of the present invention is formed on an SOI (silicon on insulator) substrate, the first channel region 20 and the second channel region 90 may be semiconductors of the same conductivity type. Therefore, possible combinations of the transistors of the first channel region 20 and the second channel region 90 of the present invention include (n channel, p channel), (n channel, n channel), (p channel, p channel). , (P channel, n channel).

  The concept of the present invention can also be applied to a memory cell having a three-dimensional structure. For example, it can be applied to a stacked flash memory (MONOS or floating gate type). Further, when the present invention is used for a MONOS memory cell, it can be applied regardless of the MONOS operation method. That is, for example, the present invention can be applied to a device operation method in which charges are accumulated in the charge accumulation layers at the source end and the drain end of the MONOS transistor to perform a multilevel operation.

  The present invention mainly relates to the elemental technology of the memory cell and does not depend on the connection method of the memory cell at the circuit level. Therefore, in addition to NAND-type non-volatile semiconductor memory, NOR-type, AND-type, DINOR-type non-volatile semiconductor memory, 2-tra type flash memory that combines the advantages of NOR-type and NAND-type, and one memory cell The present invention can also be applied to a three-tra NAND type having a structure sandwiched between two selection transistors. The present invention can also be applied to a flash memory having an architecture having both a NAND type interface and a NOR type high reliability and high speed read function.

In addition, the present invention can be embodied by modifying each component without departing from the scope of the invention. Furthermore, various inventions can be configured by appropriately combining a plurality of components disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 10, 15, 200 ... Semiconductor substrate, 20 ... 1st channel region, 30, 210 ... 1st source-drain region, 40 ... Tunnel insulating film, 50, 300 ... Charge Storage layer, 60 ... Block insulating film, 65 ... Gate electrode, 70, 75, 230 ... Semiconductor layer, 80 ... Second source / drain region, 90 ... Second channel region, 105 ... Memory cell, 100, 110 ... Arrow indicating electron injection, 120 ... Element isolation insulating film, 130 ... Mask material, 140 ... Slit, 150 ... Element isolation trench, 160 ... Electrode side wall Oxide film, 170 ... Interlayer insulating film, 301 ... Select gate transistor, 302 ... Cell transistor row, 303 ... Select gate transistor , 304: insulating film, 305 ... semiconductor layer

Claims (7)

A nonvolatile semiconductor memory device including a plurality of nonvolatile memory cells,
The nonvolatile memory cell is
A first source / drain region formed apart from the first semiconductor layer;
A first channel region formed between the first source region and the first drain region;
A block insulating film formed on the first channel region between the first source region and the first drain region;
A charge storage layer formed on the block insulating film;
A tunnel insulating film formed on the charge storage layer;
A second channel region formed in a second semiconductor layer formed on the tunnel insulating film;
A second source / drain region formed in the second semiconductor layer so as to be opposed to each other across the second channel region;
With
A nonvolatile semiconductor memory device, wherein a dopant impurity concentration in the first channel region is higher than a dopant impurity concentration in the second channel region.   The nonvolatile semiconductor memory device according to claim 1, wherein the first semiconductor layer is formed on a surface portion of a semiconductor substrate.   The nonvolatile semiconductor memory device according to claim 1, wherein the second semiconductor layer is formed on a surface portion of a semiconductor substrate.   The nonvolatile semiconductor memory device according to claim 1, wherein the first channel region and the second channel region are semiconductors of different conductivity types.   The nonvolatile semiconductor memory device according to claim 1, wherein the first channel region is an n-type semiconductor and the second channel region is a p-type semiconductor. The dopant impurity concentration of the first channel region is 10 ¹⁷ cm ⁻³ or more and 10 ²⁰ cm ⁻³ or less, and is 5 to 50 times the dopant impurity concentration of the second channel region, The nonvolatile semiconductor memory device according to claim 1.   2. The nonvolatile semiconductor memory according to claim 1, further comprising a NAND type memory cell unit in which a plurality of the nonvolatile memory cells are connected in series, and selection gate transistors are connected to both ends of the series connection portion. apparatus.

Images