JP2007273816A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an error of position of a low-concentration impurity area and a high-concentration impurity area without sacrificing a current driving ability. <P>SOLUTION: Forming a semiconductor device 10 having a first MOS transistor 12 and a second MOS transistor 14 includes a process which forms a first low-concentration impurity area by introducing impurities into a first area 18 by using a main electrode 40 as a mask, a process which forms protruded electrodes 42L, 42R to simultaneously form a first gate electrode 36 and a second gate electrode 56, and a process which simultaneously forms first sidewalls 38L, 38R and second sidewalls 58L, 58R. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device in which a low breakdown voltage MOS (Metal-Oxide Semiconductor) transistor and a high breakdown voltage MOS transistor are arranged on a common substrate.

  2. Description of the Related Art A semiconductor device in which a high breakdown voltage MOS transistor (hereinafter referred to as a high breakdown voltage MOS-Tr) and a low breakdown voltage MOS transistor (hereinafter referred to as a low breakdown voltage MOS-Tr) are formed on a common substrate is known. (For example, refer to Patent Document 1). This type of semiconductor device is used, for example, as a driver drive circuit for an LCD (Liquid Crystal Display).

  However, the semiconductor device described in Patent Document 1 cannot sufficiently increase the current drive capability of the high voltage MOS-Tr. This is because the parasitic resistance in the LDD (Lightly Doped Drain) region cannot be sufficiently reduced in the high voltage MOS-Tr.

  Reduction of parasitic resistance is a problem common to MOS-Tr, and various proposals have been made so far. As one of them, a structure in which the LDD region of the MOS-Tr overlaps with the gate electrode (hereinafter referred to as an overlap structure) has been proposed (see, for example, Patent Document 2).

The overlap structure described in Patent Document 2 is generally manufactured by the following steps (1) and (2). (1) A low concentration impurity region is formed using the gate electrode as a mask. (2) A side wall made of polysilicon covering the low concentration impurity region is formed on the side surface of the gate electrode.
JP 2000-216399 A JP-A-5-218066

  However, the technique described in Patent Document 2 cannot be applied to the high voltage MOS-Tr as it is. This is because the surface of the low-concentration impurity region (LDD region) is shaved during the etching for forming the sidewall. As a result, there arises a problem that the electric resistance of the low-concentration impurity region is increased and the current driving capability of the high voltage MOS-Tr is reduced.

  Further, another problem exists when the high breakdown voltage MOS-Tr and the low breakdown voltage MOS-Tr are formed on a common substrate. That is, in the technique described in Patent Document 1, impurities are ion-implanted using a patterned photoresist as a mask when forming a low-concentration impurity region and a high-concentration impurity region. As a result, there is a possibility that a position error occurs in the low concentration impurity region and the high concentration impurity region due to misalignment of the mask pattern.

  The present invention has been made under such a background. Accordingly, the object of the present invention is to reduce (1) without sacrificing the current driving capability of the high voltage MOS-Tr and (2) without causing a position error in the low concentration impurity region and the high concentration impurity region. An object of the present invention is to provide a method for manufacturing a semiconductor device provided with a high voltage MOS-Tr and a high voltage MOS-Tr on a common substrate.

  In order to achieve the above-described object, the present invention provides a method of forming a semiconductor device having a first MOS transistor and a second MOS transistor on a first main surface of a substrate, and includes the following steps: It is a feature.

  Here, the first MOS transistor is formed in the first region of the first main surface, and includes a first gate electrode including a main electrode and overhang electrodes connected to both side surfaces of the main electrode. The second MOS transistor is formed in the second region of the first main surface and includes a second gate electrode.

  That is, in forming the semiconductor device, the following first to ninth steps are performed.

  In the first step, a first oxide film is formed in the first region, and a second oxide film thinner than the first oxide film is formed in the second region.

  In the second step, a main electrode is formed on the first oxide film in the first region.

  In the third step, the first low concentration is introduced by introducing impurities into the first region using the mask pattern covering the first main surface outside the first region and the main electrode provided in the first region as a mask. Impurity regions are formed.

  In the fourth step, the entire upper surfaces of the first and second regions are covered with a conductive film.

  In the fifth step, the conductive film is etched to form an overhanging electrode on the first oxide film to create the first gate electrode, and at the same time, the second gate electrode is created on the second oxide film.

  In the sixth step, by using the mask pattern covering the first main surface outside the second region and the second gate electrode provided in the second region as a mask, impurities are introduced into the second region, A second low concentration impurity region is formed.

  In the seventh step, the entire upper surfaces of the first and second regions are covered with an insulating film.

  In the eighth step, by etching the insulating film, a first sidewall connected to both sides of the first gate electrode is formed on the first oxide film, and at the same time, connected to both sides of the second gate electrode. A second sidewall is formed on the second insulating film.

  In the ninth step, an impurity having the same conductivity type as that in the third step is used with the structure composed of the first gate electrode and the first sidewall and the structure composed of the second gate electrode and the second sidewall as masks. Is introduced at a higher concentration than in the third step, thereby forming a first high concentration impurity region in the first region and a second high concentration impurity region in the second region.

  Thus, according to the method of manufacturing a semiconductor device of the present invention, in the first MOS transistor (high voltage MOS-Tr), the portion adjacent to the main electrode of the first low-concentration impurity region is the overhang electrode and the first side. It is kept covered by the wall. Therefore, this portion is protected from etching performed in the fifth step and the eighth step. As a result, an increase in electrical resistance in this portion of the first low concentration impurity region is suppressed. As a result, the current driving capability of the first MOS transistor can be kept good.

  The introduction of impurities performed in the third step, the sixth step, and the ninth step is all performed in a self-aligned manner. Therefore, a position error caused by misalignment of the mask pattern does not occur in the first low concentration impurity region, the first high concentration impurity region, the second low concentration impurity region, and the second high concentration impurity region.

  Here, the current driving capability indicates the amount of current flowing between the source and the drain when the MOS transistor is turned on, that is, when a voltage is applied between the gate and the drain.

  As described above, according to the present invention, a semiconductor device is manufactured without sacrificing the current driving capability of the high voltage MOS-Tr and without causing a position error in the low concentration impurity region and the high concentration impurity region. A method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. Each drawing is merely a schematic representation of the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Moreover, although the preferable structural example of this invention is demonstrated hereafter, the material of each component, a numerical condition, etc. are only a suitable example. Therefore, the present invention is not limited to the following embodiment.

(Structure of semiconductor device)
With reference to FIG. 1, the structure of a semiconductor device manufactured according to the present invention will be described first. FIG. 1 is a diagram schematically showing a cross-sectional cut of the semiconductor device 10 with a part omitted. In FIG. 1, the horizontal direction in the drawing may be referred to as the gate length direction.

  The semiconductor device 10 includes a high breakdown voltage MOS-Tr 12 as a first MOS transistor and a low breakdown voltage MOS-Tr 14 as a second MOS transistor having a breakdown voltage lower than that of the first MOS transistor. The high breakdown voltage MOS-Tr 12 and the low breakdown voltage MOS-Tr 14 are respectively formed on the first main surface 16 a side of the substrate 16 having a p-type conductivity.

  Here, the substrate 16 is, for example, a parallel flat silicon substrate having the first main surface 16a and the second main surface 16b.

  The high voltage MOS-Tr12 is formed in the first region 18 of the first main surface 16a. Here, the first region 18 is electrically isolated from other adjacent elements by a field oxide film 22 having a thickness of about 800 nm formed in the periphery. The low breakdown voltage MOS-Tr 14 is formed in the second region 20 of the first main surface 16a. The second region 20 is electrically isolated from other adjacent elements by a field oxide film 22 having a thickness of about 800 nm formed around the second region 20.

  First, the high voltage MOS-Tr12 will be described.

  The high breakdown voltage MOS-Tr12 is designed so that the gate breakdown voltage is about 20V and the source-drain breakdown voltage is about 20V.

  The high breakdown voltage MOS-Tr 12 includes a first source region 28, a first drain region 30, a first channel region 32, a first gate oxide film 34, a first gate electrode 36, and first sidewalls 38L and 38R. And.

  As is well known, the first source region 28, the first drain region 30, and the first channel region 32 are formed in the substrate 16 from the first main surface 16a. The first channel region 32 is located between the first source region 28 and the first drain region 30.

The first source region 28 is a region whose conductivity type is n-type. The first source region 28 includes an n ⁻ region 28Lo and an n ⁺ region 28Hi.

The n ⁻ region 28Lo constituting the first source region 28 is a region where low-concentration n-type impurities (for example, P) are present. The n ⁻ region 28Lo is interposed between the n ⁺ region 28Hi and the first channel region 32 and exists below the n ⁺ region 28Hi.

The n ⁺ region 28Hi constituting the first source region 28 is a region where an n-type impurity (for example, As or P) having a higher concentration than the n ⁻ region 28Lo exists. The n ⁺ region 28Hi exists away from the first channel region 32.

The first drain region 30 is a region whose conductivity type is n-type. The first drain region 30 includes an n ⁻ region 30Lo and an n ⁺ region 30Hi.

The n ⁻ region 30Lo constituting the first drain region 30 is a region where a low concentration n-type impurity (for example, P or the like) is present. The n ⁻ region 30Lo is interposed between the n ⁺ region 30Hi and the first channel region 32 and exists below the n ⁺ region 30Hi.

The n ⁺ region 30Hi constituting the first drain region 30 is a region where an n-type impurity (for example, As or P) having a higher concentration than the n ⁻ region 30Lo exists. The n ⁺ region 30Hi exists away from the first channel region 32.

As already described, the first channel region 32 is a region inside the substrate 16 sandwiched between the first source region 28 and the first drain region 30. More specifically, the first channel region 32 is located between the n ⁻ regions 28Lo and 30Lo. The conductivity type of the first channel region 32 is p-type, similar to the substrate 16.

The first gate oxide film 34 is formed on the first major surface 16a of the substrate 16 so as to cover the n ⁻ region 28Lo, the first channel region 32, and the n ⁻ region 30Lo. In other words, the first gate oxide film 34, the ^{n +} region 28Hi, from an end portion of the first gate electrode 36 side, the ^{n +} region 30Hi, between the end portion of the first gate electrode 36 side first It is formed on main surface 16a. The first gate oxide film 34 is preferably a silicon oxide film, for example. The thickness of the first gate oxide film 34 is preferably about 50 nm, for example.

  The first gate electrode 36 is formed on the first gate oxide film 34. The first gate electrode 36 is formed so that the length in the gate length direction is shorter than that of the first gate oxide film 34. The first gate electrode 36 is located at the center of the first gate oxide film 34 in the gate length direction.

  The first gate electrode 36 includes a main electrode 40, an upper hard mask 41, and overhang electrodes provided on two side surfaces 43L and 43R that are orthogonal to the gate length direction of the first gate electrode 36 and face each other. 42L, 42R.

  The main electrode 40 constituting the first gate electrode 36 covers the first channel region 32 over the first gate oxide film 34. That is, the main electrode 40 is formed to have the same length in the gate length direction as the first channel region 32. The material of the main electrode 40 is preferably polysilicon, for example. The thickness of the main electrode 40 is preferably about 0.25 μm, for example. The length of the main electrode 40 in the gate length direction is preferably about 2.5 μm, for example.

  The hard mask 41 constituting the first gate electrode 36 has the same planar shape as the main electrode 40 and is formed on the main electrode 40. The material of the hard mask 41 is preferably NSG (Nondoped Silicate Glass), for example. The thickness of the hard mask 41 is preferably about 0.25 μm, for example.

  Hereinafter, a structure including the main electrode 40 and the hard mask 41 is referred to as a main electrode structure 43. Since the thickness of the main electrode 40 is about 0.25 μm and the thickness of the hard mask 41 is about 0.25 μm, the thickness of the main electrode structure 43 is about 0.5 μm.

  The overhang electrodes 42L and 42R constituting the first gate electrode 36 are respectively connected to the opposite side surfaces 43L and 43R of the main electrode structure 43. The overhanging electrode 42L extends over the first gate oxide film 34 on the first source region 28 side along the gate length direction. Similarly, the overhang electrode 42R extends over the first gate oxide film 34 on the first drain region 30 side along the gate length direction.

As a result, the overhang electrode 42L covers the n ⁻ region 28Lo near the side surface 43L over the first gate oxide film 34. Similarly, the overhang electrode 42R covers the n ⁻ region 30Lo near the side surface 43R over the first gate oxide film 34. The material of the extended electrodes 42L and 42R is preferably polysilicon, for example. The thickness of the overhang electrodes 42L and 42R is preferably about 0.5 μm, for example. Further, the overhang length W1 in the gate length direction of the overhang electrodes 42L and 42R is preferably about 0.25 μm, for example.

Here, a region where the overhanging electrode 42L and the n ⁻ region 28Lo overlap is referred to as an overlap region 44L. Similarly, a region where the overhang electrode 42R and the n ⁻ region 30Lo overlap is referred to as an overlap region 44R.

  Further, the first sidewalls 38L and 38R are connected to the projecting electrodes 42L and 42R, respectively. Specifically, the first sidewall 38L is in contact with the side portion 42Ls of the overhanging electrode 42L and extends in the gate length direction until reaching the end portion of the first gate oxide film 34 on the source region 28 side. . Similarly, the first sidewall 38R is in contact with the side portion 42Rs of the extending electrode 42R and extends in the gate length direction until reaching the end portion of the first gate oxide film 34 on the drain region 30 side.

As a result, the first sidewall 38L covers the n ⁻ region 28Lo extending between the n ⁺ region 28Hi and the overlap region 44L over the first gate oxide film 34. Similarly, the first sidewall 38R covers the n ⁻ region 30Lo extending between the n ⁺ region 30Hi and the overlap region 44R over the first gate oxide film 34.

  The material of the first sidewalls 38L and 38R is preferably a silicon oxide film, for example. The thickness of the first sidewalls 38L and 38R is preferably about 0.5 μm, for example. Furthermore, the overhang length W2 in the gate length direction of the first sidewalls 38L and 38R is preferably about 0.5 μm, for example.

  Here, a structure including the first gate electrode 36 and the first sidewalls 38L and 38R is referred to as a first structure 46. The thickness of the first structure 46 is equal to the main electrode structure 43 and is about 0.5 μm. The length of the first structure 46 in the gate length direction is about 4 μm. This is the sum of the lengths in the gate length direction of the main electrode 40 (2.5 μm), the overhang electrodes 42L and 42R (0.25 μm × 2), and the first sidewalls 38L and 38R (0.5 μm × 2). It is.

  Next, the low voltage MOS-Tr 14 will be described.

  First, the difference between the low breakdown voltage MOS-Tr 14 and the high breakdown voltage MOS-Tr 12 will be outlined.

  The low breakdown voltage MOS-Tr 14 is designed so that the gate breakdown voltage and the source-drain breakdown voltage are smaller than those of the high breakdown voltage MOS-Tr 12. Specifically, the gate breakdown voltage of the low breakdown voltage MOS-Tr 14 is about 3V, and the source-drain breakdown voltage is about 3V.

The low breakdown voltage MOS-Tr 14 is structurally different from the high breakdown voltage MOS-Tr 12 due to the difference in breakdown voltage described above. The main differences between the low voltage MOS-Tr14 and the high voltage MOS-Tr12 are listed below.
(1) No overlap region exists between the second gate electrode 56 and the n ⁻ regions 48Lo and 50Lo (2) No overhang electrode is provided on the second gate electrode 56 (3) Second gate The point that the oxide film 54 is thinner than the first gate oxide film 34 (4) The point that the second gate electrode 56 does not include a hard mask.

Next, the structure of the low breakdown voltage MOS-Tr 14 will be described in detail.
The low breakdown voltage MOS-Tr 14 includes a second source region 48, a second drain region 50, a second channel region 52, a second gate oxide film 54, a second gate electrode 56, and second sidewalls 58L and 58R. And.

  The second source region 48, the second drain region 50, and the second channel region 52 are formed in the substrate 16 from the first major surface 16a. The second source region 48 and the second drain region 50 are located on both sides of the second channel region 52, respectively.

The second source region 48 is a region whose conductivity type is n-type. The second source region 48 includes an n ⁻ region 48Lo and an n ⁺ region 48Hi.

The n ⁻ region 48Lo constituting the second source region 48 is a region where a low concentration n-type impurity (for example, P) is present. The n ⁻ region 48Lo is interposed between the n ⁺ region 48Hi and the second channel region 52 and exists below the n ⁺ region 48Hi.

The n ⁺ region 48Hi constituting the second source region 48 is a region where an n-type impurity (for example, As or P) having a higher concentration than the n ⁻ region 48Lo is present. The n ⁺ region 48Hi exists away from the second channel region 52.

The second drain region 50 is a region whose conductivity type is n-type. The second drain region 50 includes an n ⁻ region 50Lo and an n ⁺ region 50Hi.

The n ⁻ region 50Lo constituting the second drain region 50 is a region where low concentration n-type impurities (for example, P or the like) are present. The n ⁻ region 50Lo is interposed between the n ⁺ region 50Hi and the second channel region 52, and exists below the n ⁺ region 50Hi.

The n ⁺ region 50Hi constituting the second drain region 50 is a region where an n-type impurity (for example, As or P) having a higher concentration than the n ⁻ region 50Lo exists. The n ⁺ region 50Hi exists apart from the second channel region 52.

The second channel region 52 is a region inside the substrate 16 sandwiched between the second source region 48 and the second drain region 50. More specifically, the second channel region 52 is located between the n ⁻ regions 48Lo and 50Lo. The conductivity type of the second channel region 52 is p-type, similar to the substrate 16.

The second gate oxide film 54 is formed on the first major surface 16a of the substrate 16 so as to cover the n ⁻ region 48Lo, the second channel region 52, and the n ⁻ region 50Lo. In other words, the second gate oxide film 54, the ^{n +} region 48Hi, from an end portion of the second gate electrode 56 side, the ^{n +} region 50Hi, between the end portion of the second gate electrode 56 side first It is formed on main surface 16a. The material of the second gate oxide film 54 is preferably a silicon oxide film, for example. The thickness of the second gate oxide film 54 is preferably about 7 nm, for example.

  The second gate electrode 56 is formed on the second gate oxide film 54. The second gate electrode 56 is formed so that the length in the gate length direction is shorter than the second gate oxide film 54. The second gate electrode 56 is located at the center of the second gate oxide film 54 in the gate length direction.

  The material of the second gate electrode 56 is preferably polysilicon, for example. The thickness of the second gate electrode 56 is preferably about 0.25 μm, for example. The length of the second gate electrode 56 in the gate length direction is preferably about 0.6 μm, for example.

  Although described in detail later, the second gate electrode 56 is formed simultaneously with the overhang electrodes 42L and 42R of the high voltage MOS-Tr12.

  The second sidewalls 58L and 58R are connected to the second gate electrode 56, respectively. Specifically, the second sidewall 58L is in contact with the side surface 56L of the second gate electrode 56 and extends in the gate length direction until reaching the end of the second gate oxide film 54 on the second source region 48 side. ing. Similarly, the second sidewall 58R is in contact with the side surface 56R of the second gate electrode 56 and extends in the gate length direction until reaching the end of the second gate oxide film 54 on the second drain region 50 side. .

As a result, the second sidewall 58L covers the n ⁻ region 48Lo extending between the n ⁺ region 48Hi and the side surface 56L (second channel region 52) over the second gate oxide film 54. Similarly, the second sidewall 58R covers the n ⁻ region 50Lo extending between the n ⁺ region 50Hi and the side surface 56R (second channel region 52) over the second gate oxide film 54.

  The material of the second sidewalls 58L and 58R is preferably a silicon oxide film, for example. The thickness of the second sidewalls 58L and 58R is preferably about 0.25 μm, for example. Further, the overhang length in the gate length direction of the second sidewalls 58L and 58R is preferably about 0.2 μm, for example.

  As will be described in detail later, the second sidewalls 58L and 58R are formed simultaneously with the first sidewalls 38L and 38R of the high voltage MOS-Tr12.

  Here, a structure including the second gate electrode 56 and the second sidewalls 58L and 58R is referred to as a second structure 60. The thickness of the second structure 60 is about 0.25 μm, which is equal to the second gate electrode 56. The length of the second structure 60 in the gate length direction is about 1 μm. This is the sum of the lengths of the second gate electrode 56 (0.6 μm) and the second sidewalls 58L and 58R (0.2 μm × 2) in the gate length direction.

(Semiconductor device manufacturing process)
A manufacturing process of the semiconductor device 10 will be described with reference to FIGS. 2A and 2B are cross-sectional views schematically showing a structure obtained at a main stage in the manufacturing process of the semiconductor device 10 with a part omitted. 3A and 3B are similar cross-sectional views subsequent to FIG. FIGS. 4A and 4B are similar cross-sectional views subsequent to FIG. 5A and 5B are similar cross-sectional views subsequent to FIG. 4B. 6 (A) and 6 (B) are similar cross-sectional views subsequent to FIG. 5 (B).

  (Process A): It demonstrates with reference to FIG. 2 (A).

  In step A, first, a base oxide film 57 having a thickness of, for example, about 35 nm is preferably formed on the entire surface on the first main surface 16a side of the substrate 16 which is a silicon substrate. More specifically, the first main surface 16a is thermally oxidized at a temperature of about 850 ° C. to form a base oxide film 57 made of a silicon oxide film.

  Thereafter, a silicon nitride film pattern 59 having a thickness of, for example, about 100 nm is preferably formed on the base oxide film 57 using a conventionally known patterning technique. More specifically, a silicon nitride film is formed on the entire surface of the base oxide film 57 by a LPCVD (Low Pressure Chemical Vapor Deposition) method at a temperature of about 750 ° C.

  Thereafter, by performing photolithography and etching, portions of the silicon nitride film existing outside the first and second regions 18 and 20 are removed. Thereby, a silicon nitride film pattern 59 is formed.

  (Process B): It demonstrates with reference to FIG. 2 (B).

  In step B, a field oxide film 22 having a thickness of, for example, about 800 nm is preferably formed on the first major surface 16a exposed outside the first and second regions 18 and 20. More specifically, the field oxide film 22 is formed by performing steam oxidation at a temperature of about 1000 ° C.

  Thereafter, the underlying oxide film 57 and the silicon nitride film pattern 59 remaining in the first and second regions 18 and 20 are removed by a known method.

  Thereafter, a silicon oxide film having a thickness of, for example, about 50 nm is preferably formed on the surfaces in the first and second regions 18 and 20. More specifically, the first main surface 16a is thermally oxidized at a temperature of about 850 ° C. to form a silicon oxide film. This silicon oxide film is a precursor of the first oxide film 62.

  Thereafter, the silicon oxide film present in the second region 20 is removed by known photolithography and etching. As a result, the first oxide film 62 is patterned and formed in the first region 18. Then, a second oxide film 64 having a thickness of, for example, about 7 nm is preferably formed in the second region 20 by thermal oxidation at about 850 ° C. As a result, the structure shown in FIG. 2B is obtained.

  Here, the first oxide film 62 formed in the first region 18 is a precursor of the first gate oxide film 34. The second oxide film 64 formed in the second region 20 is a precursor of the second gate oxide film 54.

  Step A and step B correspond to the first step described above.

  (Process C): It demonstrates with reference to FIG. 3 (A).

In step C, a polysilicon film 66 having a thickness of, for example, about 0.25 μm is preferably formed on the entire first main surface 16a including the first region 18 and the second region 20. More specifically, using a source gas in which monosilane (SiH ₄ ) and phosphine (PH ₃ ) are mixed in a desired ratio, under a pressure of about 0.1 Torr and a temperature of about 600 ° C., by LPCVD, A polysilicon film 66 doped with P is formed.

Thereafter, an NSG film 68 having a thickness of, for example, about 0.25 μm is preferably formed on the entire surface of the polysilicon film 66. More specifically, a plasma CVD method is performed using a source gas in which SiH ₄ and dinitrogen monoxide (N ₂ O) are mixed at a desired ratio, a pressure of about 0.4 Torr, and a temperature of about 300 ° C. Thereby, the NSG film 68 is formed. Note that the NSG film 68 is a precursor of the hard mask 41.

  Thereafter, a positive photoresist is applied to the entire surface of the NSG film 68 with a thickness of about 1 μm. Then, a mask pattern 70 for forming a main electrode structure 43 described later is formed in the first region 18 by known photolithography.

  (Process D): It demonstrates with reference to FIG. 3 (B).

  In step D, the polysilicon film 66 and the NSG film 68 in a region not covered with the mask pattern 70 are removed by RIE (Reactive Ion Etching), which is anisotropic etching, using the mask pattern 70 as a mask. As a result, the main electrode structure 43 in which the hard mask 41 is laminated on the main electrode 40 is formed in the first region 18.

  The process from the process C to the formation of the main electrode structure 43 (process D) corresponds to the second process described above.

  Thereafter, a positive photoresist is applied to the entire surface of the first main surface 16a with a thickness of about 1 μm. Then, a mask pattern 72 that covers a portion of the first major surface 16a outside the first region 18 is formed by known photolithography to obtain the structure shown in FIG. That is, the mask pattern 72 is patterned so as to expose the first region 18.

Thereafter, ³¹ P ⁺ that is an n-type impurity is ion-implanted using the mask pattern 72 and the main electrode structure 43 as a mask. The ion implantation conditions are an implantation energy of about 500 keV and an implantation amount of about 6 × 10 ¹² atoms / cm ² . By this ion implantation, first low-concentration impurity regions 74L and 74R are formed in the first region 18 excluding the main electrode structure 43 in a self-aligning manner.

  In the process D, the process from the formation of the main electrode structure 43 to the formation of the first low-concentration impurity regions 74L and 74R corresponds to the above-described third process.

  (Process E): It demonstrates with reference to FIG. 4 (A).

In step E, the mask pattern 72 is removed by known plasma ashing. Then, a polysilicon film 76 having a thickness on the first main surface 16a of preferably about 0.25 μm, for example, is formed on the entire upper surface of the first main surface 16a. More specifically, using a source gas obtained by mixing SiH ₄ and PH ₃ in a desired ratio, a pressure of about 0.1 Torr and a temperature of about 600 ° C. A silicon film 76 is formed.

  The process from the formation of the first low-concentration impurity regions 74L and 74R to the formation of the polysilicon film 76 corresponds to the above-described fourth step.

  Thereafter, a positive photoresist is applied to the entire surface of the polysilicon film 76 with a thickness of about 1 μm. Then, a mask pattern 78 that covers a region where the second gate electrode 56 is to be formed in the second region 20 is formed by known photolithography.

  (Process F): It demonstrates with reference to FIG. 4 (B).

  In step F, the polysilicon film 76 is removed by RIE using the mask pattern 78 as a mask. Thereby, the first gate electrode 36 and the second gate electrode 56 are formed simultaneously.

  More specifically, by performing anisotropic etching from the direction perpendicular to the first main surface 16a, the polysilicon film 76 existing in the vicinity of the step portion of the main electrode structure 43 is etched in the first region 18. Instead, it remains on the first oxide film 62. The remaining polysilicon film 76 becomes the overhanging electrodes 42L and 42R. That is, the extended electrodes 42L and 42R are formed so as to be connected to both side surfaces 43L and 43R of the main electrode structure 43 and to protrude toward the outside of the main electrode structure 43, respectively.

  As a result, the extended electrodes 42L and 42R cover the first low-concentration impurity regions 74L and 74R near the main electrode structure 43 over the first oxide film 62. Thereby, the overlap regions 44L and 44R are formed.

  In this way, the first gate electrode 36 including the main electrode structure 43 and the overhang electrodes 42L and 42R is formed.

  Note that the lengths of the overlap regions 44L and 44R in the gate length direction, that is, the overhang lengths 42L and 42R, and the overhang length W1 are about 0.25 μm.

  On the other hand, in the second region 20, the polysilicon film 76 existing in the region covered with the mask pattern 78 remains without being etched. As a result, the second gate electrode 56 is formed on the second oxide film 64.

  The process from the formation of the polysilicon film 76 to the formation of the first gate electrode 36 and the second gate electrode 56 corresponds to the above-described fifth process.

  In the etching of the polysilicon film 76, the first and second oxide films 62 and 64 function as an etching stop film.

  (Process G): It demonstrates with reference to FIG.

  In Step G, a positive photoresist is applied to the entire upper surface of the first major surface 16a with a thickness of about 1 μm. Then, a mask pattern 80 that covers the portion of the first major surface 16a outside the second region 20 is formed by known photolithography. That is, the mask pattern 80 is patterned so as to expose the second region 20.

Thereafter, ³¹ P ⁺ which is an n-type impurity is ion-implanted using the mask pattern 80 and the second gate electrode 56 as a mask. The ion implantation conditions are an implantation energy of about 100 keV and an implantation amount of about 7 × 10 ¹² atoms / cm ² . By this ion implantation, second low-concentration impurity regions 82L and 82R are formed in the second region 20 on both sides of the second gate electrode 56 in a self-aligning manner.

  Step G corresponds to the above-described sixth step.

  (Process H): It demonstrates with reference to FIG.5 (B).

In step H, the mask pattern 80 is removed by known plasma ashing. Then, a silicon oxide film 83 as an insulating film having a thickness on the first main surface 16a of preferably about 0.5 μm, for example, is formed on the entire upper surface of the first main surface 16a. More specifically, the silicon oxide film 83 is formed by atmospheric pressure CVD using a source gas in which SiH ₄ and O ₂ are mixed at a desired ratio and at a temperature of about 500 ° C.

  Step H corresponds to the seventh step described above.

  (Process I): It demonstrates with reference to FIG. 6 (A).

  Subsequently, the silicon oxide film 83 is etched to reach the first major surface 16a of the substrate 16 by RIE.

  As a result, in the first region 18, the first sidewalls 38 </ b> L and 38 </ b> R are formed on the first gate electrode 36, and the first structure 46 is completed. At the same time, the first oxide film 62 in the region not covered with the first structure 46 is removed, and the first gate oxide film 34 is formed immediately below the first structure 46.

  More specifically, in the first region 18, the silicon oxide film 83 existing in the vicinity of the step portion of the first gate electrode 36 remains on the first oxide film 62 without being etched. The remaining silicon oxide film 83 becomes the first sidewalls 38L and 38R. That is, the first sidewalls 38L and 38R are connected to both side portions 42Ls and 42Rs of the extended electrodes 42L and 42R, respectively, and are formed to protrude on the first oxide film 62 toward the outside of the first gate electrode 36. Is done. As a result, the first sidewalls 38L and 38R cover the first low-concentration impurity regions 74L and 74R over the first oxide film 62.

  The overlap length along the gate length direction of the first sidewalls 38L, 38R and the first low-concentration impurity regions 74L, 74R, that is, the overhang length W2 of the first sidewalls 38L, 38R is about 0. .5 μm.

  In the second region 20, second sidewalls 58 </ b> L and 58 </ b> R are formed on the second gate electrode 56 to complete the second structure 60. At the same time, the second oxide film 64 in a region not covered with the second structure 60 is removed, and a second gate oxide film 54 is formed immediately below the second structure 60.

  More specifically, in the second region 20, the silicon oxide film 83 existing near the step portion of the second gate electrode 56 remains on the second oxide film 64 without being etched. The remaining silicon oxide film 83 becomes the second sidewalls 58L and 58R. That is, the second sidewalls 58L and 58R are formed so as to be connected to both side surfaces 56L and 56R of the second gate electrode 56, respectively, and to protrude toward the outside of the second gate electrode 56. As a result, the second sidewalls 58L and 58R cover the second low-concentration impurity regions 82L and 82R over the second oxide film 64.

  The overlap length between the second sidewalls 58L and 58R and the second low-concentration impurity regions 82L and 82R, that is, the length of the first sidewalls 58L and 58R in the gate length direction is about 0.2 μm. .

  Step I corresponds to the eighth step described above.

  (Process J): It demonstrates with reference to FIG. 6 (B).

Subsequently, ⁷⁵ As ⁺ which is an n-type impurity is ion-implanted into the first region 18 and the second region 20 using the first structure 46 and the second structure 60 as a mask. The ion implantation conditions are an implantation energy of about 70 keV and an implantation amount of about 1 × 10 ¹⁵ atoms / cm ² .

  By this ion implantation, the first source region 28 and the first drain region 30 are formed in the first region 18. At the same time, the second source region 48 and the second drain region 50 are formed in the second region 20.

More specifically, in the first region 18, the region of the first low-concentration impurity region 74 ^</ b ^> L that is not covered with the first structure 46 is changed to the n ⁺ region 28 Hi in a self-aligned manner by ion implantation. As a result, the As ion non-implanted region of the first low-concentration impurity region 74L changes to the n ⁻ region 28Lo. As a result, the first source region 28 including the n ⁻ region 28Lo and the n ⁺ region 28Hi is formed at the position where the first low concentration impurity region 74L was present.

Similarly, as a result of As ion implantation, the first low-concentration impurity region 74R that is not covered with the first structure 46 changes to the n ⁺ region 30Hi in a self-aligning manner. As a result, the As ion non-implanted region of the first low-concentration impurity region 74R changes to the n ⁻ region 30Lo. As a result, the first drain region 30 including the n ⁻ region 30Lo and the n ⁺ region 30Hi is formed at the position where the first low concentration impurity region 74R was present.

The second region 20 is substantially the same as the first region 18. That is, the n ⁺ region 48Hi is formed in the second low concentration impurity region 82L in a self-aligning manner, and at the same time, the n ⁻ region 48Lo is formed. As a result, the second source region 48 including the n ⁻ region 48Lo and the n ⁺ region 48Hi is formed at the position where the second low concentration impurity region 82L was present.

Further, the n ⁺ region 50Hi is formed in the second low concentration impurity region 82R in a self-aligned manner, and at the same time, the n ⁻ region 50Lo is formed. As a result, the second drain region 50 including the n ⁻ region 50Lo and the n ⁺ region 50Hi is formed at the position where the second low concentration impurity region 82R was present.

  In this way, the semiconductor device 10 as shown in FIG. 6B is formed.

  Next, effects of the semiconductor device manufacturing method of the present invention will be described.

In the manufacturing process of the semiconductor device 10, the n ⁻ regions 28Lo and 30Lo of the high voltage MOS-Tr 12 are continuously covered with the overhanging electrodes 42L and 42R and the first sidewalls 38L and 38R. That is, the n ⁻ regions 28Lo and 30Lo are not etched during the manufacturing process (step A to step J). Therefore, the electrical resistance of the n ⁻ regions 28Lo and 30Lo does not increase. As a result, a decrease in the current drive capability of the high voltage MOS-Tr 12 is prevented.

In addition, according to the method for manufacturing a semiconductor device of the present invention, all the impurity (P and As) ion implantations are performed in a self-aligned manner (steps D, G, and J). Therefore, there are positional errors in the n ⁻ regions 28Lo and 30Lo and the n ⁺ regions 28Hi and 30Hi of the first region 18 and the n ⁻ regions 48Lo and 50Lo and the n ⁺ regions 48Hi and 50Hi of the second region 20 formed by ion implantation. It does not occur. That is, in the technique of Patent Document 1, a dimensional margin for mask pattern misalignment is required, but in the present invention, the above-described dimensional margin is unnecessary. As a result, the semiconductor device 10 can be miniaturized by a margin on this dimension.

  Next, modifications and design conditions of the method for manufacturing a semiconductor device according to the present invention will be described.

  The source-drain breakdown voltage of the high breakdown voltage MOS-Tr 12 is mainly applied to both the extension length W1 of the extension electrodes 42L and 42R (FIG. 1) and the extension length W2 of the first sidewalls 38L and 38R (FIG. 1). Dependent.

  More specifically, the source-drain breakdown voltage increases as the overhang length W1 is increased. This is because the overlap region 44R on the first drain region 30 side becomes longer as the overhang length W1 is increased, and the electric field concentration in the first drain region 30 is alleviated.

  Specifically, the overhang length W1 of the overhang electrodes 42L and 42R is preferably 0.2 to 0.6 μm. By setting the overhang length W1 to 0.2 μm or more, a source-drain breakdown voltage of 10 V or more can be secured. By setting the overhang length W1 to 0.6 μm or less, a source-drain breakdown voltage of 25 V or less can be secured.

  The overhang length W1 is a balance between the thickness of the polysilicon film 76 (FIG. 4A) as the precursor of the overhang electrodes 42L and 42R and the thickness of the main electrode structure 43 (FIG. 3B). It is determined. In detail, the thickness of the thinner one of both 76 and 43 is substantially equal to the overhang length W1 of the overhang electrodes 42L and 42R. That is, if the thickness of the polysilicon film 76 is D1 and the thickness of the main electrode structure 43 is D2, W1≈D2 when (1) D1> D2, and (2) when D1 <D2. , W1≈D1. Therefore, by adjusting the thicknesses of the polysilicon film 76 and the main electrode structure 43, the overhang lengths W1 of the overhang electrodes 42L and 42R can be adjusted. Thereby, the source-drain breakdown voltage of the high breakdown voltage MOS-Tr 12 can be adjusted to a desired value.

  The same applies to the overhang length W2 as with the overhang length W1. That is, the source-drain breakdown voltage increases as the overhang length W2 is increased. This is because the electric field concentration in the first drain region 30 is reduced as the overhang length W2 is increased.

  Specifically, the overhang length W2 of the first sidewalls 38L and 38R is preferably 0.2 to 0.6 μm. By setting the overhang length W2 to 0.2 μm or more, a source-drain breakdown voltage of 10 V or more can be secured. By setting the overhang length W2 to 0.6 μm or less, a source-drain breakdown voltage of 25 V or less can be secured.

  As in the case of the overhanging electrodes 42L and 42R, the overhanging length W2 of the first sidewalls 38L and 38R depends on the thickness of the silicon oxide film 83 (FIG. 5B) and the first gate electrode 36 (FIG. 4). (B)). Specifically, the thickness of the thinner one of both 83 and 36 is substantially equal to the overhanging length W2 of the first sidewalls 38L and 38R. Therefore, by adjusting the thickness of the silicon oxide film 83 and the thickness of the first gate electrode 36, the overhanging length W2 of the first sidewalls 38L and 38R can be adjusted. Thereby, the source-drain breakdown voltage of the high breakdown voltage MOS-Tr 12 can be adjusted to a desired value.

It is a figure which shows typically the cross-sectional cut end of the semiconductor device manufactured based on this invention. (A) And (B) is sectional drawing which extracts and shows schematically the main steps in the manufacturing process of a semiconductor device. (A) And (B) is sectional drawing which extracts and shows schematically the main steps in the manufacturing process of the semiconductor device performed following FIG.2 (B). (A) And (B) is sectional drawing which extracts and shows schematically the main steps in the manufacturing process of the semiconductor device performed following FIG.3 (B). (A) And (B) is sectional drawing which extracts and shows roughly the main steps in the manufacturing process of the semiconductor device performed following FIG.4 (B). (A) And (B) is sectional drawing which extracts and shows roughly the main steps in the manufacturing process of the semiconductor device 10 performed following FIG.5 (B).

Explanation of symbols

10 Semiconductor device 12 High voltage MOS-Tr
14 Low voltage MOS-Tr
16 substrate 16a first main surface 16b second principal surface 18 first region 20 second region 22 field oxide film 28 first source region 28Lo n ^- region 28Hi n ⁺ region 30 first drain region 30Lo n ^- region 30Hi n ⁺ region 32 First channel region 34 First gate oxide film 36 First gate electrodes 38L, 38R First sidewall 40 Main electrode 41 Hard masks 42L, 42R Overhang electrodes 42Ls, 42Rs Side portion 43 Main electrode structures 43L, 43R Side surface 44L 44R overlap region 46 first structure 48 second source region 48Lon ⁻ region 48Hi n ⁺ region 50 second drain region 50Lon ⁻ region 50Hin ⁺ region 52 second channel region 54 second gate oxide film 56 second Gate electrodes 56L, 56R Side surface 57 Underlying oxide films 58L, 58R Wall 59 Silicon nitride film pattern 60 Second structure 62 First oxide film 64 Second oxide film 66 Polysilicon film 68 NSG film 70 Mask pattern 72 Mask patterns 74L and 74R First low-concentration impurity regions 76 Polysilicon film 78 Mask pattern 80 Mask patterns 82L and 82R Second low concentration impurity region 83 Silicon oxide film

Claims (3)

A first MOS transistor having a first gate electrode formed in a first region of a first main surface of a substrate and including a main electrode and an overhang electrode connected to both side surfaces of the main electrode;
In forming a semiconductor device having the second MOS transistor formed in the second region of the first main surface and having the second gate electrode,
A first step of forming a first oxide film in the first region and a second oxide film thinner than the first oxide film in the second region;
A second step of forming the main electrode on the first oxide film in the first region;
By introducing an impurity into the first region using the mask pattern covering the first main surface outside the first region and the main electrode provided in the first region as a mask, a first low concentration is obtained. A third step of forming an impurity region;
A fourth step of covering the entire upper surface of the first and second regions with a conductive film;
By etching the conductive film, the overhang electrode is formed on the first oxide film to form the first gate electrode, and at the same time, the second gate electrode is formed on the second oxide film. A fifth step;
By introducing an impurity into a portion of the second region by using the mask pattern covering the first main surface outside the second region and the second gate electrode provided in the second region as a mask, A sixth step of forming a second low-concentration impurity region;
A seventh step of covering the entire upper surface of the first and second regions with an insulating film;
By etching the insulating film, first sidewalls connected to both sides of the first gate electrode are formed on the first oxide film, and at the same time, first sidewalls connected to both sides of the second gate electrode are formed. An eighth step of forming two sidewalls on the second insulating film;
Impurities having the same conductivity type as in the third step, using the structure composed of the first gate electrode and the first sidewall and the structure composed of the second gate electrode and the second sidewall as masks, respectively. Is introduced at a higher concentration than in the third step, thereby forming a first high-concentration impurity region in the first region and a second high-concentration impurity region in the second region, respectively. A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the first sidewall measured along the gate length direction of the first gate electrode is 0.2 to 0.6 [mu] m. 3. The semiconductor device according to claim 1, wherein a width of one overhang electrode measured along a gate length direction of the first gate electrode is 0.2 to 0.6 μm. 4. Production method.

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