JP4572367B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a field effect transistor formed in an SOI (Silicon on Insulator) layer and a manufacturing method thereof.

2. Description of the Related Art With the recent miniaturization of semiconductor devices, field effect transistors formed in an SOI layer have attracted attention as semiconductor devices that can realize high-speed operation with low power consumption. As described above, there is a mesa (MESA) type element isolation method as one of the methods for element isolation of the semiconductor layer formed on the insulating layer. Mesa-type element isolation is performed by forming a mask layer in a region where an element isolation region of a semiconductor layer on an insulating layer is to be formed, and removing the semiconductor layer until the insulating layer is exposed. That is, element isolation is performed by forming an independent island-like semiconductor layer on the insulating layer.
JP-A-6-268224

  In the case where an island-shaped semiconductor layer is formed by the above-described mesa-type element isolation method, a parasitic MOS transistor may be generated on the sidewall of the island-shaped semiconductor layer. One possible cause of the occurrence of such parasitic MOS transistors is as follows. When the gate is formed in the island-shaped semiconductor layer, the gate electrode is formed so as to cover the upper portion of the semiconductor layer and the side wall portion through the gate insulating film. At this time, the upper end of the side wall is affected by the electric field from above and the electric field from the side wall, and due to the electric field concentration, a channel is easily formed, and a parasitic MOS having a threshold voltage lower than the normal threshold voltage is generated. . In order to reduce the leakage current due to the generation of this parasitic MOS transistor, in Patent Document 1, sidewall insulation formed on the side surface of the gate insulating layer formed on the upper surface of the island-shaped semiconductor layer is disclosed. Techniques are described that make it larger than the layer. However, with the recent miniaturization of semiconductor devices, it may be difficult to control the thickness of the gate insulating layer and the sidewall insulating layer, and the leakage current can be sufficiently reduced only by controlling the thickness. There are things you can't do.

  An object of the present invention is to provide a semiconductor device which is a field-effect transistor formed in an island-shaped semiconductor layer on an insulating layer and has a reduced leakage current, and a method for manufacturing the same.

The semiconductor device of the present invention includes an insulating layer,
An island-like semiconductor layer provided above the insulating layer;
A gate insulating layer provided on the surface of the island-shaped semiconductor layer;
A source region and a drain region formed in the island-shaped semiconductor layer;
A gate electrode provided above the gate insulating layer,
The island-like semiconductor layer has a conductivity type impurity region different from the source region and the drain region on its side.

  According to the semiconductor device of the present invention, since the impurity region is provided on the side portion of the island-shaped semiconductor layer, the threshold value of the parasitic MOS transistor that can be generated on the side surface of the island-shaped semiconductor layer can be changed. . For example, when a high concentration impurity region is provided, the threshold value of the parasitic MOS transistor can be increased. Therefore, even a semiconductor device in which mesa element isolation is performed can provide a semiconductor device in which generation of parasitic MOS transistors on the side surface is suppressed. As a result, a highly reliable semiconductor device with excellent electrical characteristics can be provided.

  In the present invention, the B layer is provided above the specific A layer means that the B layer is provided directly on the A layer via another layer in addition to the case where the B layer is provided directly on the A layer. And the case where the B layer is provided.

The semiconductor device of the present invention includes a first region and an insulating layer having a second region provided at a position where the surface is lower than the first region,
An island-like semiconductor layer provided above the insulating layer;
A gate insulating layer provided on the surface of the island-shaped semiconductor layer;
A source region and a drain region formed in the island-shaped semiconductor layer;
A gate electrode provided above the gate insulating layer;
An impurity region having a conductivity type different from that of the source region and the drain region provided on a side portion of the island-shaped semiconductor layer,
The island-like semiconductor layer includes a first portion provided above the first region and a second portion provided above the second region.

  In the semiconductor device of the present invention, the island-shaped semiconductor layer includes the first portion provided above the insulating layer in the first region and the second region in which the thickness of the insulating layer is smaller than the first region. And a second portion provided. Since the second portion is provided above the insulating layer in the second region where the surface is low, the bottom surface of the second portion is exposed. Therefore, a parasitic MOS transistor may occur on the exposed bottom portion. This leads to an increase in power consumption during standby of the MOS transistor, and also causes variations in the threshold value and ON current of the MOS transistor. According to the semiconductor device of the present invention, it is possible to suppress the generation of parasitic MOS transistors on the side surface and the bottom surface of the island-shaped semiconductor layer by providing the impurity region in the side portion of the island-shaped semiconductor layer. As a result, a highly reliable semiconductor device with excellent electrical characteristics can be provided.

  The semiconductor device of the present invention can further take the following aspects.

  In the semiconductor device of the present invention, the island-shaped semiconductor layer can include the first portion and the second portion provided on both sides of the first portion. According to this aspect, the bottom surfaces of both side portions of the island-shaped semiconductor layer do not contact the insulating layer. Therefore, a parasitic MOS transistor may be generated on the bottom surface of the second portion, but the generation of the parasitic MOS transistor on the side surface and the bottom surface can be suppressed by the impurity region provided on the side portion. As a result, a highly reliable semiconductor device with excellent electrical characteristics can be provided.

  In the semiconductor device of the present invention, the impurity region may be provided in the second portion of the island-shaped semiconductor layer.

  In the semiconductor device of the present invention, the impurity region may have an impurity concentration peak in at least one of an upper part and a lower part of the island-shaped semiconductor layer. According to this aspect, an aspect in which the impurity concentration is high at the corners of the island-like semiconductor layer can be taken. In the corner portion of the island-like semiconductor layer, since electric field concentration is likely to occur, parasitic MOS transistors are particularly likely to occur. However, in this embodiment, since the impurity concentration at the corner of the island-like semiconductor layer is made higher, such a problem can be avoided.

  In the semiconductor device of the present invention, the impurity concentration of the impurity region may be higher than the impurity concentration of a channel region provided below the gate insulating layer.

  According to this aspect, the threshold value of the parasitic MOS transistor that can be generated on the side of the island-like semiconductor layer is higher than the threshold value of the original MOS transistor. Therefore, when the MOS transistor is operated (when a voltage is applied to the gate electrode), it is possible to reliably suppress the generation of the parasitic MOS transistor on the side surface of the island-shaped semiconductor layer.

  In the semiconductor device of the present invention, the semiconductor layer may be an SOI layer. According to this aspect, it is possible to provide a semiconductor device in which low power consumption and high-speed operability are realized.

  In the semiconductor device of the present invention, the insulating layer may be a glass substrate. According to this aspect, the present invention can be applied to a thin film transistor (TFT), and a highly reliable thin film transistor can be provided.

  In the semiconductor device of the present invention, the semiconductor layer can be any of a single crystal silicon layer, an amorphous silicon layer, a polycrystalline silicon layer, and a silicon germanium layer.

A method for manufacturing a semiconductor device of the present invention includes:
Preparing a substrate provided with a semiconductor layer above the insulating layer;
Forming an island-like semiconductor layer by removing a predetermined region of the semiconductor layer;
Forming an impurity region on a side of the island-shaped semiconductor layer;
Forming a gate insulating layer above the island-shaped semiconductor layer;
Forming a gate electrode above the gate insulating layer; and forming a source region and a drain region having a conductivity type different from that of the impurity region in the island-like semiconductor layer.

  According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device in which an impurity region having a conductivity type different from that of the source region and the drain region is provided on the side portion of the island-shaped semiconductor layer can be manufactured. As described above, by providing the impurity region of a predetermined conductivity type on the side portion of the island-shaped semiconductor layer, a semiconductor device in which the generation of parasitic MOS transistors on the side surface of the island-shaped semiconductor layer is suppressed can be manufactured.

A method for manufacturing a semiconductor device of the present invention includes:
(A) preparing a substrate provided with a semiconductor layer above the insulating layer;
(B) forming an island-shaped semiconductor layer by removing a predetermined region of the semiconductor layer;
(C) removing a part of the exposed insulating layer to form a first region and a second region whose surface is lower than the first region;
(D) forming an impurity region on a side of the island-shaped semiconductor layer;
(E) forming a gate insulating layer above the island-shaped semiconductor layer;
(F) forming a gate electrode above the gate insulating layer; and (g) forming a source region and a drain region having a conductivity type different from the conductivity type of the impurity region on the island-like semiconductor layer; including.

  According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device in which an impurity region having a conductivity type different from that of the source region and the drain region is provided on the side portion of the island-shaped semiconductor layer can be manufactured. As described above, by providing the impurity region of a predetermined conductivity type on the side portion of the island-shaped semiconductor layer, a semiconductor device in which the generation of parasitic MOS transistors on the side surface of the island-shaped semiconductor layer is suppressed can be manufactured.

  The method for manufacturing a semiconductor device of the present invention can further take the following aspects.

  In the method for manufacturing a semiconductor device of the present invention, in (c), the insulating layer can be removed such that a part of the bottom surface of the island-shaped semiconductor layer is exposed. According to this aspect, a part of the bottom surface of the island-shaped semiconductor layer is not in contact with the insulating layer, and a parasitic MOS transistor may be generated on the bottom surface side of the island-shaped semiconductor layer. However, it is possible to manufacture a semiconductor device in which the generation of parasitic MOS transistors is suppressed even on the bottom surface side by the impurity region provided on the side portion of the island-shaped semiconductor layer.

  In the method for manufacturing a semiconductor device of the present invention, the impurity region can be formed by an oblique ion implantation method after forming a mask layer above the island-shaped semiconductor layer. According to this aspect, by using the oblique ion implantation method, the impurity region can be formed on the side portion of the island-shaped semiconductor layer with a simple process.

  In the method for manufacturing a semiconductor device of the present invention, the impurity region can be formed by introducing an impurity after forming a mask layer that exposes a side portion of the island-shaped semiconductor layer.

  In the method for manufacturing a semiconductor device of the present invention, the introduction of the impurity region is performed by an ion implantation method, and the ion implantation can be performed a plurality of times with different implantation energies. According to this aspect, in the impurity region, a region having a high impurity concentration can be formed, or a portion having a partially large width can be formed. For this reason, the generation of parasitic MOS transistors can be more reliably suppressed by increasing the impurity concentration at corners where electric fields tend to concentrate.

  In the method for manufacturing a semiconductor device of the present invention, the mask layer may be a hard mask.

  In the semiconductor device manufacturing method of the present invention, the mask layer may be the same as the mask layer used for patterning the island-shaped semiconductor layer. According to this aspect, since it is not necessary to provide a process of newly forming a mask layer that covers the upper part of the island-shaped semiconductor layer when forming the impurity area, the impurity area can be formed without increasing the number of manufacturing processes. It can be carried out.

  Embodiments of the present invention will be described below.

1. 1. First embodiment 1.1. Semiconductor Device A semiconductor device according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view schematically showing a semiconductor device according to the present embodiment, and FIG. 2A is a cross-sectional view schematically showing a cross section taken along line AA in FIG. (B) is sectional drawing which shows typically the cross section along the BB line of FIG.

  As shown in FIG. 1, a source region and a drain region (hereinafter referred to as “source / drain region”) 26 are formed in the island-like semiconductor layer 10 so as to face each other with the gate electrode 24 interposed therebetween. The gate electrode 24 is provided on the gate insulating layer 20 that covers the surface of the island-shaped semiconductor layer 10. Further description will be given with reference to the cross-sectional views of FIGS. As shown in FIGS. 2A and 2B, in the semiconductor device of this embodiment, an insulating layer 8 is provided on a support substrate 6, and an island-like semiconductor layer 10 is provided on the insulating layer 8. It has been. As shown in FIGS. 2A and 2B, a gate insulating layer 20 is provided on the surface of the island-like semiconductor layer 10, and a gate electrode 24 is provided on the gate insulating layer 20. In the island-like semiconductor layer 10, source / drain regions 26 are formed in the respective regions sandwiching the gate electrode 24.

  The island-like semiconductor layer 10 has an impurity region 28 on its side. The impurity region 28 is a region into which an impurity having a conductivity type different from that of the source / drain region 26 is introduced. The impurity concentration of the impurity region 28 is preferably larger than the impurity concentration of the channel region formed below the gate insulating layer 20. This is because the generation of a parasitic MOS transistor on the side surface of the island-shaped semiconductor layer 10 is suppressed by having an impurity concentration higher than that of the channel region. As can be seen from FIG. 1, the impurity region 28 is provided in a ring shape on the outermost periphery of the island-shaped semiconductor layer 10. Note that the conductivity type of the impurity region 28 that overlaps with the gate electrode 24 (impurity region 28 shown in FIG. 2A) is different from that of the source / drain region 26. On the other hand, the conductivity type of the impurity region 28 that does not overlap with the gate electrode 24 has the same conductivity type as the source / drain region because the concentration of the source / drain region 26 is higher than the concentration of the impurity region 28. ing.

  According to the semiconductor device of the present embodiment, since the impurity region 28 is provided on the side portion of the island-shaped semiconductor layer 10, the threshold value of the parasitic MOS transistor that can be generated on the side surface of the island-shaped semiconductor layer 10 is set. Can be controlled. For example, when the high concentration impurity region 28 is provided, the threshold value of the parasitic MOS transistor can be increased. Therefore, even in the case of a semiconductor device in which mesa element isolation is performed as in the present embodiment, a semiconductor device in which the generation of parasitic MOS transistors on the side surface is suppressed can be provided. As a result, it is possible to provide a highly reliable semiconductor device in which leakage current is suppressed and electrical characteristics are excellent.

1.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 3 to 7 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment, and FIGS. 3 to 6 and FIG. 7A show cross sections corresponding to FIG. FIG. 7B is a diagram showing a cross section corresponding to FIG.

  (1) First, as shown in FIG. 3, an SOI substrate is prepared in which an insulating layer 8 and a semiconductor layer 10 a are sequentially stacked on a support substrate 6. Examples of the semiconductor layer 10a include a single crystal silicon layer, an amorphous silicon layer, a polycrystalline silicon layer, and a silicon germanium layer.

  Thereafter, a thermal oxide film 30 and a silicon nitride film 32 are sequentially formed on the semiconductor layer 10a. The thermal oxide film 30 and the silicon nitride film 32 serve as a mask layer when forming the impurity region 28 (see FIG. 2) on the side portion of the island-like semiconductor layer 10 (see FIG. 2) in a process described later. . The thermal oxide film 30 and the silicon nitride film 32 can be formed by a known manufacturing method. Next, a resist layer R 1 having a predetermined pattern is formed on the silicon nitride film 32. The resist layer R1 is formed in a region where the island-shaped semiconductor layer 10 is to be formed.

(2) Next, as shown in FIG. 4, element isolation of the semiconductor layer 10a is performed to define the transistor formation region, and the island-shaped semiconductor layer 10 is formed. The island-shaped semiconductor layer 10 is formed by a mesa type element isolation method. In the mesa element isolation, first, the thermal oxide film 30 and the silicon nitride film 32 are etched using the resist layer R1 formed above the semiconductor layer 10a as a mask. Using the resist layer R1, the thermal oxide film 30 and the silicon nitride film 32 as a mask, the semiconductor layer 10a is removed until the insulating layer 8 is exposed. Thereby, the island-shaped semiconductor layer 10 is formed. The removal of the semiconductor layer 10a can be performed by a known general etching method. Thereafter, the resist layer R1 is removed by ashing or the like.
Next, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10a in order to adjust the threshold value as necessary. The introduction of impurities can be performed by, for example, a known ion implantation technique.

  (3) Next, an impurity region 28 (see FIGS. 1 and 2) is formed on the side portion of the island-shaped semiconductor layer 10. Impurity region 28 is implanted with an impurity of a predetermined conductivity type by oblique ion implantation as shown in FIG. 5 with thermal oxide film 30 and silicon nitride film 32 remaining on island-like semiconductor layer 10. To do. At this time, when other island-like semiconductor layers (not shown) provided on the same insulating layer 8 are regions where MOS transistors having different channel conductivity types are formed. Is performed in a state where a mask layer (not shown) is formed so that impurities are not introduced. The impurity region 28 is preferably formed by controlling the amount of impurity implantation so that the impurity concentration is higher than the impurity concentration of the region to be the channel region. Further, the impurity implantation energy and the like can be controlled as necessary so that the width of the impurity region 28 becomes a desired width so that the formation region of the MOS transistor is not substantially reduced.

  The formation of the impurity region 28 is performed by forming a mask layer in the island-like semiconductor layer 10 in a region where the source / drain region 26 and the channel region are formed so that impurities are not implanted. In the manufacturing method of the present embodiment, the thermal oxide film 30 and the silicon nitride film 32 (so-called hard mask) used as a mask when forming the island-like semiconductor layer 10 can also serve as a mask when forming the impurity region 28. . Therefore, it is not necessary to form separate mask layers for the formation of the island-shaped semiconductor layer 10 and the formation of the impurity regions 28, and the number of processes can be reduced. Further, after the impurities are implanted into the island-like semiconductor layer 10, a diffusion treatment such as a heat treatment may be performed as necessary.

  (4) Next, as shown in FIG. 6, the thermal oxide film 30 and the silicon nitride film 32 are removed. Thereby, the island-like semiconductor layer 10 having the impurity region 28 on its side can be formed. At this time, as shown in FIG. 1, the impurity region 28 is provided in a ring shape on the outermost periphery of the island-shaped conductor layer 10.

  (5) Next, as shown in FIGS. 7A and 7B, a gate insulating layer 20 is formed so as to cover the surface of the island-like semiconductor layer 10. As the gate insulating layer 20, for example, a silicon oxide film can be formed by a thermal oxidation method or the like. Next, a gate electrode 24 is formed on the gate insulating layer 20. In forming the gate electrode 24, first, a conductive layer (not shown) is formed on the entire surface of the island-like semiconductor layer 10. Thereafter, by patterning the conductive layer, the gate electrode 24 is formed as shown in FIGS. 7A and 7B. For example, a polycrystalline silicon layer is used as the conductive layer.

  Next, as shown in FIGS. 2A and 2B, source / drain regions 26 are formed. The source / drain region 26 is formed by injecting an impurity having a conductivity type different from that of the impurity region 28 into a desired region of the island-shaped semiconductor layer 10. In addition, after introducing impurities into the island-shaped semiconductor layer 10, diffusion treatment such as heat treatment may be performed. Through the above steps, the semiconductor device of this embodiment can be manufactured.

  According to the manufacturing method of the semiconductor device of the present embodiment, the impurity is introduced into the side portion of the island-shaped semiconductor layer 10 by oblique ion implantation while covering the upper surface of the island-shaped semiconductor layer 10. A semiconductor device having an impurity region 28 having a conductivity type different from that of the source / drain region 26 on the side portion of the island-like semiconductor layer 10 can be manufactured. As described above, by providing the impurity region 28 of a predetermined conductivity type on the side portion of the island-shaped semiconductor layer 10, a semiconductor device in which the generation of parasitic MOS transistors on the side surface of the island-shaped semiconductor layer 10 is suppressed is manufactured. Can do. As a result, a semiconductor device with suppressed leakage current and excellent electrical characteristics can be manufactured.

2. Second Embodiment 2.1. Semiconductor Device A semiconductor device according to the present embodiment will be described with reference to FIG. A plan view schematically showing the semiconductor device according to the second embodiment is the same as FIG. 1 showing a plan view schematically showing the semiconductor device of the first embodiment. I want. FIG. 8 is a cross-sectional view schematically showing the semiconductor device according to the present embodiment, and FIG. 8A is a cross-sectional view schematically showing a cross section along the line AA in FIG. ) Is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 1.

  As shown in FIG. 1, similarly to the semiconductor device according to the first embodiment, a source / drain region 26 is formed in the island-like semiconductor layer 10 so as to sandwich the gate electrode 24. The gate electrode 24 is provided on the gate insulating layer 20 that covers the surface of the island-shaped semiconductor layer 10. Next, a cross-sectional structure will be described with reference to FIGS. As shown in FIGS. 8A and 8B, in the semiconductor device of this embodiment, an insulating layer 8 is provided on a support substrate 6, and an island-like semiconductor layer 10 is provided on the insulating layer 8. It has been. As shown in FIGS. 8A and 8B, a gate insulating layer 20 is provided on the surface of the island-shaped semiconductor layer 10, and a gate electrode 24 is provided on the gate insulating layer 20. In the island-like semiconductor layer 10, source / drain regions 26 are formed on the sides of the gate electrode 24.

  In the semiconductor device of the present embodiment, as shown in FIGS. 8A and 8B, the insulating layer 8 at the lower end of the island-shaped semiconductor layer 10 has a first region 8A and a second region B. The thickness of the insulating layer 8 in the second region 8B is smaller than the thickness of the insulating layer 8 in the first region 8A. That is, in the second region 8B, the surface height of the insulating layer 8 is lower than that of the first region 8A. The island-shaped semiconductor layer 10 includes a first portion 10A provided on the first region 8A and a second portion 10B provided above the second region 8B. The bottom surface of the second portion 10B is , Not in contact with the insulating layer 8.

  The island-like semiconductor layer 10 has an impurity region 28 on its side. The impurity region 28 is a region into which an impurity having a conductivity type different from that of the source / drain region 26 is introduced. In the present embodiment, a case where the impurity region 28 is provided in the second portion 10B is shown. The impurity concentration of the impurity region 28 is preferably higher than the impurity concentration of the channel region formed below the gate insulating layer 20. This is because the generation of a parasitic MOS transistor on the side surface of the island-shaped semiconductor layer 10 is suppressed by having an impurity concentration higher than that of the channel region. As can be seen from FIG. 1, the impurity region 28 is provided in a ring shape on the outermost periphery of the island-shaped semiconductor layer 10. Note that the conductivity type of the impurity region 28 that overlaps with the gate electrode 24 (impurity region 28 shown in FIG. 8A) is different from that of the source / drain region 26. On the other hand, the conductivity type of the impurity region 28 that does not overlap with the gate electrode 24 has the same conductivity type as the source / drain region because the concentration of the source / drain region 26 is higher than the concentration of the impurity region 28. ing.

  In the semiconductor device according to the second embodiment, the island-shaped semiconductor layer 10 includes the first portion 10A provided above the insulating layer 8 in the first region 8A and the insulating layer 8 as compared with the first region 8A. The second portion 10B is provided above the second region 8B having a small film thickness. Since the second portion 10B is provided above the insulating layer 8 in the second region 8B whose surface is low, the bottom surface of the second portion 10B is exposed. Therefore, a parasitic MOS transistor may occur on the exposed bottom portion. In particular, in the vicinity of the exposed bottom side wall, a thin oxide film and electric field concentration are large due to a difference in crystal orientation, and a parasitic MOS transistor having a low threshold voltage is likely to occur. This leads to an increase in power consumption during standby of the MOS transistor, and also causes variations in the threshold value and ON current of the MOS transistor. However, according to the semiconductor device of the present embodiment, the generation of parasitic MOS transistors on the side surface and the bottom surface of the island-shaped semiconductor layer 10 is suppressed by providing the impurity region 28 on the side portion of the island-shaped semiconductor layer 10. Can do. As a result, a highly reliable semiconductor device with excellent electrical characteristics can be provided. FIG. 8A shows the case where the second portion 10B of the island-like semiconductor 10 and the impurity region 28 substantially coincide with each other. However, when the bottom surface of the second portion 10B is flat and the same as the crystal plane orientation of the surface and no electric field concentration occurs, the second portion 10B can be made wider than the impurity region 28.

2.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 9 to 12 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to this embodiment, and FIGS. 9 to 11 and FIG. 12 (A) show cross sections corresponding to FIG. 8 (A). FIG. 12B is a diagram showing a cross section corresponding to FIG. 8B. In the following description, detailed description of processes that can be performed in the same manner as in the manufacturing method of the first embodiment may be omitted.

  (1) First, as shown in FIG. 9, an SOI substrate in which an insulating layer 8 and a semiconductor layer 10 a are sequentially laminated on a support substrate 6 is prepared. Examples of the semiconductor layer 10a include a single crystal silicon layer, an amorphous silicon layer, a polycrystalline silicon layer, and a silicon germanium layer. Thereafter, a resist layer R1 having a predetermined pattern is formed on the semiconductor layer 10a. The resist layer R1 is formed on a region where the island-shaped semiconductor layer 10 is to be formed.

  (2) Next, the semiconductor layer 10a is etched using the resist layer R1 (see FIG. 9) as a mask to form the island-shaped semiconductor layer 10 as shown in FIG. The island-shaped semiconductor layer 10 is formed by a mesa type element isolation method. Although not particularly illustrated, another island-shaped semiconductor layer is also formed on the same insulating layer 8 in this step. The removal of the semiconductor layer 10a can be performed by a known general etching method. Thereafter, the resist layer R1 is removed by ashing or the like. Next, impurities of a predetermined conductivity type are introduced into the island-shaped semiconductor layer 10 in order to adjust the threshold value as necessary. The introduction of impurities can be performed by, for example, a known ion implantation technique.

  Next, as shown in FIG. 10, a mask layer having a smaller pattern than the resist layer R <b> 1 is formed on the island-shaped semiconductor layer 10. As the mask layer, a resist layer R2 can be formed. An impurity of a predetermined conductivity type is implanted into the island-shaped semiconductor layer 10 using the resist layer R2 as a mask. Thereby, as shown in FIG. 10, impurity regions 28 are formed on the side portions of the island-like semiconductor layer 10. At this time, when another island-shaped semiconductor layer (not shown) provided on the same insulating layer 8 is a region where MOS transistors having different channel conductivity types are formed. Is performed in a state where a mask layer (not shown) is formed so that impurities are not introduced. The impurity region 28 is preferably formed by controlling the amount of impurity implantation so that the impurity concentration is higher than the impurity concentration of the region to be the channel region. Also, the impurity implantation energy and the like can be controlled as necessary so that the width of the impurity region 28 becomes a desired width so that the formation region of the MOS transistor is not substantially reduced. Further, after the impurities are implanted into the island-like semiconductor layer 10, a diffusion treatment such as a heat treatment may be performed as necessary. Thereafter, the resist layer R2 is removed by ashing or the like.

  (3) Next, although not particularly shown, a gate insulating layer (not shown) of another MOS transistor having a different driving voltage is formed on another island-like semiconductor layer provided on the same insulating layer 8. To do.

  Generally, when MOS transistors having different driving voltages are mounted on the same substrate, the thicknesses of the respective gate insulating layers are different. In order to create different gate insulating layers in this way, the gate insulating layer having the largest film thickness is formed by repeating the thermal oxidation process a plurality of times, and the gate insulating layer having the smallest film thickness is There is a method in which an unnecessary thermal oxide film is selectively removed repeatedly and then formed in a final thermal oxidation process.

  When gate insulating layers having different film thicknesses are separately formed by the above-described method, the insulating layer 8 having an island-like semiconductor layer 10 on which a MOS transistor having a small gate insulating film thickness is formed is formed a plurality of times. A region where the film thickness of the insulating layer 8 is small is formed by the etching process. Furthermore, in the second and subsequent etchings, the etchant enters from the stepped portions of the small and large regions generated by the previous etching, and the insulating layer 8 located on the bottom surface of the island-like semiconductor layer 10 is partially covered. May be removed. As a result, as shown in FIG. 11, the insulating layer 8 has the first region 10A and the second region 8B whose surface height is lower than that of the first region 10A. The island-shaped semiconductor layer 10 is formed on the first region 8A and includes a first portion 10A and a second portion 10B provided above the second region 8B and having a bottom surface exposed. It will be.

  As shown in FIG. 11, as a result, the impurity region 28 provided in the previous step is provided in the whole or a part of the second portion 10B.

  (4) The gate insulating layer 20 is formed so as to cover the surface of the island-shaped semiconductor layer 10. As the gate insulating layer 20, for example, a silicon oxide film can be formed by a thermal oxidation method or the like. Next, a gate electrode 24 is formed on the gate insulating layer 20. In forming the gate electrode 24, first, a conductive layer (not shown) is formed on the entire surface of the island-like semiconductor layer 10. Thereafter, by patterning the conductive layer, a gate electrode 24 is formed as shown in FIGS. For example, a polycrystalline silicon layer is used as the conductive layer.

  Next, as shown in FIGS. 8A and 8B, source / drain regions 26 are formed. The source / drain region 26 is formed by injecting an impurity having a conductivity type different from that of the impurity region 28 into a desired region of the island-shaped semiconductor layer 10. In addition, after introducing impurities into the island-shaped semiconductor layer 10, diffusion treatment such as heat treatment may be performed. Through the above steps, the semiconductor device of this embodiment can be manufactured.

  According to the semiconductor device manufacturing method of the second embodiment, a semiconductor device in which an impurity region 28 having a conductivity type different from that of the source / drain region 26 is provided on the side portion of the island-shaped semiconductor layer 10 can be manufactured. it can. In the method of manufacturing the semiconductor device according to the present embodiment, the first portion 10A provided on the first region 8A of the insulating layer 8 is above the second region 8B and is in contact with the insulating layer 8. The island-shaped semiconductor layer 10 including the second portion 10B that is not present is formed. Therefore, a parasitic MOS transistor may be generated on the bottom surface side of the second portion 10B. However, the semiconductor device in which the generation of the parasitic MOS transistor is suppressed also on the bottom surface side by the impurity region 28 can be manufactured. As a result, the generation of parasitic MOS transistors on the bottom and side surfaces is suppressed, and a semiconductor device having excellent electrical characteristics with reduced leakage current can be manufactured.

  Further, when the bottom surface of the second portion 10B region of the semiconductor layer 10 is flat and has the same plane orientation with the surface, when the second portion 10B is set wider than the impurity region 28, the bottom surface of the second portion 10B A MOS transistor having the same threshold voltage as that of the MOS formed on the surface of the semiconductor layers 10A and 10B can be formed. Since the MOS transistor generated on the bottom surface side of the semiconductor layer of the second portion 10B has the same threshold voltage as the target MOS transistor, it contributes to an increase in the ON current and can improve the performance of the semiconductor device.

(Modification 1)
Next, a modification of the second embodiment will be described with reference to FIG. This modification differs from the second embodiment in that the impurity region 28 has an impurity concentration peak at one of the upper part and the lower part thereof. FIG. 13 is a cross-sectional view schematically showing a semiconductor device according to the first modification, and is a view showing the same portion as the cross-sectional view shown in FIG.

  As shown in FIG. 13, an insulating layer 8 having a first region 8A and a second region 8B in which the surface of the insulating layer 8 is lower than the first region 8A is provided on the support substrate 6. It has been. An island-like semiconductor layer 10 is provided on the insulating layer 8, and the island-like semiconductor layer 10 is provided above the first portion 10A provided on the first region 8A and the second region 8B. It consists of the second part 10B.

  A gate insulating layer 24 and a gate electrode 24 are provided on the island-like semiconductor layer 10 as in the above-described embodiment. An impurity region 28 is provided on the side of the island-shaped semiconductor layer 10. This modification shows a case where the impurity region 28 is provided in the second portion 10B. The impurity region 28 has an impurity concentration peak above and below it. That is, the impurity concentration is higher in the corner portion of the island-like semiconductor layer 10 than in other regions.

  Next, a method for manufacturing a semiconductor device according to this modification will be described. The semiconductor device according to this modification can be formed, for example, by changing the formation process of the impurity region 28 in the method for manufacturing the semiconductor device of the second embodiment. As shown in FIG. 10, a resist layer R2 is formed. Using this resist layer R2 as a mask, impurities of a predetermined conductivity type are ion-implanted. By controlling the energy at the time of ion implantation and performing ion implantation a plurality of times, the impurity region 28 having the impurity concentration peak at the lower side and the upper side can be formed.

  According to the semiconductor device according to the present modification, the impurity region 28 can take a form in which the impurity concentration is high at the corner of the island-shaped semiconductor layer 10. In the corner portion of the island-like semiconductor layer 10, electric field concentration is particularly likely to occur, and parasitic MOS transistors are likely to occur. However, according to this modification, such a problem can be avoided by increasing the impurity concentration of the island-shaped semiconductor layer 10.

(Modification 2)
Next, a semiconductor device according to Modification 2 of the present invention will be described with reference to FIG. The semiconductor device according to Modification 2 is an example in which the impurity region 28 is different from the above embodiment. FIG. 14 is a cross-sectional view schematically showing a semiconductor device according to the second modification, and is a view showing the same portion as the cross-sectional view shown in FIG.

  As shown in FIG. 14, a gate insulating layer 20 and a gate electrode 24 are provided on the island-like semiconductor layer 10 in the same manner as in the above-described embodiment. An impurity region 28 is provided on the side of the island-shaped semiconductor layer 10. The width X of the impurity region 28 provided on the upper end side and the lower end side of the second portion 10B is larger than the inner width. That is, a U-shaped impurity region 28 is provided on one side of the island-shaped semiconductor 10, and an inverted U-shaped impurity region 28 is provided on the other side.

  As a method for manufacturing the semiconductor device according to the second modification, the process for forming the impurity region 28 in the second embodiment may be changed. For example, as shown in FIG. 10, a resist layer R2 is formed, and impurities of a predetermined conductivity type are introduced by ion implantation using the resist layer R2 as a mask. By controlling the energy at the time of ion implantation and performing ion implantation a plurality of times, the impurity regions 28 provided on the lower end side and the upper end side can be formed to have a large width.

  According to the semiconductor device according to the modified example 2, the width of the impurity region 28 provided on the upper end side and the lower end side of the island-shaped semiconductor layer 10 can be made larger than the inner width. In this way, by forming a larger impurity region at the corner of the island-shaped semiconductor layer 10 where the electric field tends to concentrate, generation of parasitic MOS transistors can be further suppressed. As a result, a semiconductor device with favorable characteristics can be provided.

  The present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention. For example, in the above-described embodiment, the semiconductor device in which the LDD region or the extension region is not provided has been described as an example. However, the present invention is not limited thereto, and the LDD region or the extension region may be provided. In manufacturing the semiconductor device of this aspect, after forming the gate electrode 24, impurity implantation for the LDD region or the extension region is performed. Thereafter, a sidewall insulating layer is formed on the side surface of the gate electrode 24, and the source / drain region 26 is formed.

  In the manufacturing method of the present embodiment, the case where the impurity region 28 is formed on the side portion of the island-shaped semiconductor layer 10 by the oblique ion implantation method after patterning the island-shaped semiconductor layer 10 has been described. However, it is not limited to this manufacturing method, For example, the following methods can be taken. A first mask layer having an opening above the region where the impurity region 28 is formed and the region where the element isolation region is formed is formed above the semiconductor layer 10a. Thereafter, impurities for the impurity region 28 are implanted into the semiconductor layer 10a. Next, a second mask layer for forming the island-shaped semiconductor layer 10 is formed, and the semiconductor layer 10a is patterned using the second mask layer. The second mask layer has a pattern larger than the first mask layer by the width of the impurity region 28. Thereby, the island-like semiconductor layer 10 having the impurity region 28 on the side portion can be formed. In this embodiment, the island-shaped semiconductor layer 10 having the impurity regions 28 on the side portions can be formed without using the oblique ion implantation method.

  In the semiconductor device of the second embodiment, the case where the insulating layer 8 on the bottom surface of the island-shaped semiconductor layer 10 is removed in the process of separately forming gate insulating layers having different thicknesses has been described. However, the process in which the insulating layer 8 on the bottom surface of the island-like semiconductor layer 10 is removed is not limited to this process. For example, the same phenomenon may occur by repeatedly forming a sacrificial oxide film and etching it to form a gate insulating layer on the surface of a clean semiconductor layer.

  Further, although an SOI substrate is described as an example in this embodiment, the present invention is not limited to this, and the present invention can also be applied to a case where a silicon layer provided over a glass substrate is provided.

  In the first and second modified examples, the case where the modified example is applied to the semiconductor device of the second embodiment has been described as an example. However, the present invention is not limited to this, and the semiconductor device of the first embodiment. The impurity region 28 may be deformed.

  In the first modification, the case where the impurity region 28 has an impurity concentration peak at the upper part and the lower part has been described as an example, but the present invention is not limited to this and may be provided at either the upper part or the lower part. In addition, when the upper and lower portions have impurity concentration peaks, the upper and lower concentrations are not necessarily the same.

  In the second modification, the case where the upper and lower widths of the impurity region 28 are larger than the inner width has been described. However, the present invention is not limited to this, and the upper or lower width is increased. It may be formed.

1 is a plan view schematically showing a semiconductor device according to a first embodiment. The semiconductor device of 1st Embodiment is shown, (A) is sectional drawing along the AA line of FIG. 1, (B) is sectional drawing along the BB line of FIG. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment typically. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment typically. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment typically. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment typically. FIGS. 3A and 3B show a manufacturing process of the semiconductor device of the first embodiment, wherein FIG. 2A is a cross-sectional view corresponding to FIG. 2A and FIG. 2B is a cross-sectional view corresponding to FIG. The semiconductor device of 2nd Embodiment is shown, (A) is sectional drawing corresponding to FIG. 2 (A), (B) is sectional drawing corresponding to FIG. 2 (B). Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment typically. FIGS. 9A to 9C are cross-sectional views corresponding to FIG. 8A, and FIGS. 8B and 8B are cross-sectional views corresponding to FIG. Sectional drawing which shows the semiconductor device of the modification 1 typically. Sectional drawing which shows the semiconductor device of the modification 2 typically.

Explanation of symbols

6 support substrate, 8 insulating layer, 8A first region, 8B second region, 10 semiconductor layer, 10A first portion, 10B second portion 20 gate insulating layer, 24 gate electrode, 26 source / drain region, 28 impurity region, 30 thermal oxide film, 32 silicon nitride film

Claims (13)

An insulating layer;
An island-like semiconductor layer provided above the insulating layer;
A gate insulating layer provided on the surface of the island-shaped semiconductor layer;
A source region and a drain region formed in the island-shaped semiconductor layer;
A gate electrode provided above the gate insulating layer,
The island-shaped semiconductor layer has an impurity region of a conductivity type different from that of the source region and the drain region on a side portion thereof ,
The semiconductor device, wherein the impurity region has an impurity concentration peak in at least one of an upper part and a lower part of the island-shaped semiconductor layer . An insulating layer having a first region and a second region whose surface is lower than that of the first region;
An island-like semiconductor layer provided above the insulating layer;
A gate insulating layer provided on the surface of the island-shaped semiconductor layer;
A source region and a drain region formed in the island-shaped semiconductor layer;
A gate electrode provided above the gate insulating layer;
An impurity region having a conductivity type different from that of the source region and the drain region provided on a side portion of the island-shaped semiconductor layer,
The island-shaped semiconductor layer includes a first portion provided above the first region, and a second portion provided above the second region provided on both sides of the first portion ,
The semiconductor device, wherein the impurity region has an impurity concentration peak in at least one of an upper part and a lower part of the island-shaped semiconductor layer . In claim 2 ,
The impurity region is a semiconductor device provided in the second portion of the island-shaped semiconductor layer. In claim 3,
The semiconductor device, wherein the impurity region coincides with the second portion of the island-shaped semiconductor layer. In any one of Claims 1-4 ,
The semiconductor device, wherein an impurity concentration of the impurity region is higher than an impurity concentration of a channel region provided below the gate insulating layer. In any one of Claims 1-5 ,
The semiconductor device, wherein the semiconductor layer is an SOI layer. In any one of Claims 1-6 ,
The semiconductor device, wherein the insulating layer is a glass substrate. In any of the claims 1-7,
The semiconductor device, wherein the semiconductor layer is any one of a single crystal silicon layer, an amorphous silicon layer, a polycrystalline silicon layer, and a silicon germanium layer. Preparing a substrate provided with a semiconductor layer above the insulating layer;
Forming an island-like semiconductor layer by removing a predetermined region of the semiconductor layer;
Forming an impurity region on a side of the island-shaped semiconductor layer;
Forming a gate insulating layer above the island-shaped semiconductor layer;
Forming a gate electrode above the gate insulating layer; and forming a source region and a drain region of a conductivity type different from the conductivity type of the impurity region in the island-like semiconductor layer ,
The formation of the impurity region is performed by introducing an impurity by an ion implantation method after forming a mask layer that exposes the side portion of the island-shaped semiconductor layer,
The method of manufacturing a semiconductor device, wherein the ion implantation is performed a plurality of times with different implantation energies to form the impurity region having an impurity concentration peak in at least one of an upper part and a lower part of the island-shaped semiconductor layer . (A) preparing a substrate provided with a semiconductor layer above the insulating layer;
(B) forming an island-shaped semiconductor layer by removing a predetermined region of the semiconductor layer;
(C) A part of the insulating layer is removed so that a part of the bottom surface of the island-like semiconductor layer is exposed , and the first region and the second region whose surface is lower than the first region. Forming a region;
(D) forming an impurity region on a side of the island-shaped semiconductor layer;
(E) forming a gate insulating layer above the island-shaped semiconductor layer;
(F) forming a gate electrode above the gate insulating layer; and (g) forming a source region and a drain region having a conductivity type different from the conductivity type of the impurity region on the island-like semiconductor layer; Including
The formation of the impurity region is performed by introducing an impurity by an ion implantation method after forming a mask layer that exposes the side portion of the island-shaped semiconductor layer,
The method of manufacturing a semiconductor device, wherein the ion implantation is performed a plurality of times with different implantation energies to form the impurity region having an impurity concentration peak in at least one of an upper part and a lower part of the island-shaped semiconductor layer . In claim 10,
The method for manufacturing a semiconductor device, wherein the impurity region is provided in an entire portion of the island-shaped semiconductor layer where a bottom surface above the second region is exposed. In any one of Claims 9-11 ,
The method for manufacturing a semiconductor device, wherein the mask layer is a hard mask. In any one of Claims 9-11 ,
The method for manufacturing a semiconductor device, wherein the mask layer is the same as the mask layer used for patterning the island-shaped semiconductor layer.

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