JP3963463B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOSFET having a thin film SOI structure and a manufacturing method thereof.

  A thin-film SOI (Silicon-On-Insulator) element, for example, an SOI transistor formed on an insulating film, has recently attracted attention as a 0.1 μm generation device.

  Since this thin film SOI element is electrically insulated from the underlying semiconductor substrate by an insulating film, it has a great advantage that the parasitic capacitance is small. It is also known that there are advantages such as being strong against soft errors for the same reason.

  Furthermore, when the SOI layer is completely depleted due to the thinning of the SOI layer, it is easy to improve the operating speed, reduce the power consumption, and improve the switching characteristics by increasing the mobility. Can do. Further, it has been reported that the threshold voltage Vth decrease (so-called short channel effect) accompanying the miniaturization of the channel length is smaller than that of a MOSFET formed in bulk (Non-patent Document 1).

  In addition, in the 0.1 μm generation thin film SOI element, low power consumption is essential, and the power supply voltage is expected to be about 1V. To achieve this, it is most important to set the device thresholds appropriately.

  However, in the thin film SOI element, there is a problem that it is difficult to set a threshold value and circuit design becomes difficult. In order to solve this problem, the conventional method adjusts the threshold value by increasing the impurity concentration of the channel region. However, this method has a drawback that the increase in mobility, which is a major feature of the thin film SOI device, is lost.

  On the other hand, good subthreshold characteristics are indispensable for reducing power consumption during standby in a thin film SOI element. Originally, an excellent subthreshold characteristic is expected as a feature of an SOI element. However, when the element is actually manufactured, the subthreshold characteristic is deteriorated.

  FIG. 8 shows IV characteristics of an SOI element manufactured by the present inventors. The horizontal axis is the gate voltage, and the vertical axis is the drain current. A hump is seen in the region where the drain current rises, and an increase in the drain current is confirmed on the low gate voltage side. That is, it is clear that the threshold characteristics of the element are lowered and the subthreshold characteristic is deteriorated.

  FIG. 9 is a cross-sectional view of a thin film SOI element for explaining the deterioration of the subthreshold characteristic. Reference numeral 213 denotes an element isolation region formed by the LOCOS method, and a region 215a having a smaller thickness than the channel region 215 of the original SOI layer is formed under the bird's beak region. 211 is a silicon substrate, 212 is a buried silicon oxide film, and 214 is a gate electrode.

Thus, when the region 215a is formed, a parasitic transistor having a low threshold value is present in this portion, and the threshold value of the entire transistor becomes lower than that of the original transistor due to the operation of this parasitic transistor. . That is, when a gate voltage is applied, a current flows through the parasitic transistor first, and then a current flows through the original transistor, so that a hump characteristic as shown in FIG. 8 appears. A detailed analysis of this phenomenon is shown in Non-Patent Document 2, for example.
M. Yoshimi et al., IEICE Trans., Vol.E74, p. 337, 1991 IEEE, Transactions on Electron Devices, vol. 39, p. 874, 1992.

  As described above, in the conventional thin film SOI element, it is indispensable to adjust the threshold setting for circuit design, and the impurity concentration of the channel is increased to achieve this, and for this reason, the thin film SOI element It was difficult to achieve the original ultra-high speed.

  In addition, it is necessary to achieve good subthreshold characteristics in order to reduce power consumption during standby. However, conventional thin-film SOI elements have humps, and the threshold value of the elements decreases. There is a problem that the subthreshold characteristic is deteriorated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film SOI element in which a threshold value can be appropriately set and which can operate at high speed.

(First invention)
The present invention relates to an insulating layer, a semiconductor layer formed in an island shape in an element formation region on the insulating layer, a source region and a drain region formed separately from the semiconductor layer, and the source region and the drain region. A gate insulating film formed on a surface of the semiconductor layer serving as a channel between the semiconductor layer and a semiconductor layer formed on an element isolation region on the insulating layer and including a portion adjacent to the channel in a width direction of the channel; An element isolation insulating film having a substantially constant film thickness in a side wall region of the substrate and having a film thickness larger than the film thickness in a peripheral region of the region having the substantially constant film thickness; and the gate insulating film There is provided a semiconductor device comprising a gate electrode pattern formed from above to the element isolation insulating film.

In the present invention, the following embodiments are preferable.
(1) The region having the substantially constant film thickness is a region of the side wall portion around the entire semiconductor layer.
(2) The region having the substantially constant film thickness is selectively formed in a region of the side wall portion of the semiconductor layer located in the width direction of the channel.
(3) The width between the semiconductor layer and the outer peripheral region in the region having the substantially constant film thickness is 0.5 μm or less.

Furthermore, as a method for manufacturing the semiconductor device of the present invention, an element isolation insulating film is formed by selectively oxidizing the element isolation scheduled region of the semiconductor layer on the insulating layer, and the semiconductor is formed in an island shape in the element formation region. A step of leaving a layer, a step of forming a gate insulating film on the surface of the semiconductor layer, a step of forming a gate electrode pattern from the gate insulating film to the element isolation insulating film, and leaving the island shape Forming a source region and a drain region in the semiconductor layer so as to be separated from each other, and selectively oxidizing the element isolation scheduled region of the semiconductor layer in the width direction of the channel between the source region and the drain region. position is, and by selectively etching only the semiconductor layer in a region to be the side wall portion of the semiconductor layer to leave the island, reducing the thickness of the semiconductor layer in this region To provide a method of manufacturing a semiconductor device characterized by comprising a degree.

  As another method for manufacturing the semiconductor device of the present invention, a source region and a drain region are formed in a semiconductor layer formed in an island shape on an insulating layer, and a gate electrode pattern is formed on the semiconductor layer. A method for manufacturing an apparatus, the step of selectively forming a first insulating pattern in an island shape on a semiconductor layer formed on an insulating layer, and etching the semiconductor layer using the first insulating pattern as a mask Reducing the film thickness of the portion of the semiconductor layer not covered with the first insulating pattern, forming a second insulating pattern on the side wall of the first insulating pattern, By etching the semiconductor layer using the first and second insulating patterns as a mask, a portion of the semiconductor layer that is not covered with the first and second insulating patterns is selectively removed. And a step of removing the second insulation pattern, and selectively oxidizing the semiconductor layer using the first insulation pattern as a mask, thereby forming a channel between the source region and the drain region in the width direction of the channel. Forming a sidewall insulating film on the sidewall of the semiconductor layer including a portion adjacent to the channel; removing the first insulating pattern; and forming a gate insulating film on the surface of the semiconductor layer. And a step of forming a gate electrode pattern from the gate insulating film to an element isolation region on the insulating layer, and a step of forming a source region and a drain region separately from each other in the semiconductor layer. A method for manufacturing a semiconductor device is provided.

(Second invention)
As a method for manufacturing a semiconductor device of the present invention , a source region and a drain region are formed in a semiconductor layer formed in an island shape on an insulating layer, and a gate electrode pattern is formed on the semiconductor layer. A step of selectively forming a first insulating pattern in an island shape on the semiconductor layer formed on the insulating layer, and etching the semiconductor layer using the first insulating pattern as a mask. Reducing a film thickness of a portion of the layer not covered with the first insulating pattern, forming a second insulating pattern on a side wall of the first insulating pattern, and the first and second by etching the semiconductor layer to the insulating pattern as a mask, selectively removing the first and part of the second are not covered with the insulating pattern of the semiconductor layer, the second Of removing the insulating pattern, by selectively oxidizing the semiconductor layer to the first insulating pattern as a mask, the source region and a part adjacent to the said channel in the width direction of the channel between the drain region Including a step of forming a sidewall insulating film on the sidewall portion of the semiconductor layer, a step of removing the first insulating pattern, a step of forming a gate insulating film on the surface of the semiconductor layer, and a step on the gate insulating film A method for manufacturing a semiconductor device, comprising: forming a gate electrode pattern from an element isolation region on the insulating layer to forming a source region and a drain region in the semiconductor layer apart from each other. I will provide a.

[Action]
(First and second inventions)
According to the first and second inventions, the thickness of the semiconductor layer in the region which forms the element isolation and is in contact with the element formation region and overlaps at least the region where the gate electrode pattern is wired is reduced. Then, by oxidizing this, an element isolation region is formed. Thereby, it is possible to suppress the formation of bird's beaks during oxidation, and it is possible to prevent a thin semiconductor layer from remaining in this portion. Therefore, the parasitic transistor effect can be eliminated and good cut-off characteristics can be achieved.

  According to the present invention, it is possible to provide an SOI element capable of appropriately setting a threshold and capable of high speed operation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
In the first embodiment, the first invention described above will be described. FIG. 1 is a schematic view showing the structure of an SOI structure MOSFET according to the present invention. FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG.

  As shown in FIG. 1B, a silicon oxide film 142 is formed on a silicon substrate 141, and an island-like single crystal silicon region 145 is formed on the silicon oxide film 142. Further, as shown in FIG. 1A, before the LOCOS oxidation is performed, the SOI layer in the hatched region of the region where the wiring region 144 of the gate electrode and the element isolation region 143 overlap is thinly formed in advance. It becomes. Here, the thinned region may extend over the entire circumference of the island-shaped single crystal silicon region 145. As shown in FIG. 1B, in the region where the SOI layer is thinned, when the element isolation is formed by the LOCOS method, the element isolation oxide film 143a becomes thin and the film thickness becomes substantially constant. The beak is suppressed. Therefore, the parasitic transistor as shown in FIG. Therefore, an excellent subthreshold characteristic can be realized only by a normal simple LOCOS process. Naturally, a thick oxide film is obtained in other element isolation regions.

The invention of this embodiment can of course be applied to an element in which the SOI layer in the entire element isolation region is thinned. This is also effective from the viewpoint of improving the threshold characteristics. However, since the element isolation oxide film is thinned as a whole, there is a concern that the parasitic capacitance between the wiring and the substrate increases, and the high speed inherent in the SOI device cannot be sufficiently exhibited.
For this reason, it is desirable to reduce the thickness locally as shown in FIG. 1 from the viewpoint of speeding up.

  When the SOI film thickness before element isolation is set to about 1100 A (angstrom, the same applies hereinafter), it can be seen that hump characteristics are observed, and therefore the thickness of the SOI layer to be thinned is at least 1000 A or less. It is desirable. However, this value is considered to increase and decrease depending on the conditions of LOCOS oxidation, and may be optimized as appropriate depending on the case.

FIG. 2 is a characteristic diagram showing IV characteristics of the SOI element according to the present invention. The thickness of the thinned SOI layer is about 500 A, and the width of the region where the SOI layer is thinned is 0.5 μm. The conditions for element isolation are the same as those for the element shown in FIG. It can be seen that by providing a thinned SOI layer, the parasitic transistor effect can be eliminated, the hump characteristic is not seen, and the subthreshold characteristic is drastically improved. Therefore, it is possible to obtain a good cut-off characteristic according to the present invention. Note that the width of the region where the SOI layer is thinned does not need to be larger than 0.5 μm from the viewpoint of miniaturization.

  FIG. 3 is a process cross-sectional view illustrating a method of manufacturing the SOI structure MOSFET according to the present invention shown in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals. First, as shown in FIG. 3A, a region of the SOI layer (single crystal silicon film) 146 on the silicon oxide film 142 to be thinned is patterned to form a step 146a in the SOI layer 146. As a method of shaving silicon, in addition to a method using ordinary CDE (chemical dry etching) or RIE (reactive ion etching), a method of oxidizing silicon and removing the oxide film is effective. .

  Thereafter, as shown in FIG. 3B, selective oxidation is performed using a LOCOS method using a normal MOS process, and an element isolation region (element isolation oxide film) 143 is formed. At this time, an element isolation oxide film 143a having a substantially constant film thickness is formed in a region adjacent to the island-like single crystal silicon region 145, thereby suppressing bird's beaks. Further, a gate electrode wiring is formed in the wiring region 144 of the gate electrode, and a source / drain region (not shown) is formed.

FIG. 4 is a process cross-sectional view showing a reference example of a method of manufacturing the conventional thin film SOI structure MOSFET shown in FIG. First, as shown in FIG. 4A, an SOI substrate in which a silicon oxide film 172 is formed on a silicon substrate 171 and an SOI layer (single crystal silicon film) 176 is formed on the silicon oxide film 172 is prepared. In the SOI layer 176, the source / drain regions, the channel formation region, and the peripheral region thereof are selectively thinned. As a result, a step 176a is formed in the SOI layer 176. Note that only a channel region and a region adjacent to the channel region in the channel width direction (a direction perpendicular to the direction connecting the source region and the drain region) may be selectively thinned.

Thereafter, the cross-sectional structure shown in FIG. 9 can be obtained in the same manner as the step shown in FIG .

  According to the manufacturing method described above, the above-described effects can be obtained, and an element with an extremely thin SOI layer in the channel region can be manufactured. It is generally known that the short channel effect is improved when the SOI layer in the channel region is thinned. Therefore, this manufacturing method is very effective from the viewpoint of miniaturization of SOI elements.

(Second Embodiment)
In the second embodiment, the above-described second invention will be described. FIG. 5 is a schematic diagram showing the structure of a MOSFET having an SOI structure according to the present invention. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line AA ′ of FIG.

  As shown in FIG. 5B, a silicon oxide film (also referred to as an element isolation region) 182 is formed on the silicon substrate 181, and an island-shaped single crystal silicon region 185 is formed on the silicon oxide film 182. ing. Further, as shown in FIG. 5A, a thin sidewall oxide film (element isolation oxide film) 181a having a substantially constant film thickness is selectively formed in a hatched region surrounding the island-shaped single crystal silicon region 185. Is formed. Here, the thin sidewall oxide film 181a may be selectively provided on the sidewall portion of the island-like single crystal silicon region 185 adjacent to the channel region in the channel width direction. Reference numeral 184 denotes a gate electrode wiring region (gate electrode wiring).

  In the SOI MOSFET having the structure shown in FIG. 5 as well, as in the first embodiment, the SOI layer in the element isolation formation region adjacent to the element formation region is thinned in advance before the LOCOS oxidation. The For this reason, the element isolation oxide film 181a obtained by oxidation is thin, and its film thickness is substantially constant, so that bird's beak is suppressed. For this reason, parasitic transistors are hardly generated, and excellent subthreshold characteristics can be realized. Note that the SOI layers in other element isolation regions are all removed in advance before the LOCOS oxidation. According to this structure, the same effect as that of the SOI MOSFET having the structure shown in FIG. 1 can be obtained, and there is an advantage that microfabrication is relatively easy.

  FIG. 6 is a process sectional view showing a method of manufacturing the SOI structure MOSFET according to the present invention shown in FIG. The same parts as those in FIG. 5 are denoted by the same reference numerals. First, as shown in FIG. 6A, the surface of the SOI layer (single crystal silicon film) 186 on the silicon oxide film 182 is oxidized to form a silicon oxide film 187, and then LPCVD is formed on the silicon oxide film 187. A silicon nitride film 188 is deposited by the method, and a silicon oxide film 189a is deposited on the entire surface of the silicon nitride film 188 by the CVD method.

  Thereafter, a resist pattern (not shown) is formed on the element formation region, and the silicon oxide film 189a, the silicon nitride film 188, and the silicon oxide film 187 are sequentially patterned using the resist pattern as a mask, so that the SOI layer in the element isolation region is formed. 186 is exposed, and the SOI layer 186 is further thinned. As a result, a step 186 a is formed in the SOI layer 186.

  Next, as shown in FIG. 6B, a silicon oxide film 189b is deposited on the entire surface by a CVD method. Then, the silicon oxide film 189b is selectively left on the side wall portion of the laminated film including the silicon oxide film 187, the silicon nitride film 188, and the silicon oxide film 189a by anisotropic etching. Further, the exposed SOI layer 186 is removed using the silicon oxide film 189a and the silicon oxide film 189b as a mask.

Next, as shown in FIG. 6C, the silicon oxide film 189a and the silicon oxide film 189b are removed, and LOCOS oxidation is performed using the silicon nitride film 188 as a mask. By this oxidation process, the SOI layer 186 existing under the silicon oxide film 189b is selectively oxidized to form a silicon oxide film 181a. Further, the silicon nitride film 188 and the silicon oxide film 187 are removed, and a gate insulating film, a gate electrode wiring 184, and source / drain regions are formed.

Also by the method according to the present embodiment, a thin side wall oxide film (element isolation oxide film) 18 having a substantially constant film thickness is formed adjacent to the silicon region 185 on the side wall portion of the island-like single crystal silicon region 185.
Since 1a is selectively formed, bird's beak is suppressed.

(Third embodiment)
In the third embodiment, a reference example of a thin film SOI element will be described. FIG. 7 is a schematic diagram showing a reference example of the structure of an SOI structure MOSFET . 7A is a plan view thereof, FIG. 7B is a cross-sectional view taken along the line AA ′ of FIG. 7A, and FIG. 7C is a cross-sectional view taken along the line BB ′ of FIG.

  As shown in FIGS. 7B and 7C, a silicon oxide film (also referred to as an element isolation region) 702 is formed on a silicon substrate 701, and an island-shaped single crystal is formed on the silicon oxide film 702. A silicon region 703 is formed. A silicon oxide film 704 is embedded between the island-like single crystal silicon regions 703. Further, source / drain regions 706a and 706b are formed on the surface of the island-like single crystal silicon region.

  The source / drain regions 706a and 706b are provided separately from the outer edge of the island-like single crystal silicon region 703, and on the outer edge of the island-like single crystal silicon region 703 and the source / drain regions 706a. , 706b, a gate electrode 705 is formed via a gate insulating film 704 ′. That is, the gate electrode 705 is shaped so as to surround the source / drain regions 706a and 706b, while the channel region formed between the source / drain regions 706a and 706b is the island-shaped single crystal silicon region 703. It is provided separately from the outer edge. Further, a silicon oxide film 707 is formed thereon as an interlayer insulating film, and contact holes for opening source / drain regions 706a and 706b are formed in the silicon oxide film 707, and buried in the inside thereof. An electrode 708 is formed.

  According to the invention of this embodiment, the channel region is formed in the island-like single crystal silicon region 703 on the silicon oxide film (also serving as the element isolation region) 702 so as to be isolated from the outer edge portion of the silicon region 703. Therefore, the channel region is formed avoiding the outer edge where the parasitic transistor is likely to be generated. Therefore, the parasitic transistor effect can be eliminated and good cut-off characteristics can be achieved.

(Fourth embodiment)
In the fourth embodiment, another reference example of the thin film SOI element will be described. The MOSFET element of the SOI structure of the reference example has the following configuration. That is, a silicon oxide film (also serving as an element isolation region) is formed on the silicon substrate, and an island-like single crystal silicon region is formed on the silicon oxide film. A silicon oxide film is buried between the island-like single crystal silicon regions. A source / drain region is formed on the surface of the island-like single crystal silicon region.

  On the source / drain regions, a gate electrode is formed in a donut shape via a gate insulating film. The shape of the gate electrode is not limited to an annular shape such as a donut shape, but may be a square shape or other polygonal shape. In short, it may be a closed shape so as to separate the inside and the outside.

  The source / drain regions are formed separately inside and outside the gate electrode. That is, in the element of this embodiment, the channel region under the gate electrode is provided separately from the outer edge portion of the island-shaped single crystal silicon region. Further, a silicon oxide film is formed as an interlayer insulating film on these, and a contact hole opening the source / drain region is formed in this silicon oxide film, and a buried electrode is formed therein. Yes.

  Also according to the invention according to the present embodiment, the channel region is formed in the island-like single crystal silicon region on the silicon oxide film (also serving as the element isolation region) separately from the outer edge portion of the silicon region. The channel region is formed avoiding the outer edge where the transistor is likely to occur. Therefore, the parasitic transistor effect can be eliminated and good cut-off characteristics can be achieved.

  In addition, this invention is not limited to the method of embodiment mentioned above. For example, the SOI layer is formed by the SIMOX method in which oxygen ions are ion-implanted into the silicon substrate, but the SOI layer may be formed by single-crystallizing the polycrystalline silicon film on the silicon oxide layer by a laser beam annealing technique. Good. Further, the SOI layer may be formed by bonding silicon substrates to each other through a silicon oxide film. In addition, various modifications can be made without departing from the scope of the present invention.

1A and 1B are a plan view and a cross-sectional view showing a structure of a thin film SOI element according to a first embodiment of the present invention. The characteristic view which shows the electrical property of the thin film SOI element which concerns on the 1st Embodiment of this invention. FIG. 6 is a process cross-sectional view illustrating another method for manufacturing the thin-film SOI element according to the first embodiment of the present invention. Process sectional drawing which shows the reference example of the manufacturing method of the conventional thin film SOI element. The top view and sectional drawing which show the structure of the thin film SOI element which concerns on the 2nd Embodiment of this invention. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the thin film SOI device of FIG. 5. The top view and sectional drawing which show the structure of the thin film SOI element which concerns on 3rd Embodiment . The characteristic view which shows the electrical property of the conventional thin film SOI element. Sectional drawing which shows the structure of the conventional thin film SOI element.

Explanation of symbols

  141: silicon substrate, 142: silicon oxide film, 145: single crystal silicon region, 144: wiring region, 143: element isolation region

Claims (7)

  An insulating layer; a semiconductor layer formed in an island shape in an element formation region on the insulating layer; a source region and a drain region formed apart from the semiconductor layer; and a channel between the source region and the drain region. A gate insulating film formed on the surface of the semiconductor layer, and an isolation region formed on the element isolation region on the insulating layer and including a portion adjacent to the channel in the width direction of the channel. An element isolation insulating film having a substantially constant film thickness in the region and having a film thickness larger than the film thickness in a peripheral region of the region having the substantially constant film thickness; and the element from above the gate insulating film And a gate electrode pattern formed over the isolation insulating film.   2. The semiconductor device according to claim 1, wherein the region having the substantially constant film thickness is a region of a side wall portion around the entire semiconductor layer.   2. The semiconductor device according to claim 1, wherein the region having a substantially constant film thickness is selectively formed in a region of a side wall portion of the semiconductor layer located in the width direction of the channel. The semiconductor device according to claim 1 , wherein a width between the semiconductor layer and the outer peripheral region in the region having the substantially constant film thickness is 0.5 μm or less. A step of selectively oxidizing an element isolation scheduled region of the semiconductor layer on the insulating layer to form an element isolation insulating film, leaving the semiconductor layer in an island shape in the element formation region, and a gate on the surface of the semiconductor layer Forming an insulating film; forming a gate electrode pattern from the gate insulating film to the element isolation insulating film; and forming a source region and a drain region apart from each other in the island-like semiconductor layer And selectively etching only the semiconductor layer in a region that becomes a side wall portion of the entire periphery of the semiconductor layer to be left in the island shape before selectively oxidizing the element isolation scheduled region of the semiconductor layer. A method for manufacturing a semiconductor device, comprising: a step of reducing the thickness of the semiconductor layer in this region. A step of selectively oxidizing an element isolation scheduled region of the semiconductor layer on the insulating layer to form an element isolation insulating film, leaving the semiconductor layer in an island shape in the element formation region, and a gate on the surface of the semiconductor layer Forming an insulating film; forming a gate electrode pattern from the gate insulating film to the element isolation insulating film; and forming a source region and a drain region apart from each other in the island-like semiconductor layer A sidewall portion of the semiconductor layer that is positioned in the width direction of the channel between the source region and the drain region and remains in the island shape before selectively oxidizing the element isolation scheduled region of the semiconductor layer A method of manufacturing a semiconductor device, comprising: a step of selectively etching only the semiconductor layer in a region to be reduced to reduce the thickness of the semiconductor layer in this region. A method for manufacturing a semiconductor device, wherein a source region and a drain region are formed in an island-shaped semiconductor layer on an insulating layer, and a gate electrode pattern is formed on the semiconductor layer, the semiconductor device being formed on the insulating layer Forming a first insulating pattern selectively in an island shape on the layer, and etching the semiconductor layer using the first insulating pattern as a mask, thereby covering the semiconductor layer with the first insulating pattern. Etching the semiconductor layer using the first and second insulating patterns as a mask, reducing the thickness of the unexposed portion, forming a second insulating pattern on a sidewall of the first insulating pattern, and by the steps of selectively removing the first and part of the second are not covered with the insulating pattern of the semiconductor layer, removing the second insulating pattern before By selectively oxidizing the semiconductor layer a first insulating pattern as a mask, the sidewall insulating side wall portion of said semiconductor layer including a portion adjacent to the channel in the width direction of the channel between the source region and the drain region A step of forming a film, a step of removing the first insulating pattern, a step of forming a gate insulating film on the surface of the semiconductor layer, and an element isolation region on the insulating layer from the gate insulating film A method for manufacturing a semiconductor device, comprising: forming a gate electrode pattern; and forming a source region and a drain region in the semiconductor layer so as to be separated from each other.

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