KR20070095062A - Fin fet and method for fabricating the same - Google Patents

Abstract

A fin field effect transistor and its manufacturing method are provided to increase the mobility of a carrier by enclosing an active pattern with a stress inducing layer. An active pattern(105) protrudes from a surface of a semiconductor substrate(100), and extends in a first direction, and a first hard mask pattern(120) is formed on the active pattern. An isolation film(140) is formed on the substrate in such a way that a portion of the active pattern protrudes. A stress inducing layer(130) is disposed between the isolation film and the active pattern. A gate structure(165) extends in a second direction to enclose the protruded portion of the active pattern and the first hard mask pattern.

Description

Fin field effect transistor and its manufacturing method {F FET and method for fabricating the same}

1 is a perspective view of a fin field effect transistor according to an embodiment of the present invention.

2A to 2H are perspective views illustrating a method of manufacturing the fin field effect transistor of FIG. 1.

3A to 3G are cross-sectional views illustrating a method of manufacturing a fin field effect transistor, taken along line III-III of FIG. 1.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 105 active pattern

120, 170: hard mask pattern 130: stress-inducing layer

140: device isolation layer 150: gate insulating film

160: gate electrode pattern 165: gate structure

181, 185: source and drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a fin field effect transistor and a method of manufacturing the same, which induce stress and increase driving capability.

The size of the system using silicon semiconductor technology is becoming smaller and the device size is smaller while requiring low power consumption. As a result, the gate size of the transistor continues to decrease, causing problems such as a short channel effect. MOS transistor manufacturing technology using a bulk silicon substrate has a limit to high integration of the MOS transistor, and research on the MOS transistor using the SOI substrate is being actively conducted. However, in the MOS transistor using the SOI substrate, since the body silicon is floated without being connected to the substrate, there is a problem in that the performance of the device is deteriorated due to poor floating body effect and thermal conductivity.

Recently, a fin field effect transistor (FinFET) has been proposed as a double gate transistor in which gates exist on both sides of a channel. In the fin field effect transistor, since gate electrodes exist on both sides of a channel through which current flows, the control characteristics of the channel by the gate electrode can be improved. In the fin field effect transistor, when the control characteristic of the channel by the gate electrode is large, the leakage current between the source and the drain can be greatly improved as compared with the conventional single gate transistor, thereby improving the drain induced barrier leakage (DIBL) characteristics. can do. In addition, since gate electrodes exist on both sides of the channel to dynamically change the threshold voltage of the device, the on-off characteristic of the channel can be improved compared to the conventional single gate transistor and the short channel effect can be suppressed.

However, the fin field-effect transistor has also been limited in improving the current driving capability due to the inherent mobility characteristics of the silicon constituting the fin as the size of the device is gradually reduced with high integration.

Accordingly, it is an object of the present invention to provide a fin field effect transistor and a method of manufacturing the same, which induce stress and improve current driving capability.

In order to achieve the above technical problem of the present invention, the present invention provides a fin field effect transistor. The active pattern protrudes from the surface of the semiconductor substrate to extend in the first direction, and a first hard mask pattern is formed on the active pattern. An isolation layer is formed on the semiconductor substrate so that a portion of the active pattern protrudes. A stress inducing layer is arranged between the device isolation layer and the active pattern. The gate structure extends in a second direction while surrounding the protrusion of the active pattern and the first hard mask pattern.

The stress inducing layer is a material having a larger lattice constant than the active pattern, and includes SiGe or SiGeC.

The present invention also provides a method for manufacturing a fin field effect transistor. First, a pad oxide film and a first hard mask pattern extending in a first direction are formed on a semiconductor substrate. The semiconductor substrate is etched using the first hard mask pattern to form an active pattern protruding from the surface of the semiconductor substrate and extending in the first direction. A stress inducing layer and an isolation layer surrounding the active pattern are formed on the semiconductor substrate so that a portion of the active pattern and the first hard mask pattern are exposed. Subsequently, a gate structure extending in a second direction is formed to surround the protruding portion of the active pattern and the first hard mask pattern.

The stress inducing layer and the device isolation layer may be formed by first growing the stress inducing layer to surround the active pattern, forming an insulating layer to fill the etched portion of the semiconductor substrate, and then exposing the stress inducing layer. The insulating film is etched until the insulating film is etched. Subsequently, the stress inducing layer and the device isolation layer are etched to expose the portion of the active pattern and the first hard mask pattern.

In forming the gate structure, first, a gate insulating layer is formed on both sides of a portion of the exposed active pattern, and a gate electrode layer is formed to cover the gate insulating layer and the first hard mask pattern. A hard mask layer is formed on the gate electrode layer. Subsequently, the gate insulating layer, the gate electrode layer, and the hard mask layer are etched to form a gate structure including the gate insulating layer, the gate electrode pattern extending in the second direction, and the second hard mask pattern.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

1 is a perspective view of a fin field effect transistor according to an embodiment of the present invention. Referring to FIG. 1, the active pattern 105 is integrated with the semiconductor substrate 100 to protrude from the surface of the substrate. The active pattern 105 is arranged to extend in a first direction. The pad oxide layer 110 and the hard mask pattern 120 are formed on the active pattern 105. The hard mask pattern 120 not only maintains insulation from the gate structure 165, but also protects source and drain regions 181 and 185 formed in the active pattern 105.

An isolation layer 140 is formed on the semiconductor substrate 100 to separate the active pattern 105. The device isolation layer 140 is formed only up to a predetermined height of the active pattern 105, and a portion of the active pattern 105 protrudes from the device isolation layer 140. A portion of the active pattern 105 protruding from the device isolation layer 140 corresponds to the height of the channel.

A gate structure 165 extending in the second direction is formed to surround the active pattern 105, the pad oxide layer 110, and the hard mask pattern 120 protruding from the device isolation layer 140. The gate structure 165 may include a gate insulating layer 150 formed on both sidewalls of the active pattern 105, the gate insulating layer 150, the active pattern 105, a pad oxide layer 110, and a hard mask pattern 120. The gate electrode pattern 160 extending in the second direction and surrounding the gate electrode 160 and the hard mask pattern 170 formed on the gate electrode pattern 160 are provided.

Source and drain regions 181 and 185 in which impurities of a predetermined conductivity type are implanted are formed in the protruding portions of the active pattern 105 at both sides of the gate structure 165. The stress inducing layer 130 is disposed between the device isolation layer 140 and the active pattern 105 surrounded by the device isolation layer 140. The stress inducing layer 130 includes a material having a lattice constant different from silicon of the active pattern 105, for example, a lattice constant larger than silicon. The stress inducing layer 130 may include SiGe or SiGeC. Since the active pattern 105 separated by the device isolation layer 140 is surrounded by the stress inducing layer 130, the carrier mobility of the active pattern 105 is applied by applying stress to the active pattern 105. Improves. In this case, when the source and drain regions 181 and 185 formed in the active pattern 105 are n-type impurity regions, the stress-inducing layer 130 applies tensile stress to the active pattern 105. Therefore, the mobility of electrons is increased, and in the case of p-type impurity regions, compressive stress is applied to increase the mobility of holes.

2A to 2H are perspective views illustrating a method of manufacturing the fin field effect transistor illustrated in FIG. 1. 3A to 3G are cross-sectional views illustrating a method of manufacturing a fin field effect transistor, taken along line III-III of FIG. 1.

2A and 3A, the pad oxide layer 110 and the hard mask layer are sequentially formed on the silicon substrate 100. The pad oxide layer 110 may be formed by thermally oxidizing the silicon substrate 100 or may be formed by depositing a CVD oxide layer. The hard mask layer includes a nitride film. After forming a photoresist pattern (not shown) on the hard mask layer, the hard mask layer and the pad oxide layer 110 are patterned using the photoresist pattern. Thus, the hard mask pattern 120 extending in the first direction is formed.

After removing the photoresist pattern, the silicon substrate 100 is dry-etched by a predetermined thickness using the hard mask pattern 120 as a mask. Therefore, the silicon substrate 100 is integrated with the silicon substrate 100 to form an active pattern 105 protruding from the silicon substrate 100 and extending in the first direction. In this case, instead of the silicon substrate 100, a silicon-on-insulator (SOI) substrate having a support substrate, an investment oxide layer, and an active pattern may be used.

 2B and 3B, the stress inducing layer 130 is grown to surround the active pattern 105, the pad oxide layer 110, and the hard mask pattern 120. The stress inducing layer 130 may include a single crystal SiGe film or a SiGeC film having a larger lattice constant than the active pattern 105 made of silicon.

2C and 3C, an isolation layer 140 is formed by depositing an insulating film on the silicon substrate 100 to fill the etched portion to form the active pattern 105, and then performing a CMP process or the like. do. In this case, the CMP process of the insulating film is performed until the stress inducing layer 130 is exposed. The device isolation layer 140 may include an HDP oxide film, an SOG-based insulating film, or a CVD oxide film. When the interval between neighboring active patterns 105 is minute, it is preferable to use SOG series TOSZ.

Although not shown in the drawing, before forming the device isolation layer 140, a liner made of a silicon nitride layer may be formed on sidewalls of the active pattern 105 to prevent oxidation of the active pattern 105. In addition, the side well oxide layer 120 may be formed between the liner and the active pattern 105 to relieve stress between the liner and the active pattern 105.

2D and 3D, the device isolation layer 140 and the stress-inducing layer 130 are etched by a predetermined thickness through an etch back process or the like, so that the active pattern 105 is removed from the device isolation layer 140. Protrude to a certain thickness. Therefore, a portion of the active pattern 105, the pad oxide layer 110, and the hard mask pattern 120 are exposed.

2E and 3E, gate insulating layers 150 are formed on both side surfaces of the active pattern 105 protruding from the device isolation layer 140. The gate insulating layer 150 may be formed by thermally oxidizing the exposed side surface of the active pattern 105 or by depositing a CVD oxide layer. Before the gate insulating layer 150 is formed, channel doping may be performed with the protruding active pattern 105.

2F and 3F, the gate electrode layer 160a is deposited on the device isolation layer 140 to cover the gate insulating layer 150 and the hard mask pattern 120, and then planarized by performing a CMP process or the like. Let it be. The hard mask layer 170a is formed on the gate electrode layer 160a. The pad oxide layer 110 and the hard mask pattern 120 may be removed before the gate electrode layer 160a is formed. The gate electrode layer 160a may be formed of a multilayer film, and the lower layer may include a polycrystalline silicon film, a polycrystalline silicon germanium, a doped polycrystalline silicon film, or a doped polycrystalline silicon germanium, and the upper layer may be a tungsten silicide film or nickel. Or a silicide film or a titanium silicide film. A tungsten film, tungsten nitride film, molybdenum film, or the like may be further formed on the upper film layer. The hard mask layer 170a may include a nitride film.

2G and 3G, a photoresist pattern (not shown) is formed on the hard mask layer 170a, and the hard mask layer 170a and the gate electrode layer are formed using the photoresist pattern. The gate structure 165 is formed by patterning the 160a and the gate insulating layer 150. In this case, only the hard mask layer 170a and the gate electrode layer 160a may be patterned during the patterning process for forming the gate structure 165.

The gate structure 165 extends in a second direction while surrounding the active pattern 110 and the hard mask pattern 115 protruding from the device isolation layer 140. The gate structure 165 may include a gate insulating layer 150 formed on both sidewalls of the active pattern 105, the gate insulating layer 150, the active pattern 105, a pad oxide layer 110, and a hard mask pattern 120. The gate electrode pattern 160 extending in the second direction and enclosing the hard mask pattern 170 is formed on the gate electrode pattern 160.

Referring to FIG. 2H, the photoresist pattern is removed, and then the impurity 190 of a predetermined conductivity type is implanted into the protrusion of the active pattern 105 not overlapping with the gate structure 150 to form the gate structure 165. Source and drain regions 181 and 185 are formed on both sides of the substrate.

As described in detail above, the fin field effect transistor of the present invention and a method of manufacturing the same are formed by forming an active pattern made of silicon so as to surround a stress-inducing layer having a large lattice constant, thereby applying a stress to the active pattern, thereby allowing carrier mobility. Can increase Accordingly, the current driving capability can be improved in the high integration device.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (9)

Semiconductor substrates; An active pattern protruding from a surface of the semiconductor substrate and extending in a first direction; A first hard mask pattern formed on the active pattern; An isolation layer formed on the semiconductor substrate and formed to protrude a portion of the active pattern; A stress inducing layer arranged between the device isolation layer and the active pattern; And And a gate structure extending in a second direction while surrounding the protruding portion of the active pattern and the first hard mask pattern. The fin field effect transistor of claim 1, wherein the stress inducing layer comprises a material having a larger lattice constant than the active pattern. 3. The fin field effect transistor of claim 2, wherein the stress inducing layer comprises SiGe or SiGeC. The method of claim 1, wherein the gate structure Gate insulating layers formed on both sides of the protruding portion of the active pattern; A gate electrode pattern extending in the second direction to surround the gate insulating layer and the first hard mask pattern; And And a second hard mask pattern formed on the gate electrode pattern. Forming a pad oxide layer and a first hard mask pattern extending in a first direction on the semiconductor substrate; Etching the semiconductor substrate using the first hard mask pattern to form an active pattern protruding from a surface of the semiconductor substrate and extending in a first direction; Forming a stress inducing layer and an isolation layer surrounding the active pattern on the semiconductor substrate to expose a portion of the active pattern and a first hard mask pattern; And And forming a gate structure extending in a second direction while surrounding the protruding portion of the active pattern and the first hard mask pattern. The method of claim 5, wherein the stress inducing layer comprises a material having a larger lattice constant than the active pattern. The method of claim 6, wherein the stress inducing layer comprises SiGe or SiGeC. The method of claim 5, wherein the forming of the stress inducing layer and the device isolation layer is performed. Growing the stress inducing layer to surround the active pattern; Forming an insulating layer to fill the etched portion of the semiconductor substrate; Etching the insulating film until the stress inducing layer is exposed; And And etching the stress-inducing layer and the device isolation layer to expose the portion of the active pattern and the first hard mask pattern. The method of claim 5, wherein forming the gate structure Forming gate insulating layers on both sides of a part of the exposed active pattern; Forming a gate electrode layer covering the gate insulating layer and the first hard mask pattern; Forming a hard mask layer on the gate electrode layer; And Etching the gate insulating layer, the gate electrode layer, and the hard mask layer to form a gate structure including the gate insulating layer, the gate electrode pattern extending in the second direction, and the second hard mask pattern. Method for manufacturing a fin field effect transistor.

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