CN111048524A - Array substrate, preparation method and display panel - Google Patents
Array substrate, preparation method and display panel Download PDFInfo
- Publication number
- CN111048524A CN111048524A CN201911171222.9A CN201911171222A CN111048524A CN 111048524 A CN111048524 A CN 111048524A CN 201911171222 A CN201911171222 A CN 201911171222A CN 111048524 A CN111048524 A CN 111048524A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- gate
- active layer
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The array substrate at least comprises a substrate, an active layer, a grid insulating layer, a grid layer, an interlayer insulating layer and a source drain, wherein the active layer is formed on the substrate; the projection area of the grid layer on the substrate is positioned in the projection area of the active layer on the substrate. Through the mode, the parasitic channel can be eliminated, and therefore the hump phenomenon is eliminated.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method and a display panel.
Background
A top gate type thin film field effect transistor generally includes a substrate, an IGZO (indium gallium zinc oxide) active layer, a gate insulating layer, a gate electrode layer, and source and drain electrodes. In addition, the top gate type thin film transistor is usually formed by a self-aligned process in the manufacturing process, that is, a channel is automatically formed along with the photoetching of a gate, but the edge of an IGZO active layer is covered by a gate layer to form a parasitic channel, so that the thin film transistor has an abnormal drift phenomenon, and a Hump (Hump) phenomenon is formed.
The reason for the generation of the parasitic channel is analyzed to be that the electric field of the nearby area is abnormally increased due to the irregularity of the wet etching on the edge of the IGZO active layer in the preparation process, so that the parasitic channel is formed.
Disclosure of Invention
The application provides an array substrate, a preparation method and a display panel, which can solve the problem that in the prior art, a conductive channel region in a top gate type thin film transistor comprises an irregular source layer edge region, so that a parasitic channel is generated to cause a hump phenomenon.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing an array substrate, wherein the array substrate at least comprises a substrate base plate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer insulating layer and a source drain electrode, the active layer is formed on the substrate base plate, the grid electrode insulating layer, the grid electrode layer and the interlayer insulating layer are sequentially stacked on the active layer from bottom to top, a first through hole and two second through holes are formed in the interlayer insulating layer, and the source drain electrode is connected with the active layer through the two second through holes; wherein a projection area of the gate layer on the substrate is located in a projection area of the active layer on the substrate.
The array substrate further comprises a grid signal line layer, and the grid signal line layer is connected with the grid layer through the first through hole.
The active layer is made of indium gallium zinc semiconductor oxide and comprises a semiconductor layer and a doped semiconductor layer, and the grid insulation layer and the grid layer are formed on the semiconductor layer.
The thin film transistor further comprises a light shielding layer and a buffer layer which are sequentially formed between the substrate and the active layer.
Wherein, the array substrate still includes: the passivation layer covers the source and drain electrodes and the grid signal line layer, and a third through hole is formed in the passivation layer; and the pixel electrode is formed on the passivation layer and is connected with the source and drain electrodes through the third through hole.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a method for preparing an array substrate, the method comprising: forming a patterned active layer on a base substrate; sequentially forming a gate insulating layer and a gate electrode layer on the active layer, wherein the projection area of the gate electrode layer on the substrate is positioned in the projection area of the active layer on the substrate; conducting a conductor treatment on the active layer which is not covered by the gate insulating layer and the gate layer; depositing an interlayer insulating layer on the active layer, and patterning the interlayer insulating layer to form a first via hole and two second via holes; and depositing a metal layer on the interlayer insulating layer, and patterning the metal layer to form a source drain, wherein the source drain is connected with the active layer through the two second via holes.
The preparation method further comprises the step of patterning the metal layer and simultaneously forming a grid signal line layer, wherein the grid signal line layer is connected with the grid layer through the first through hole.
Wherein, the preparation method further comprises the following steps: depositing a passivation layer on the metal layer, and patterning the passivation layer to form a third via hole; and forming a patterned pixel electrode on the passivation layer, wherein the pixel electrode is connected with the source and drain electrodes through the third through hole.
Wherein the forming a patterned active layer on the base substrate further comprises: forming a patterned light-shielding layer on the substrate; depositing a buffer layer on the light-shielding layer.
In order to solve the above technical problem, another technical solution adopted by the present application is: a display panel is provided, wherein the display panel comprises the array substrate or the array substrate prepared by any preparation method.
The beneficial effect of this application is: different from the prior art, the application provides an array substrate, a manufacturing method thereof and a display panel, wherein the projection area of the gate layer on the substrate is set to be located in the projection area of the active layer on the substrate (namely, the width of the active layer is set to be larger than that of the gate layer), so that the irregular area of the edge of the active layer is not included in the conductive channel area in the thin film transistor, a parasitic channel is eliminated, and a hump phenomenon is eliminated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic flow chart illustrating an embodiment of a method for fabricating an array substrate according to the present application;
FIG. 2 is a schematic flow chart illustrating the fabrication of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic view of another structure of an embodiment of an array substrate of the present application;
FIG. 4 is a schematic structural diagram of an embodiment of an array substrate according to the present application;
fig. 5 is a schematic structural diagram of an embodiment of a display panel according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a method for manufacturing an array substrate according to the present application, the method including the following steps:
and S100, forming a patterned active layer on the substrate.
With further reference to fig. 2, fig. 2 is a schematic view of a manufacturing process of an embodiment of the array substrate of the present application. Referring to fig. 2, a substrate 100 is first provided, and the substrate 100 may be made of a transparent material, and specifically may be any type of substrate such as glass, a ceramic substrate, a transparent plastic, and a polyimide flexible substrate, which is not limited in this application.
Optionally, before forming the active layer on the substrate, the method further includes performing processes such as photoresist coating, exposing, developing, etching, and photoresist stripping on the substrate 100 to form the patterned light shielding layer 110. In practical applications, the light-shielding layer 110 is an unnecessary functional pattern, and can prevent the backlight source below the substrate 100 from directly illuminating the source region and the drain region, thereby affecting the performance of the source region and the drain region.
Further, in order to ensure the subsequent film forming effect, a buffer layer (buffer) 120 is deposited on the light-shielding layer 110, wherein the buffer layer 120 is made of at least one of silicon nitride (SiNx) and silicon dioxide (SiO 2). Of course, other materials may be used and the application is not limited specifically.
Optionally, a patterned active layer 130 is formed on the buffer layer 120.
The active layer 130 may be made of indium gallium zinc oxide. Specifically, a thin film of indium gallium zinc oxide is deposited on the buffer layer 120, followed by processes of photoresist coating, exposure, development, etching, and photoresist stripping to form the patterned active layer 130. Of course, in other embodiments, the material of the active layer 130 may also be selected to be InGaZnO.
And S200, sequentially forming a gate insulating layer and a gate electrode layer on the active layer, wherein the projection area of the gate electrode layer on the substrate is positioned in the projection area of the active layer on the substrate.
Further referring to fig. 2, the gate insulating layer 140 serves to isolate and insulate the gate layer 150. Alternatively, the gate insulating layer 140 and the gate layer 150 are sequentially formed on the active layer 130. The gate insulating layer 140 may be a silicon oxide (SiO2) film layer or a silicon nitride (SiNx) film layer, or a stack of a silicon oxide (SiO2) and a silicon nitride (SiNx), which is not limited herein. The material of the gate layer 150 may be a stack of multiple layers of metals, such as: it can be a stack of Ti/Al/Ti multi-layer metals, or a stack of Mo/Al/Mo multi-layer metals, and of course, the gate layer 150 can also include only one metal layer, such as: ti, Mo, Al, etc., are merely two cases of the gate layer 150, and there are many other cases or a multilayer metal stacked structure, and are not limited herein.
In an embodiment of the present invention, the gate insulating layer 140 and the gate electrode layer 150 may be deposited on the active layer 130, and then a photolithography process is used to pattern the gate insulating layer 140 and the gate electrode layer 150 to expose a portion of the active layer 130.
Of course, in another embodiment of the present invention, a gate insulating layer 150 may be deposited on the active layer 130 by using a Chemical Vapor Deposition (CVD) and photolithography etching processes, and then a metal layer may be deposited on the gate insulating layer 150, followed by photoresist coating, exposing, developing, etching, and photoresist stripping processes to form the gate layer 140 with a predetermined pattern. That is, in this embodiment, two photolithography processes are used to form the patterned gate insulating layer 140 and the gate electrode layer 150.
Optionally, referring to fig. 3, fig. 3 is another schematic structural diagram of an embodiment of the array substrate of the present application, and as shown in fig. 3, a projection area a of the gate layer 150 on the substrate 100 in the present application is located in a projection area B of the active layer 130 on the substrate 100.
Specifically, the projection area is defined to include a first direction X and a second direction Y perpendicular to each other. In this application, the width of the active layer 130 is set to be greater than the width of the gate layer 150 during the process, which is shown in fig. 3 as the width W1 of the projection area B of the active layer 130 on the substrate 100 being greater than the width W2 of the projection area a of the gate layer 150 on the substrate 100, and optionally, the specific values of the width W1 and the width W2 in this application need to be combined with practical applications, and are not further limited herein. Therefore, the irregular edge area of the active layer (IGZO)130 is not included in the conductive channel area of the thin film transistor, so that a parasitic channel is eliminated, and a hump phenomenon is eliminated.
S300, a conductor process is performed on the active layer not covered by the gate insulating layer and the gate layer.
Further, helium (He) or hydrogen (H) is used2) The active layer 130 not covered by the gate insulating layer 140 and the gate layer 150 is subjected to a conductor process, thereby reducing the resistance of Indium Gallium Zinc Oxide (IGZO). Among them, the active layer subjected to the conductor forming process forms the doped semiconductor layer 131, which has a good conductivity, and the semiconductor layer 132 is not subjected to the conductor forming process.
S400, depositing an interlayer insulating layer on the active layer, and patterning the interlayer insulating layer to form a first via hole and two second via holes.
An interlayer Insulating Layer (ILD)160 is optionally deposited on the active layer 130. typically, the ILD 160 in the prior art comprises at least an inorganic layer (not shown) and an organic layer (not shown). The inorganic film layer may be SiOX, SiNX, or Al2O3, and may be formed on the gate layer 150 and the active layer 130 by Physical Vapor Deposition (PVD), Sputtering, or Chemical Vapor Deposition (CVD), where the inorganic film layer serves to increase the conductivity of the active layer structure 130 during the film forming process, and the organic film layer may be an organic photosensitive material, for example: JSR PC405G, TorayDL1001C, or the like, and an organic film layer capable of increasing the thickness of the interlayer insulating layer 160 can be formed by coating, spin coating, or dipping.
Further, the interlayer insulating layer 160 is patterned to form a first via H1 and two second vias H2, and specifically, the first via H1 and the two second vias H2 are formed by using photolithography and etching processes, and specific process flows can refer to specific descriptions in the prior art, which are not described herein again.
S500, depositing a metal layer on the interlayer insulating layer, patterning the metal layer to form a source drain, and connecting the source drain with the active layer through the two second through holes.
Alternatively, a metal layer is deposited on the interlayer insulating layer 160, wherein the material of the metal layer is generally selected from metal aluminum or metal molybdenum. The source electrode S and the drain electrode D are further formed in the same patterning process (photolithography and etching process), and the source electrode S and the drain electrode D of the thin film transistor are located in the same layer in this application. Wherein the source electrode S and the drain electrode D are connected to the active layer 130 through two second vias H2 formed on the interlayer insulating layer 160 in step S400.
In addition, in the present application, the metal layer may be patterned and simultaneously formed with the gate signal line layer 170, and the gate signal line layer 170 may be connected to the gate layer through the first via H2.
In the above embodiment, by setting the projection area of the gate layer on the substrate to be located in the projection area of the active layer on the substrate (i.e. the width of the active layer is set to be greater than the width of the gate layer), and setting the separate gate signal input line above the gate layer to supply signals, the irregular area of the edge of the active layer is not included in the conductive channel area in the thin film transistor, and the parasitic channel is eliminated, thereby eliminating the hump phenomenon.
Specifically, the preparation method of the present application further comprises:
a passivation layer 180 is deposited on the metal layer, and the passivation layer 180 is patterned to form a third via H3, in particular a third via H3, by a photolithographic etching process. The passivation layer 180 may be made of silicon nitride (SiNX).
Further, a patterned pixel electrode 190 is formed on the passivation layer 180, and the pixel electrode 190 is connected to the source and drain electrodes through a third via H3.
In the above embodiment, by setting the projection area of the gate layer on the substrate to be located in the projection area of the active layer on the substrate (i.e. the width of the active layer is set to be greater than the width of the gate layer), and setting the separate gate signal input line above the gate layer to supply signals, the irregular area of the edge of the active layer is not included in the conductive channel area in the thin film transistor, and the parasitic channel is eliminated, thereby eliminating the hump phenomenon.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of an array substrate according to the present application. Referring to fig. 4, the array substrate of the present application includes a substrate 100, an active layer 130, a gate insulating layer 140, a gate layer 150, an interlayer insulating layer 160, and a source/drain S/D.
The substrate 100 may be made of a transparent material, and may specifically be any type of substrate such as glass, a ceramic substrate, a transparent plastic, and a polyimide flexible substrate, which is not limited in this application.
Optionally, the present application further includes a light-shielding layer 110 deposited on the substrate 100 and a buffer layer 120 provided to ensure a subsequent film-forming effect. The buffer layer 120 is made of at least one of silicon nitride (SiNx) and silicon dioxide (SiO 2).
The active layer 130 is formed on the substrate 100, the active layer 130 may be indium gallium zinc oxide, and the active layer 130 that is not covered by the gate insulating layer 140 and the gate layer 150 in the preparation process is subjected to a conductor processing to form the doped semiconductor layer 131, and the semiconductor layer 132 that is not subjected to the conductor processing is the semiconductor layer 132, so as to reduce the resistance of Indium Gallium Zinc Oxide (IGZO).
Alternatively, the gate insulating layer 140, the gate electrode layer 150, and the interlayer insulating layer 160 are sequentially stacked on the active layer 130 from bottom to top.
Further referring to fig. 3, a projection area a of the gate layer 150 on the substrate 100 is located in a projection area B of the active layer 130 on the substrate 100. The projection area is defined to include a first direction X and a second direction Y which are perpendicular to each other. In this application, the width of the active layer 130 is set to be greater than the width of the gate layer 150 during the process, which is shown in fig. 3 as the width W1 of the projection area B of the active layer 130 on the substrate 100 being greater than the width W2 of the projection area a of the gate layer 150 on the substrate 100, and optionally, the specific values of the width W1 and the width W2 in this application need to be combined with practical applications, and are not further limited herein. Therefore, the irregular edge area of the active layer (IGZO)130 is not included in the conductive channel area of the thin film transistor, so that a parasitic channel is eliminated, and a hump phenomenon is eliminated.
Optionally, the interlayer insulating layer 160 is provided with a first via H1 and two second vias H2, and the source and drain S/D are connected to the active layer 130 through the two second vias H2. An interlayer Insulating Layer (ILD)160 is deposited on the active layer 130. typically, the ILD 160 in the prior art comprises at least an inorganic layer (not shown) and an organic layer (not shown). The inorganic film layer may be formed of SiOX, SiNX, or Al2O3, which is used to increase the conductivity of the active layer 130 during the film formation process, and the organic film layer may be formed of an organic photosensitive material, such as: JSR PC405G, TorayDL1001C, or the like, which functions to increase the thickness of the interlayer insulating layer 160. The source electrode S/D is generally made of metal aluminum or metal molybdenum, and the source electrode S and the drain electrode D of the thin film transistor are located in the same layer.
Optionally, the array substrate in this application further includes a gate signal line layer 170, and the gate signal line layer 170 is connected to the gate layer 150 through the first via H1, wherein the gate signal line layer 160 can realize separate supply of gate signals.
Further, the array substrate of the present application further includes:
and the passivation layer 180 covers the source/drain S/D and the gate signal line layer 170, and a third via H3 is formed on the passivation layer 180.
And the pixel electrode 190 is formed on the passivation layer 180, and the pixel electrode 190 is connected with the source drain electrode S/D through the third via H3.
In the above embodiment, by setting the projection area of the gate layer on the substrate to be located in the projection area of the active layer on the substrate (i.e. the width of the active layer is set to be greater than the width of the gate layer), and setting the separate gate signal input line above the gate layer to supply signals, the irregular area of the edge of the active layer is not included in the conductive channel area in the thin film transistor, and the parasitic channel is eliminated, thereby eliminating the hump phenomenon.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a display panel of the present application, where the display panel 200 includes an array substrate C with any structure, and a preparation method and a structure of the array substrate C are described in detail in the foregoing embodiments, and are not repeated herein.
In summary, it is easily understood by those skilled in the art that the present application provides an array substrate, a method for manufacturing the array substrate, and a display panel, in which a projection area of a gate layer on a substrate is set to be located in a projection area of an active layer on the substrate (i.e., a width of the active layer is set to be greater than a width of the gate layer), so that an irregular area of an edge of the active layer is not included in a conductive channel area in a thin film transistor, a parasitic channel is eliminated, and a hump phenomenon is eliminated.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. An array substrate is characterized by at least comprising a substrate base plate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer insulating layer and a source drain electrode, wherein the active layer is formed on the substrate base plate, the grid electrode insulating layer, the grid electrode layer and the interlayer insulating layer are sequentially stacked on the active layer from bottom to top, a first through hole and two second through holes are formed in the interlayer insulating layer, and the source drain electrode is connected with the active layer through the two second through holes;
wherein a projection area of the gate layer on the substrate is located in a projection area of the active layer on the substrate.
2. The array substrate of claim 1, further comprising a gate signal line layer, wherein the gate signal line layer is connected to the gate layer through the first via.
3. The array substrate of claim 1, wherein the active layer is an InGaZn semiconductor oxide comprising a semiconductor layer and a doped semiconductor layer, and the gate insulating layer and the gate layer are formed on the semiconductor layer.
4. The array substrate of claim 1, wherein the thin film transistor further comprises a light-shielding layer and a buffer layer sequentially formed between the substrate and the active layer.
5. The array substrate of claim 1, further comprising:
the passivation layer covers the source and drain electrodes and the grid signal line layer, and a third through hole is formed in the passivation layer;
and the pixel electrode is formed on the passivation layer and is connected with the source and drain electrodes through the third through hole.
6. A preparation method of an array substrate is characterized by comprising the following steps:
forming a patterned active layer on a base substrate;
sequentially forming a gate insulating layer and a gate electrode layer on the active layer, wherein the projection area of the gate electrode layer on the substrate is positioned in the projection area of the active layer on the substrate;
conducting a conductor treatment on the active layer which is not covered by the gate insulating layer and the gate layer;
depositing an interlayer insulating layer on the active layer, and patterning the interlayer insulating layer to form a first via hole and two second via holes;
and depositing a metal layer on the interlayer insulating layer, and patterning the metal layer to form a source drain, wherein the source drain is connected with the active layer through the two second via holes.
7. The method of claim 6, further comprising forming a gate signal line layer while patterning the metal layer, the gate signal line layer being connected to the gate layer through the first via.
8. The method of manufacturing according to claim 7, further comprising:
depositing a passivation layer on the metal layer, and patterning the passivation layer to form a third via hole;
and forming a patterned pixel electrode on the passivation layer, wherein the pixel electrode is connected with the source and drain electrodes through the third through hole.
9. The method of claim 7, wherein the step of forming the patterned active layer on the substrate further comprises:
forming a patterned light-shielding layer on the substrate;
depositing a buffer layer on the light-shielding layer.
10. A display panel comprising the array substrate according to any one of claims 1 to 5 or the array substrate prepared by the preparation method according to any one of claims 6 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911171222.9A CN111048524A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911171222.9A CN111048524A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111048524A true CN111048524A (en) | 2020-04-21 |
Family
ID=70234179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911171222.9A Pending CN111048524A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111048524A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111463267A (en) * | 2020-04-08 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113707692A (en) * | 2021-07-13 | 2021-11-26 | 信利（惠州）智能显示有限公司 | AMOLED display screen manufacturing method and structure |
| WO2022213463A1 (en) * | 2021-04-08 | 2022-10-13 | 深圳市华星光电半导体显示技术有限公司 | Display apparatus and preparation method therefor |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020096684A (en) * | 2001-06-21 | 2002-12-31 | 주식회사 하이닉스반도체 | Gate line structure of transistor |
| JP2004153296A (en) * | 2003-12-24 | 2004-05-27 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
| CN1841781A (en) * | 2005-03-30 | 2006-10-04 | 三星Sdi株式会社 | Thin film transistor, flat panel display device, and method of fabricating the same |
| CN101110435A (en) * | 2006-07-20 | 2008-01-23 | 三菱电机株式会社 | Thin film transistor substrate and method for manufacturing the same |
| US20090294848A1 (en) * | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Semiconductor device having transistor and method of manufacturing the same |
| US20130270553A1 (en) * | 2012-04-17 | 2013-10-17 | Masatoshi Yokoyama | Semiconductor device |
| US20150129854A1 (en) * | 2013-11-14 | 2015-05-14 | Samsung Display Co. Ltd. | Thin-film transistor, method of manufacturing the same, and organic light-emitting diode (oled) display including the same |
| CN105226100A (en) * | 2014-06-27 | 2016-01-06 | 乐金显示有限公司 | The thin-film transistor of display unit |
| CN107452755A (en) * | 2017-07-27 | 2017-12-08 | 武汉天马微电子有限公司 | Array base palte and preparation method thereof and display panel |
| CN107895726A (en) * | 2017-11-30 | 2018-04-10 | 武汉天马微电子有限公司 | A kind of array base palte and preparation method thereof and display device |
| CN108666218A (en) * | 2017-03-29 | 2018-10-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and display base plate and preparation method thereof, display device |
| CN109509793A (en) * | 2017-09-15 | 2019-03-22 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), its manufacturing method and electronic device |
| CN110034189A (en) * | 2018-01-03 | 2019-07-19 | 三星电子株式会社 | Integrated circuit device |
-
2019
- 2019-11-26 CN CN201911171222.9A patent/CN111048524A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020096684A (en) * | 2001-06-21 | 2002-12-31 | 주식회사 하이닉스반도체 | Gate line structure of transistor |
| JP2004153296A (en) * | 2003-12-24 | 2004-05-27 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
| CN1841781A (en) * | 2005-03-30 | 2006-10-04 | 三星Sdi株式会社 | Thin film transistor, flat panel display device, and method of fabricating the same |
| CN101110435A (en) * | 2006-07-20 | 2008-01-23 | 三菱电机株式会社 | Thin film transistor substrate and method for manufacturing the same |
| US20090294848A1 (en) * | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Semiconductor device having transistor and method of manufacturing the same |
| US20130270553A1 (en) * | 2012-04-17 | 2013-10-17 | Masatoshi Yokoyama | Semiconductor device |
| US20150129854A1 (en) * | 2013-11-14 | 2015-05-14 | Samsung Display Co. Ltd. | Thin-film transistor, method of manufacturing the same, and organic light-emitting diode (oled) display including the same |
| CN105226100A (en) * | 2014-06-27 | 2016-01-06 | 乐金显示有限公司 | The thin-film transistor of display unit |
| CN108666218A (en) * | 2017-03-29 | 2018-10-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and display base plate and preparation method thereof, display device |
| CN107452755A (en) * | 2017-07-27 | 2017-12-08 | 武汉天马微电子有限公司 | Array base palte and preparation method thereof and display panel |
| CN109509793A (en) * | 2017-09-15 | 2019-03-22 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), its manufacturing method and electronic device |
| CN107895726A (en) * | 2017-11-30 | 2018-04-10 | 武汉天马微电子有限公司 | A kind of array base palte and preparation method thereof and display device |
| CN110034189A (en) * | 2018-01-03 | 2019-07-19 | 三星电子株式会社 | Integrated circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111463267A (en) * | 2020-04-08 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2022213463A1 (en) * | 2021-04-08 | 2022-10-13 | 深圳市华星光电半导体显示技术有限公司 | Display apparatus and preparation method therefor |
| CN113707692A (en) * | 2021-07-13 | 2021-11-26 | 信利（惠州）智能显示有限公司 | AMOLED display screen manufacturing method and structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10795478B2 (en) | Array substrate and preparation method therefor, and display apparatus | |
| JP5324111B2 (en) | Thin film transistor array panel and manufacturing method thereof | |
| KR100865451B1 (en) | TFT LCD pixel unit and manufacturing method thereof | |
| CN107221501B (en) | Vertical thin film transistor and preparation method thereof | |
| US10236388B2 (en) | Dual gate oxide thin-film transistor and manufacturing method for the same | |
| JPH1093102A (en) | Method of manufacture thin-film transistor | |
| CN111048524A (en) | Array substrate, preparation method and display panel | |
| US9721978B2 (en) | Thin film transistor device, manufacturing method thereof, and display apparatus | |
| WO2013127201A1 (en) | Array substrate, manufacturing method and display device thereof | |
| WO2019011071A1 (en) | Method for manufacturing thin-film transistor, thin-film transistor, array substrate and display panel | |
| US20150115258A1 (en) | Array substrate for liquid crystal display device and method of manufacturing the same | |
| WO2017215075A1 (en) | Array substrate and manufacturing method therefor | |
| CN109860305B (en) | Thin film transistor, manufacturing method thereof, display substrate and display device | |
| CN106997892B (en) | Display device and method for manufacturing the same | |
| WO2019100465A1 (en) | Method for producing top-gate thin film transistor, and top-gate thin film transistor | |
| US10468537B2 (en) | Metal oxide thin-film transistor and manufacturing method for the same | |
| WO2015010404A1 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN110993612A (en) | Array substrate and manufacturing method thereof | |
| CN108447916B (en) | Thin film transistor, preparation method thereof, array substrate and display device | |
| WO2019196191A1 (en) | Method for preparing tft array substrate, tft array substrate, and display panel | |
| CN111564454B (en) | Display substrate, manufacturing method thereof and display device | |
| CN109037241B (en) | LTPS array substrate, manufacturing method thereof and display panel | |
| WO2019210776A1 (en) | Array substrate, display device, thin film transistor, and array substrate manufacturing method | |
| US10497724B2 (en) | Manufacturing method of a thin film transistor and manufacturing method of an array substrate | |
| US10249654B1 (en) | Manufacturing method of top-gate TFT and top-gate TFT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200421 |