WO2015010404A1

WO2015010404A1 - Thin film transistor, manufacturing method thereof, array substrate and display device

Info

Publication number: WO2015010404A1
Application number: PCT/CN2013/088101
Authority: WO
Inventors: 张文余; 谢振宇; 田宗民; 李婧
Original assignee: 北京京东方光电科技有限公司
Priority date: 2013-07-25
Filing date: 2013-11-29
Publication date: 2015-01-29
Also published as: CN103413834A; CN103413834B

Abstract

Provided are a thin film transistor, a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate electrode (31), a gate insulating layer (7), an active layer (8), a first electrode and a second electrode, wherein the gate electrode (31), the gate insulating layer (7) and the active layer (8) are arranged on a substrate (1) and the first electrode and the second electrode are mutually insulated. Along the direction perpendicular to the substrate (1), the first electrode is arranged on one side, close to the substrate (1), of the active layer (8), the second electrode is arranged on one side, away from the substrate (1), of the active layer (8), and the first electrode and the second electrode are in contact with the active layer (8).

Description

Thin film transistor and manufacturing method thereof, array substrate and display device

Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique

The liquid crystal display panel includes an array substrate, a counter substrate, and a liquid crystal disposed between the array substrate and the counter substrate. As shown in FIG. 1, the array substrate includes: a substrate substrate 1, a plurality of gate lines 2 formed on the substrate substrate 1, and a plurality of data lines 4, and the gate lines 2 and the data lines 4 are formed to cross each other. Multiple pixel units. Each pixel unit includes a thin film transistor (TFT) 3 that functions as a switch. Referring to the cross-sectional view of the thin film transistor shown in FIG. 2, the thin film transistor 3 includes: a gate electrode 31 disposed on the substrate 1 , a gate insulating layer 7 , an active layer 8 , and an active layer 8 on both sides of the gate Drain 33 and source 32. The gate 31 is connected to the gate line 2, the source 32 is connected to the data line 4, and the drain 33 is connected to the pixel electrode 5. When the gate line 2 supplies a gate signal to the gate 31 and the data line 4 supplies a data signal to the source 32, the source 32 and the drain 33 of the thin film transistor 3 are turned on to charge the pixel electrode 5 connected to the drain 33. To achieve display.

Since the on-state current of the TFT is inversely proportional to the channel length, that is, the channel length is larger, the larger the on-state current of the TFT, the larger the drain current. Here, the channel length is the distance between the source and the drain, as shown in Figure 2, the channel length is b. At present, due to the manufacturing process, the channel length of the TFT is generally only a minimum of 3 to 4 um, which causes the on-state current of the TFT to be not too large. Summary of the invention

According to an aspect of the invention, a thin film transistor is provided. The thin film transistor includes a gate electrode disposed on a substrate substrate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other. In a direction perpendicular to the substrate of the substrate, the first electrode is disposed on a side of the active layer adjacent to the substrate, and the second electrode is disposed on a side of the active layer away from the substrate, and the An electrode and the second electrode are in contact with the active layer.

For example, the gate is disposed in the same layer as the first electrode, and the gate and the first electrode Insulation.

For example, the first electrode is a drain and the second electrode is a source.

For example, the gate insulating layer covers the gate, the active layer and the drain, and the source is formed on the gate insulating layer, whereby the gate insulating layer is disposed on the source And the active layer; and the source is in contact with the active layer through a first via provided on the gate insulating layer.

For example, the thin film transistor further includes: a gate auxiliary electrode, the gate auxiliary electrode is disposed on the upper surface of the gate insulating layer, and the gate auxiliary electrode passes through the second via hole disposed on the gate insulating layer The gate is electrically connected.

For example, the drain, the active layer, and the source are sequentially disposed in an overlapping manner.

For example, in the direction perpendicular to the substrate of the substrate, the active layer includes an amorphous silicon semiconductor layer located in the middle, and an ohmic contact layer on both sides of the amorphous silicon semiconductor layer.

For example, the gate insulating layer is made of a material having a dielectric constant of 3-15.

According to another aspect of the present invention, there is provided an array substrate comprising the thin film transistor of any of the above.

For example, the array substrate further includes a pixel electrode, the first electrode is a drain, a gate insulating layer is disposed between the drain and the pixel electrode, and the pixel electrode passes through a third via disposed on the gate insulating layer The drain is electrically connected.

For example, the array substrate further includes a pixel electrode, the first electrode is a drain, and the pixel electrode is disposed under the drain and is in direct contact with the drain.

According to still another aspect of the present invention, there is provided a display device comprising any of the array substrates as described above.

According to still another aspect of the present invention, a method of fabricating a thin film transistor is provided, comprising: forming a gate, a gate insulating layer, an active layer, and a first electrode and a second electrode insulated from each other on a substrate. In a direction perpendicular to the substrate of the substrate, the first electrode is disposed on a side of the active layer adjacent to the substrate, and the second electrode is disposed on a side of the active layer away from the substrate, and the An electrode and the second electrode are in contact with the active layer.

For example, the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode.

For example, the gate and the first electrode are formed by one patterning process.

For example, the first electrode is a drain and the second electrode is a source. For example, the gate insulating layer covers the gate, the active layer and the drain, and the source is formed on the gate insulating layer, whereby the gate insulating layer is disposed on the source And the active layer; and the source is in contact with the active layer through a first via provided on the gate insulating layer.

For example, the method further includes: forming a gate auxiliary electrode, wherein the gate auxiliary electrode is disposed in the same layer as the second electrode, and passing through the second via and the gate disposed on the gate insulating layer Electrical connection.

For example, the gate auxiliary electrode and the second electrode are formed by one patterning process.

For example, the drain, the active layer, and the source are sequentially disposed in an overlapping manner. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.

1 is a schematic top plan view of a conventional array substrate;

2 is a cross-sectional structural view of the thin film transistor of FIG. 1;

FIG. 3 is a cross-sectional structural view of a thin film transistor according to an embodiment of the present invention; FIG. 4 is a cross-sectional structural view of another thin film transistor according to an embodiment of the present invention; and FIG. A schematic cross-sectional view of a thin film transistor. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the invention, without departing from the scope of the invention, are within the scope of the invention.

An embodiment of the present invention provides a thin film transistor including a gate electrode disposed on a substrate substrate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other; and a direction perpendicular to the substrate of the substrate The first electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are The active layer is in contact. It should be noted that the first electrode and the second electrode are in contact with the active layer, and may be a direct contact or a via contact. The contact manner of the embodiment of the present invention is not specifically limited.

A thin film transistor includes a gate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other, in a direction perpendicular to the substrate substrate, the first embodiment of the present invention An electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are coupled to the active Layer contact. At this time, the channel length of the thin film transistor is determined by the thickness of the active layer, so that the channel length can be reduced by appropriately setting the thickness of the active layer between the source and the drain. Increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor.

For example, the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode. For example, the gate is disposed in the same layer as the second electrode, and the gate is insulated from the second electrode. It should be noted that the gate electrode may not be disposed in the same layer as the first electrode or the second electrode, and the thin film transistor may be turned on after a voltage is applied to the gate electrode. As an example, in the following description, the gate is provided in the same layer as the first electrode, and the gate is insulated from the first electrode as an example for detailed description.

For example, the first electrode is a drain and the second electrode is a source. For example, as shown in FIG. 3 to FIG. 5, the drain electrode 33 is disposed on a side of the active layer 8 adjacent to the substrate substrate 1, and the source electrode 32 is disposed on a side of the active layer 8 away from the substrate substrate 1. , that is, the first electrode is a drain and the second electrode is a source. Of course, the first electrode may also be a source, and the second electrode is a drain. As an example, in the following description, the first electrode is a drain and the second electrode is a source.

For example, the gate insulating layer is disposed between the source and the active layer, and the source is in contact with the active layer through a first via provided on the gate insulating layer. As shown in FIG. 3 and FIG. 4, a gate insulating layer 7 covers the gate electrode 31, the active layer 8 and the drain electrode 33, and a source electrode 32 is formed on the gate insulating layer 7, thereby making the gate insulating layer 7 is located between the source 32 and the active layer 8, and the source 32 is in contact with the active layer 8 through a first via provided on the gate insulating layer 7.

For example, the thin film transistor further includes: a gate auxiliary electrode, the gate auxiliary electrode is disposed on the upper surface of the gate insulating layer, and the gate auxiliary electrode passes through the second via hole disposed on the gate insulating layer The gate is electrically connected. As shown in FIG. 4, the thin film transistor further includes a gate auxiliary electrode 34 disposed on the upper surface of the gate insulating layer 7 and passing through the second via hole on the gate insulating layer 7. Electrically connected to the gate 31, the distance between the gate 31 and the active layer 8 can be reduced. If the gate auxiliary electrode is not provided, the distance between the gate 31 and the active layer 8 is its horizontal distance d, which is limited by the exposure process, and the distance is large, which affects the opening effect. When the gate auxiliary electrode is disposed, as shown in FIG. 4, the distance between the gate auxiliary electrode 34 and the active layer 8 is c, c is equal to the thickness of the gate insulating layer, and the opening effect can be effectively improved by controlling the thickness c of the gate insulating layer.

For example, the drain, the active layer, and the source are sequentially overlapped and stacked. As shown in Fig. 5, the drain 33, the active layer 8, and the source 32 are sequentially arranged in an overlapping manner. Thus, the formed thin film transistor has good flatness, which is advantageous for improving the display effect.

For example, in the direction perpendicular to the substrate of the substrate, the active layer includes an amorphous silicon semiconductor layer located in the middle, and an ohmic contact layer on both sides of the amorphous silicon semiconductor layer. As shown in FIG. 5, the active layer 8 includes an amorphous silicon semiconductor layer 80 in the middle and an ohmic contact layer 81 on both sides of the amorphous silicon semiconductor layer 80 in a direction perpendicular to the substrate of the substrate. .

For example, the gate insulating layer is made of a material having a dielectric constant of 3-15. It should be noted that the higher the dielectric constant of the gate insulating layer, the more favorable it is to increase the on-state current of the thin film transistor. For example, the gate insulating layer may be SiN _x , SiO _x , SiON, a resin, or the like.

An embodiment of the present invention provides an array substrate, including the thin film transistor according to any one of the embodiments of the present invention.

For example, the array substrate further includes a pixel electrode, the first electrode is a drain, a gate insulating layer is disposed between the drain and the pixel electrode, and the pixel electrode passes through a third via disposed on the gate insulating layer The drain is electrically connected. As shown in Figs. 3 and 4, the pixel electrode 5 is electrically connected to the drain 33 through a third via provided on the gate insulating layer 7, and is charged by the drain 33 to effect display.

For example, the array substrate further includes a pixel electrode, the first electrode is a drain, and the pixel electrode is disposed under the drain and is in direct contact with the drain. As shown in FIG. 5, the pixel electrode 5 is disposed under the drain 33, which is electrically connected in direct contact with the drain 33, and is charged by the drain 33 to effect display.

It should be noted that, the array substrate includes the thin film transistor provided by the embodiment of the invention, and the first electrode may be a drain or a source. The second electrode is a source when the first electrode is a drain, and the second electrode is a drain when the first electrode is a source. As an example, the case where the first electrode is the drain and the second electrode is the source will be described in detail. In addition, the array substrate may also include other thin film or layer structures. As shown in FIG. 3 to FIG. 5, a flat layer is disposed on the array substrate. 9. Other thin films or layer structures may be disposed on the array substrate according to actual needs, and are not described herein. An embodiment of the present invention provides a display device, including any of the array substrates provided by the embodiments of the present invention. The display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display-enabled product such as a television, a digital camera, a mobile phone, a tablet, or the like including the display device. Or parts.

Embodiments of the present invention provide a method of fabricating a thin film transistor, including: forming a gate, a gate insulating layer, an active layer, and a first electrode and a second electrode insulated from each other on a substrate of the substrate; a direction of the substrate of the substrate, the first electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the The second electrode is in contact with the active layer.

For example, the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode. At this time, the gate electrode and the first electrode may be formed by one patterning process. The so-called "patterning process" is a process of forming a film into a layer containing at least one pattern. The patterning process generally comprises: coating the film on the film, exposing the photoresist by using a mask, etching away the photoresist to be removed by using a developing solution, and etching away the portion of the film not covered with the photoresist, Finally, the remaining photoresist is stripped. In all of the embodiments of the present invention, the "primary patterning process" refers to a process of forming a desired layer structure by one exposure. The gate and the first electrode are formed by one patterning process to reduce the number of exposures, thereby reducing the fabrication process and reducing the production cost.

For example, the gate is disposed in the same layer as the second electrode, and the gate is insulated from the second electrode. At this time, the gate electrode and the second electrode may be formed by one patterning process.

It should be noted that the gate electrode may not be disposed in the same layer as the first electrode or the second electrode, as long as the thin film transistor can be turned on after a voltage is applied to the gate. As an example, in the following description, the gate is provided in the same layer as the first electrode, and the gate is insulated from the first electrode as an example.

For example, the first electrode is a drain and the second electrode is a source. Of course, the first electrode may also be a source, and the second electrode is a drain. As an example, in the following description, the first electrode is a drain and the second electrode is a source.

It should be noted that the first electrode and the second electrode are in contact with the active layer, which may be a direct contact or a contact through a via. Limited.

A specific example will be provided below to describe in detail a method of fabricating a thin film transistor according to an embodiment of the present invention. For example, the manufacturing method of the thin film transistor includes the following steps:

Step S101, forming a first electrode and a gate on the substrate of the village.

For example, the first electrode is a drain. For example, a metal film having a thickness of ιοοο to 7000A can be prepared on a substrate substrate using a magnetron sputtering method. The metal thin film can usually be made of a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials. Then, a drain 33 and a gate 31 as shown in Figs. 3 to 5 are formed on the substrate of the village by a patterning process. It should be noted that the gate and the drain may also be separately formed by two patterning processes.

Step S102, forming an active layer on the substrate of the village.

The substrate substrate may be a substrate substrate having a gate and a drain formed after the step S101. For example, a semiconductor thin film can be deposited on a substrate substrate on which a drain and a gate are formed by chemical vapor deposition. Then, an active layer 8 as shown in Figs. 3 to 5 is formed on the substrate of the village by a patterning process.

For example, an amorphous silicon film and an n+ amorphous silicon film having a thickness of ΙΟΟθΑ to 6000A are deposited on the substrate on which the drain electrode 33 and the gate electrode 31 are formed. Then, an active layer 8 as shown in Fig. 5 is formed on the substrate of the substrate by a patterning process, and the active layer 8 includes an amorphous silicon semiconductor layer 80 in the middle and a contact layer 81.

The substrate substrate may be a substrate substrate on which an active layer is formed after step S102. For example, an insulating film having a thickness of 1000 A to 6000 A may be continuously deposited on a substrate by chemical vapor deposition. The material of the insulating film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like may also be used. Then, a gate insulating layer 7 having a first via hole as shown in Figs. 3 to 5 is formed by a patterning process. The source and the active layer are in contact through the first via.

Step S104, forming a second electrode on the substrate of the village.

The substrate substrate may be a village substrate on which a gate insulating layer is formed after step S103. For example, the second electrode is a source. For example, a metal thin film having a thickness of ΙΟΟθΑ to 7000A can be prepared on a substrate of a village using a magnetron sputtering method. The metal film can usually be made of a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a group of the above-mentioned materials. Structure. Then, a source electrode 32 that is in contact with the active layer 8 through the first via hole is formed on the substrate of the village by a patterning process.

If the thin film transistor further includes a gate auxiliary electrode as shown in FIG. 4, the manufacturing method further includes: forming a gate auxiliary electrode on the substrate. For example, the gate auxiliary electrode is formed in the same layer as the second electrode and is formed by one patterning process. That is, the gate auxiliary electrode and the second electrode are simultaneously formed by a patterning process on the substrate of the village. Of course, other thin film transistors of the embodiment of the present invention may also form a gate auxiliary electrode as needed.

It should be noted that the method for fabricating the thin film transistor provided by the embodiment of the present invention is not limited to the specific examples described above. The embodiment of the present invention is described by taking the above specific example as an example.

For the array substrate including the thin film transistor prepared by the above method, as shown in FIGS. 3 and 4, a passivation layer 9 and a pixel electrode 5 may be formed on the substrate substrate after forming the thin film transistor, wherein The pixel electrode 5 is electrically connected to the drain 33 through a second via formed on the passivation layer 9 and the gate insulating layer 7. The steps of fabricating the pixel electrode and the passivation layer will not be described in detail herein.

For the array substrate including the thin film transistor prepared by the above method, as shown in Fig. 5, the pixel electrode 5 may be formed before step S101, and the passivation layer 9 is formed after step S104. The steps of fabricating the pixel electrode and the passivation layer will not be described in detail herein.

It should be noted that, for the array substrate including the thin film transistor provided by the embodiment of the present invention, the manufacturing method may be different according to the type of the array substrate. Other thin films or layer structures may be disposed on the array substrate according to actual needs, and are not described herein.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims

1. A thin film transistor, including a gate electrode, a gate insulating layer, an active layer, and a first electrode and a second electrode that are insulated from each other on a substrate, wherein

Along the direction perpendicular to the base substrate, the first electrode is disposed on a side of the active layer close to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the third electrode is disposed on a side of the active layer away from the substrate. An electrode and the second electrode are in contact with the active layer.

2. The thin film transistor according to claim 1, wherein the gate electrode and the first electrode are arranged in the same layer, and the gate electrode is insulated from the first electrode.

3. The thin film transistor according to claim 1 or 2, wherein the first electrode is a drain electrode and the second electrode is a source electrode.

4. The thin film transistor according to claim 3, wherein the gate insulating layer covers the gate electrode, the active layer and the drain electrode, and the source electrode is formed on the gate insulating layer, whereby The gate insulating layer is disposed between the source electrode and the active layer; and

The source electrode contacts the active layer through a first via hole provided on the gate insulation layer.

5. The thin film transistor according to claim 4, further comprising: a gate auxiliary electrode, the gate auxiliary electrode is disposed on the gate insulating layer, and the gate auxiliary electrode is disposed on the gate insulating layer. The second via hole is electrically connected to the gate.

6. The thin film transistor according to claim 3, wherein the drain electrode, active layer and source electrode are overlapped in sequence.

7. The thin film transistor according to any one of claims 1 to 6, wherein in a direction perpendicular to the base substrate, the active layer includes an amorphous silicon semiconductor layer located in the middle, and an amorphous silicon semiconductor layer located in the middle. Ohmic contact layers on both sides of the semiconductor layer.

8. The thin film transistor according to any one of claims 1 to 7, wherein the gate insulating layer is made of a material with a dielectric constant of 3 to 15.

9. An array substrate, comprising the thin film transistor according to any one of claims 1 to 8.

10. The array substrate according to claim 9, further comprising a pixel electrode, the first electrode being a drain, a gate insulating layer being disposed between the drain electrode and the pixel electrode, the pixel electrode being disposed on the gate insulating layer The third via is electrically connected to the drain.

11. The array substrate according to claim 9, further comprising a pixel electrode, the first The electrode is a drain electrode, and the pixel electrode is arranged below the drain electrode and is in direct contact with the drain electrode.

12. A display device, comprising the array substrate according to any one of claims 9-11.

13. A method of manufacturing a thin film transistor, including: the steps of forming a gate electrode, a gate insulating layer, an active layer and mutually insulated first electrodes and second electrodes on a base substrate; wherein the steps are along the vertical direction of the base substrate. direction, the first electrode is disposed on a side of the active layer close to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode An electrode is in contact with the active layer.

14. The manufacturing method according to claim 13, wherein the gate electrode and the first electrode are arranged in the same layer, and the gate electrode is insulated from the first electrode.

15. The manufacturing method according to claim 14, wherein the gate electrode and the first electrode are formed through a patterning process.

16. The manufacturing method according to any one of claims 13 to 15, wherein the first electrode is a drain electrode and the second electrode is a source electrode.

17. The manufacturing method according to claim 16, wherein the gate insulating layer covers the gate electrode, the active layer and the drain electrode, and the source electrode is formed on the gate insulating layer, whereby The gate insulating layer is disposed between the source electrode and the active layer; and

18. The manufacturing method according to claim 17, further comprising: the step of forming a gate auxiliary electrode, the gate auxiliary electrode being arranged in the same layer as the second electrode, and being arranged on the gate insulating layer. The second via is electrically connected to the gate.

19. The manufacturing method according to claim 18, wherein the gate auxiliary electrode and the second electrode are formed through a patterning process.

20. The manufacturing method according to claim 16, wherein the drain electrode, active layer and source electrode are overlapped in sequence.