WO2013181902A1 - Thin film transistor and manufacturing method thereof, array substrate, and display device - Google Patents

Thin film transistor and manufacturing method thereof, array substrate, and display device Download PDF

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Publication number
WO2013181902A1
WO2013181902A1 PCT/CN2012/084761 CN2012084761W WO2013181902A1 WO 2013181902 A1 WO2013181902 A1 WO 2013181902A1 CN 2012084761 W CN2012084761 W CN 2012084761W WO 2013181902 A1 WO2013181902 A1 WO 2013181902A1
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Prior art keywords
drain
source
thin film
gate
film transistor
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PCT/CN2012/084761
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French (fr)
Chinese (zh)
Inventor
刘永
金在光
李小和
李红敏
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Publication of WO2013181902A1 publication Critical patent/WO2013181902A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the electric field generated between the pixel electrode and the common electrode is mainly used to control the rotation of the liquid crystal molecules to achieve the effect of the desired picture.
  • Whether the potential of the pixel electrode can reach the required value is mainly the opening current of the thin film transistor (TFT) ⁇
  • the inventors have found that the channel length is difficult to reduce due to the limitation of the process capability.
  • the method of improving the method mainly increases the channel width, but the increase of the channel width tends to increase the parasitic capacitance. Increase the load; and reduce the aperture ratio.
  • the prior art mainly forms the source and the drain of the thin film transistor at the same time by one exposure. Due to the limitation of the process capability, the distance between the source and the drain is difficult to achieve a small value, so the trench The reduction in the length of the track is also difficult. Summary of the invention
  • An embodiment of the present invention provides a thin film transistor including: a substrate; a gate formed on the substrate, a gate insulating layer, an active layer, and a source and a drain, wherein the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, the active layer being corresponding to the source and A portion of the space between the drains forms a channel, wherein the drain and the source are formed substantially by two patterning processes, respectively.
  • a further embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate, a gate insulating layer, an active layer, and a source and a drain on a substrate such that the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, wherein the drain and the source pass twice The patterning process is separately formed.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of still another array substrate according to an embodiment of the present invention.
  • FIG. 8a-8e are schematic structural diagrams of an array substrate manufacturing process according to the flow shown in FIG. 8 according to an embodiment of the present invention. detailed description
  • a thin film transistor according to an embodiment of the present invention, comprising: a substrate (not shown), a gate on the substrate, a gate insulating layer 2 covering the gate 1, and a gate insulating layer 2.
  • a source 4 and a drain 5 are formed over the active layer 3, covering the protective layer 8 of the source 4 and the drain 5, wherein active between the source 4 and the drain 5 A first channel 7 is formed on the layer 3.
  • the drain 5 and the source 4 can be formed by two patterning processes.
  • the steps used in the patterning process may be to form a pattern of the drain and the source on the metal film by exposure, development, etching, and stripping, or by directly etching the material layer through the mask.
  • a patterning process is used to form the material layer into an effective pattern.
  • the drain and the source are fabricated by one patterning process by exposure, development, etching, and stripping. Due to the accuracy of the exposure machine, the source and the drain are finally formed by one exposure in one patterning process. The length of the channel between the poles is limited.
  • a thin film transistor manufactured by one patterning process generally has a channel length of 4 micrometers or more, and a two patterning process is used to form a source and a drain respectively by two exposure processes, so that the length of the channel is only the line width.
  • Accuracy and alignment accuracy so theoretically the length of the channel can be infinitely small, but the channel length formed in the actual operation can be controlled to about 2 microns, so the two patterning processes are formed by two exposures respectively.
  • the drain and source can achieve a reduction in channel length.
  • a channel 7 is formed on the active layer 3 between the source 4 and the drain 5. Therefore, the length of the channel 7 corresponds to the spacing between the source and the drain.
  • the source 4 and the drain 5 are respectively formed by two patterning processes, and the pitch can be made smaller than 4 ⁇ m or even 2 ⁇ m.
  • Embodiments of the present invention provide a thin film transistor in which a drain and a source are respectively formed by double exposure, so that a source and a drain of an array substrate are respectively formed on different layers, thereby reducing a channel length and improving a thin film.
  • the turn-on current of the transistor achieves the purpose of improving the charging capability of the thin film transistor.
  • the thin film transistor further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein a second trench is formed between the source 4 and the auxiliary drain 9. Road 11.
  • the drain 5 and the source 4 are formed by two patterning processes, the length of the first channel between the source 4 and the drain 5 is smaller than the second groove between the source 4 and the auxiliary drain 9.
  • the length of the track 11; optionally, the source 4 and the auxiliary drain 9 are formed by one patterning process; thus, the source 4 and the auxiliary drain 9 are made of the same layer of conductive material, which saves the manufacturing steps.
  • the spacing between the source 4 and the drain 5 is smaller than that between the auxiliary drain 9 and the source 4, as shown in Figs.
  • the source 4 may be formed of a metal material
  • the drain 5 may be formed of a transparent conductive material such as ITO, ruthenium or the like.
  • the thin film transistor provided by the above embodiments of the present invention can be applied as a switching device, and is particularly suitable for various display devices such as a liquid crystal, an organic light emitting display (OLED), an electronic paper, and a flexible display.
  • the array substrate includes: a substrate; a gate line (not shown) and a gate 1 are formed on the substrate; a gate insulating layer 2 is formed on the gate line and the gate 1; An active layer 3 is formed on the layer 2; a source 4 and a drain 5 are formed on the active layer 3, wherein a first channel 7 is formed between the source 4 and the drain 5; and on the gate insulating layer 2
  • a data line (not shown) and a pixel electrode 4 connected to the drain 5 are formed, and a protective layer 8 covering the source 4, the drain 5, the pixel electrode 6, and the data line is further formed on the substrate, and the protective layer is formed
  • a peripheral via (not shown) is formed on 8.
  • the drain 5 and the pixel electrode 6 are formed by one patterning process; the drain 5 and the source 4 are formed by two patterning processes.
  • the drain 5 and the pixel electrode 6 may be integrally formed of a transparent conductive material.
  • the source and the drain of the thin film transistor are respectively formed by double exposure, and the channel width can be reduced to achieve the purpose of improving the charging capability of the thin film transistor, and no additional process steps are added.
  • an array substrate provided by an embodiment of the present invention further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein the source 4 and the auxiliary drain 9 A second channel 11 is formed therebetween.
  • the auxiliary drain 9 is located above the drain 5. In the cross-sectional view of the array substrate shown in FIG. 3, the auxiliary drain 9 is located below the drain 5, where the auxiliary drain 9 is eliminated. The step difference between the source 4 and the drain 5.
  • an array substrate according to an embodiment of the present invention further includes: a strip-shaped common electrode 10 formed on the protective layer.
  • the array substrate according to this embodiment includes the thin film transistor according to the above embodiment, the above description of the thin film transistor is also applicable to the array substrate.
  • the bottom gate structure is taken as an example for description.
  • the thin film transistor of the present invention may also be a top gate structure or any other suitable structure.
  • each of the stacked layers on the substrate may be a source and a drain, an active layer, a gate insulating layer, a gate, or the like.
  • Top gate structure, bottom gate In a structure or other structure, a gate insulating layer is interposed between the gate electrode and the active layer, and a source and the drain are spaced apart from each other and are at least partially in contact with the active layer, and the active layer is A portion corresponding to a space between the source and the drain forms a channel.
  • the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS) and other display modes.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • AD-SDS Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS
  • other display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS) and other display modes.
  • Embodiments of the present invention provide a display device including any of the above array substrates.
  • the display device can be a display device for electronic paper, mobile phones, televisions, digital photo frames, and the like.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including the following steps:
  • a gate electrode 1 is formed on the substrate, and a gate insulating layer 2 is formed over the gate electrode 1.
  • a metal film having a thickness of 1000 A to 7000 A can be prepared on the substrate by a magnetron sputtering method.
  • the metal material for forming the metal thin film may be usually made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • the gate plate 1 is formed on a certain area of the substrate by a process such as exposure, development, etching, and stripping using a reticle; then, a thickness of 1,000 to 6,000 people can be continuously deposited on the substrate by chemical vapor deposition.
  • the gate insulating layer film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • the film forming method of the gate film 1 or the metal thin film may be a plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming method, and the film forming method of the gate insulating layer may be deposited by using a deposition method. Spin coating or roller coating.
  • An active layer 3 is formed on the gate insulating layer 2.
  • An amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000 A to 6000 A may be deposited on the gate insulating layer by chemical vapor deposition, or a metal oxide semiconductor film may be deposited on the gate insulating film;
  • the reticle exposes the amorphous silicon film, and then the amorphous silicon film is dry etched to form an active layer over the gate.
  • a metal oxide semiconductor film is deposited as an active layer on the gate insulating film, a patterning process is performed on the metal oxide film to form an active layer, that is, after the photoresist is coated,
  • the mask plate may expose, develop, and etch the substrate to form a semiconductor active layer.
  • a first conductive material layer covering the active layer 3 is formed, and the drain 5 or the source 4 is formed by one patterning process.
  • the first conductive material layer is deposited on the semiconductor active layer of the entire substrate by using a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and engraved. After the etching and stripping, the source 4 or the drain 5 is formed.
  • the first conductive material layer can use the same material as the gate, and the thin film transistor is used as the array substrate due to the drain and the pixel.
  • the electrodes are electrically connected, so that the first conductive material layer can also be fabricated by the same patterning process using the same material as the pixel electrodes.
  • a second conductive material layer is formed, and a source 4 corresponding to the drain 5 or a drain 5 corresponding to the source 4 is formed by one patterning process.
  • a second conductive material layer is deposited on the active layer of the entire substrate by a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and etched. After stripping, the drain 5 or the source 4 is formed.
  • the second conductive material layer can be made of the same material as the gate, and if the step is to form the drain 5, the thin film transistor is used as an array substrate. Since the drain 5 is electrically connected to the pixel electrode during the fabrication, the drain 5 can also be fabricated by the same patterning process using the same material as the pixel electrode.
  • a protective layer with a thickness of 700 A 2000 A is deposited by chemical vapor deposition (PECVD) or other film formation methods, and an oxide layer may be selected as the protective layer.
  • PECVD chemical vapor deposition
  • nitride or oxynitride, corresponding to the reaction gas may be Si3 ⁇ 4, a mixed gas of 3, N 2 or SiH 2 Cl 2, NH 3, N 2 mixed gas of NH.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced and improved.
  • the turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor.
  • the method further includes: forming an auxiliary drain 9 by the same patterning process as forming the source 4, wherein the second channel 11 is formed between the source 4 and the auxiliary drain 9;
  • the source and the drain are formed by the same patterning process, and in the embodiment of the invention, the source and the drain are formed by two patterning processes, so the mask in both fabrication processes is required. Reset, and the auxiliary drain can be used as the drain of the conventional thin film transistor fabrication method, and only the thin film transistor provided by the embodiment of the present invention needs to be reset.
  • the reticle used in the drain is directly used to fabricate the source and drain reticle in the conventional thin film transistor fabrication method to fabricate the source and the auxiliary drain of the thin film transistor provided by the embodiment of the present invention, thereby realizing the trench The length of the track is reduced while saving costs.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention can be directly applied to the fabrication of the array substrate.
  • a metal thin film having a thickness of 1000 A to 7000 A can be prepared on a substrate by a magnetron sputtering method.
  • the metal material for forming the metal thin film may be usually made of molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • a plurality of lateral gate lines and a gate electrode 1 connected to the gate lines are formed on a certain area of the substrate by a process such as exposure, development, etching, and lift-off using a mask plate.
  • the substrate here may be a glass substrate.
  • the method for forming the film of the gate electrode, that is, the metal film may specifically be plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
  • PECVD plasma enhanced chemical vapor deposition
  • a gate insulating layer film having a thickness of 1000A to 6000A and an amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000A to 6000 people may be continuously deposited on the glass substrate by chemical vapor deposition.
  • a metal oxide semiconductor thin film is deposited over the gate insulating film.
  • the material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • the film formation method of the gate insulating layer can be deposited by using a deposition method , spin coating or rolling: the remaining way.
  • the semiconductor active layer can be formed by performing a patterning process on the metal oxide semiconductor film, that is, after the photoresist is coated.
  • the substrate may be exposed, developed, and etched by an ordinary reticle to form an active layer.
  • a method similar to that of the gate insulating layer and the semiconductor active layer is used.
  • a first layer of conductive material is deposited over the semiconductor active layer of the entire substrate.
  • the commonly used first conductive material layer is Indium Tin Oxides (ITO) or Indium Zinc Oxide (IZO), and the thickness is between 100A and 100OA; in this embodiment, ITO is used as the first conductive
  • ITO Indium Tin Oxides
  • IZO Indium Zinc Oxide
  • the material layer is coated with a photoresist on the first conductive material layer, and after exposure, development, etching, and stripping, the pixel electrode 6 and the drain electrode 5 are formed.
  • a method similar to that of preparing a gate line can be used to deposit a metal film having a thickness similar to that of a gate metal of 1,000 to 7,000 on the substrate.
  • the source 4 and the data line are formed in a certain area by a patterning process.
  • a channel 7 is formed between the source and the drain by an etching process on the semiconductor active layer 3. For example, in this step, the n+ amorphous silicon film between the source 4 and the drain 5 is removed.
  • a thickness of 700 A is deposited by chemical vapor deposition (PECVD) or other film formation method.
  • PECVD chemical vapor deposition
  • a protective layer the protective layer may be oxide, nitride or oxynitride, corresponding to the reaction gas may be Si3 ⁇ 4, N3 ⁇ 4, N 2 or a mixed gas Si3 ⁇ 4Cl 2, N3 ⁇ 4, N 2 gas mixture.
  • a peripheral via hole (not shown) for supplying power to the gate line or the data line is formed on the periphery of the pixel region by a masking process by a patterning process such as exposure and etching.
  • the source and the drain are respectively formed in different patterning processes, and the materials of the first conductive material layer and the second conductive material layer may also be different.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced.
  • the opening current of the thin film transistor is increased to achieve the purpose of improving the charging capability of the thin film transistor.
  • the method further includes:
  • Steps S201 to S208 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional) Switching, advanced super-dimensional field switches, referred to as ADS) and other display modes.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • AD-SDS Advanced-Super Dimensional Switching
  • ADS Advanced-Super Dimensional
  • Another embodiment of the present invention provides a method of fabricating an array substrate.
  • the array substrate manufactured by the method is also the thin film transistor provided in the above embodiment.
  • the manufacturing method includes the following steps:
  • a gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced.
  • Increasing the turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor without additional process steps.
  • the above methods further include:
  • Steps S301 to S308 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
  • Embodiments of the present invention provide a method for fabricating an array substrate.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
  • a further embodiment of the present invention provides a method of fabricating an array substrate.
  • the array substrate manufactured by the method is also a thin film transistor provided in the above embodiment.
  • the manufacturing method includes the following steps:
  • a gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
  • the drain, the source and the auxiliary drain are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel can be realized.
  • the length is reduced, the opening current of the thin film transistor is increased, and the charging capability of the thin film transistor is improved, and no additional process steps are added.
  • the above methods further include:
  • Steps S401 to S408 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
  • the thin film transistor of the bottom gate structure is taken as an example for description.
  • the method according to an embodiment of the present invention is not limited to a thin film transistor which is applied to a bottom gate structure, but can be applied to a top gate structure or other structure of a thin film transistor.
  • a source and a drain an active layer, a gate insulating layer, and a gate may be sequentially formed.
  • a gate insulating layer is interposed between the gate electrode and the active layer, and the source and the drain are spaced apart from each other and are at least partially in contact with the active layer.
  • Embodiments of the present invention provide a method for fabricating an array substrate.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
  • the array substrate and the manufacturing method thereof are all based on the thin film transistor provided by the embodiment of the present invention, and the difference is only due to the difference in connection manner between the pixel electrode and the drain caused by using different thin film transistors. Only a few array substrates and their manufacturing methods are shown here, as long as they are manufactured by the thin film transistor provided by the embodiment of the present invention and the manufacturing method thereof, and are all within the protection scope of the present invention.
  • a thin film transistor comprising:
  • drain and the source are formed separately by two patterning processes.
  • An array substrate comprising the thin film transistor according to any one of (1) to (7).
  • a display device comprising the array substrate according to (8) or (9).
  • a method of manufacturing a thin film transistor comprising:
  • drain and the source are formed separately by two patterning processes.
  • a second conductive material layer is formed, and a source corresponding to the drain or a drain corresponding to the source is formed by one patterning process.
  • a protective layer is formed over the source and drain.

Abstract

Embodiments of the present invention provide a thin film transistor and a manufacturing method thereof, an array substrate, and a display device. The thin film transistor comprises: a substrate; and a gate, a gate insulation layer, an active layer, a source, and a drain formed on the substrate. The gate insulation layer being sandwiched between the gate and the active layer. The source and the drain are spaced from each other, and both at least partially contact the active layer. The part, corresponding to the spacing between the source and the drain, of the active layer is provided with a groove. The drain and the source are manufactured through two patterning processes respectively.

Description

薄膜晶体管及其制造方法、 阵列基板和显示装置 技术领域  Thin film transistor and manufacturing method thereof, array substrate and display device
本发明的实施例涉及一种薄膜晶体管及其制造方法、 阵列基板和显示装 置。 背景技术  Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique
在薄膜场效应晶体管液晶显示器 （Thin Film Transistor-Liquid Crystal Display, TFT-LCD ) 中， 主要是通过像素电极和公共电极之间产生的电场， 来控制液晶分子的转动， 达到所要显示画面的效果。 像素电极的电位能否达 到要求值， 主要是由薄膜晶体管（ Thin Film Transistor , TFT )的开启电流 ^  In a Thin Film Transistor-Liquid Crystal Display (TFT-LCD), the electric field generated between the pixel electrode and the common electrode is mainly used to control the rotation of the liquid crystal molecules to achieve the effect of the desired picture. Whether the potential of the pixel electrode can reach the required value is mainly the opening current of the thin film transistor (TFT) ^
1 W 2 1 W 2
决定的。 理论上 ^ ^^T v _ vth , 式中 为载流子迁移率， 为单位面 积的平行板电容， W为沟道宽度， L为沟道长度， Vs为栅极电压， V 为阔 值电压。 decided. Theoretically ^ ^^T v _ vth , where is the carrier mobility, is the parallel plate capacitance per unit area, W is the channel width, L is the channel length, V s is the gate voltage, V is the threshold Voltage.
在现有技术中， 发明人发现由于工艺能力的限制， 沟道长度很难减小， 提高 ^的方法， 主要是增大沟道宽度， 但是沟道宽度的增加， 势必会增加寄 生电容， 从而增加负载； 并且会减少开口率。 而且， 现有技术主要是通过一 次曝光的方式同时形成薄膜晶体管的源极和漏极，由于工艺制程能力的限制， 源极和漏极之间的距离很难做到较小的值，因此沟道长度的减小也比较困难。 发明内容  In the prior art, the inventors have found that the channel length is difficult to reduce due to the limitation of the process capability. The method of improving the method mainly increases the channel width, but the increase of the channel width tends to increase the parasitic capacitance. Increase the load; and reduce the aperture ratio. Moreover, the prior art mainly forms the source and the drain of the thin film transistor at the same time by one exposure. Due to the limitation of the process capability, the distance between the source and the drain is difficult to achieve a small value, so the trench The reduction in the length of the track is also difficult. Summary of the invention
本发明的一个实施例提供一种薄膜晶体管， 包括： 基板； 形成于所述基 板上的栅极、 栅绝缘层、 有源层以及源极和漏极， 其中所述栅绝缘层夹设在 所述栅极和所述有源层之间， 所述源极和所述漏极彼此间隔开且均至少部分 地与所述有源层接触， 所述有源层在对应于所述源极和漏极之间的间隔的部 分形成沟道， 其中所述漏极和所述源极为通过两次构图工艺分别制作形成。  An embodiment of the present invention provides a thin film transistor including: a substrate; a gate formed on the substrate, a gate insulating layer, an active layer, and a source and a drain, wherein the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, the active layer being corresponding to the source and A portion of the space between the drains forms a channel, wherein the drain and the source are formed substantially by two patterning processes, respectively.
本发明的另一个实施例提供一种阵列基板， 包括根据本发明实施例的薄 膜晶体管。 本发明的再一个实施例提供一种显示装置， 包括根据本发明实施例的阵 列基板。 Another embodiment of the present invention provides an array substrate including a thin film transistor according to an embodiment of the present invention. Still another embodiment of the present invention provides a display device including an array substrate according to an embodiment of the present invention.
本发明的又一个实施例提供一种薄膜晶体管的制造方法， 包括： 在基板 上形成栅极、 栅绝缘层、 有源层以及源极和漏极， 以使得所述栅绝缘层夹设 在所述栅极和所述有源层之间， 所述源极和所述漏极彼此间隔开且均至少部 分地与所述有源层接触， 其中所述漏极和所述源极为通过两次构图工艺分别 制作形成。 附图说明  A further embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate, a gate insulating layer, an active layer, and a source and a drain on a substrate such that the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, wherein the drain and the source pass twice The patterning process is separately formed. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1为本发明实施例提供的一种薄膜晶体管结构示意图；  1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
图 2为本发明实施例提供的另一种薄膜晶体管结构示意图；  2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
图 3为本发明实施例提供的又一种薄膜晶体管结构示意图；  FIG. 3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention; FIG.
图 4为本发明实施例提供的一种阵列基板结构示意图；  4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
图 5为本发明实施例提供的另一种阵列基板结构示意图  FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
图 6为本发明实施例提供的又一种阵列基板结构示意图  6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
图 7为本发明实施例提供的再一种阵列基板结构示意图； 以及  FIG. 7 is a schematic structural diagram of still another array substrate according to an embodiment of the present invention;
图 8a~8e为本发明实施例提供的按照如图 8所示流程制作的阵列基板制 造过程中的结构示意图。 具体实施方式  8a-8e are schematic structural diagrams of an array substrate manufacturing process according to the flow shown in FIG. 8 according to an embodiment of the present invention. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
参照图 1所示为本发明实施例提供的一种薄膜晶体管， 包括： 基板（图 中未示出） 、 基板上的栅极 1、 覆盖栅极 1 的栅绝缘层 2、 位于栅绝缘层 2 上方的有源层 3 ,在有源层 3上方形成有源极 4和漏极 5,覆盖源极 4和漏极 5的保护层 8, 其中在源极 4和漏极 5之间的有源层 3上形成有第一沟道 7。 1 is a thin film transistor according to an embodiment of the present invention, comprising: a substrate (not shown), a gate on the substrate, a gate insulating layer 2 covering the gate 1, and a gate insulating layer 2. Above the active layer 3, a source 4 and a drain 5 are formed over the active layer 3, covering the protective layer 8 of the source 4 and the drain 5, wherein active between the source 4 and the drain 5 A first channel 7 is formed on the layer 3.
漏极 5和源极 4可通过两次构图工艺制作形成。  The drain 5 and the source 4 can be formed by two patterning processes.
当然这里构图工艺所釆用的步骤可以为通过曝光、 显影、 刻蚀、 剥离最 终在金属薄膜上形成漏极和源极的图形， 也可以通过掩模板直接对材料层进 行干刻蚀形成图形。 一次构图工艺以将材料层形成有效的图形为准。 现有技 术中釆用通过曝光、 显影、 刻蚀、 剥离的一次构图工艺制作漏极和源极， 由 于受限于曝光机的精度， 在一次构图工艺中通过一次曝光最终形成的源极和 漏极之间的沟道长度受限制。 现有技术通过一次构图工艺制造的薄膜晶体管 的沟道长度一般在 4微米以上， 而釆用两次构图工艺通过两次曝光过程分别 形成源极和漏极， 这样沟道的长度只是和线宽精度及对位精度有关， 这样理 论上沟道的长度可以做到无限小， 但实际操作中形成的沟道长度可以控制在 2微米左右， 因此釆用两次构图工艺即通过两次曝光分别形成漏极和源极可 以实现沟道长度的减小。 根据本发明的实施例， 在源极 4和漏极 5之间的有 源层 3上形成有沟道 7。 因此， 沟道 7的长度对应于源极和漏极之间的间距。 在源极 4和漏极 5通过两次构图工艺分别形成， 其间距可以制作为小于 4微 米， 甚至达到 2微米左右。  Of course, the steps used in the patterning process may be to form a pattern of the drain and the source on the metal film by exposure, development, etching, and stripping, or by directly etching the material layer through the mask. A patterning process is used to form the material layer into an effective pattern. In the prior art, the drain and the source are fabricated by one patterning process by exposure, development, etching, and stripping. Due to the accuracy of the exposure machine, the source and the drain are finally formed by one exposure in one patterning process. The length of the channel between the poles is limited. In the prior art, a thin film transistor manufactured by one patterning process generally has a channel length of 4 micrometers or more, and a two patterning process is used to form a source and a drain respectively by two exposure processes, so that the length of the channel is only the line width. Accuracy and alignment accuracy, so theoretically the length of the channel can be infinitely small, but the channel length formed in the actual operation can be controlled to about 2 microns, so the two patterning processes are formed by two exposures respectively. The drain and source can achieve a reduction in channel length. According to an embodiment of the present invention, a channel 7 is formed on the active layer 3 between the source 4 and the drain 5. Therefore, the length of the channel 7 corresponds to the spacing between the source and the drain. The source 4 and the drain 5 are respectively formed by two patterning processes, and the pitch can be made smaller than 4 μm or even 2 μm.
本发明的实施例提供一种薄膜晶体管， 通过两次曝光分别形成漏极和源 极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现沟道长度 减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力的目的。  Embodiments of the present invention provide a thin film transistor in which a drain and a source are respectively formed by double exposure, so that a source and a drain of an array substrate are respectively formed on different layers, thereby reducing a channel length and improving a thin film. The turn-on current of the transistor achieves the purpose of improving the charging capability of the thin film transistor.
进一步的， 如图 2和图 3所示， 上述薄膜晶体管还包括： 位于漏极 5上 方或漏极 5下方的辅助漏极 9, 其中源极 4与辅助漏极 9之间形成有第二沟 道 11。 此外， 由于漏极 5和源极 4为通过两次构图工艺制作形成， 源极 4与 漏极 5之间的第一沟道的长度小于源极 4与辅助漏极 9之间的第二沟道 11 的长度； 可选的， 源极 4与辅助漏极 9为经过一次构图工艺制作形成； 这样 通过同一层导电材料制作源极 4与辅助漏极 9, 这样可以节省制作步骤。 在 该实施例中 , 源极 4和漏极 5之间的间距小于辅助漏极 9和源极 4之间的间 巨， 如图 2和 3所示。  Further, as shown in FIG. 2 and FIG. 3, the thin film transistor further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein a second trench is formed between the source 4 and the auxiliary drain 9. Road 11. In addition, since the drain 5 and the source 4 are formed by two patterning processes, the length of the first channel between the source 4 and the drain 5 is smaller than the second groove between the source 4 and the auxiliary drain 9. The length of the track 11; optionally, the source 4 and the auxiliary drain 9 are formed by one patterning process; thus, the source 4 and the auxiliary drain 9 are made of the same layer of conductive material, which saves the manufacturing steps. In this embodiment, the spacing between the source 4 and the drain 5 is smaller than that between the auxiliary drain 9 and the source 4, as shown in Figs.
例如， 源极 4可以由金属材料形成， 漏极 5可以由诸如 ITO、 ΙΖΟ等的 透明导电材料形成。 以上本发明实施实例提供的薄膜晶体管可以作为开关器件应用， 尤其适 用于液晶， 有机发光显示器（OLED ) , 电子纸， 柔性显示等各类显示装置。 For example, the source 4 may be formed of a metal material, and the drain 5 may be formed of a transparent conductive material such as ITO, ruthenium or the like. The thin film transistor provided by the above embodiments of the present invention can be applied as a switching device, and is particularly suitable for various display devices such as a liquid crystal, an organic light emitting display (OLED), an electronic paper, and a flexible display.
本发明实施例提供的一种阵列基板， 参照图 4进行说明， 其中这里的阵 列基板为釆用上述实施例中的任一薄膜晶体管。 具体的本发明实施例提供的 阵列基板， 包括： 基板； 在基板上形成有栅线（图中未示出）和栅极 1 ; 在 栅线和栅极 1上形成栅绝缘层 2; 栅绝缘层 2上形成有源层 3; 在有源层 3 上形成有源极 4和漏极 5,其中源极 4和漏极 5之间形成有第一沟道 7;在栅 绝缘层 2上还形成有数据线（图中未示出）和与漏极 5连接的像素电极 4, 在基板上还形成有覆盖源极 4、 漏极 5、 像素电极 6和数据线的保护层 8, 保 护层 8上形成有外围过孔（图中未示出） 。  An array substrate according to an embodiment of the present invention is described with reference to FIG. 4, wherein the array substrate herein is any one of the above-described embodiments. The array substrate provided by the embodiment of the present invention includes: a substrate; a gate line (not shown) and a gate 1 are formed on the substrate; a gate insulating layer 2 is formed on the gate line and the gate 1; An active layer 3 is formed on the layer 2; a source 4 and a drain 5 are formed on the active layer 3, wherein a first channel 7 is formed between the source 4 and the drain 5; and on the gate insulating layer 2 A data line (not shown) and a pixel electrode 4 connected to the drain 5 are formed, and a protective layer 8 covering the source 4, the drain 5, the pixel electrode 6, and the data line is further formed on the substrate, and the protective layer is formed A peripheral via (not shown) is formed on 8.
例如， 漏极 5和像素电极 6经过一次构图工艺制作形成； 漏极 5和源极 4通过两次构图工艺制作形成。 例如， 漏极 5和像素电极 6可以由透明导电 材料一体形成。  For example, the drain 5 and the pixel electrode 6 are formed by one patterning process; the drain 5 and the source 4 are formed by two patterning processes. For example, the drain 5 and the pixel electrode 6 may be integrally formed of a transparent conductive material.
本发明的实施例提供的阵列基板， 通过两次曝光分别形成薄膜晶体管的 源极和漏极，可以实现沟道宽度减小，达到提高薄膜晶体管充电能力的目的， 并且没有额外增加工艺步骤。  In the array substrate provided by the embodiment of the present invention, the source and the drain of the thin film transistor are respectively formed by double exposure, and the channel width can be reduced to achieve the purpose of improving the charging capability of the thin film transistor, and no additional process steps are added.
进一步的， 如图 5和图 6所示， 本发明实施例提供的一种阵列基板还包 括： 位于漏极 5上方或漏极 5下方的辅助漏极 9, 其中源极 4与辅助漏极 9 之间形成有第二沟道 11。  Further, as shown in FIG. 5 and FIG. 6 , an array substrate provided by an embodiment of the present invention further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein the source 4 and the auxiliary drain 9 A second channel 11 is formed therebetween.
图 2所示的阵列基板横截面图中辅助漏极 9位于漏极 5的上方； 图 3所 示的阵列基板横截面图中辅助漏极 9位于漏极 5的下方， 这里辅助漏极 9消 除源极 4和漏极 5之间的段差。  In the cross-sectional view of the array substrate shown in FIG. 2, the auxiliary drain 9 is located above the drain 5. In the cross-sectional view of the array substrate shown in FIG. 3, the auxiliary drain 9 is located below the drain 5, where the auxiliary drain 9 is eliminated. The step difference between the source 4 and the drain 5.
进一步的， 以图 7所示为例，本发明实施例提供的一种阵列基板还包括： 形成于保护层上的条状公共电极 10。  Further, as shown in FIG. 7, an array substrate according to an embodiment of the present invention further includes: a strip-shaped common electrode 10 formed on the protective layer.
另夕卜，由于根据该实施例的阵列基板包括根据上述实施例的薄膜晶体管， 因此， 以上对薄膜晶体管的描述也适用于该阵列基板。  In addition, since the array substrate according to this embodiment includes the thin film transistor according to the above embodiment, the above description of the thin film transistor is also applicable to the array substrate.
在以上对根据本发明实施例的薄膜晶体管或包括该薄膜晶体管的阵列基 板的描述中， 均以底栅极结构为例进行了描述。 然而， 本发明的薄膜晶体管 也可以为顶栅极结构或其他任何合适的结构。 例如， 在基板上的各层叠放可 以依次为源极和漏极、 有源层、 栅绝缘层、 栅极等。 在顶栅极结构、 底栅极 结构或其他结构中， 栅绝缘层夹设在所述栅极和所述有源层之间， 源极和所 述漏极彼此间隔开且均至少部分地与有源层接触， 有源层在对应于所述源极 和漏极之间的间隔的部分形成沟道。 In the above description of the thin film transistor or the array substrate including the thin film transistor according to the embodiment of the present invention, the bottom gate structure is taken as an example for description. However, the thin film transistor of the present invention may also be a top gate structure or any other suitable structure. For example, each of the stacked layers on the substrate may be a source and a drain, an active layer, a gate insulating layer, a gate, or the like. Top gate structure, bottom gate In a structure or other structure, a gate insulating layer is interposed between the gate electrode and the active layer, and a source and the drain are spaced apart from each other and are at least partially in contact with the active layer, and the active layer is A portion corresponding to a space between the source and the drain forms a channel.
以上本发明实施实例提供的阵列基板可以适用于不同显示模式包括： TN ( Twisted Nematic ,扭曲向列）、 IPS ( In-Plane Switching,平面转换 )、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场开关， 简称为 ADS ) 等各种显示模式。  The array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS) and other display modes.
本发明实施例提供一种显示装置， 包括上述的任一阵列基板。 该显示装 置可以为电子纸、 手机、 电视、 数码相框等等显示设备。  Embodiments of the present invention provide a display device including any of the above array substrates. The display device can be a display device for electronic paper, mobile phones, televisions, digital photo frames, and the like.
本发明实施例提供一种薄膜晶体管的制造方法， 包括以下步骤：  Embodiments of the present invention provide a method of fabricating a thin film transistor, including the following steps:
5101、 在基板上形成栅极 1 , 在栅极 1上方形成栅绝缘层 2。  5101. A gate electrode 1 is formed on the substrate, and a gate insulating layer 2 is formed over the gate electrode 1.
可以使用磁控溅射方法，在基板上制备一层厚度在 1000A至 7000A的金 属薄膜。 制作金属薄膜的金属材料通常可以釆用钼、 铝、 铝镍合金、 钼钨合 金、 铬、 或铜等， 也可以使用上述几种材料薄膜的组合结构。 然后， 用掩模 版通过曝光、 显影、 刻蚀、 剥离等工艺处理， 在基板的一定区域上形成栅极 1 ; 然后可以利用化学汽相沉积法在基板上连续沉积厚度为 1000人至 6000人 的栅绝缘层薄膜； 栅绝缘层的材料通常是氮化硅， 也可以使用氧化硅和氮氧 化硅等。 栅极 1成膜即金属薄膜的成膜方法具体可以为等离子增强化学气相 沉积（PECVD )、 磁控溅射、 热蒸发或其它成膜方法， 栅绝缘层的成膜方法 可以釆用沉积方式、 旋涂方式或滚涂方式。  A metal film having a thickness of 1000 A to 7000 A can be prepared on the substrate by a magnetron sputtering method. The metal material for forming the metal thin film may be usually made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials. Then, the gate plate 1 is formed on a certain area of the substrate by a process such as exposure, development, etching, and stripping using a reticle; then, a thickness of 1,000 to 6,000 people can be continuously deposited on the substrate by chemical vapor deposition. The gate insulating layer film; the material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used. The film forming method of the gate film 1 or the metal thin film may be a plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming method, and the film forming method of the gate insulating layer may be deposited by using a deposition method. Spin coating or roller coating.
5102、 在栅绝缘层 2上形成有源层 3。  5102. An active layer 3 is formed on the gate insulating layer 2.
可以在栅绝缘层上利用化学气相沉积法沉积厚度为 1000A至 6000A的非 晶硅薄膜和 n+非晶硅薄膜，也可以是在栅绝缘层薄膜之上沉积金属氧化物半 导体薄膜； 用有源层的掩模版对非晶硅薄膜进行曝光， 之后对该非晶硅薄膜 进行干法刻蚀， 在栅极的上方形成有源层。 此外， 如果是在栅绝缘层薄膜之 上沉积金属氧化物半导体薄膜作为有源层， 则对金属氧化物薄膜进行一次构 图工艺即可形成有源层， 即在光刻胶涂覆后， 用普通的掩模版对基板进行曝 光、 显影、 刻蚀形成半导体有源层即可。  An amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000 A to 6000 A may be deposited on the gate insulating layer by chemical vapor deposition, or a metal oxide semiconductor film may be deposited on the gate insulating film; The reticle exposes the amorphous silicon film, and then the amorphous silicon film is dry etched to form an active layer over the gate. In addition, if a metal oxide semiconductor film is deposited as an active layer on the gate insulating film, a patterning process is performed on the metal oxide film to form an active layer, that is, after the photoresist is coated, The mask plate may expose, develop, and etch the substrate to form a semiconductor active layer.
5103、 制作覆盖有源层 3的第一导电材料层， 通过一次构图工艺形成漏 极 5或源极 4。 釆用和栅绝缘层以及有源层相类似的方法， 在整个基板的半导体有源层 上沉积第一导电材料层， 在第一导电材料层上涂覆光刻胶， 经过曝光、显影、 刻蚀、 剥离之后， 形成源极 4或漏极 5, 当然这里的第一导电材料层可以釆 用和栅极相同的材料， 此外该薄膜晶体管在用作阵列基板的制作时由于漏极 是与像素电极电连接的， 因此该第一导电材料层也可以釆用与像素电极相同 的材料通过同一次构图工艺制作。 5103. A first conductive material layer covering the active layer 3 is formed, and the drain 5 or the source 4 is formed by one patterning process. The first conductive material layer is deposited on the semiconductor active layer of the entire substrate by using a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and engraved. After the etching and stripping, the source 4 or the drain 5 is formed. Of course, the first conductive material layer can use the same material as the gate, and the thin film transistor is used as the array substrate due to the drain and the pixel. The electrodes are electrically connected, so that the first conductive material layer can also be fabricated by the same patterning process using the same material as the pixel electrodes.
S104、 制作第二导电材料层， 通过一次构图工艺形成对应漏极 5的源极 4或对应源极 4的漏极 5。  S104. A second conductive material layer is formed, and a source 4 corresponding to the drain 5 or a drain 5 corresponding to the source 4 is formed by one patterning process.
釆用和栅绝缘层以及有源层相类似的方法， 在整个基板的有源层上沉积 第二导电材料层， 在第一导电材料层上涂覆光刻胶， 经过曝光、 显影、 刻蚀、 剥离之后， 形成漏极 5或源极 4, 当然这里的第二导电材料层可以釆用和栅 极相同的材料， 此外若该步骤形成的是漏极 5则该薄膜晶体管在用作阵列基 板的制作时由于漏极 5是与像素电极电连接的， 因此漏极 5也可以釆用与像 素电极相同的材料通过同一次构图工艺制作。  A second conductive material layer is deposited on the active layer of the entire substrate by a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and etched. After stripping, the drain 5 or the source 4 is formed. Of course, the second conductive material layer can be made of the same material as the gate, and if the step is to form the drain 5, the thin film transistor is used as an array substrate. Since the drain 5 is electrically connected to the pixel electrode during the fabrication, the drain 5 can also be fabricated by the same patterning process using the same material as the pixel electrode.
S105、 在源极 4和漏极 5之间形成第一沟道 7。  S105, forming a first channel 7 between the source 4 and the drain 5.
S106、 形成覆盖源极 4和漏极 5的保护层 8。  S106, forming a protective layer 8 covering the source 4 and the drain 5.
在已形成的源极、 漏极、 薄膜晶体管沟道区域的图形上， 釆用化学气相 沉积（PECVD )或其他成膜方法， 沉积厚度为 700 A 2000 A的保护层， 保 护层可以选用氧化物、 氮化物或氧氮化合物， 对应的反应气体可以为 Si¾、 NH3、 N2的混合气体或 SiH2Cl2、 NH3、 N2的混合气体。 On the pattern of the formed source, drain, and thin film transistor channel regions, a protective layer with a thickness of 700 A 2000 A is deposited by chemical vapor deposition (PECVD) or other film formation methods, and an oxide layer may be selected as the protective layer. , nitride or oxynitride, corresponding to the reaction gas may be Si¾, a mixed gas of 3, N 2 or SiH 2 Cl 2, NH 3, N 2 mixed gas of NH.
本发明的实施例提供的薄膜晶体管制作方法， 通过两次曝光分别形成漏 极和源极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现沟 道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力的 目的。  In the method for fabricating a thin film transistor provided by the embodiment of the present invention, the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced and improved. The turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor.
此外可选的， 该方法还包括： 通过和形成源极 4的同一次构图工艺形成 辅助漏极 9 , 其中源极 4与辅助漏极 9之间形成有第二沟道 11； 针对传统的 薄膜晶体管制作方法源极和漏极是通过同一次构图工艺制作成型的， 而本本 发明的实施例中源极和漏极是通过两次构图工艺制作成型， 因此两次制作工 艺中的掩模板都需要重新设置， 而这里可将辅助漏极当做传统的薄膜晶体管 制作方法制作的漏极， 则只需重新设置制作本发明实施例提供的薄膜晶体管 的漏极使用的掩模板， 而直接釆用传统的薄膜晶体管制作方法中制作源极和 漏极的掩模板来制作本发明实施例提供的薄膜晶体管的源极和辅助漏极， 因 此在实现沟道长度减小的同时相对可以节省成本。 In addition, the method further includes: forming an auxiliary drain 9 by the same patterning process as forming the source 4, wherein the second channel 11 is formed between the source 4 and the auxiliary drain 9; In the transistor fabrication method, the source and the drain are formed by the same patterning process, and in the embodiment of the invention, the source and the drain are formed by two patterning processes, so the mask in both fabrication processes is required. Reset, and the auxiliary drain can be used as the drain of the conventional thin film transistor fabrication method, and only the thin film transistor provided by the embodiment of the present invention needs to be reset. The reticle used in the drain is directly used to fabricate the source and drain reticle in the conventional thin film transistor fabrication method to fabricate the source and the auxiliary drain of the thin film transistor provided by the embodiment of the present invention, thereby realizing the trench The length of the track is reduced while saving costs.
本发明实施例提供的薄膜晶体管制造方法可以直接应用于阵列基板的制 造， 以下给出了釆用上述实施例中提供的薄膜晶体管时的阵列基板的制造方 法， 包括：  The method for fabricating the thin film transistor provided by the embodiment of the present invention can be directly applied to the fabrication of the array substrate. The following describes the method for manufacturing the array substrate when the thin film transistor provided in the above embodiment is used, including:
S201、 在基板上形成栅线和栅极 1。  S201, forming a gate line and a gate electrode 1 on the substrate.
参照图 8a 所示， 可以使用磁控溅射方法， 在基板上制备一层厚度在 1000A至 7000A的金属薄膜。制作金属薄膜的金属材料通常可以釆用钼、铝、 铝镍合金、 钼钨合金、 铬、 或铜等， 也可以使用上述几种材料薄膜的组合结 构。 然后， 用掩模版通过曝光、 显影、 刻蚀、 剥离等工艺处理， 在基板的一 定区域上形成多条横向的栅线和与栅线相连的栅极 1 , 当然这里的基板可以 为玻璃基板。 其中， 栅极 1成膜即金属薄膜的成膜方法具体可以为等离子增 强化学气相沉积（PECVD ) 、 磁控溅射、 热蒸发或其它成膜方法。  Referring to Fig. 8a, a metal thin film having a thickness of 1000 A to 7000 A can be prepared on a substrate by a magnetron sputtering method. The metal material for forming the metal thin film may be usually made of molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials. Then, a plurality of lateral gate lines and a gate electrode 1 connected to the gate lines are formed on a certain area of the substrate by a process such as exposure, development, etching, and lift-off using a mask plate. Of course, the substrate here may be a glass substrate. The method for forming the film of the gate electrode, that is, the metal film, may specifically be plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
S202、 制作覆盖栅线和栅极 1的栅绝缘层 2, 在栅绝缘层 2上形成有源 层 3。  S202, forming a gate insulating layer 2 covering the gate line and the gate 1, and forming an active layer 3 on the gate insulating layer 2.
参照图 8a所示，可以利用化学气相沉积法在玻璃基板上连续沉积厚度为 1000A至 6000A的栅绝缘层薄膜和厚度为 1000A至 6000人的非晶硅薄膜和 n+非晶硅薄膜， 也可以是在栅绝缘层薄膜之上沉积金属氧化物半导体薄膜。 栅绝缘层的材料通常是氮化硅， 也可以使用氧化硅和氮氧化硅等。 用有源层 的掩模版对非晶硅薄膜进行曝光， 之后对该非晶硅薄膜进行干法刻蚀， 在栅 极的上方形成有源层； 栅绝缘层的成膜方法可以釆用沉积方式、 旋涂方式或 滚：余方式。  Referring to FIG. 8a, a gate insulating layer film having a thickness of 1000A to 6000A and an amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000A to 6000 people may be continuously deposited on the glass substrate by chemical vapor deposition. A metal oxide semiconductor thin film is deposited over the gate insulating film. The material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used. Exposing the amorphous silicon film with a mask of the active layer, and then dry etching the amorphous silicon film to form an active layer over the gate; the film formation method of the gate insulating layer can be deposited by using a deposition method , spin coating or rolling: the remaining way.
具体的 , 如果是在栅绝缘层薄膜之上沉积金属氧化物半导体薄膜作为有 源层，则对金属氧化物半导体薄膜进行一次构图工艺即可形成半导体有源层， 即在光刻胶涂覆后， 用普通的掩模版对基板进行曝光、 显影、 刻蚀形成有源 层即可。  Specifically, if a metal oxide semiconductor film is deposited as an active layer on the gate insulating film, the semiconductor active layer can be formed by performing a patterning process on the metal oxide semiconductor film, that is, after the photoresist is coated. The substrate may be exposed, developed, and etched by an ordinary reticle to form an active layer.
S203、 形成覆盖有源层 3的第一导电材料层， 通过一次构图工艺形成像 素电极 6和漏极 5。  S203, forming a first conductive material layer covering the active layer 3, and forming the pixel electrode 6 and the drain electrode 5 by one patterning process.
如图 8b所示，具体的，釆用和栅绝缘层以及半导体有源层相类似的方法， 在整个基板的半导体有源层上沉积第一导电材料层。 常用的第一导电材料层 为铟锡氧化物（ Indium Tin Oxides, ITO )或铟辞氧化物（ Indium Zinc Oxide, IZO ) , 厚度在 lOOA至 lOOOA之间； 本实施例釆用 ITO作为第一导电材料 层， 在第一导电材料层上涂覆光刻胶， 经过曝光、 显影、 刻蚀、 剥离之后， 形成像素电极 6和漏极 5。 As shown in FIG. 8b, specifically, a method similar to that of the gate insulating layer and the semiconductor active layer is used. A first layer of conductive material is deposited over the semiconductor active layer of the entire substrate. The commonly used first conductive material layer is Indium Tin Oxides (ITO) or Indium Zinc Oxide (IZO), and the thickness is between 100A and 100OA; in this embodiment, ITO is used as the first conductive The material layer is coated with a photoresist on the first conductive material layer, and after exposure, development, etching, and stripping, the pixel electrode 6 and the drain electrode 5 are formed.
5204、 形成覆盖像素电极 6和漏极 5的第二导电材料层， 通过一次构图 工艺形成源极 4和数据线。  5204, forming a second conductive material layer covering the pixel electrode 6 and the drain 5, and forming the source 4 and the data line by one patterning process.
如图 8c所示， 具体的， 可以釆用和制备栅线类似的方法， 在基板上沉积 一层类似于栅极金属的厚度在 1000人到 7000人金属薄膜。通过构图工艺处理 在一定区域形成源极 4和数据线。  As shown in Fig. 8c, specifically, a method similar to that of preparing a gate line can be used to deposit a metal film having a thickness similar to that of a gate metal of 1,000 to 7,000 on the substrate. The source 4 and the data line are formed in a certain area by a patterning process.
5205、 在源极 4和漏极 5之间形成第一沟道 7。  5205. Form a first channel 7 between the source 4 and the drain 5.
如图 8d所示，在半导体有源层 3上通过刻蚀工艺在源极和漏极之间形成 沟道 7。 例如， 在此步骤中， 将源极 4和漏极 5之间的 n+非晶硅薄膜去除。  As shown in Fig. 8d, a channel 7 is formed between the source and the drain by an etching process on the semiconductor active layer 3. For example, in this step, the n+ amorphous silicon film between the source 4 and the drain 5 is removed.
5206、 形成覆盖像素电极 6、 源极 4、 漏极 5和数据线的保护层 8。  5206. Forming a protective layer 8 covering the pixel electrode 6, the source electrode 4, the drain electrode 5, and the data line.
如图 8e所示， 在已形成的数据线、 像素电极、 源极、 漏极、 薄膜晶体管 沟道区域的图形上， 釆用化学气相沉积（PECVD )或其他成膜方法， 沉积厚 度为 700 A -2000 A的保护层， 保护层可以选用氧化物、 氮化物或氧氮化合 物， 对应的反应气体可以为 Si¾、 N¾、 N2的混合气体或 Si¾Cl2、 N¾、 N2 的混合气体。 As shown in FIG. 8e, on the pattern of the formed data line, the pixel electrode, the source, the drain, and the thin film transistor channel region, a thickness of 700 A is deposited by chemical vapor deposition (PECVD) or other film formation method. -2000 a protective layer, the protective layer may be oxide, nitride or oxynitride, corresponding to the reaction gas may be Si¾, N¾, N 2 or a mixed gas Si¾Cl 2, N¾, N 2 gas mixture.
S207、 通过一次构图工艺在保护层 8上形成外围过孔。  S207, forming a peripheral via hole on the protective layer 8 by one patterning process.
具体的， 此时通过掩模版， 利用曝光和刻蚀等构图工艺处理， 在像素区 域的外围形成用于给栅线或数据线供电的外围过孔（图中未示出） 。  Specifically, at this time, a peripheral via hole (not shown) for supplying power to the gate line or the data line is formed on the periphery of the pixel region by a masking process by a patterning process such as exposure and etching.
在上述实施例中源极和漏极分别在不同的构图工艺中形成， 第一导电材 料层和第二导电材料层的材料也可以不同。  In the above embodiments, the source and the drain are respectively formed in different patterning processes, and the materials of the first conductive material layer and the second conductive material layer may also be different.
本发明的实施例提供的阵列基板的制造方法， 通过两次曝光分别形成漏 极和源极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现沟 道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力的 目的。  In the method for fabricating an array substrate provided by the embodiment of the present invention, the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. The opening current of the thin film transistor is increased to achieve the purpose of improving the charging capability of the thin film transistor.
进一步的， 该方法还包括：  Further, the method further includes:
S208、 在保护层 8上形成第三导电材料层， 通过一次构图工艺形成公共 电极。 S208, forming a third conductive material layer on the protective layer 8, forming a common through a patterning process Electrode.
其中步骤 S201 ~ S208可以用来制造应用于 ADS显示模式的阵列基板。 以上本发明各实施实例提供的阵列基板的制造方法可以适用于不同显示模式 包括： TN ( Twisted Nematic, 扭曲向列） 、 IPS ( In-Plane Switching, 平面转 换） 、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场开关， 简称为 ADS )等各种显示模式。  Steps S201 to S208 can be used to manufacture an array substrate applied to the ADS display mode. The method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional) Switching, advanced super-dimensional field switches, referred to as ADS) and other display modes.
本发明另一实施例提供一种阵列基板的制造方法， 同样釆用该方法制造 的阵列基板也是包括上述实施例中提供的薄膜晶体管的， 该制造方法包括以 下步骤：  Another embodiment of the present invention provides a method of fabricating an array substrate. The array substrate manufactured by the method is also the thin film transistor provided in the above embodiment. The manufacturing method includes the following steps:
S301、 在基板上形成栅线和栅极。  S301. Form a gate line and a gate on the substrate.
5302、 制作覆盖栅线和栅极的栅绝缘层， 在栅绝缘层上形成有源层。 5302. A gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
5303、 形成覆盖有源层的第一导电材料层， 通过一次构图工艺形成像素 电极和漏极。 5303. Form a first conductive material layer covering the active layer, and form a pixel electrode and a drain by one patterning process.
5304、 形成覆盖像素电极和漏极的第二导电材料层， 通过一次构图工艺 形成源极、 数据线和辅助漏极。  5304. Form a second conductive material layer covering the pixel electrode and the drain, and form a source, a data line, and an auxiliary drain by one patterning process.
5305、 在源极和漏极之间形成第一沟道。  5305. Form a first channel between the source and the drain.
5306、 形成覆盖像素电极、 源极、 漏极和数据线的保护层。  5306. Form a protective layer covering the pixel electrode, the source, the drain, and the data line.
5307、 通过一次构图工艺在保护层上形成外围过孔。  5307. Form a peripheral via hole on the protective layer by one patterning process.
本发明的实施例提供的阵列基板的制造方法， 通过两次曝光分别形成漏 极和源极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现沟 道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力的 目的， 并且没有额外增加工艺步骤。  In the method for fabricating an array substrate provided by the embodiment of the present invention, the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. Increasing the turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor without additional process steps.
进一步的， 以上方法还包括：  Further, the above methods further include:
5308、 在保护层上形成第三导电材料层， 通过一次构图工艺形成公共电 极。  5308. Form a third conductive material layer on the protective layer, and form a common electrode by one patterning process.
以上步骤 S301 ~ S308中的具体制作过程可参照步骤 S201 S208的制作 过程， 这里不再赘述。  For the specific manufacturing process in the above steps S301 to S308, refer to the manufacturing process of step S201 S208, and details are not described herein again.
其中步骤 S301 ~ S308可以用来制造应用于 ADS显示模式的阵列基板。 以上本发明各实施实例提供的阵列基板的制造方法可以适用于不同显示模式 包括： TN ( Twisted Nematic, 扭曲向列） 、 IPS ( In-Plane Switching, 平面转 换） 、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场开关， 简称为 ADS )等各种显示模式。 Steps S301 to S308 can be used to manufacture an array substrate applied to the ADS display mode. The method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
本发明的实施例提供一种阵列基板的制造方法， 通过两次曝光分别形成 漏极和源极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现 沟道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力 的目的。  Embodiments of the present invention provide a method for fabricating an array substrate. The drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
本发明再一实施例提供一种阵列基板的制造方法， 同样釆用该方法制造 的阵列基板也是包括上述实施例中提供的薄膜晶体管的， 该制造方法包括如 下步骤：  A further embodiment of the present invention provides a method of fabricating an array substrate. The array substrate manufactured by the method is also a thin film transistor provided in the above embodiment. The manufacturing method includes the following steps:
S401、 在基板上形成栅线和栅极。  S401. Form a gate line and a gate on the substrate.
5402、 制作覆盖栅线和栅极的栅绝缘层， 在栅绝缘层上形成有源层。 5402. A gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
5403、形成覆盖有源层的第一导电材料层，通过一次构图工艺形成源极、 数据线和辅助漏极。 5403. Form a first conductive material layer covering the active layer, and form a source, a data line, and an auxiliary drain by one patterning process.
5404、 形成覆盖源极、 数据线和辅助漏极的第二导电材料层， 通过一次 构图工艺形成漏极和像素电极。  5404. Form a second conductive material layer covering the source, the data line, and the auxiliary drain, and form the drain and the pixel electrode by a single patterning process.
5405、 在源极和漏极之间的有源层上形成第一沟道。  S405. Form a first channel on the active layer between the source and the drain.
5406、 形成覆盖像素电极、 源极、 漏极和数据线的保护层。  5406. Form a protective layer covering the pixel electrode, the source, the drain, and the data line.
5407、 通过一次构图工艺在保护层上形成外围过孔。  5407. Form a peripheral via hole on the protective layer by one patterning process.
本发明的实施例提供的阵列基板的制造方法， 通过两次曝光分别形成漏 极、 源极和辅助漏极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现沟道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管 充电能力的目的， 并且没有额外增加工艺步骤。  In the method for fabricating the array substrate provided by the embodiment of the present invention, the drain, the source and the auxiliary drain are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel can be realized. The length is reduced, the opening current of the thin film transistor is increased, and the charging capability of the thin film transistor is improved, and no additional process steps are added.
进一步的， 以上方法还包括：  Further, the above methods further include:
5408、 在保护层上形成第三导电材料层， 通过一次构图工艺形成公共电 极。  5408. Form a third conductive material layer on the protective layer, and form a common electrode by one patterning process.
以上步骤 S401 ~ S408中的具体制作过程可参照步骤 S201 S208的制作 过程， 这里不再赘述。  For the specific manufacturing process in the above steps S401 to S408, refer to the manufacturing process of step S201 S208, and details are not described herein again.
其中步骤 S401 ~ S408可以用来制造应用于 ADS显示模式的阵列基板。 以上本发明各实施实例提供的阵列基板的制造方法可以适用于不同显示模式 包括： TN ( Twisted Nematic, 扭曲向列） 、 IPS ( In-Plane Switching, 平面转 换） 、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场开关， 简称为 ADS )等各种显示模式。 Steps S401 to S408 can be used to manufacture an array substrate applied to the ADS display mode. The method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
在以上薄膜晶体管和阵列基板的制造方法的实施例中， 均以底栅极结构 的薄膜晶体管为例进行了描述。 然而， 根据本发明的实施例的方法不限于应 用到底栅极结构的薄膜晶体管中， 而是可以应用到顶栅极结构或其他结构的 薄膜晶体管中。例如，在顶栅极结构的晶体管中， 可以依次形成源极和漏极、 有源层、 栅绝缘层和栅极。 在顶栅极结构和底栅极结构中， 栅绝缘层夹设在 栅极和有源层之间， 源极和漏极彼此间隔开且均至少部分地与有源层接触。  In the above embodiments of the thin film transistor and the method of fabricating the array substrate, the thin film transistor of the bottom gate structure is taken as an example for description. However, the method according to an embodiment of the present invention is not limited to a thin film transistor which is applied to a bottom gate structure, but can be applied to a top gate structure or other structure of a thin film transistor. For example, in a transistor of a top gate structure, a source and a drain, an active layer, a gate insulating layer, and a gate may be sequentially formed. In the top gate structure and the bottom gate structure, a gate insulating layer is interposed between the gate electrode and the active layer, and the source and the drain are spaced apart from each other and are at least partially in contact with the active layer.
本发明的实施例提供一种阵列基板的制造方法， 通过两次曝光分别形成 漏极和源极， 使得阵列基板的源极和漏极分别形成在不同的层上， 可以实现 沟道长度减小， 提高薄膜晶体管的开启电流， 达到提高薄膜晶体管充电能力 的目的。  Embodiments of the present invention provide a method for fabricating an array substrate. The drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
当然以上给出的阵列基板及其制造方法均是釆用了本发明实施例提供的 薄膜晶体管， 其区别只是由于釆用了不同的薄膜晶体管造成的像素电极与漏 极的连接方式的不同， 当然这里只是示出了几种阵列基板及其制造方法， 只 要是釆用本发明实施例提供的薄膜晶体管及其制造方法制造生产的阵列基板 均应在本发明的保护范围内。  Of course, the array substrate and the manufacturing method thereof are all based on the thin film transistor provided by the embodiment of the present invention, and the difference is only due to the difference in connection manner between the pixel electrode and the drain caused by using different thin film transistors. Only a few array substrates and their manufacturing methods are shown here, as long as they are manufactured by the thin film transistor provided by the embodiment of the present invention and the manufacturing method thereof, and are all within the protection scope of the present invention.
( 1 )一种薄膜晶体管， 包括： (1) A thin film transistor comprising:
基板；  Substrate
形成于所述基板上的栅极、 栅绝缘层、 有源层以及源极和漏极， 其中所述栅绝缘层夹设在所述栅极和所述有源层之间， 所述源极和所述 漏极彼此间隔开且均至少部分地与所述有源层接触， 所述有源层在对应于所 述源极和漏极之间的间隔的部分形成沟道，  a gate, a gate insulating layer, an active layer, and a source and a drain formed on the substrate, wherein the gate insulating layer is interposed between the gate and the active layer, the source And the drains are spaced apart from each other and are at least partially in contact with the active layer, the active layer forming a channel at a portion corresponding to a space between the source and the drain,
其中所述漏极和所述源极为通过两次构图工艺分别制作形成。  Wherein the drain and the source are formed separately by two patterning processes.
( 2 )根据（1 )所述的薄膜晶体管， 其中所述栅绝缘层覆盖所述栅极， 所述有源层位于所述栅绝缘层上方，所述源极和漏极形成在所述有源层上方。  (2) The thin film transistor according to (1), wherein the gate insulating layer covers the gate, the active layer is located above the gate insulating layer, and the source and the drain are formed in the Above the source layer.
( 3 )根据（ 1 )或（ 2 )所述的薄膜晶体管， 还包括覆盖所述源极和漏极 的保护层。  (3) The thin film transistor according to (1) or (2), further comprising a protective layer covering the source and the drain.
( 4 )根据（ 2 )或（ 3 )所述的薄膜晶体管， 还包括： 位于所述漏极上方 或所述漏极下方的辅助漏极， 所述源极和所述漏极之间的间距小于所述辅助 漏极和所述源极之间的间距。 (4) The thin film transistor according to (2) or (3), further comprising: above the drain Or an auxiliary drain under the drain, a spacing between the source and the drain is smaller than a spacing between the auxiliary drain and the source.
(5)根据（4)所述的薄膜晶体管， 其中所述源极与所述辅助漏极为经 过一次构图工艺制作形成。  (5) The thin film transistor according to (4), wherein the source and the auxiliary drain are formed by one patterning process.
( 6 )根据（ 1 ) - ( 5 ) 中任一项所述的薄膜晶体管， 其中所述源极和所 述漏极之间的间距小于 4微米。  The thin film transistor according to any one of (1) to (5), wherein a distance between the source and the drain is less than 4 μm.
(7)根据（1 ) - (6) 中任一项所述的薄膜晶体管， 其中所述源极由金 属材料形成， 且所述漏极由透明导电材料形成。  The thin film transistor according to any one of (1), wherein the source is formed of a metal material, and the drain is formed of a transparent conductive material.
( 8 )一种阵列基板， 包括（ 1 ) - ( 7 ) 中任一项所述的薄膜晶体管。 (9)根据（8)所述的阵列基板， 还包括位于基板上的像素电极， 所述 漏极和所述像素电极经过一次构图工艺制作形成。  (8) An array substrate comprising the thin film transistor according to any one of (1) to (7). (9) The array substrate according to (8), further comprising a pixel electrode on the substrate, wherein the drain and the pixel electrode are formed by one patterning process.
(10)根据（8)或（9)所述的阵列基板， 其中所述漏极和所述像素电 极以透明导电材料一体形成。  (10) The array substrate according to (8) or (9), wherein the drain and the pixel electrode are integrally formed with a transparent conductive material.
(11)一种显示装置， 包括（8)或（9)所述的阵列基板。  (11) A display device comprising the array substrate according to (8) or (9).
(12)—种薄膜晶体管的制造方法， 包括：  (12) A method of manufacturing a thin film transistor, comprising:
在基板上形成栅极、 栅绝缘层、 有源层以及源极和漏极， 以使得所述栅 绝缘层夹设在所述栅极和所述有源层之间， 所述源极和所述漏极彼此间隔开 且均至少部分地与所述有源层接触，  Forming a gate, a gate insulating layer, an active layer, and a source and a drain on the substrate such that the gate insulating layer is interposed between the gate and the active layer, the source and the The drains are spaced apart from each other and are at least partially in contact with the active layer,
其中所述漏极和所述源极为通过两次构图工艺分别制作形成。  Wherein the drain and the source are formed separately by two patterning processes.
(13)根据 (12)所述的方法， 其中在基板上形成栅极、 栅绝缘层、 有 源层以及源极和漏极包括：  (13) The method of (12), wherein forming a gate, a gate insulating layer, an active layer, and a source and a drain on the substrate comprises:
在基板上形成所述栅极；  Forming the gate on a substrate;
在所述栅极上方形成所述栅绝缘层；  Forming the gate insulating layer over the gate;
在所述栅绝缘层上形成所述有源层；  Forming the active layer on the gate insulating layer;
制作覆盖所述有源层的第一导电材料层， 通过一次构图工艺形成所述漏 极或所述源极；  Forming a first conductive material layer covering the active layer, forming the drain or the source by a patterning process;
制作第二导电材料层， 通过一次构图工艺形成对应所述漏极的源极或对 应所述源极的漏极。  A second conductive material layer is formed, and a source corresponding to the drain or a drain corresponding to the source is formed by one patterning process.
( 14 )根据 ( 13 )所述的方法， 还包括：  (14) The method according to (13), further comprising:
在所述源极和所述漏极之间形成沟道； 以及 在所述源极和漏极上方形成保护层。 Forming a channel between the source and the drain; A protective layer is formed over the source and drain.
(15)根据（13)或 （14)所述的方法， 还包括： 通过和形成所述源极 的同一次构图工艺形成辅助漏极， 以使得所述源极和所述漏极间的间距小于 所述辅助漏极和所述源极之间的间距。  (15) The method of (13) or (14), further comprising: forming an auxiliary drain by a same patterning process as forming the source, such that a spacing between the source and the drain Less than the spacing between the auxiliary drain and the source.
(16)根据 (14)所述的方法， 其中所述有源层包括依次形成的半导体 层和掺杂半导体层， 形成所述沟道的步骤包括去除所述源极和所述漏极之间 部分有源层， 且在该步骤中至少去除所述源极和所述漏极之间的掺杂半导体 层。  (16) The method according to (14), wherein the active layer includes a semiconductor layer and a doped semiconductor layer which are sequentially formed, and the step of forming the channel includes removing between the source and the drain Part of the active layer, and at least removing the doped semiconductor layer between the source and the drain in this step.
(17)根据（13) - (16)中任一项所述的方法， 其中所述第一导电材料 层和第二导电材料层为不同的材料。  The method of any one of (13) to (16), wherein the first conductive material layer and the second conductive material layer are different materials.
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要求书 Claim
I、 一种薄膜晶体管， 包括： I. A thin film transistor comprising:
基板；  Substrate
形成于所述基板上的栅极、 栅绝缘层、 有源层以及源极和漏极， 其中所述栅绝缘层夹设在所述栅极和所述有源层之间， 所述源极和所述 漏极彼此间隔开且均至少部分地与所述有源层接触， 所述有源层在对应于所 述源极和漏极之间的间隔的部分形成沟道，  a gate, a gate insulating layer, an active layer, and a source and a drain formed on the substrate, wherein the gate insulating layer is interposed between the gate and the active layer, the source And the drains are spaced apart from each other and are at least partially in contact with the active layer, the active layer forming a channel at a portion corresponding to a space between the source and the drain,
其中所述漏极和所述源极为通过两次构图工艺分别制作形成。  Wherein the drain and the source are formed separately by two patterning processes.
2、根据权利要求 1所述的薄膜晶体管，其中所述栅绝缘层覆盖所述栅极， 所述有源层位于所述栅绝缘层上方，所述源极和漏极形成在所述有源层上方。  2. The thin film transistor of claim 1, wherein the gate insulating layer covers the gate, the active layer is over the gate insulating layer, and the source and drain are formed at the active Above the layer.
3、根据权利要求 1或 2所述的薄膜晶体管，还包括覆盖所述源极和漏极 的保护层。  The thin film transistor according to claim 1 or 2, further comprising a protective layer covering the source and the drain.
4、根据权利要求 2或 3所述的薄膜晶体管，还包括： 位于所述漏极上方 或所述漏极下方的辅助漏极， 所述源极和所述漏极间的间距小于所述辅助漏 极和所述源极之间的间距。  The thin film transistor according to claim 2 or 3, further comprising: an auxiliary drain located above or below the drain, and a spacing between the source and the drain is smaller than the auxiliary The spacing between the drain and the source.
5、根据权利要求 4所述的薄膜晶体管，其中所述源极与所述辅助漏极为 经过一次构图工艺制作形成。  The thin film transistor according to claim 4, wherein said source and said auxiliary drain are formed by one patterning process.
6、根据权利要求 1-5中任一项所述的薄膜晶体管， 其中所述源极和所述 漏极之间的间距小于 4微米。  The thin film transistor according to any one of claims 1 to 5, wherein a distance between the source and the drain is less than 4 μm.
7、根据权利要求 1-6中任一项所述的薄膜晶体管， 其中所述源极由金属 材料形成， 且所述漏极由透明导电材料形成。  The thin film transistor according to any one of claims 1 to 6, wherein the source is formed of a metal material, and the drain is formed of a transparent conductive material.
8、 一种阵列基板， 包括权利要求 1-7中任一项所述的薄膜晶体管。  An array substrate comprising the thin film transistor according to any one of claims 1-7.
9、根据权利要求 8所述的阵列基板，还包括位于基板上的像素电极， 所 述漏极和所述像素电极经过一次构图工艺制作形成。  9. The array substrate of claim 8, further comprising a pixel electrode on the substrate, the drain and the pixel electrode being formed by a patterning process.
10、 根据权利要求 8或 9所述的阵列基板， 其中所述漏极和所述像素电 极以透明导电材料一体形成。  The array substrate according to claim 8 or 9, wherein the drain and the pixel electrode are integrally formed with a transparent conductive material.
I I、 一种显示装置， 包括权利要求 8或 9所述的阵列基板。  I I. A display device comprising the array substrate of claim 8 or 9.
12、 一种薄膜晶体管的制造方法， 包括：  12. A method of fabricating a thin film transistor, comprising:
在基板上形成栅极、 栅绝缘层、 有源层以及源极和漏极， 以使得所述栅 绝缘层夹设在所述栅极和所述有源层之间， 所述源极和所述漏极彼此间隔开 且均至少部分地与所述有源层接触， Forming a gate, a gate insulating layer, an active layer, and a source and a drain on the substrate such that the gate An insulating layer is interposed between the gate and the active layer, the source and the drain being spaced apart from each other and at least partially in contact with the active layer,
其中所述漏极和所述源极为通过两次构图工艺分别制作形成。  Wherein the drain and the source are formed separately by two patterning processes.
13、 根据权利要求 12所述的方法， 其中在基板上形成栅极、 栅绝缘层、 有源层以及源极和漏极包括：  13. The method of claim 12, wherein forming a gate, a gate insulating layer, an active layer, and a source and a drain on the substrate comprises:
在基板上形成所述栅极；  Forming the gate on a substrate;
在所述栅极上方形成所述栅绝缘层；  Forming the gate insulating layer over the gate;
在所述栅绝缘层上形成所述有源层；  Forming the active layer on the gate insulating layer;
制作覆盖所述有源层的第一导电材料层， 通过一次构图工艺形成所述漏 极或所述源极；  Forming a first conductive material layer covering the active layer, forming the drain or the source by a patterning process;
制作第二导电材料层， 通过一次构图工艺形成对应所述漏极的源极或对 应所述源极的漏极。  A second conductive material layer is formed, and a source corresponding to the drain or a drain corresponding to the source is formed by one patterning process.
14、 根据权利要求 13所述的方法， 还包括：  14. The method of claim 13 further comprising:
在所述源极和所述漏极之间形成沟道； 以及  Forming a channel between the source and the drain;
在所述源极和漏极上方形成保护层。  A protective layer is formed over the source and drain.
15、 根据权利要求 13或 14所述的方法， 还包括： 通过和形成所述源极 的同一次构图工艺形成辅助漏极， 以使得所述源极和所述漏极间的间距小于 所述辅助漏极和所述源极之间的间距。  15. The method of claim 13 or 14, further comprising: forming an auxiliary drain by a same patterning process as forming the source such that a spacing between the source and the drain is less than The spacing between the auxiliary drain and the source.
16、根据权利要求 14所述的方法，其中所述有源层包括依次形成的半导 体层和掺杂半导体层， 形成所述沟道的步骤包括去除所述源极和所述漏极之 间部分有源层， 且在该步骤中至少去除所述源极和所述漏极之间的掺杂半导 体层。  16. The method of claim 14, wherein the active layer comprises a sequentially formed semiconductor layer and a doped semiconductor layer, the step of forming the channel comprising removing a portion between the source and the drain An active layer, and at least a doped semiconductor layer between the source and the drain is removed in this step.
17、 根据权利要求 13-16中任一项所述的方法， 其中所述第一导电材料 层和第二导电材料层为不同的材料。  The method according to any one of claims 13 to 16, wherein the first conductive material layer and the second conductive material layer are different materials.
PCT/CN2012/084761 2012-06-08 2012-11-16 Thin film transistor and manufacturing method thereof, array substrate, and display device WO2013181902A1 (en)

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