WO2013181902A1 - Transistor à couche mince et son procédé de fabrication, substrat de matrice et dispositif d'affichage - Google Patents

Transistor à couche mince et son procédé de fabrication, substrat de matrice et dispositif d'affichage Download PDF

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Publication number
WO2013181902A1
WO2013181902A1 PCT/CN2012/084761 CN2012084761W WO2013181902A1 WO 2013181902 A1 WO2013181902 A1 WO 2013181902A1 CN 2012084761 W CN2012084761 W CN 2012084761W WO 2013181902 A1 WO2013181902 A1 WO 2013181902A1
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Prior art keywords
drain
source
thin film
gate
film transistor
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PCT/CN2012/084761
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English (en)
Chinese (zh)
Inventor
刘永
金在光
李小和
李红敏
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Publication of WO2013181902A1 publication Critical patent/WO2013181902A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the electric field generated between the pixel electrode and the common electrode is mainly used to control the rotation of the liquid crystal molecules to achieve the effect of the desired picture.
  • Whether the potential of the pixel electrode can reach the required value is mainly the opening current of the thin film transistor (TFT) ⁇
  • the inventors have found that the channel length is difficult to reduce due to the limitation of the process capability.
  • the method of improving the method mainly increases the channel width, but the increase of the channel width tends to increase the parasitic capacitance. Increase the load; and reduce the aperture ratio.
  • the prior art mainly forms the source and the drain of the thin film transistor at the same time by one exposure. Due to the limitation of the process capability, the distance between the source and the drain is difficult to achieve a small value, so the trench The reduction in the length of the track is also difficult. Summary of the invention
  • An embodiment of the present invention provides a thin film transistor including: a substrate; a gate formed on the substrate, a gate insulating layer, an active layer, and a source and a drain, wherein the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, the active layer being corresponding to the source and A portion of the space between the drains forms a channel, wherein the drain and the source are formed substantially by two patterning processes, respectively.
  • a further embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate, a gate insulating layer, an active layer, and a source and a drain on a substrate such that the gate insulating layer is interposed Between the gate and the active layer, the source and the drain are spaced apart from each other and are at least partially in contact with the active layer, wherein the drain and the source pass twice The patterning process is separately formed.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of still another array substrate according to an embodiment of the present invention.
  • FIG. 8a-8e are schematic structural diagrams of an array substrate manufacturing process according to the flow shown in FIG. 8 according to an embodiment of the present invention. detailed description
  • a thin film transistor according to an embodiment of the present invention, comprising: a substrate (not shown), a gate on the substrate, a gate insulating layer 2 covering the gate 1, and a gate insulating layer 2.
  • a source 4 and a drain 5 are formed over the active layer 3, covering the protective layer 8 of the source 4 and the drain 5, wherein active between the source 4 and the drain 5 A first channel 7 is formed on the layer 3.
  • the drain 5 and the source 4 can be formed by two patterning processes.
  • the steps used in the patterning process may be to form a pattern of the drain and the source on the metal film by exposure, development, etching, and stripping, or by directly etching the material layer through the mask.
  • a patterning process is used to form the material layer into an effective pattern.
  • the drain and the source are fabricated by one patterning process by exposure, development, etching, and stripping. Due to the accuracy of the exposure machine, the source and the drain are finally formed by one exposure in one patterning process. The length of the channel between the poles is limited.
  • a thin film transistor manufactured by one patterning process generally has a channel length of 4 micrometers or more, and a two patterning process is used to form a source and a drain respectively by two exposure processes, so that the length of the channel is only the line width.
  • Accuracy and alignment accuracy so theoretically the length of the channel can be infinitely small, but the channel length formed in the actual operation can be controlled to about 2 microns, so the two patterning processes are formed by two exposures respectively.
  • the drain and source can achieve a reduction in channel length.
  • a channel 7 is formed on the active layer 3 between the source 4 and the drain 5. Therefore, the length of the channel 7 corresponds to the spacing between the source and the drain.
  • the source 4 and the drain 5 are respectively formed by two patterning processes, and the pitch can be made smaller than 4 ⁇ m or even 2 ⁇ m.
  • Embodiments of the present invention provide a thin film transistor in which a drain and a source are respectively formed by double exposure, so that a source and a drain of an array substrate are respectively formed on different layers, thereby reducing a channel length and improving a thin film.
  • the turn-on current of the transistor achieves the purpose of improving the charging capability of the thin film transistor.
  • the thin film transistor further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein a second trench is formed between the source 4 and the auxiliary drain 9. Road 11.
  • the drain 5 and the source 4 are formed by two patterning processes, the length of the first channel between the source 4 and the drain 5 is smaller than the second groove between the source 4 and the auxiliary drain 9.
  • the length of the track 11; optionally, the source 4 and the auxiliary drain 9 are formed by one patterning process; thus, the source 4 and the auxiliary drain 9 are made of the same layer of conductive material, which saves the manufacturing steps.
  • the spacing between the source 4 and the drain 5 is smaller than that between the auxiliary drain 9 and the source 4, as shown in Figs.
  • the source 4 may be formed of a metal material
  • the drain 5 may be formed of a transparent conductive material such as ITO, ruthenium or the like.
  • the thin film transistor provided by the above embodiments of the present invention can be applied as a switching device, and is particularly suitable for various display devices such as a liquid crystal, an organic light emitting display (OLED), an electronic paper, and a flexible display.
  • the array substrate includes: a substrate; a gate line (not shown) and a gate 1 are formed on the substrate; a gate insulating layer 2 is formed on the gate line and the gate 1; An active layer 3 is formed on the layer 2; a source 4 and a drain 5 are formed on the active layer 3, wherein a first channel 7 is formed between the source 4 and the drain 5; and on the gate insulating layer 2
  • a data line (not shown) and a pixel electrode 4 connected to the drain 5 are formed, and a protective layer 8 covering the source 4, the drain 5, the pixel electrode 6, and the data line is further formed on the substrate, and the protective layer is formed
  • a peripheral via (not shown) is formed on 8.
  • the drain 5 and the pixel electrode 6 are formed by one patterning process; the drain 5 and the source 4 are formed by two patterning processes.
  • the drain 5 and the pixel electrode 6 may be integrally formed of a transparent conductive material.
  • the source and the drain of the thin film transistor are respectively formed by double exposure, and the channel width can be reduced to achieve the purpose of improving the charging capability of the thin film transistor, and no additional process steps are added.
  • an array substrate provided by an embodiment of the present invention further includes: an auxiliary drain 9 located above the drain 5 or below the drain 5, wherein the source 4 and the auxiliary drain 9 A second channel 11 is formed therebetween.
  • the auxiliary drain 9 is located above the drain 5. In the cross-sectional view of the array substrate shown in FIG. 3, the auxiliary drain 9 is located below the drain 5, where the auxiliary drain 9 is eliminated. The step difference between the source 4 and the drain 5.
  • an array substrate according to an embodiment of the present invention further includes: a strip-shaped common electrode 10 formed on the protective layer.
  • the array substrate according to this embodiment includes the thin film transistor according to the above embodiment, the above description of the thin film transistor is also applicable to the array substrate.
  • the bottom gate structure is taken as an example for description.
  • the thin film transistor of the present invention may also be a top gate structure or any other suitable structure.
  • each of the stacked layers on the substrate may be a source and a drain, an active layer, a gate insulating layer, a gate, or the like.
  • Top gate structure, bottom gate In a structure or other structure, a gate insulating layer is interposed between the gate electrode and the active layer, and a source and the drain are spaced apart from each other and are at least partially in contact with the active layer, and the active layer is A portion corresponding to a space between the source and the drain forms a channel.
  • the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS) and other display modes.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • AD-SDS Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS
  • other display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional Switching, Advanced Super Dimensional field switches, abbreviated as ADS) and other display modes.
  • Embodiments of the present invention provide a display device including any of the above array substrates.
  • the display device can be a display device for electronic paper, mobile phones, televisions, digital photo frames, and the like.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including the following steps:
  • a gate electrode 1 is formed on the substrate, and a gate insulating layer 2 is formed over the gate electrode 1.
  • a metal film having a thickness of 1000 A to 7000 A can be prepared on the substrate by a magnetron sputtering method.
  • the metal material for forming the metal thin film may be usually made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • the gate plate 1 is formed on a certain area of the substrate by a process such as exposure, development, etching, and stripping using a reticle; then, a thickness of 1,000 to 6,000 people can be continuously deposited on the substrate by chemical vapor deposition.
  • the gate insulating layer film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • the film forming method of the gate film 1 or the metal thin film may be a plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming method, and the film forming method of the gate insulating layer may be deposited by using a deposition method. Spin coating or roller coating.
  • An active layer 3 is formed on the gate insulating layer 2.
  • An amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000 A to 6000 A may be deposited on the gate insulating layer by chemical vapor deposition, or a metal oxide semiconductor film may be deposited on the gate insulating film;
  • the reticle exposes the amorphous silicon film, and then the amorphous silicon film is dry etched to form an active layer over the gate.
  • a metal oxide semiconductor film is deposited as an active layer on the gate insulating film, a patterning process is performed on the metal oxide film to form an active layer, that is, after the photoresist is coated,
  • the mask plate may expose, develop, and etch the substrate to form a semiconductor active layer.
  • a first conductive material layer covering the active layer 3 is formed, and the drain 5 or the source 4 is formed by one patterning process.
  • the first conductive material layer is deposited on the semiconductor active layer of the entire substrate by using a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and engraved. After the etching and stripping, the source 4 or the drain 5 is formed.
  • the first conductive material layer can use the same material as the gate, and the thin film transistor is used as the array substrate due to the drain and the pixel.
  • the electrodes are electrically connected, so that the first conductive material layer can also be fabricated by the same patterning process using the same material as the pixel electrodes.
  • a second conductive material layer is formed, and a source 4 corresponding to the drain 5 or a drain 5 corresponding to the source 4 is formed by one patterning process.
  • a second conductive material layer is deposited on the active layer of the entire substrate by a method similar to the gate insulating layer and the active layer, and the photoresist is coated on the first conductive material layer, exposed, developed, and etched. After stripping, the drain 5 or the source 4 is formed.
  • the second conductive material layer can be made of the same material as the gate, and if the step is to form the drain 5, the thin film transistor is used as an array substrate. Since the drain 5 is electrically connected to the pixel electrode during the fabrication, the drain 5 can also be fabricated by the same patterning process using the same material as the pixel electrode.
  • a protective layer with a thickness of 700 A 2000 A is deposited by chemical vapor deposition (PECVD) or other film formation methods, and an oxide layer may be selected as the protective layer.
  • PECVD chemical vapor deposition
  • nitride or oxynitride, corresponding to the reaction gas may be Si3 ⁇ 4, a mixed gas of 3, N 2 or SiH 2 Cl 2, NH 3, N 2 mixed gas of NH.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced and improved.
  • the turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor.
  • the method further includes: forming an auxiliary drain 9 by the same patterning process as forming the source 4, wherein the second channel 11 is formed between the source 4 and the auxiliary drain 9;
  • the source and the drain are formed by the same patterning process, and in the embodiment of the invention, the source and the drain are formed by two patterning processes, so the mask in both fabrication processes is required. Reset, and the auxiliary drain can be used as the drain of the conventional thin film transistor fabrication method, and only the thin film transistor provided by the embodiment of the present invention needs to be reset.
  • the reticle used in the drain is directly used to fabricate the source and drain reticle in the conventional thin film transistor fabrication method to fabricate the source and the auxiliary drain of the thin film transistor provided by the embodiment of the present invention, thereby realizing the trench The length of the track is reduced while saving costs.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention can be directly applied to the fabrication of the array substrate.
  • a metal thin film having a thickness of 1000 A to 7000 A can be prepared on a substrate by a magnetron sputtering method.
  • the metal material for forming the metal thin film may be usually made of molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • a plurality of lateral gate lines and a gate electrode 1 connected to the gate lines are formed on a certain area of the substrate by a process such as exposure, development, etching, and lift-off using a mask plate.
  • the substrate here may be a glass substrate.
  • the method for forming the film of the gate electrode, that is, the metal film may specifically be plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
  • PECVD plasma enhanced chemical vapor deposition
  • a gate insulating layer film having a thickness of 1000A to 6000A and an amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000A to 6000 people may be continuously deposited on the glass substrate by chemical vapor deposition.
  • a metal oxide semiconductor thin film is deposited over the gate insulating film.
  • the material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • the film formation method of the gate insulating layer can be deposited by using a deposition method , spin coating or rolling: the remaining way.
  • the semiconductor active layer can be formed by performing a patterning process on the metal oxide semiconductor film, that is, after the photoresist is coated.
  • the substrate may be exposed, developed, and etched by an ordinary reticle to form an active layer.
  • a method similar to that of the gate insulating layer and the semiconductor active layer is used.
  • a first layer of conductive material is deposited over the semiconductor active layer of the entire substrate.
  • the commonly used first conductive material layer is Indium Tin Oxides (ITO) or Indium Zinc Oxide (IZO), and the thickness is between 100A and 100OA; in this embodiment, ITO is used as the first conductive
  • ITO Indium Tin Oxides
  • IZO Indium Zinc Oxide
  • the material layer is coated with a photoresist on the first conductive material layer, and after exposure, development, etching, and stripping, the pixel electrode 6 and the drain electrode 5 are formed.
  • a method similar to that of preparing a gate line can be used to deposit a metal film having a thickness similar to that of a gate metal of 1,000 to 7,000 on the substrate.
  • the source 4 and the data line are formed in a certain area by a patterning process.
  • a channel 7 is formed between the source and the drain by an etching process on the semiconductor active layer 3. For example, in this step, the n+ amorphous silicon film between the source 4 and the drain 5 is removed.
  • a thickness of 700 A is deposited by chemical vapor deposition (PECVD) or other film formation method.
  • PECVD chemical vapor deposition
  • a protective layer the protective layer may be oxide, nitride or oxynitride, corresponding to the reaction gas may be Si3 ⁇ 4, N3 ⁇ 4, N 2 or a mixed gas Si3 ⁇ 4Cl 2, N3 ⁇ 4, N 2 gas mixture.
  • a peripheral via hole (not shown) for supplying power to the gate line or the data line is formed on the periphery of the pixel region by a masking process by a patterning process such as exposure and etching.
  • the source and the drain are respectively formed in different patterning processes, and the materials of the first conductive material layer and the second conductive material layer may also be different.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced.
  • the opening current of the thin film transistor is increased to achieve the purpose of improving the charging capability of the thin film transistor.
  • the method further includes:
  • Steps S201 to S208 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching), AD-SDS (Advanced-Super Dimensional) Switching, advanced super-dimensional field switches, referred to as ADS) and other display modes.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • AD-SDS Advanced-Super Dimensional Switching
  • ADS Advanced-Super Dimensional
  • Another embodiment of the present invention provides a method of fabricating an array substrate.
  • the array substrate manufactured by the method is also the thin film transistor provided in the above embodiment.
  • the manufacturing method includes the following steps:
  • a gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced.
  • Increasing the turn-on current of the thin film transistor achieves the purpose of improving the charging capability of the thin film transistor without additional process steps.
  • the above methods further include:
  • Steps S301 to S308 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
  • Embodiments of the present invention provide a method for fabricating an array substrate.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
  • a further embodiment of the present invention provides a method of fabricating an array substrate.
  • the array substrate manufactured by the method is also a thin film transistor provided in the above embodiment.
  • the manufacturing method includes the following steps:
  • a gate insulating layer covering the gate line and the gate is formed, and an active layer is formed on the gate insulating layer.
  • the drain, the source and the auxiliary drain are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel can be realized.
  • the length is reduced, the opening current of the thin film transistor is increased, and the charging capability of the thin film transistor is improved, and no additional process steps are added.
  • the above methods further include:
  • Steps S401 to S408 can be used to manufacture an array substrate applied to the ADS display mode.
  • the method for manufacturing the array substrate provided by the above embodiments of the present invention can be applied to different display modes including: TN (Twisted Nematic), IPS (In-Plane Switching) Various display modes such as AD-SDS (Advanced-Super Dimensional Switching, ADS for short).
  • the thin film transistor of the bottom gate structure is taken as an example for description.
  • the method according to an embodiment of the present invention is not limited to a thin film transistor which is applied to a bottom gate structure, but can be applied to a top gate structure or other structure of a thin film transistor.
  • a source and a drain an active layer, a gate insulating layer, and a gate may be sequentially formed.
  • a gate insulating layer is interposed between the gate electrode and the active layer, and the source and the drain are spaced apart from each other and are at least partially in contact with the active layer.
  • Embodiments of the present invention provide a method for fabricating an array substrate.
  • the drain and the source are respectively formed by double exposure, so that the source and the drain of the array substrate are respectively formed on different layers, and the channel length can be reduced. , to increase the opening current of the thin film transistor, to achieve the purpose of improving the charging ability of the thin film transistor.
  • the array substrate and the manufacturing method thereof are all based on the thin film transistor provided by the embodiment of the present invention, and the difference is only due to the difference in connection manner between the pixel electrode and the drain caused by using different thin film transistors. Only a few array substrates and their manufacturing methods are shown here, as long as they are manufactured by the thin film transistor provided by the embodiment of the present invention and the manufacturing method thereof, and are all within the protection scope of the present invention.
  • a thin film transistor comprising:
  • drain and the source are formed separately by two patterning processes.
  • An array substrate comprising the thin film transistor according to any one of (1) to (7).
  • a display device comprising the array substrate according to (8) or (9).
  • a method of manufacturing a thin film transistor comprising:
  • drain and the source are formed separately by two patterning processes.
  • a second conductive material layer is formed, and a source corresponding to the drain or a drain corresponding to the source is formed by one patterning process.
  • a protective layer is formed over the source and drain.

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Abstract

Des modes de réalisation de la présente invention concernent un transistor à couche mince et son procédé de fabrication, un substrat de matrice et un dispositif d'affichage. Le transistor à couche mince comprend : un substrat ; et une grille, une couche d'isolation de grille, une couche active, une source et un drain formés sur le substrat. La couche d'isolation de grille est intercalée entre la grille et la couche active. La source et le drain sont séparés l'un de l'autre et tous deux sont au moins partiellement en contact avec la couche active. La partie, correspondant à l'espace entre la source et le drain, de la couche active comporte un sillon. Le drain et la source sont fabriqués au moyen de deux processus de traçage de motif respectivement.
PCT/CN2012/084761 2012-06-08 2012-11-16 Transistor à couche mince et son procédé de fabrication, substrat de matrice et dispositif d'affichage WO2013181902A1 (fr)

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CN102723365B (zh) * 2012-06-08 2015-06-10 京东方科技集团股份有限公司 一种薄膜晶体管及其制造方法、阵列基板和显示装置
CN105514032A (zh) 2016-01-11 2016-04-20 深圳市华星光电技术有限公司 Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板
CN108646488A (zh) * 2018-05-18 2018-10-12 信利半导体有限公司 一种液晶显示装置
CN109494257B (zh) * 2018-10-26 2021-01-01 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制造方法、阵列基板、显示装置
CN113964191B (zh) * 2021-10-20 2023-06-23 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置

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