CN107895726A - A kind of array base palte and preparation method thereof and display device - Google Patents
A kind of array base palte and preparation method thereof and display device Download PDFInfo
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- CN107895726A CN107895726A CN201711242532.6A CN201711242532A CN107895726A CN 107895726 A CN107895726 A CN 107895726A CN 201711242532 A CN201711242532 A CN 201711242532A CN 107895726 A CN107895726 A CN 107895726A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
The invention discloses a kind of array base palte and preparation method thereof and display device.Array base palte, including multiple thin film transistor (TFT)s, thin film transistor (TFT) include：Active layer, active layer includes main channel region and edge channels area, and in the first direction, edge channels area is located at the both sides of main channel region；Insulating barrier, is arranged at active layer, and the orthographic projection of insulating barrier plane where active layer covers main channel region and edge channels area；Gate metal layer, it is arranged on insulating barrier, gate metal layer includes grid and gate line, wherein, gate line is connected with grid, and gate line extends in a first direction, and grid orthographic projection of plane where active layer overlaps with main channel region, on in a second direction, the width of grid is more than the width of gate line.According to technical scheme, hump effect caused by thin film transistor (TFT) can be avoided, improves array base palte and display device performance reliability.
Description
Technical field
The present invention relates to display technology field, is filled more particularly, to a kind of array base palte and preparation method thereof and display
Put.
Background technology
Display panel mainly includes two major classes at present：LCD display panel (Liquid Crystal Display, liquid crystal
Show panel) and OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display panel.In display panel
In technology, TFT (Thin Film Transistor, TFT) is the core component of display panel, typically in
Array arrangement is produced on substrate, the switching device as display panel pixel unit.Thin film transistor (TFT) includes：Grid, source electrode,
Drain electrode and active layer, source electrode and drain electrode are connected with active layer respectively, after voltage is applied to grid, as grid voltage increases,
Active layer surface will be changed into electron accumulation layer by depletion layer, be formed inversion layer, (be reached cut-in voltage when reaching strong inversion
When), active layer has carrier movement to realize the conducting between source electrode and drain electrode.For structure, according to the position of grid, film
Transistor is generally divided into two kinds of structures of top-gated and bottom gate.
But found in actual application, the reliability of conventional thin film transistor (TFT) is poor.It is therefore it provides a kind of
Array base palte of dependable performance and preparation method thereof and display device, it is this area urgent problem to be solved.
The content of the invention
In view of this, the invention provides a kind of array base palte and preparation method thereof and display device, solves raising
The technical problem of energy reliability.
In a first aspect, in order to solve the above-mentioned technical problem, the present invention proposes a kind of array base palte, including multiple film crystals
Pipe, thin film transistor (TFT) include：
Active layer, active layer includes main channel region and edge channels area, and in the first direction, edge channels area is positioned at master
The both sides of channel region；
Insulating barrier, is arranged at active layer, the orthographic projection of insulating barrier plane where active layer cover main channel region and
Edge channels area；
Gate metal layer, it is arranged on insulating barrier, gate metal layer includes grid and gate line,
Wherein, gate line is connected with grid, and gate line extends in a first direction, and plane is being just where active layer for grid
Projection overlaps with main channel region, in a second direction on, the width of grid is more than the width of gate line, first direction and second direction
It is parallel with the plane where active layer, and first direction intersects with second direction.
Second aspect, in order to solve the above-mentioned technical problem, the present invention propose a kind of preparation method of array base palte, array base
Plate includes multiple thin film transistor (TFT)s, and preparation method includes：
The active layer of thin film transistor (TFT) is made, active layer includes main channel region and edge channels area, in the first direction,
Edge channels area is located at the both sides of main channel region；
The insulating barrier of thin film transistor (TFT), the orthographic projection covering of insulating barrier plane where active layer are made in active layer
Main channel region and edge channels area；
The gate metal layer of thin film transistor (TFT) is made on insulating barrier, gate metal layer includes grid and gate line, its
In, gate line is connected with grid, and gate line extends in a first direction, the grid orthographic projection of plane and tap drain where active layer
Road area overlaps, in a second direction on, the width of grid is more than the width of gate line, first direction with second direction and active layer
The plane at place is parallel, and first direction intersects with second direction.
The third aspect, in order to solve the above-mentioned technical problem, the present invention propose a kind of display device, including proposed by the present invention
Any one array base palte.
Compared with prior art, array base palte of the invention and preparation method thereof and display device, realizing following has
Beneficial effect：
Thin film transistor (TFT) in array base palte provided by the invention, when being passed through voltage in grid and gate line, marginal ditch
Because the effect of grid voltage produces electric current in road area, but at least side of top edge channel region is present not by grid in a second direction
The region of line covering, edge channels area can not go up source electrode and drain electrode in direct conducting membrane transistor in a second direction, avoid
Edge channels area, which is preferentially opened, makes thin film transistor (TFT) produce hump effect, and then lifts display device performance reliability.
By referring to the drawings to the present invention exemplary embodiment detailed description, further feature of the invention and its
Advantage will be made apparent from.
Brief description of the drawings
It is combined in the description and the accompanying drawing of a part for constitution instruction shows embodiments of the invention, and even
It is used for the principle for explaining the present invention together with its explanation.
Fig. 1 is the schematic top plan view of thin film transistor (TFT) in correlation technique；
Fig. 2 is the schematic top plan view of thin film transistor (TFT) in array base palte provided in an embodiment of the present invention；
Fig. 3 is the diagrammatic cross-section of tangentially A-A ' in Fig. 2；
Fig. 4 is that another optional embodiment vertical view of the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention is shown
It is intended to；
Fig. 5 is that another optional embodiment vertical view of the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention is shown
It is intended to；
Fig. 6 is the schematic cross-sectional view of tangentially C-C ' in Fig. 5；
Fig. 7 is a kind of optional embodiment schematic diagram of thin film transistor (TFT) in correlation technique；
Fig. 8 is that another optional embodiment vertical view of the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention is shown
It is intended to；
Fig. 9 is that another optional embodiment vertical view of the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention is shown
It is intended to；
Figure 10 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention；
Figure 11 is the flow chart of the preparation method another kind optional embodiment of array base palte provided in an embodiment of the present invention；
Figure 12 is display device schematic diagram provided in an embodiment of the present invention.
Embodiment
The various exemplary embodiments of the present invention are described in detail now with reference to accompanying drawing.It should be noted that：Unless have in addition
Body illustrates that the unlimited system of part and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The scope of invention.
The description only actually at least one exemplary embodiment is illustrative to be never used as to the present invention below
And its application or any restrictions that use.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely exemplary, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined, then it need not be further discussed in subsequent accompanying drawing in individual accompanying drawing.
The present invention relates to a kind of array base palte, formed with thin film transistor (TFT) (Thin- on array base palte
Filmtransistor, TFT), array base palte provided by the invention can be applied to liquid crystal display panel, be readily applicable to
Machine light emitting display panel.Switching devices of the TFT formed on array base palte as pixel cell, including：Grid, source electrode, drain electrode
And active layer, source electrode and drain electrode are connected with active layer respectively, after voltage is applied to grid, are formed between grid and active layer
Electric field, and then cause the movement of carrier in active layer to realize the conducting between source electrode and drain electrode.It is also formed with array base palte
Gate line and data wire, gate line are connected to transmit gated sweep signal for display panel with grid, and data wire connects with drain electrode
Connect for transmitting data-signal.
Fig. 1 is the schematic top plan view of thin film transistor (TFT) in correlation technique, as shown in figure 1, thin film transistor (TFT) includes active layer
101 ', active layer 101 ' includes main channel region Z ' and edge channels area B ', and grid 102 ' is in the top of active layer 101 ' along direction a '
Cross active layer 101 ', when to grid 102 ' apply voltage when, the main channel region Z ' of electric field controls caused by the voltage of grid 102 ' and
Carrier interior edge channels area B ' produces movement, and then realizes the conducting of source electrode 103 ' and drain electrode 104 ', in the related art,
When applying voltage to grid 102 ', main channel region Z ' can produce source electrode and the drain electrode of carrier mobility conducting membrane transistor,
Edge channels area B ' can produce source electrode and the drain electrode of carrier mobility conducting membrane transistor, and edge channels in correlation technique
When area B ' can reach saturation current prior to main channel region Z ' and open in advance, cause thin film transistor (TFT) to produce hump effect, influence thin
Film transistor performance.
It is real by designing a kind of structure of new thin film transistor (TFT) the present invention relates to a kind of array base palte and display panel
The characteristic of the main channel region of existing thin film transistor (TFT) major embodiment, avoid thin film transistor (TFT) and produce hump effect, improve film crystalline substance
Body pipe performance reliability, and then lift array base palte performance reliability.
The present invention provides a kind of array base palte, and array base palte includes multiple thin film transistor (TFT)s, and Fig. 2 is battle array provided by the invention
The schematic top plan view of thin film transistor (TFT) in row substrate.Fig. 3 is the diagrammatic cross-section of tangentially A-A ' in Fig. 2.With reference to Fig. 2 and
Shown in Fig. 3, thin film transistor (TFT) includes：Active layer 101, active layer 101 include main channel region Z and edge channels area B, along first
On a of direction, edge channels area B is located at main channel region Z both sides；Insulating barrier 102 is arranged on active layer 101, insulating barrier 102
For gate insulator, insulating barrier 102 covers main channel region Z and edge channels area B in the orthographic projection of the place plane of active layer 101；
Gate metal layer 103 is arranged on insulating barrier 102, and gate metal layer 103 includes grid 1031 and gate line 1032, wherein,
Gate line 1032 is connected with grid 1031, and a extends gate line 1032 in the first direction, and grid 1031 is where active layer 101
The orthographic projection of plane overlaps with main channel region Z, wherein, gate line 1032 includes the grid line segment being connected with grid 1031
10321, grid line segment 10321 overlaps in the orthographic projection of the place plane of active layer 101 with edge channels area B, in a second direction b
On, the width d1 of grid 1031 be more than the width d2, first direction a and second direction b of gate line 1032 with active layer place
Plane it is parallel, and first direction a intersects with second direction b.It should be noted that in array base palte provided by the invention, film
Transistor also includes source electrode and drain electrode and other necessary insulation layer structures (being not shown in fig. 2).
Array base palte provided by the invention, when being passed through voltage in grid 1031 and gate line 1032, main channel region Z and side
Edge channel region B produces the migration of carrier due to the effect of grid voltage, but in b top edges channel region B in a second direction at least
Side has the region that is not covered by gate line 1032, and (situation about being shown in region B1 in such as Fig. 2, Fig. 2 is along second party
To the b top edge channel regions B equal domain of the existence B1 in both sides), the source electrode that edge channels area B can not be directly in conducting membrane transistor
And drain electrode, avoid edge channels area B and preferentially open generation hump effect, improve thin-film transistor performance reliability, and then
Lift array base palte performance reliability.
The making material of the active layer of thin film transistor (TFT) is semi-conducting material in array base palte, array base palte manufacturing process
In, the active layer to complete first is non-conductive state, when completing to make the gate insulator and grid of thin film transistor (TFT),
Conductive region would generally be formed to not carrying out conductive treatment by the region that gate insulator and grid cover in active layer
(such as region Q in Fig. 2), in the postorder manufacture craft of array base palte, conductive region can accordingly with thin film transistor (TFT)
Source electrode and drain electrode connect, and when applying voltage to grid and gate line, due to the effect of grid voltage, channel region is (by grid in active layer
Pole and the region of gate line covering) in carrier movement, and then realize the conducting between thin film transistor (TFT) source-drain electrode.
In array base palte provided by the invention, insulating barrier 102 is in the orthographic projection covering tap drain road of the place plane of active layer 101
Area Z and edge channels area B, the then part not covered in active layer 101 by insulating barrier 102 (region Q in Fig. 2) will pass through conduction
Change processing and form conductive region；Grid 1031 is connected with gate line 1032, and in a second direction on b, the width d1 of grid 1031 is big
In the width d2 of gate line 1032, grid 1031 overlaps in the orthographic projection of the place plane of active layer 101 with main channel region Z, this hair
The part of grid pole line segment 10321 being in contact in bright with grid 1031 is in the orthographic projection position of the place plane of active layer 101 and marginal ditch
Road area B overlaps (the grid line segment 10321 referring to figs. 2 and 3 in), namely in the present invention in a second direction on b in marginal ditch
The region B1 not covered by grid 1031 and gate line 1032 be present (referring to figs. 2 and 3 middle region B1's in road area B at least sides
Position), when being passed through voltage to grid 1031 and gate line 1032, the effect in main channel region Z due to electric field produces carrier
Main channel region Z conducting is realized in migration, and carrier mobility can be also produced in the edge channels area B that grid line segment 10321 covers, but
Be region B1 because corresponding top position is not provided with grid 1031 or gate line 1032, so the active layer material at the B1 of region
Material is always semi-conducting material, it is impossible to conducting can not be realized by producing carrier mobility, namely in the present invention edge channels area B the
On two direction b can not direct conducting membrane transistor source-drain electrode.
Array base palte provided by the invention, when being passed through voltage in grid 1031 and gate line 1032, produced in edge road area B
Raw carrier mobility can not be directly in conducting membrane transistor source electrode and drain electrode, avoid edge channels area B and preferentially open production
Raw hump effect, thin-film transistor performance reliability is improved, and then lift array base palte performance reliability.
It should be noted that insulating barrier 102 and the position relationship of gate metal layer 103 are only exemplary expressions in Fig. 2,
By designing the difference of the length of upper grid and gate line in a second direction, realize in top edge channel region in a second direction extremely
There is the region for being covered but do not covered by gate metal layer by gate insulator in few side, carrier is produced in edge channels area
The design method that migration can not directly form the conducting in thin film transistor (TFT) between source-drain electrode belongs to the scope of protection of the invention
Within.For example, another optional embodiment that Fig. 4 is the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention is overlooked
Schematic diagram, as shown in figure 4, grid 1031 is connected with gate line 1032, in a second direction on b, the width d1 of grid 1031 is more than
The width d2 of gate line 1032, the interior presence of active layer 101 are covered by insulating barrier 102, but not by grid 1031 or gate line
The region B1 of 1032 coverings, region B1 is semi-conducting material, when applying voltage to gate metal layer, region B1 top phase
Position is answered not have electric field covering, it is impossible to carrier movement is produced, namely on b, edge channels area can not be direct in a second direction
The conducting between source-drain electrode in thin film transistor (TFT) is formed, edge channels area can be avoided preferentially to open and produce hump effect.
Further, in some optional embodiments, the film crystal of array base palte provided in an embodiment of the present invention
Guan Zhong, as shown in Fig. 2 in a second direction on b, the width d2 of the gate line 1032 and width d1 of grid 1031 ratio is 0.1
~0.9.In practice, according to the different design requirement of thin film transistor (TFT), such as the material selected of gate metal layer or in grid
The difference of the voltage applied on metal level, the specific width of design upper grid and gate line in a second direction, meet grid and
On gate line in the case of voltage requirements, the Ratio control of the width of the width of upper gate line and grid in a second direction is existed
Between 0.1~0.9, it can meet exist by gate insulator covering still in the edge channels area at least side of thin film transistor (TFT)
The region not covered by gate metal layer, and then avoid edge channels area and preferentially open and produce hump effect, improve battle array
The performance reliability of row substrate.
Further, in some optional embodiments, Fig. 5 is the film of array base palte provided in an embodiment of the present invention
Another optional embodiment schematic top plan view of transistor, Fig. 6 are the schematic cross-sectional view of tangentially C-C ' in Fig. 5, are joined simultaneously
Examine shown in Fig. 5 and Fig. 6, thin film transistor (TFT) includes：Active layer 101, active layer 101 include main channel region Z and edge channels area,
In the first direction on a, edge channels area (not shown) is located at main channel region Z both sides；Insulating barrier 102 be arranged at active layer it
On, insulating barrier 102 covers main channel region Z and edge channels area in the orthographic projection of the place plane of active layer 101；Gate metal layer
103 are arranged on insulating barrier 102, and gate metal layer 103 includes grid 1031 and gate line 1032, wherein, gate line 1032
It is connected with grid 1031, a extends gate line 1032 in the first direction, positive throwing of the grid 1031 in the place plane of active layer 101
Shadow overlaps with main channel region Z, and in a second direction on b, the width d1 of grid 1031 is more than the width d2 of gate line 1032, this implementation
In mode, insulating barrier 102 includes the first insulation branch 1021, and the first insulation branch 1021 covers main channel region Z；In a second direction
On b, the width d1 of grid 1031 is less than the width d3 of the first insulation branch 1021.
Array base palte when making can to active layer in not by the region of insulating barrier (referred to gate insulator) covering
Carry out conductive treatment, it is necessary to carry out conductive treatment region namely present embodiment in shown in Fig. 5 and Fig. 6 along second
It is located at the region of the both sides of insulating barrier 102 on the b of direction, namely the region Q identified in Fig. 6, conductive treatment enable to both sides
The increase of region Q carriers concentration, such as the Lacking oxygen in the Q of region can be increased by corona treatment to increase current-carrying
Sub- concentration.
Fig. 7 is a kind of optional embodiment schematic diagram of thin film transistor (TFT) in correlation technique, as shown in fig. 7, in related skill
In art, grid 103 ' is channel region Z ' in the view field of the place of active layer 101 ' plane, along the upper active layers 101 ' of direction b '
Be disposed with region Q ', channel region Z ' and region Q ', Lacking oxygen interior the region Q ' after conductive treatment can along direction b ' to
The interior diffusions of channel region Z ', so that carrier concentration increase interior channel region Z ', causes in correlation technique in region Z1 ' positions
Parasitic capacitance be present, when applying voltage to grid 103 ', the bad stability of film transistor device.
The array base palte that embodiment of the present invention provides, exist in edge channels area at least side by insulating barrier covering still
The region not covered by gate metal layer, leading between source-drain electrode in thin film transistor (TFT) can not be directly formed in edge channels area
It is logical, avoid edge channels area and preferentially open and produce hump effect, improve array base palte performance reliability；Conductive treatment
The Lacking oxygen in the Q of region afterwards can the side of b to main channel region Z in a second direction diffuse up, such as diffusion zone is region Z1,
And in the embodiment, in a second direction on b, the width of grid 1031 is less than the width of the first insulation branch 1021, can drop
Low grid 1031 is in the projection (i.e. main channel region Z) of active layer 101 and region Z1 overlapping area, or even main channel region Z side
Boundary just overlaps with region Z1 border, so as to reduce parasitic capacitance, when applying voltage to grid 1031, and thin film transistor (TFT)
It can be turned on when reaching threshold voltage, ensure that thin-film transistor performance stability.
The embodiment provide array base palte, optionally, make when thin film transistor (TFT) in film layer insulating barrier and grid
Metal level can make respectively, i.e., made using different mask plates, form insulating barrier 102 and grid gold as shown in Figure 5
Belong to the shape of layer 103.Optionally, Fig. 8 is the another optional of the thin film transistor (TFT) of array base palte provided in an embodiment of the present invention
Embodiment schematic top plan view.When making in thin film transistor (TFT) insulating barrier 102 and gate metal layer 103 can also use it is same
Individual mask plate makes, and increases certain etch period when making the pattern of gate metal layer 103, and over etching forms gate metal
The pattern of layer 103, inside contracts than insulating barrier 102 equivalent to gate metal layer 103, realizes simultaneously, in a second direction on b, grid
1031 width d1 is more than the width d2 of gate line 1032, and the width d1 of grid 1031 is less than the width of the first insulation branch 1021
D3, while solve the problems, such as the problem of hump effect and parasitic capacitance in thin film transistor (TFT).
Further, in some optional embodiments, in array base palte provided in an embodiment of the present invention, such as Fig. 5 institutes
Show in a second direction on b, the width d1 of grid 1031 is smaller 1~2 μm than the width d3 of the first insulation branch 1021.Film crystal
In pipe active layer, diffusion of the oxygen vacancies in region to channel region direction after conductive treatment is due to oxygen vacancies concentration height
Caused by low difference, so oxygen vacancies is limited to the length for being diffused in upper diffusion in a second direction in channel region direction, it is somebody's turn to do
In embodiment, set in a second direction, the width of grid is smaller 1~2 μm than the width of the first insulation branch, guarantees to drop
Low grid is in the projection (i.e. main channel region) of active layer and the overlapping area of oxygen vacancies diffusion zone, or even the border of main channel region
Just overlapped with the border of oxygen vacancies diffusion zone, so as to reduce parasitic capacitance, avoid the grid of setting in a second direction
Width it is too small so that in the region that the electric field that active layer has grid voltage can not be covered and oxygen vacancies can not be diffused into
(namely grid situation about not overlapped completely in projection and the oxygen vacancies diffusion zone of active layer), the region remains as semiconductor
Region, channel region is caused to be unable to normally, so as to have impact on array base palte performance.
Further, in some optional embodiments, Fig. 9 is the film of array base palte provided in an embodiment of the present invention
Another optional embodiment schematic top plan view of transistor, as shown in figure 9, positive throwing of the grid in the place plane of insulating barrier 102
Shadow is the first projection Y；First projection Y has the symmetry axis S of a extensions in the first direction, and the first insulation branch 1021 is on symmetrical
Axle S is symmetrical, and distances of the border J1 away from symmetry axis S of the first projection Y extensions of a in the first direction is the first distance d4, and first is exhausted
Distances of the border J2 away from symmetry axis S of the extensions of a in the first direction in fate portion 1021 is less than for second distance d5, the first distance d4
Second distance d5.Implication in Fig. 9 represented by drawing reference numeral can accordingly in reference chart 2 embodiment explanation.Optionally,
One distance d4 is smaller than second distance d5 0.5~1 μm.
The embodiment provide array base palte, edge channels area at least side exist by insulating barrier cover but not by
The region of gate metal layer covering, edge channels area can not directly form the conducting in thin film transistor (TFT) between source-drain electrode, avoid
Edge channels areas preferentially open and make it that thin film transistor (TFT) produces hump effect, improves array base palte performance reliability；Edge
In second direction, the width of grid is less than the width of the first insulation branch, can reduce parasitic capacitance, ensure thin film transistor (TFT)
Stability；Meanwhile in the embodiment, the first projection and the first insulation branch are on same symmetrical axial symmetry, explanation
Grid in a second direction on the distance that is inside contracted relative to insulating barrier of the left and right sides it is identical, this regular symmetrical structure,
Using mask plate etching grid metal level pattern or insulating barrier pattern when, be more easy to make.Moreover, the embodiment provides
Array base palte when making, insulating barrier and gate metal layer can use same mask plate to make, and be increased without technique system
Journey, cost of manufacture is saved.
Further, in some optional embodiments, with reference to shown in figure 3, edge channels area B surface M1 with it is active
The bottom surface M2 of layer 101 forms angle of gradient θ.The array base palte that the embodiment provides, the edge of the middle active layer of thin film transistor (TFT)
The surface of channel region and the bottom surface of active layer form the angle of gradient, and the size of the angle of gradient is acute angle, and the edge for ensureing active layer is
Suitable step shape as shown in Figure 3, active layer generally use wet-etching technique make, and edge is that ensure that active layer along step shape
Marginal position is less prone to the residual of etching solution and influences other film layers laid on active layer, while is set again on active layer
When putting metal level, metal level improves array base palte to having preferable spreadability to reduce the risk that metal breaks along step
Performance reliability.
Further, in some optional embodiments, with reference to shown in figure 3, a top edges channel region B in the first direction
Length L be 0.1~1 μm.Edge channels area can not direct conducting membrane transistor in the array base palte that the embodiment provides
Source-drain electrode, avoid edge channels area and preferentially open and make it that thin film transistor (TFT) produces hump effect, set in the embodiment
It is 0.1~1 μm to count length of the edge channels area of thin film transistor (TFT) in the first direction, and edge channels area accounts for smaller, energy
Enough to meet for edge channels area to be designed to suitable step shape as shown in Figure 3, metal level along step to having preferable spreadability to drop
The risk of low metal broken string.
Further, in some optional embodiments, in array base palte provided in an embodiment of the present invention, film crystal
The making material of the active layer of pipe can be oxide semiconductor material.But not limited to this, the making material of active layer can also
For polysilicon semiconductor or amorphous silicon semiconductor etc..Using oxide semiconductor material make active layer, generally have compared with
High mobility (μFE>10cm2/ Vs), the small sub- threshold values amplitude of oscillation and relatively low off-state current, array base palte provided by the invention,
When the making material of thin film transistor active layer is oxide semiconductor material, array base palte can be applied to large scale display surface
Plate, and the displays such as driving superelevation fine liquid crystal display panel, organic electroluminescence display panel or Electronic Paper can be applied to
Part.
Optionally, oxide semiconductor material can be indium gallium zinc oxide (IGZO), and indium gallium zinc oxygen is used in the present invention
Semi-conducting material of the compound as thin film transistor (TFT), carrier mobility is 20~30 times of non-crystalline silicon in indium gallium zinc oxide,
Charge-discharge velocity of the thin film transistor (TFT) to pixel electrode can be greatly improved, improves the response speed of pixel, realizes brush faster
New rate, while response also substantially increases the line scanning rate of pixel faster, improves display resolution.
The present invention also provides a kind of preparation method of array base palte, preparation method provided by the invention with it is provided by the invention
Product belongs to a total inventive concept, when understanding of the invention, for array base palte and the reality of the preparation method of array base palte
Applying example can mutually refer to.
Figure 10 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention.As shown in Figure 10, array base
Plate includes multiple thin film transistor (TFT)s, and preparation method provided by the invention includes：
Step S101：The active layer of thin film transistor (TFT) is made, active layer includes main channel region and edge channels area, along the
On one direction, edge channels area is located at the both sides of main channel region；
Step S102：The insulating barrier of thin film transistor (TFT), insulating barrier plane where active layer are made in active layer
Orthographic projection covers main channel region and edge channels area；
Step S103：On insulating barrier make thin film transistor (TFT) gate metal layer, gate metal layer include grid and
Gate line, wherein, gate line is connected with grid, and gate line extends in a first direction, and plane is being just where active layer for grid
Projection overlaps with main channel region, in a second direction on, the width of grid is more than the width of gate line, first direction and second direction
It is parallel with the plane where active layer, and first direction intersects with second direction.
The thin film transistor (TFT) schematic diagram of the array base palte made using the embodiment may be referred to shown in Fig. 2 and Fig. 3, adopt
With the embodiment make array base palte, when being passed through voltage in grid and gate line, main channel region and edge channels area by
Carrier mobility is produced in the effect of grid voltage, but is existed at least side of top edge channel region in a second direction not by grid
The region of polar curve covering, the source electrode and drain electrode that edge channels area can not be directly in conducting membrane transistor, avoids edge channels
Generation hump effect is preferentially opened in area, improves thin-film transistor performance reliability, and then lift array base palte performance reliability.
Further, in some optional embodiments, step S102 is further：Film is made in active layer
The insulating barrier of transistor, the orthographic projection of insulating barrier plane where active layer cover main channel region and edge channels area, wherein, absolutely
Edge layer includes the first insulation branch, and the first insulation branch covers main channel region；Step S103 is further：Made on insulating barrier
Make the gate metal layer of thin film transistor (TFT), gate metal layer includes grid and gate line, wherein, gate line is connected with grid,
Gate line extends in a first direction, and grid orthographic projection of plane where active layer overlaps with main channel region, in a second direction on,
The width of grid is more than the width of gate line, and the width of grid is less than the width of the first insulation branch.
The thin film transistor (TFT) of the array base palte made using the embodiment is referred to shown in Fig. 5 and Fig. 6, using the reality
The array base palte that the mode of applying makes, top edge channel region at least side in a second direction exist by insulating barrier cover but not by
The region of gate metal layer covering, edge channels area can not directly form the conducting in thin film transistor (TFT) between source-drain electrode, avoid
Edge channels area preferentially opens and produces hump effect, improves array base palte performance reliability；Meanwhile in a second direction
On, the width of grid is less than the width of the first insulation branch, can reduce parasitic capacitance, when applying voltage to grid, film
Transistor can turn on when reaching threshold voltage, ensure that thin-film transistor performance stability.
Figure 11 is the flow chart of the preparation method another kind optional embodiment of array base palte provided in an embodiment of the present invention.
As shown in figure 11, array base palte includes multiple thin film transistor (TFT)s, and preparation method provided by the invention includes：
Step S201：The active layer of thin film transistor (TFT) is made, active layer includes main channel region and edge channels area, along the
On one direction, edge channels area is located at the both sides of main channel region；
Step S202：Insulation film and gate metal film are made successively in active layer；
Step S203：Processing, over etching grid gold are patterned to gate metal film by mask of the first mask plate
Belonging to film, form the pattern of the gate metal layer of thin film transistor (TFT), gate metal layer includes grid and gate line, wherein, grid
Line extends in a first direction, and grid orthographic projection of plane where active layer overlaps with main channel region, in a second direction on, grid
Width be more than gate line width, first direction is parallel with the plane where active layer with second direction, and first direction
Intersect with second direction；
Step S204：Processing is patterned to insulation film by mask of the first mask plate, forms thin film transistor (TFT)
The pattern of insulating barrier, wherein, insulating barrier includes the first insulation branch, and the first insulation branch covers main channel region, in a second direction
On, the width of grid is less than the width of the first insulation branch.
Thin film transistor (TFT) in the array base palte made using the embodiment is referred to shown in Fig. 8, the embodiment
In when making, insulating barrier and gate metal layer are made using same mask plate in thin film transistor (TFT), in making gate metal layer
Pattern when increase certain etch period, over etching forms the pattern of gate metal layer, equivalent to gate metal layer than insulating
Layer inside contracts, and realizes simultaneously, in a second direction on, the width of gate line is less than the width of grid, and the width of grid is less than first
Insulate the width of branch, and the embodiment solves the problems, such as asking for hump effect and parasitic capacitance in thin film transistor (TFT) simultaneously
Topic, also, insulating barrier and gate metal layer are made using same mask plate, are increased without manufacturing process, have been saved and be fabricated to
This.
Further, the present invention also provides a kind of display device, including any one array provided in an embodiment of the present invention
Substrate.Figure 12 is display device schematic diagram provided in an embodiment of the present invention.Display device provided by the invention, can be liquid crystal
Showing device or organic light-emitting display device.Include liquid crystal display panel and backlight mould when display device is liquid crystal display device
Group, liquid crystal display panel include color membrane substrates, liquid crystal layer and any one array base palte provided in an embodiment of the present invention.Display dress
When being set to machine luminous display unit, including organic electroluminescence display panel, organic electroluminescence display panel include light emitting device layer and this
Any one array base palte that inventive embodiments provide.
In the array base palte of display device provided by the invention, when being passed through voltage in grid and gate line, main channel region
With edge channels area because the effect of grid voltage produces carrier mobility, but at least the one of top edge channel region in a second direction
There is the region not covered by gate line in side, the source electrode and drain electrode that edge channels area can not be directly in conducting membrane transistor,
Avoid edge channels area and preferentially open generation hump effect, improve thin-film transistor performance reliability, and then lift array
Substrate performance reliability.
By above-described embodiment, array base palte of the invention and preparation method thereof and display device, reach as follows
Beneficial effect：
When being passed through voltage in grid and gate line, main channel region and edge channels area produces current-carrying due to the effect of grid voltage
Son migration, but the region not covered by gate line, edge at least side of top edge channel region in a second direction be present
Channel region can not be directly in conducting membrane transistor source electrode and drain electrode, avoid edge channels area and preferentially open and produce hump effect
Should, thin-film transistor performance reliability is improved, and then lift array base palte performance reliability.
Although some specific embodiments of the present invention are described in detail by example, the skill of this area
Art personnel it should be understood that example above merely to illustrating, the scope being not intended to be limiting of the invention.The skill of this area
Art personnel to above example it should be understood that can modify without departing from the scope and spirit of the present invention.This hair
Bright scope is defined by the following claims.
Claims (11)
1. a kind of array base palte, it is characterised in that including multiple thin film transistor (TFT)s, the thin film transistor (TFT) includes：
Active layer, the active layer include main channel region and edge channels area, in the first direction, the edge channels position
In the both sides of the main channel region；
Insulating barrier, it is arranged at the active layer, the orthographic projection covering institute of insulating barrier plane where the active layer
State main channel region and the edge channels area；
Gate metal layer, it is arranged on the insulating barrier, the gate metal layer includes grid and gate line,
Wherein, the gate line is connected with the grid, and the gate line extends along the first direction, and the grid is in institute
The orthographic projection for stating plane where active layer overlaps with the main channel region, in a second direction on, the width of the grid is more than institute
The width of gate line is stated, the first direction is parallel with the plane where the active layer and described with the second direction
First direction intersects with the second direction.
2. array base palte according to claim 1, it is characterised in that
Along in the second direction, the ratio of the width of the gate line and the width of the grid is 0.1~0.9.
3. array base palte according to claim 1, it is characterised in that
The insulating barrier includes the first insulation branch, and the first insulation branch covers the main channel region；
Along in the second direction, the width of the grid is less than the width of the described first insulation branch.
4. array base palte according to claim 3, it is characterised in that
Along in the second direction, the width of the grid is smaller 1~2 μm than the width of the described first insulation branch.
5. array base palte according to claim 4, it is characterised in that
The orthographic projection of grid plane where the insulating barrier is the first projection；
First projection is with the symmetry axis extended along the first direction, and the first insulation branch is on the symmetry axis
Symmetrically,
Distance of the border away from the symmetry axis along first direction extension of first projection is the first distance, described the
Distance of the border away from the symmetry axis along first direction extension of one insulation branch is second distance, first distance
Less than the second distance.
6. array base palte according to claim 1, it is characterised in that
The length in the edge channels area is 0.1~1 μm along the first direction.
7. array base palte according to claim 1, it is characterised in that
The surface in the edge channels area forms the angle of gradient with the bottom surface of the active layer.
8. array base palte according to claim 1, it is characterised in that
The making material of the active layer is oxide semiconductor material.
9. a kind of preparation method of array base palte, it is characterised in that the array base palte includes multiple thin film transistor (TFT)s, the system
Include as method：
The active layer of the thin film transistor (TFT) is made, the active layer includes main channel region and edge channels area, along first party
Upwards, the edge channels area is located at the both sides of the main channel region；
The insulating barrier of the thin film transistor (TFT), insulating barrier plane where the active layer are made in the active layer
Orthographic projection cover the main channel region and the edge channels area；
The gate metal layer of the thin film transistor (TFT) is made on the insulating barrier, the gate metal layer includes grid and grid
Polar curve, wherein, the gate line is connected with the grid, and the gate line extends along the first direction, and the grid exists
The orthographic projection of plane overlaps with the main channel region where the active layer, in a second direction on, the width of the grid is more than
The width of the gate line, the first direction is parallel with the plane where the active layer with the second direction, and institute
First direction is stated with the second direction to intersect.
10. the preparation method of array base palte according to claim 9, it is characterised in that made in the active layer
The insulating barrier of the thin film transistor (TFT) and the step of the gate metal layer of the thin film transistor (TFT) is made on the insulating barrier,
It is further：
Insulation film and gate metal film are made successively in the active layer；
Processing is patterned to the gate metal film using the first mask plate as mask, gate metal described in over etching is thin
Film, form the pattern of the gate metal layer of the thin film transistor (TFT)；
Processing is patterned to the insulation film using first mask plate as mask, forms the exhausted of the thin film transistor (TFT)
The pattern of edge layer；
Wherein, the insulating barrier includes the first insulation branch, and the first insulation branch covers the main channel region, along described the
On two directions, the width of the grid is less than the width of the described first insulation branch.
11. a kind of display device, it is characterised in that including the array base palte described in any one of claim 1 to 8.
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| CN111048524A (en) * | 2019-11-26 | 2020-04-21 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method and display panel |
| WO2020108196A1 (en) * | 2018-11-27 | 2020-06-04 | 京东方科技集团股份有限公司 | Display substrate and method for manufacturing same, and display device |
| CN111463267A (en) * | 2020-04-08 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112786707A (en) * | 2021-01-28 | 2021-05-11 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method, array substrate, display panel and display device |
| CN113327989A (en) * | 2021-05-19 | 2021-08-31 | 厦门天马微电子有限公司 | Thin film transistor, array substrate, display panel and display device |
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Application publication date: 20180410 |