CN104009043B - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN104009043B CN104009043B CN201410209616.XA CN201410209616A CN104009043B CN 104009043 B CN104009043 B CN 104009043B CN 201410209616 A CN201410209616 A CN 201410209616A CN 104009043 B CN104009043 B CN 104009043B
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- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000010409 thin film Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 243
- 239000012212 insulator Substances 0.000 claims description 41
- 238000003860 storage Methods 0.000 claims description 39
- 239000003990 capacitor Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 33
- 239000011241 protective layer Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 32
- 238000009413 insulation Methods 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 30
- 239000010408 film Substances 0.000 description 22
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 15
- 229910052750 molybdenum Inorganic materials 0.000 description 15
- 239000011733 molybdenum Substances 0.000 description 15
- 239000004411 aluminium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 239000004020 conductor Substances 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 208000034699 Vitreous floaters Diseases 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000003475 lamination Methods 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 6
- -1 IGZO) Chemical compound 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910001195 gallium oxide Inorganic materials 0.000 description 3
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011513 prestressed concrete Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
Abstract
The invention discloses a pixel structure, which comprises a thin film transistor element. The thin film transistor element comprises an oxide semiconductor layer, a grid insulating layer, a grid, a first connecting electrode, a second connecting electrode, a dielectric layer, a source electrode and a drain electrode. The oxide semiconductor layer is provided with a channel region, and a first contact region and a second contact region are respectively positioned at two opposite sides of the channel region. The first connecting electrode covers the upper surface of the first contact region, and the second connecting electrode covers the upper surface of the second contact region, wherein the first connecting electrode and the second connecting electrode do not overlap with the gate insulating layer in a vertical projection direction. The source electrode is electrically connected with the first contact area of the oxide semiconductor layer through the first connecting electrode, and the drain electrode is electrically connected with the second contact area of the oxide semiconductor layer through the second connecting electrode.
Description
Technical field
The present invention is that espespecially one kind is using connection electrode connection source/drain with regard to a kind of dot structure and preparation method thereof
Dot structure of pole and oxide semiconductor layer and preparation method thereof.
Background technology
Thin film transistor (TFT) (thin film transistor, TFT) element is a kind of to be widely used in the half of display floater
Conductor element, for example, apply in display panels (liquid crystal display panel, LCD panel), organic
Light emitting diode indicator (organic light emitting diode display panel, OLED display
) and the display floater such as Electronic Paper (electronic paper, E-paper) panel.The electron mobility of thin-film transistor element
(mobility) switch speed of thin-film transistor element is directly influenced, therefore for display picture quality has very big shadow
Ring.
At present the thin-film transistor element of display floater mainly can be distinguished according to the difference of the semiconductor layer material for using
Into amorphous silicon film transistor (amorphous silicon TFT, a-Si TFT) element, polycrystalline SiTFT (poly
Silicon TFT) element and oxide semiconductor thin-film transistor (oxide semiconductor TFT) element.Amorphous
Silicon thin film transistor element is limited to use amorphous silicon semiconductor material, therefore its electron mobility is relatively low, and (current non-crystalline silicon is thin
The electron mobility of film transistor element is about within 1cm2/Vs), therefore more high standard of visible future at present cannot be met and shown
The demand of device.Polycrystalline SiTFT is indebted to the characteristic of its polycrystalline silicon material, and having in electron mobility significantly improves
(electron mobility of polycrystalline SiTFT is optimal about up to 100cm2/Vs).But polycrystalline SiTFT element
Complex process (relatively cost), and crystallization degree uniformity not good problem is had when large size panel application deposit
, therefore at present polycrystalline SiTFT element is still based on small size panel application.Oxide semiconductor thin-film transistor unit
Part is then that, using the new oxide semiconductor material for emerging in recent years, such material is generally amorphous phase (amorphous) lattice
Structure, is not applied to the not good problem of uniformity on large size panel, and using various ways film forming, such as sputter
(sputter), the mode such as spin coating (spin-on) and printing (printing), therefore the more amorphous silicon thin film crystal in technique
Tube elements more have the elasticity that technique simplifies.The electron mobility of oxide semiconductor thin-film transistor element typically can more amorphous silicon
(electron mobility of oxide semiconductor thin-film transistor is generally arrived high more than 10 times of thin film transistor (TFT) between 10cm2/Vs
Between 50cm2/Vs), this degree can meet the demand of current visible following high standard display floater.
However, the contact in oxide semiconductor thin-film transistor element, between source/drain and oxide semiconductor layer
If impedance is excessive, the efficiency for causing thin-film transistor element is reduced and cannot effectively be played the characteristic of its high electron mobility,
Therefore be necessary to reduce the contact impedance between oxide semiconductor layer and source electrode/drain electrode, so that oxide semiconductor
Thin-film transistor element represents the characteristic of high electron mobility.
The content of the invention
An object of the present invention is to provide a kind of dot structure and preparation method thereof, to lift the film of dot structure
The element characteristic of transistor unit.
One embodiment of the invention provides a kind of dot structure, including a substrate, a thin-film transistor element, one first guarantor
Sheath and one first pixel electrode.Thin-film transistor element is arranged on substrate, and thin-film transistor element is including an oxidation
Thing semiconductor layer, a gate insulator, a grid, one first connection electrode, one second connection electrode, a dielectric layer, a source electrode
With a drain electrode.Oxide semiconductor layer is arranged on substrate, and oxide semiconductor layer has a channel region, and one first connects
Tactile area is with one second contact zone respectively positioned at the two opposite sides of channel region.Gate insulator is arranged on oxide semiconductor layer,
And gate insulator covers a upper surface of channel region and exposes a upper surface and second contact zone of the first contact zone
One upper surface.Grid is arranged on gate insulator.First connection electrode is respectively arranged at gate insulator with the second connection electrode
The both sides of layer, the first connection electrode cover the upper surface of the first contact zone and with the upper surface of the first contact zone, and second
Connection electrode cover the upper surface of the second contact zone and with the upper surface of the second contact zone, wherein the first connection electrode and the
Two connection electrodes are not Chong Die on a upright projection direction with gate insulator.Dielectric layer is arranged at grid, the first connection electrode
In the second connection electrode, there is its dielectric layer one first contact hole at least partly to expose a upper table of the first connection electrode
Face, and one second contact hole at least partly exposes a upper surface of the second connection electrode.Source electrode is arranged at dielectric with drain electrode
On layer, wherein source electrode is electrically connected with via the first contact hole and the first connection electrode, and drains via the second contact hole and second
Connection electrode is electrically connected with.First protective layer is arranged on dielectric layer, wherein the first protective layer has one the 3rd contact hole, at least
Part exposes drain electrode.First pixel electrode is arranged on the first protective layer, wherein the first pixel electrode is via the 3rd contact hole
Drain electrode with thin-film transistor element is electrically connected with.
Another embodiment of the present invention provides a kind of method for making dot structure, comprises the following steps.One substrate is provided,
And a patterned oxide semiconductor layer is formed on substrate, wherein patterned oxide semiconductor layer is partly led including monoxide
Body layer, and oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone are located at respectively passage
The two opposite sides in area.An insulating barrier and one first conductive layer are sequentially formed on substrate and patterned oxide semiconductor layer.
A patterned shielding is formed on the first conductive layer, wherein patterned shielding part covers the first conductive layer.Remove pattern
Change the first conductive layer for being exposed of shielding layer to form one first patterned conductive layer, and to remove patterned shielding institute sudden and violent
To form a patterned insulation layer, wherein patterned insulation layer includes a gate insulator, gate insulator to the insulating barrier for exposing
Cover a upper surface of channel region and expose a upper surface of the first contact zone and a upper surface of the second contact zone, and
First patterned conductive layer includes that a grid is located on gate insulator.On the substrate that patterned shielding is exposed, oxygen
One second conductive layer is formed on the upper surface of the first contact zone of compound semiconductor layer and on the upper surface of the second contact zone.Enter
Row one lifts off technique, while removing patterned shielding and the second conductive layer in patterned shielding to form one
Two patterned conductive layers, wherein the second patterned conductive layer includes one first connection electrode and one second connection electrode, with voluntarily
Alignment is respectively formed on the upper surface of the first contact zone and on the upper surface of the second contact zone, and the first connection electrode
It is not Chong Die on a upright projection direction with gate insulator with the second connection electrode.In grid, the first connection electrode and second
A dielectric layer is formed in connection electrode, there is its dielectric layer one first contact hole at least partly to expose the first connection electrode
One upper surface, and one second contact hole at least partly exposes a upper surface of the second connection electrode.Formed on dielectric layer
One the 3rd patterned conductive layer, wherein the 3rd patterned conductive layer includes a source electrode and a drain electrode, source electrode is via the first contact hole
It is electrically connected with the first connection electrode, and drains via the second contact hole and the electric connection of the second connection electrode.On dielectric layer
One first protective layer is formed, wherein the first protective layer has one the 3rd contact hole, drain electrode is at least partly exposed.In the first protection
One first pixel electrode is formed on layer.
Description of the drawings
Fig. 1 to Fig. 8 depicts the schematic diagram of the method for the making dot structure of the first embodiment of the present invention；
Fig. 9 and Figure 10 depicts the schematic diagram of the making dot structure of the second embodiment of the present invention；
Figure 11 depicts the schematic diagram of the dot structure of a comparative examples of the present invention；
Figure 12 depict the present invention comparative examples dot structure thin-film transistor element grid voltage VG with
The graph of a relation of drain current ID；
Figure 13 depicts the grid voltage VG's and drain current ID of the thin-film transistor element of the dot structure of the present invention
Graph of a relation；
Accompanying drawing identifier declaration：
10 substrates
10S switch elements area
10C storage capacitors area
10P pixel regions
12 cushions
14 patterned oxide semiconductor layers
14S oxide semiconductor layers
14C channel regions
141 first contact zones
142 second contact zones
14B storage capacitors bottom electrodes
16 insulating barriers
161 first insulation films
162 second insulation films
18 first conductive layers
20 patterned shieldings
201 first shielding layers
202 second shielding layers
22 first patterned conductive layers
24 patterned insulation layers
GI gate insulators
CD capacitance dielectric layers
14X upper surfaces
14Y upper surfaces
14Z upper surfaces
G grids
22T storage capacitors Top electrodes
Cst storage capacitors elements
26 second conductive layers
28 second patterned conductive layers
281 first connection electrodes
282 second connection electrodes
Z upright projections direction
283 conductive patterns
30 dielectric layers
TH1 first contacts hole
TH2 second contacts hole
32 the 3rd patterned conductive layers
S source electrodes
D drains
TFT thin-film transistor elements
34 first protective layers
TH3 the 3rd contacts hole
36 first pixel electrodes
50 dot structures
38 second protective layers
38A is open
40 display dielectric layers
42 second pixel electrodes
44 display elements
60 dot structures
70 dot structures
A curves
A ' curves
B curves
B ' curves
C curves
C ' curves
D curves
D ' curves
E curves
E ' curves
Specific embodiment
It is hereafter special to arrange to enable the those skilled in the art for being familiar with the technical field of the invention to be further understood that the present invention
Presently preferred embodiments of the present invention is lifted, and coordinates institute's accompanying drawings, the constitution content for describing the present invention in detail and the effect to be reached.
Refer to Fig. 1 to Fig. 8.Fig. 1 to Fig. 8 depicts the method for the making dot structure of the first embodiment of the present invention
Schematic diagram.As shown in figure 1, providing a substrate 10 first.Substrate 10 can be transparency carrier, and it can be hard substrate or bendable
Substrate such as glass substrate, quartz base plate or plastic base, but be not limited.Substrate 10 can have a switch element area 10S,
An one storage capacitors area 10C and pixel region 10P.Then, a cushion 12 is optionally formed on substrate 10.Cushion
12 can have insulation characterisitic, and its material can be inorganic insulating material such as silica, silicon nitride or silicon oxynitride, but not with this
It is limited, the material of cushion 12 also can be organic insulation.Additionally, cushion 12 can be single layer structure or lamination layer structure.
Subsequently, a patterned oxide semiconductor layer 14 is formed on substrate 10, if cushion 12 is present, patterned oxide is partly led
Body layer 14 is formed on cushion 12.The material of patterned oxide semiconductor layer 14 may include such as indium gallium zinc
(indium gallium zinc oxide, IGZO), indium gallium (indium gallium oxide, IGO), indium zinc oxide
(indium zinc oxide, IZO), tin indium oxide (indium tin oxide, ITO), zinc oxide (zinc oxide,
ZnO), indium oxide (indium oxide, InO), (indium tin zinc oxide, ITZO), gallium oxide (gallium
Oxide, GaO) or other suitable oxide semiconductor materials.Patterned oxide semiconductor layer 14 can have amorphous phase
(amorphous) structure, and it is formed using such as sputter, spin coating, printing or other suitable modes.Patterned oxide
Semiconductor layer 14 includes monoxide semiconductor layer 14S, is arranged in switch element area 10S, wherein oxide semiconductor layer 14S
It is relative with two that one second contact zone 142 is located at respectively channel region 14C with a channel region 14C, and one first contact zone 141
Side.In the present embodiment, channel region 14C, the first contact zone 141 and the second contact zone 142 are in the same plane, and passage
The two ends of area 14C are structurally joining together respectively with the first contact zone 141 and the second contact zone 142, that is, channel region 14C,
One contact zone 141 and the three of the second contact zone 142 are respectively a part of oxide semiconductor layer 14S.Additionally, patterning oxygen
Compound semiconductor layer 14 more may include a storage capacitors bottom electrode 14B, be arranged in the storage capacitors area 10C of substrate 10.
As shown in Fig. 2 then sequentially form an insulating barrier 16 on substrate 10 and patterned oxide semiconductor layer 14 with
And one first conductive layer 18.The material of insulating barrier 16 can be inorganic insulating material such as silica, silicon nitride or silicon oxynitride, but
It is not limited.In the present embodiment, insulating barrier 16 can be a compound layer insulating, and it may include one first insulation film 161
With one second insulation film 162, wherein the first insulation film 161 is formed on patterned oxide semiconductor layer 14, and second
Insulation film 162 is then formed on the first insulation film 161.First insulation film 161 can be by phase with the second insulation film 162
Constitute with material, wherein the first insulation film 161 can be formed using low temperature process, can thereby avoid patterned oxide semiconductor
Layer is 14 by high temperature, and the second insulation film 162 can be formed using high-temperature technology, thereby can have preferably insulation characterisitic and
Structural strength.In an alternate embodiment, insulating barrier 16 also can be a monolayer insulating layer.Additionally, the material of the first conductive layer 18
Transparent conductive material is may include, for example：Metal conductive oxide material (such as tin indium oxide), opaque conductive material, for example：
Metal such as aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, the alloy of above-mentioned metal composition or other suitable metal or alloy, but not
As limit.First conductive layer 18 can be single layer structure or lamination layer structure.
As shown in 3 figures, a patterned shielding 20 is then formed on the first conductive layer 18, part covers the first conductive layer
18.Patterned shielding 20 can be a such as photoresist layer, its using exposure and developing process be patterned, but not as
Limit.Patterned shielding 20 may include one first shielding layer 201 and one second shielding layer 202, wherein the first shielding layer 201 is located at
In the switch element area 10S of substrate 10 and cover corresponding to patterned oxide semiconductor layer 14 channel region 14C above
First conductive layer 18, and the second shielding layer 202 is located in the storage capacitors area 10C of substrate 10 and covers corresponding to storage capacitors
The first conductive layer 18 above bottom electrode 14B.In the present embodiment, the size of the first shielding layer 201 is substantially equal to patterned
The size of the channel region 14C of oxide semiconductor layer 14, and the second shielding layer 202 is dimensioned slightly smaller than storage capacitors bottom electrode
The size of 14B, but be not limited.For example in an alternate embodiment, the size of the second shielding layer 202 can be equal to storage capacitors
The size of bottom electrode 14B.Subsequently, the first conductive layer 18 that removal patterned shielding 20 is exposed is to form one first pattern
Change conductive layer 22, and the insulating barrier 16 that removal patterned shielding 20 is exposed to form a patterned insulation layer 24.Figure
Case insulating barrier 24 includes that an a gate insulator GI and capacitance dielectric layer CD, wherein gate insulator GI are located at switch element
In area 10S, and cover the upper surface 14X of channel region 14C and expose the upper surface 14Y of the first contact zone 141 and second and connect
The upper surface 14Z in tactile area 142；Capacitance dielectric layer CD is located in storage capacitors area 10C and part covers storage capacitors bottom electrode
14B.In the present embodiment, gate insulator GI and capacitance dielectric layer CD is respectively by the first insulation film 161 and the second insulation
162 storehouses of film are formed, but are not limited.First patterned conductive layer 22 is included in a grid G and a storage capacitors
Electrode 22T, wherein grid G are located in switch element area 10S and are located on gate insulator GI；Storage capacitors Top electrode 22T position
In storage capacitors area 10C and on storage capacitors bottom electrode 14B.Storage capacitors bottom electrode 14B, storage capacitors Top electrode
22T and the capacitance dielectric layer CD being located between storage capacitors bottom electrode 14B and storage capacitors Top electrode 22T constitute a storage electricity
Hold element Cst.Additionally, the first patterned conductive layer 22 more may include that a gate line (not shown) is electrically connected with grid G, or its
Its necessary wire such as common line (not shown).In the present embodiment, patterned shielding 20 is exposed first is removed
Conductive layer 18 is forming the first patterned conductive layer 22 and remove insulating barrier 16 that patterned shielding 20 exposed to be formed
The step of patterned insulation layer 24, is realized by the use of patterned shielding 20 as etch shield and using etch process.Example
Such as, etch process can select anisotropic etch process such as dry etching process, therefore the pattern of grid G with gate insulator GI's
Pattern substantially can be equal, that is to say, that the side wall of grid G substantially can be trimmed with the side wall of gate insulator GI, but not with
This is limited.
As shown in 4 figures, with the substrate 10 exposed after patterned shielding 20, oxide semiconductor layer 14
One second conductive layer 26 is formed on the upper surface 14Y of one contact zone 141 and on the upper surface 14Z of the second contact zone 142.Also
To say, on the upper surface 14Y of the first contact zone 141 of the oxide semiconductor layer 14 that the first shielding layer 201 is exposed and
On the upper surface 14Z of the second contact zone 142, the second shielding layer 202 part of storage capacitors bottom electrode 14B for being exposed
On upper surface, and the second conductive layer 26 can be formed on substrate 10 (or cushion 12).The material of the second conductive layer 26 can be wrapped
Transparent conductive material is included, for example：Metal conductive oxide material (such as tin indium oxide), opaque conductive material, for example：Metal
Such as aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, the alloy of above-mentioned metal composition or other suitable metal or alloy, but not with this
It is limited.Second conductive layer 26 can be single layer structure or lamination layer structure.The thickness visual material of the second conductive layer 26 is different in addition
Adjustment.For example, if the material selection metal such as molybdenum of the second conductive layer 26, its thickness substantially can be between 50 angstroms
(angstrom) between 200 angstroms, but it is not limited；If the material selection transparent conductive material of the second conductive layer 26, for example
Tin indium oxide, then its thickness can be thickness compared with metal, be greater than 200 angstroms, but be not limited.
As shown in figure 5, then carrying out one lifts off (lift-off) technique, while removing patterned shielding 20 and being located at
The second conductive layer 26 in patterned shielding 20 is forming one second patterned conductive layer 28.Second patterned conductive layer 28 is wrapped
One first connection electrode 281 and one second connection electrode 282 are included, to be voluntarily directed at (self-align) mode is respectively formed in
On the upper surface 14Y of one contact zone 141 and on the upper surface 14Z of the second contact zone 142, and the first connection electrode 281 and
Two connection electrodes 282 are not Chong Die on the Z of upright projection direction with gate insulator GI.Speak by the book, the first connection electrode 281
Side wall substantially can be trimmed respectively with the side wall of gate insulator GI and be completely covered respectively with the side wall of the second connection electrode 282
The upper surface 14Z of on the upper surface 14Y of the first contact zone 141 and the second contact zone 142.Additionally, the second patterned conductive layer
28 separately include a conductive pattern 283, be arranged at least side (such as both sides simultaneously) of capacitance dielectric layer CD and part covers storage
Capacitor lower electrode 14B, can thereby reduce the resistance of storage capacitors bottom electrode 14B.When the material selection metal of the second conductive layer 26
During oxide such as tin indium oxide, then the first connection electrode 281 and the second connection electrode 282 are metal conductive oxide electrode example
Such as indium oxide thing electrode；When the material selection metal or alloy of the second conductive layer 26, then the first connection electrode 281 and second connects
Receiving electrode 282 is metal electrode such as aluminium electrode, titanium/aluminium/Ti electrode, molybdenum electrode or molybdenum/aluminium/molybdenum electrode.From the foregoing, by
Utilize in the first connection electrode 281 and the second connection electrode 282 and lift off (lift-off) technique while removing patterned shielding
20 and the second conductive layer 26 in patterned shielding 20 formed, and patterned shielding 20 itself also have definition
Grid G and the pattern of gate insulator GI and the effect of position, therefore, the practice of the present embodiment has the effect being voluntarily aligned,
That is, grid G and gate insulator GI and the first connection electrode 281 and the relative position of the second connection electrode 282 are fixed
, it is possible to guarantee that the first connection electrode 281 can be completely covered the upper surface 14Y of the first contact zone 141, the second connection electrode
The 282 upper surface 14Z that the second contact zone 142 can be completely covered, and the first connection electrode 281 and the second connection electrode 282 will not
It is Chong Die on the Z of upright projection direction with gate insulator GI OR gates pole G.
As shown in fig. 6, retaining after the first connection electrode 281, the second connection electrode 282 and conductive pattern 283, and remove
Other unnecessary portions of second patterned conductive layer 28, such as the second pattern conductive on substrate 10 or cushion 12
Layer 28.Subsequently, a dielectric layer 30 is formed in grid G, the first connection electrode 281 and the second connection electrode 282, and in dielectric layer
One first is formed in 30 and contacts the upper surface 281S that hole TH1 at least partly exposes the first connection electrode 281, and one second connects
Tactile hole TH2 at least partly exposes the upper surface 282S of the second connection electrode 282.Dielectric layer 30 can have a planarization surface,
With the formation of sharp subsequent film.The material of dielectric layer 30 can be organic dielectric materials or Inorganic Dielectric Material, and dielectric layer 30 can
For single layer structure or lamination layer structure.
As shown in fig. 7, with one the 3rd patterned conductive layer 32 of formation on dielectric layer 30.3rd patterned conductive layer 30
Including a source S and a drain D, wherein source S is contacted with the first connection electrode 281 and electrically connected via the first contact hole TH1
Connect, and drain D is contacted and is electrically connected with via the second contact hole TH2 with the second connection electrode 282, to produce the present embodiment
Thin-film transistor element TFT.The material of the 3rd patterned conductive layer 32 may include transparent conductive material, for example：Metal oxide
Conductive material (such as tin indium oxide), opaque conductive material, for example：Metal such as aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, on
The alloy or other suitable metal or alloy of metal composition are stated, but is not limited.Additionally, the 3rd patterned conductive layer 32 can
For single layer structure or lamination layer structure.Additionally, the 3rd patterned conductive layer 32 more may include data wire (not shown) with source S electricity
Property connection, or other necessary wires.With one first protective layer 34 is formed on dielectric layer 30, wherein the first protective layer 34 has
There is one the 3rd contact hole TH3, at least partly expose drain D.First protective layer 34 can have a planarization surface, with sharp follow-up
The formation of film layer.The material of the first protective layer 34 can be organic insulation or inorganic insulating material, and the first protective layer 34 can
For single layer structure or lamination layer structure.
As shown in figure 8, the pixel that one first pixel electrode 36 is formed on the first protective layer 34 to form the present embodiment is tied
Structure 50, wherein the first pixel electrode 36 is located in pixel region 10P and extends in switch element area 10S and via the 3rd contact hole
TH3 is contacted and is electrically connected with the drain D of thin-film transistor element TFT.In the present embodiment, dot structure 50 is applied to organic
Electric exciting light emitting display panel, therefore can more further include the following steps.One second protective layer is formed on the first protective layer 34
38, wherein the second protective layer 38 has an opening 38A, expose in pixel region 10P and at least partly the first pixel electrode
36.The material of the second protective layer 38 can be tied for organic insulation or inorganic insulating material, and the second protective layer 38 for individual layer
Structure or lamination layer structure.After, a display dielectric layer 40, wherein display medium are formed in the opening 38A of the second protective layer 38
Layer 40 is an organic electric-excitation luminescent layer.Finally, one second pixel electrode 42 is formed on display dielectric layer 40.First pixel electrode
36 and second pixel electrode 42 can respectively as such as anode and negative electrode, and with display dielectric layer 40 formed display element 44, its
Middle display element 44 is organic electroluminescent element such as organic light-emitting diode element.First pixel electrode 36 and the second pixel
The one of which of electrode 42 is through electrode, and another one can be reflecting electrode or through electrode.For example, if display element 44 is
Upper light emitting-type display element, then the first pixel electrode 36 is reflecting electrode, and the second pixel electrode 42 is through electrode；If showing
Element 44 is bottom light emitting-type display element, then the first pixel electrode 36 is through electrode, and the second pixel electrode 42 is reflection electricity
Pole；If display element 44 is dual-side luminescent type display element, the first pixel electrode 36 can be with the second pixel electrode 42 and wear
Transflective electrode.Additionally, separately can optionally be formed selectively electric hole injection between the first pixel electrode 36 and the second pixel electrode 42
The film layers such as layer, electric hole transport layer, electron injecting layer and electron transfer layer.
The dot structure 50 of the present embodiment is not limited to apply on organic electric-excitation luminescent displaying panel and can be applicable to
On other various emissive types or non-spontaneous light type display floater, for example display panels, electrophoretic display panel, electricity moistening are aobvious
Show on panel or other various suitable display floaters.If dot structure 50 is intended to apply on other types of display floater,
Other corresponding solid-states or liquid film layer such as liquid crystal layer, electrophoresis layer or hydrophilic/hydrophobic mixing liquid may be selected.Wherein, when aobvious
Show dielectric layer 40 for non-luminescent section bar material or during other emissive type materials, the second protective layer 38 and the second pixel electrode 42 its
In at least one, alternative is not provided with.
Dot structure of the present invention and preparation method thereof is not limited with above-described embodiment.Hereafter will sequentially introduce the present invention
The dot structure of other preferred embodiments and preparation method thereof, and the deviation for the ease of relatively more each embodiment and simplifying says
It is bright, in the following embodiments identical element is marked using identical symbol, and mainly for the deviation of each embodiment
Illustrate, and no longer repeating part is repeated.
Refer to Fig. 9 and Figure 10.Fig. 9 and Figure 10 depicts the signal of the making dot structure of the second embodiment of the present invention
Figure.Different from first embodiment, in the present embodiment, the side wall of grid G is recessed in the side wall of gate insulator GI.Please hookup
Fig. 9 is referred to after 2, as shown in figure 9, in the present embodiment, the first patterned conductive layer 22 is formed and is formed patterned insulation layer 24
The step of it is by the use of patterned shielding 20 as etch shield and in addition real using isotropic etch process such as wet etching process
It is existing.Although therefore the pattern of grid G and gate insulator GI both of which are to use patterned shielding 20 as etch shield,
The pattern of grid G can be different with the pattern of gate insulator GI.That is, because grid G is located at gate insulator GI
It is upper, therefore etching period of the etching period of grid G compared with gate insulator GI can be for length, therefore a part of side wall of grid G
The continuation of etching gate insulator GI is etched, and the side wall in the post tensioned unbonded prestressed concrete G of etching can be recessed in gate insulator GI
Side wall.In the same manner, the side wall of storage capacitors Top electrode 22T can also be recessed in the side wall of capacitance dielectric layer CD.Then the 4th is sequentially carried out
Step disclosed in figure to Fig. 8, you can form the dot structure 60 of the present embodiment, as shown in Figure 10.What deserves to be explained is, due to
First connection electrode 281 and the second connection electrode 282 are utilized and lift off technique while removing patterned shielding 20 and positioned at figure
The second conductive layer 26 on case shielding layer 20 is formed, therefore grid G inside contracts side wall and can more effectively guarantee lifting act
Short circuit will not be produced between technique post tensioned unbonded prestressed concrete G and the connection electrode 282 of the first connection electrode 281/ second.
The method of the making dot structure of the present invention has following advantages：
1. source S and drain D are respectively via the first connection electrode 281 and the second connection electrode 282 and patterned oxide
First contact zone 141 of semiconductor layer 14 is contacted with the second contact zone 142, therefore be can select and patterned oxide semiconductor layer
14 materials with preferably contact, to reduce resistance, and then increase the electron mobility of thin-film transistor element TFT.
2. because the first connection electrode 281 and the second connection electrode 282 are formed using lifting act technique, therefore with voluntarily right
Quasi- effect is without producing bit errors, and source S and drain D respectively via the first connection electrode 281 and the second connection electrode
282 contact with the first contact zone 141 of patterned oxide semiconductor layer 14 with the second contact zone 142, even if therefore first connecing
Tactile hole TH1 contacts hole TH2 with second and produces process shifts, also will not be because of source S/drain D and patterned oxide semiconductor
The contact position of the first contact zone 141 and second contact zone 142 of layer 14 asymmetric and impact element characteristic.
3. it is the first connection electrode 281 of exposure and the second connection electrode because the first contact hole TH1 contacts hole TH2 with second
282, rather than exposure pattern oxide semiconductor layer 14, therefore patterned oxide semiconductor layer 14 will not be in etching dielectric
Sustain damage during layer 30, and the material of dielectric layer 30 selects to be not limited by it with patterned oxide semiconductor layer
14 etching selectivity and there is larger elasticity.
4. the preparation method of the present invention uses three pattern layers conductive layers (including the first patterned conductive layer 22, the second figure
The patterned conductive layer 32 of case conductive layer 28 and the 3rd) the practice compared to known preparation method use two-layer patterned conductive layer
The practice there is larger design flexibility.
Refer to Figure 11.Figure 11 depicts the schematic diagram of the dot structure of a comparative examples of the present invention.Such as Figure 11 institutes
Show, in the dot structure 70 of this comparative examples, the first contact hole TH1 contacts hole TH2 and directly exposes patterning with second
Oxide semiconductor layer 14, and source S contacts hole TH1 and the contacts of hole TH2 and first is contacted with second via first respectively with drain D
The directly contact of 141 and second contact zone of area 142.The dot structure 70 of this comparative examples has the disadvantage that：
1. source S/drain D is directly to contact with patterned oxide semiconductor layer 14, therefore source S/drain D and pattern
The contact for changing oxide semiconductor layer 14 is poor.
2. when dielectric layer 30 is etched to form the first contact hole TH1 and contact hole TH2 with second, it is impossible to use dry ecthing,
The damage of patterned oxide semiconductor layer 14 can be otherwise caused, and also to dielectric layer 30 in material in the case of using wet etching
Selection on material causes to limit, for example, cannot use using the material of hydrofluoric acid etch.
3. when the position that the first contact hole TH1 contacts hole TH2 with second has offset because of process deviation, source S/
The corresponding grid G of drain D can form dissymmetrical structure, for the element characteristic of thin-film transistor element affects very.
Refer again to Figure 12 and Figure 13.Figure 12 depicts the thin film transistor (TFT) of the dot structure of the comparative examples of the present invention
The graph of a relation of the grid voltage VG and drain current ID of element, Figure 13 depicts the thin film transistor (TFT) unit of the dot structure of the present invention
The graph of a relation of the grid voltage VG and drain current ID of part.Figure 12 shows that the film of three same sizes of comparative examples is brilliant
The relation of the grid voltage VG and drain current ID of the sample of body tube elements, wherein curve A is sample 1 in drain voltage VD=
The result that 0.1V is measured, the result that curve A ' is measured by sample 1 in drain voltage VD=10V, curve B is sample 2 in leakage
The result that pole tension VD=0.1V is measured, the result that curve B ' is measured by sample 2 in drain voltage VD=10V, curve C is
The result that sample 3 is measured in drain voltage VD=0.1V, the knot that curve C ' is measured by sample 3 in drain voltage VD=10V
Really.As shown in figure 12, can significantly be found out by curve A-C, even if under identical drain voltage VD=0.1V, sample 1-3
The relation of grid voltage VG and drain current ID of thin-film transistor element there is obvious difference.Similarly, by curve A '-
C ' can significantly find out, even if under identical drain voltage VD=10V, the grid of the thin-film transistor element of sample 1-3
The relation of voltage VG and drain current ID also has obvious difference.In addition, the critical electricity of the thin-film transistor element of sample 1-3
Pressure (threshold voltage) also has obvious difference.Therefore, comparative examples can be confirmed by the measurement of Figure 12
Thin-film transistor element under the situation for being not provided with connection electrode, its element uniformity is not good with element characteristic.Figure
The relation of the grid voltage VG and drain current ID of the sample of 13 two thin-film transistor elements for showing the present embodiment, wherein
Sample 4 uses the molybdenum of thickness=50 angstrom (angstrom) as connection electrode, and sample 5 uses the molybdenum conduct of thickness=100 angstrom
Connection electrode, the result that curve D is measured by sample 4 in drain voltage VD=0.1V, curve D ' is sample 4 in drain voltage VD
The result that=5V is measured, the result that curve E is measured by sample 5 in drain voltage VD=0.1V, curve E ' is sample 5 in leakage
The result that pole tension VD=5V is measured.As shown in figure 13, (such as VD=5V or VD=under different drain voltages (VD)
0.1V), the critical voltage (threshold voltage) of the thin-film transistor element of sample 4-5 is almost consistent, it was confirmed that this reality
The thin-film transistor element for applying example has good element uniformity and element characteristic.Further, since the connection electrode of sample 5
Thickness is more than the thickness of the connection electrode of sample 4, therefore the resistance of the connection electrode of sample 5 less than the connection electrode of sample 4
Resistance, and by Figure 13 it is also seen that under identical grid voltage VG and drain voltage VD, sample 5 (curve E or curve E ')
Drain current ID be considerably higher than sample 4 (curve E or curve E ') drain current ID.Confirm the setting of connection electrode
The element characteristic of thin-film transistor element can be changed, and the resistance of connection electrode is less, drain current ID is bigger.It is worth explanation
, when the thickness of connection electrode is selected, in addition to the impact of its drain current ID to thin-film transistor element, Ying Yi
And consider whether the second conductive layer is easily removed in technique is lifted off.
In sum, dot structure of the invention connects source/drain and oxide semiconductor layer using connection electrode, can
To be prevented effectively from the shortcoming that source/drain is directly contacted with oxide semiconductor layer, the unit of thin-film transistor element is effectively lifted
Part characteristic.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent with
Modification, should all belong to the covering scope of the present invention.
Claims (15)
1. a kind of dot structure, including：
One substrate；
One thin-film transistor element, is arranged on the substrate, and the thin-film transistor element includes：
Monoxide semiconductor layer, is arranged on the substrate, and the oxide semiconductor layer has a channel region, and one first connects
Tactile area is with one second contact zone respectively positioned at the two opposite sides of the channel region；
One gate insulator, is arranged on the oxide semiconductor layer, and the gate insulator is arranged at a upper table of the channel region
Face and a upper surface of first contact zone and a upper surface of second contact zone are not covered；
One grid, is arranged on the gate insulator；
One first connection electrode and one second connection electrode, are respectively arranged at the both sides of the gate insulator, the first connection electricity
Pole covers the upper surface of first contact zone and covers with the upper surface of first contact zone, and second connection electrode
Cover second contact zone the upper surface and with the upper surface of second contact zone, wherein first connection electrode with should
Second connection electrode is not Chong Die on a upright projection direction with the gate insulator；
One dielectric layer, is arranged in the grid, first connection electrode and second connection electrode, and wherein the dielectric layer has one
First contact hole does not cover a upper surface of at least part of first connection electrode, and one second contact hole does not cover at least
One upper surface of partial second connection electrode；And
One source electrode and a drain electrode, are arranged on the dielectric layer, and wherein the source electrode first is connected electricity via the first contact hole with this
Pole is electrically connected with, and the drain electrode is electrically connected with via the second contact hole with second connection electrode；
One first protective layer, is arranged on the dielectric layer, and wherein first protective layer has one the 3rd contact hole, does not cover at least
The partial drain electrode；
One first pixel electrode, is arranged on first protective layer, wherein first pixel electrode via the 3rd contact hole with
The drain electrode of the thin-film transistor element is electrically connected with；And
One storage capacitors element is arranged on the substrate, and wherein the storage capacitors element includes：
One storage capacitors bottom electrode, is arranged on the substrate；
One capacitance dielectric layer, is arranged on the storage capacitors bottom electrode and partly covers a upper table of the storage capacitors bottom electrode
Face；
One storage capacitors Top electrode, is arranged on the capacitance dielectric layer；And
One conductive pattern, is arranged at least side of the capacitance dielectric layer and partly covers the upper table of the storage capacitors bottom electrode
Face；
Wherein, the conductive pattern, first connection electrode and second connection electrode are made up of same layer patterned conductive layer
And it is separated from one another in structure, the conductive pattern, first connection electrode and second connection electrode include metal electrode；And should
Storage capacitors bottom electrode with the oxide semiconductor layer is made up of same layer patterned oxide semiconductor layer.
2. dot structure as claimed in claim 1, it is characterised in that first connection electrode and second connection electrode not with
The grid is overlapped on the upright projection direction.
3. dot structure as claimed in claim 1, it is characterised in that the side wall of the grid is recessed in the gate insulator
Side wall.
4. dot structure as claimed in claim 1, further includes：
One display dielectric layer, is arranged on first pixel electrode；And
One second pixel electrode, is arranged on the display dielectric layer.
5. dot structure as claimed in claim 4, it is characterised in that the display dielectric layer is an organic electric-excitation luminescent layer.
6. dot structure as claimed in claim 4, it is characterised in that separately include one second protective layer, is arranged at this and first protects
On sheath, wherein second protective layer does not at least partly cover first pixel electrode, and the display dielectric layer with an opening
It is arranged in the opening of second protective layer.
7. dot structure as claimed in claim 1, it is characterised in that the capacitance dielectric layer is with the gate insulator by same layer
Patterned insulation layer is constituted, and the storage capacitors Top electrode is made up of with the grid same layer patterned conductive layer.
8. a kind of method for making dot structure, it is characterised in that include：
One substrate is provided；
A patterned oxide semiconductor layer is formed on the substrate, wherein the patterned oxide semiconductor layer includes an oxidation
Thing semiconductor layer, and the oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone difference
Positioned at the two opposite sides of the channel region；
An insulating barrier and one first conductive layer are sequentially formed on the substrate and the patterned oxide semiconductor layer；
A patterned shielding is formed on first conductive layer, wherein to cover this first conductive for the patterned shielding part
Layer；
First conductive layer that the patterned shielding exposed is removed to form one first patterned conductive layer, and is removed
To form a patterned insulation layer, wherein the patterned insulation layer includes one to the insulating barrier that the patterned shielding is exposed
Gate insulator, the gate insulator cover a upper surface of the channel region and expose a upper surface of first contact zone with
And a upper surface of second contact zone, and first patterned conductive layer include a grid be located at the gate insulator on；
On the substrate that the patterned shielding is exposed, the upper table of first contact zone of the oxide semiconductor layer
One second conductive layer is formed on face and on the upper surface of second contact zone；
Carry out one and lift off (lift-off) technique, while removing the patterned shielding and in the patterned shielding
To form one second patterned conductive layer, wherein second patterned conductive layer includes one first connection electrode to second conductive layer
With one second connection electrode, it is respectively formed on the upper surface of first contact zone with being voluntarily directed at (self-align) mode
And on the upper surface of second contact zone, and first connection electrode and second connection electrode not with the gate insulator
Overlap on a upright projection direction；
A dielectric layer is formed in the grid, first connection electrode and second connection electrode, wherein the dielectric layer has one
First contact hole at least partly exposes a upper surface of first connection electrode, and one second contact hole at least partly exposes
Go out a upper surface of second connection electrode；And
One the 3rd patterned conductive layer is formed on the dielectric layer, wherein the 3rd patterned conductive layer includes a source electrode and a leakage
Pole, the source electrode is electrically connected with via the first contact hole with first connection electrode, and the drain electrode via the second contact hole with
Second connection electrode is electrically connected with；
One first protective layer is formed on the dielectric layer, wherein first protective layer has one the 3rd contact hole, at least partly sudden and violent
Expose the drain electrode；And
One first pixel electrode is formed on first protective layer.
9. the method for making dot structure as claimed in claim 8, it is characterised in that first connection electrode and second company
Receiving electrode is underlapped on the upright projection direction with the grid.
10. the method for making dot structure as claimed in claim 8, it is characterised in that remove patterned shielding institute sudden and violent
The step of first conductive layer for exposing is to form first patterned conductive layer includes making the grid using an isotropic etching
Side wall be recessed in the side wall of the gate insulator.
The 11. as claimed in claim 8 methods for making dot structures, it is characterised in that first connection electrode with this second
Connection electrode includes metal electrode.
The 12. as claimed in claim 8 methods for making dot structures, it is characterised in that first connection electrode with this second
Connection electrode includes metal conductive oxide electrode.
13. methods for making dot structure as claimed in claim 8, it is characterised in that further include：
One second protective layer is formed on first protective layer, wherein second protective layer is with an opening, at least partly exposure
Go out first pixel electrode；
A display dielectric layer is formed in the opening of second protective layer；And
One second pixel electrode is formed on the display dielectric layer.
14. methods for making dot structure as claimed in claim 13, it is characterised in that the display dielectric layer is an Organic Electricity
Excite photosphere.
15. methods for making dot structure as claimed in claim 8, it is characterised in that the patterned oxide semiconductor layer
Separately include that a storage capacitors bottom electrode, the patterned insulation layer are separately arranged at the storage capacitors bottom electrode including a capacitance dielectric layer
Upper, first patterned conductive layer is separately arranged on the capacitance dielectric layer including a storage capacitors Top electrode, and second pattern
Changing conductive layer separately includes a conductive pattern, is arranged at least side of the capacitance dielectric layer and partly covers electricity under the storage capacitors
Pole.
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| TWI572020B (en) | 2016-01-19 | 2017-02-21 | 友達光電股份有限公司 | Array substrate and manufacturing method thereof |
| TWI629797B (en) | 2017-05-09 | 2018-07-11 | 友達光電股份有限公司 | Thin film transistor and the optoelectronic device |
| TWI688802B (en) * | 2017-11-03 | 2020-03-21 | 曾世憲 | Pixel array and manufacturing method thereof |
| US10930631B2 (en) | 2017-11-03 | 2021-02-23 | Shih-Hsien Tseng | Display apparatus, pixel array and manufacturing method thereof |
| US11362034B2 (en) * | 2018-04-04 | 2022-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a laminate contact plug of specified configuration including a conductive metal oxide layer |
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| CN103296034A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
| CN103346093A (en) * | 2013-06-13 | 2013-10-09 | 北京大学深圳研究生院 | Top grid self-alignment thin-film transistor with source/drain areas raised and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103295909A (en) * | 2012-02-28 | 2013-09-11 | 索尼公司 | Transistor, method of manufacturing the transistor, semiconductor unit, method of manufacturing the semiconductor unit, and display |
| CN103296034A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
| CN103346093A (en) * | 2013-06-13 | 2013-10-09 | 北京大学深圳研究生院 | Top grid self-alignment thin-film transistor with source/drain areas raised and manufacturing method thereof |
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