CN104009043A - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN104009043A CN104009043A CN201410209616.XA CN201410209616A CN104009043A CN 104009043 A CN104009043 A CN 104009043A CN 201410209616 A CN201410209616 A CN 201410209616A CN 104009043 A CN104009043 A CN 104009043A
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- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 239000010409 thin film Substances 0.000 claims abstract description 42
- 239000010410 layer Substances 0.000 claims description 236
- 239000012212 insulator Substances 0.000 claims description 40
- 239000003990 capacitor Substances 0.000 claims description 39
- 238000003860 storage Methods 0.000 claims description 39
- 239000011241 protective layer Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 32
- 238000000059 patterning Methods 0.000 claims description 30
- 238000009413 insulation Methods 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 8
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 description 31
- 239000010408 film Substances 0.000 description 21
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 15
- 229910052750 molybdenum Inorganic materials 0.000 description 15
- 239000011733 molybdenum Substances 0.000 description 15
- 239000004411 aluminium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 238000000576 coating method Methods 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
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- 239000002356 single layer Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
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- 238000003475 lamination Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
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- 229910003437 indium oxide Inorganic materials 0.000 description 5
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 3
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
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Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a pixel structure, which comprises a thin film transistor element. The thin film transistor element comprises an oxide semiconductor layer, a grid insulating layer, a grid, a first connecting electrode, a second connecting electrode, a dielectric layer, a source electrode and a drain electrode. The oxide semiconductor layer is provided with a channel region, and a first contact region and a second contact region are respectively positioned at two opposite sides of the channel region. The first connecting electrode covers the upper surface of the first contact region, and the second connecting electrode covers the upper surface of the second contact region, wherein the first connecting electrode and the second connecting electrode do not overlap with the gate insulating layer in a vertical projection direction. The source electrode is electrically connected with the first contact area of the oxide semiconductor layer through the first connecting electrode, and the drain electrode is electrically connected with the second contact area of the oxide semiconductor layer through the second connecting electrode.
Description
Technical field
The invention relates to a kind of dot structure and preparation method thereof, espespecially a kind of dot structure that utilizes connecting electrode connection source/drain and oxide semiconductor layer and preparation method thereof.
Background technology
Thin-film transistor (thin film transistor, TFT) element is a kind of semiconductor element that is widely used in display floater, for example be applied in display panels (liquid crystal display panel, LCD panel), organic light emitting diode display (organic light emitting diode display panel, OLED display panel) and the display floater such as Electronic Paper (electronic paper, E-paper).The electron mobility (mobility) of thin-film transistor element directly has influence on the switch speed of thin-film transistor element, therefore has a great impact for display frame quality.
The thin-film transistor element of display floater is according to the difference of the semiconductor layer material using at present, mainly can be distinguished into amorphous silicon film transistor (amorphous silicon TFT, a-Si TFT) element, polycrystalline SiTFT (poly silicon TFT) element and oxide semiconductor thin-film transistor (oxide semiconductor TFT) element.Amorphous silicon film transistor element is limited to and uses amorphous silicon semiconductor material, therefore its electron mobility lower (electron mobility of amorphous silicon film transistor element is in 1cm2/Vs at present), therefore cannot meet the more demand of high standard display in current visible future.Polycrystalline SiTFT is indebted to the characteristic of its polycrystalline silicon material, has significantly and improve (the best Yue Keda 100cm2/Vs of electron mobility of polycrystalline SiTFT) in electron mobility.But the complex process of polycrystalline SiTFT element (relatively cost lifting), and in the time that large size panel is applied, have the not good problem of crystallization degree uniformity and exist, therefore current polycrystalline SiTFT element is still taking small size panel application as main.Oxide semiconductor thin-film transistor element is to apply the new oxide semiconductor material emerging in recent years, this type of material is generally amorphous phase (amorphous) lattice structure, be not applied to the not good problem of uniformity on large size panel, and can utilize various ways film forming, the modes such as such as sputter (sputter), spin coating (spin-on) and printing (printing) therefore more have the elasticity of work simplification in technique compared with amorphous silicon film transistor element.The electron mobility of oxide semiconductor thin-film transistor element generally can be compared with high 10 times above (electron mobility of oxide semiconductor thin-film transistor substantially between 10cm2/Vs between 50cm2/Vs) of amorphous silicon film transistor, and this degree can meet the demand of current visible following high standard display floater.
But, in oxide semiconductor thin-film transistor element, if the contact impedance between source/drain and oxide semiconductor layer is excessive, to make the usefulness of thin-film transistor element reduce and cannot effectively bring into play the characteristic of its high electron mobility, therefore be necessary to reduce the contact impedance between oxide semiconductor layer and source electrode/drain electrode, to make oxide semiconductor thin-film transistor element represent the characteristic of high electron mobility.
Summary of the invention
One of object of the present invention is to provide a kind of dot structure and preparation method thereof, to promote the element characteristic of thin-film transistor element of dot structure.
One embodiment of the invention provide a kind of dot structure, comprise a substrate, a thin-film transistor element, one first protective layer and one first pixel electrode.Thin-film transistor element is arranged on substrate, and thin-film transistor element comprises monoxide semiconductor layer, a gate insulator, a grid, one first connecting electrode, one second connecting electrode, a dielectric layer, one source pole and a drain electrode.Oxide semiconductor layer is arranged on substrate, and oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone lay respectively at the two opposite sides of channel region.Gate insulator is arranged on oxide semiconductor layer, and gate insulator covers a upper surface of channel region and exposes a upper surface of the first contact zone and a upper surface of the second contact zone.Grid is arranged on gate insulator.The first connecting electrode and the second connecting electrode are arranged at respectively the both sides of gate insulator, the first connecting electrode covers the upper surface of the first contact zone and contacts with the upper surface of the first contact zone, and the second connecting electrode covers the upper surface of the second contact zone and contacts with the upper surface of the second contact zone, wherein the first connecting electrode and the second connecting electrode are not overlapping in a upright projection direction with gate insulator.Dielectric layer is arranged on grid, the first connecting electrode and the second connecting electrode, its dielectric layer has one first contact hole and exposes at least partly a upper surface of the first connecting electrode, and one second contact hole exposes a upper surface of the second connecting electrode at least partly.Source electrode and drain electrode are arranged on dielectric layer, and wherein source electrode is electrically connected via the first contact hole and the first connecting electrode, and drain electrode is electrically connected via the second contact hole and the second connecting electrode.The first protective layer is arranged on dielectric layer, and wherein the first protective layer has one the 3rd contact hole, exposes at least partly drain electrode.The first pixel electrode is arranged on the first protective layer, and wherein the first pixel electrode is electrically connected via the drain electrode of the 3rd contact hole and thin-film transistor element.
Another embodiment of the present invention provides a kind of method of making dot structure, comprises the following steps.One substrate is provided, and on substrate, form a patterning oxide semiconductor layer, wherein patterning oxide semiconductor layer comprises monoxide semiconductor layer, and oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone lay respectively at the two opposite sides of channel region.On substrate and patterning oxide semiconductor layer, sequentially form an insulating barrier and one first conductive layer.On the first conductive layer, form a patterned shielding, wherein patterned shielding part covers the first conductive layer.The first conductive layer that removal patterned shielding exposes is to form one first patterned conductive layer, and the insulating barrier that removal patterned shielding exposes is to form a patterned insulation layer, wherein patterned insulation layer comprises a gate insulator, gate insulator covers a upper surface of channel region and exposes a upper surface of the first contact zone and a upper surface of the second contact zone, and the first patterned conductive layer comprises that a grid is positioned on gate insulator.On the substrate exposing in patterned shielding, form one second conductive layer on the upper surface of on the upper surface of the first contact zone of oxide semiconductor layer and the second contact zone.Carry out one and lift off technique, remove patterned shielding simultaneously and be positioned at the second conductive layer in patterned shielding to form one second patterned conductive layer, wherein the second patterned conductive layer comprises one first connecting electrode and one second connecting electrode, be formed at respectively with alignment so voluntarily on the upper surface of the first contact zone and on the upper surface of the second contact zone, and the first connecting electrode and the second connecting electrode not overlapping in a upright projection direction with gate insulator.On grid, the first connecting electrode and the second connecting electrode, form a dielectric layer, its dielectric layer has one first contact hole and exposes at least partly a upper surface of the first connecting electrode, and one second contact hole exposes a upper surface of the second connecting electrode at least partly.On dielectric layer, form one the 3rd patterned conductive layer, wherein the 3rd patterned conductive layer comprises one source pole and a drain electrode, and source electrode is electrically connected via the first contact hole and the first connecting electrode, and drain electrode is electrically connected via the second contact hole and the second connecting electrode.On dielectric layer, form one first protective layer, wherein the first protective layer has one the 3rd contact hole, exposes at least partly drain electrode.On the first protective layer, form one first pixel electrode.
Brief description of the drawings
Fig. 1 to Fig. 8 has illustrated the schematic diagram of the method for the making dot structure of the first embodiment of the present invention;
Fig. 9 and Figure 10 have illustrated the schematic diagram of the making dot structure of the second embodiment of the present invention;
Figure 11 has illustrated the schematic diagram of the dot structure of a control Example of the present invention;
Figure 12 has illustrated the grid voltage VG of thin-film transistor element and the graph of a relation of drain current ID of the dot structure of control Example of the present invention;
Figure 13 has illustrated the grid voltage VG of thin-film transistor element and the graph of a relation of drain current ID of dot structure of the present invention;
Accompanying drawing identifier declaration:
10 substrates
10S switch element district
10C storage capacitors district
10P pixel region
12 resilient coatings
14 patterning oxide semiconductor layers
14S oxide semiconductor layer
14C channel region
141 first contact zones
142 second contact zones
14B storage capacitors bottom electrode
16 insulating barriers
161 first insulation films
162 second insulation films
18 first conductive layers
20 patterned shielding
201 first shielding layers
202 second shielding layers
22 first patterned conductive layers
24 patterned insulation layers
GI gate insulator
CD capacitance dielectric layer
14X upper surface
14Y upper surface
14Z upper surface
G grid
22T storage capacitors top electrode
Cst storage capacitors element
26 second conductive layers
28 second patterned conductive layers
281 first connecting electrodes
282 second connecting electrodes
Z upright projection direction
283 conductive patterns
30 dielectric layers
TH1 first contacts hole
TH2 second contacts hole
32 the 3rd patterned conductive layers
S source electrode
D drain electrode
TFT thin-film transistor element
34 first protective layers
TH3 the 3rd contact hole
36 first pixel electrodes
50 dot structures
38 second protective layers
38A opening
40 display dielectric layers
42 second pixel electrodes
44 display elements
60 dot structures
70 dot structures
A curve
A ' curve
B curve
B ' curve
C curve
C ' curve
D curve
D ' curve
E curve
E ' curve
Embodiment
For making the those skilled in the art that are familiar with the technical field of the invention can further understand the present invention, below spy enumerates preferred embodiment of the present invention, and coordinate appended graphic, describe in detail constitution content of the present invention and effect of wanting to reach.
Please refer to Fig. 1 to Fig. 8.Fig. 1 to Fig. 8 has illustrated the schematic diagram of the method for the making dot structure of the first embodiment of the present invention.As shown in Figure 1, first provide a substrate 10.Substrate 10 can be transparency carrier, and it can be hard substrate or bendable substrate for example glass substrate, quartz base plate or plastic base, but not as limit.Substrate 10 can have a switch element district 10S, a storage capacitors district 10C and a pixel region 10P.Then, optionally on substrate 10, form a resilient coating 12.Resilient coating 12 can have insulation characterisitic, and its material can be inorganic insulating material for example silica, silicon nitride or silicon oxynitride, but not as limit, the material of resilient coating 12 also can be organic insulating material.In addition, resilient coating 12 can be single layer structure or lamination layer structure.Subsequently, form a patterning oxide semiconductor layer 14 on substrate 10, if resilient coating 12 exists, patterning oxide semiconductor layer 14 is formed on resilient coating 12.The material of patterning oxide semiconductor layer 14 can comprise for example indium oxide gallium zinc (indium gallium zinc oxide, IGZO), indium oxide gallium (indium gallium oxide, IGO), indium zinc oxide (indium zinc oxide, IZO), tin indium oxide (indium tin oxide, ITO), zinc oxide (zinc oxide, ZnO), indium oxide (indium oxide, InO), (indium tin zinc oxide, ITZO), gallium oxide (gallium oxide, or other suitable oxide semiconductor material GaO).Patterning oxide semiconductor layer 14 can have amorphous phase (amorphous) structure, and it can utilize for example sputter, spin coating, printing or other applicable mode to form.Patterning oxide semiconductor layer 14 comprises monoxide semiconductor layer 14S, be arranged in switch element district 10S, wherein oxide semiconductor layer 14S has a channel region 14C, and one first contact zone 141 and one second contact zone 142 lay respectively at the two opposite sides of channel region 14C.In the present embodiment, channel region 14C, the first contact zone 141 and the second contact zone 142 are in the same plane, and the two ends of channel region 14C are structurally connected with the first contact zone 141 and the second contact zone 142 respectively, that is channel region 14C, the first contact zone 141 and the second contact zone 142 threes are respectively a part of oxide semiconductor layer 14S.In addition, patterning oxide semiconductor layer 14 more can comprise a storage capacitors bottom electrode 14B, is arranged in the storage capacitors district 10C of substrate 10.
As shown in Figure 2, then on substrate 10 and patterning oxide semiconductor layer 14, sequentially form an insulating barrier 16 and one first conductive layer 18.The material of insulating barrier 16 can be inorganic insulating material for example silica, silicon nitride or silicon oxynitride, but not as limit.In the present embodiment, insulating barrier 16 can be a composite bed insulating barrier, it can comprise one first insulation film 161 and one second insulation film 162, and wherein the first insulation film 161 is formed on patterning oxide semiconductor layer 14, and the second insulation film 162 is formed on the first insulation film 161.The first insulation film 161 and the second insulation film 162 can be made up of same material, wherein the first insulation film 161 can utilize low temperature process to form, can avoid by this patterning oxide semiconductor layer 14 to be destroyed by high temperature, and the second insulation film 162 can utilize high-temperature technology to form, can there is by this preferably insulation characterisitic and structural strength.In an alternate embodiment, insulating barrier 16 also can be a monolayer insulating layer.In addition, the material of the first conductive layer 18 can comprise transparent conductive material, for example: metal conductive oxide material (for example tin indium oxide), opaque electric conducting material, for example: metal alloy or other applicable metal or alloy that for example aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, above-mentioned metal form, but not as limit.The first conductive layer 18 can be single layer structure or lamination layer structure.
As shown in 3 figure, then on the first conductive layer 18, form a patterned shielding 20, part covers the first conductive layer 18.Patterned shielding 20 can be a for example photoresist layer, and it can utilize exposure and developing process to be patterned, but not as limit.Patterned shielding 20 can comprise one first shielding layer 201 and one second shielding layer 202, wherein the first shielding layer 201 is positioned at the switch element district 10S of substrate 10 and has covered the first conductive layer 18 corresponding to the channel region 14C top of patterning oxide semiconductor layer 14, and the second shielding layer 202 is positioned at the storage capacitors district 10C of substrate 10 and covered the first conductive layer 18 corresponding to storage capacitors bottom electrode 14B top.In the present embodiment, the size of the first shielding layer 201 equals in fact the size of the channel region 14C of patterning oxide semiconductor layer 14, and the undersized of the second shielding layer 202 is in the size of storage capacitors bottom electrode 14B, but not as limit.For example, in an alternate embodiment, the size of the second shielding layer 202 can equal the size of storage capacitors bottom electrode 14B.Subsequently, the first conductive layer 18 that removal patterned shielding 20 exposes is to form one first patterned conductive layer 22, and the insulating barrier 16 that removal patterned shielding 20 exposes is to form a patterned insulation layer 24.Patterned insulation layer 24 comprises a gate insulator GI and a capacitance dielectric layer CD, wherein gate insulator GI is positioned at switch element district 10S, and covers the upper surface 14X of channel region 14C and expose the upper surface 14Y of the first contact zone 141 and the upper surface 14Z of the second contact zone 142; Capacitance dielectric layer CD is positioned at storage capacitors district 10C and part covers storage capacitors bottom electrode 14B.In the present embodiment, gate insulator GI and capacitance dielectric layer CD are formed by the first insulation film 161 and 162 storehouses of the second insulation film respectively, but not as limit.The first patterned conductive layer 22 comprises a grid G and a storage capacitors top electrode 22T, and wherein grid G is positioned at switch element district 10S and is positioned on gate insulator GI; Storage capacitors top electrode 22T is positioned at storage capacitors district 10C and is positioned on storage capacitors bottom electrode 14B.Storage capacitors bottom electrode 14B, storage capacitors top electrode 22T and be located in storage capacitors bottom electrode 14B and storage capacitors top electrode 22T between capacitance dielectric layer CD form a storage capacitors element Cst.In addition, the first patterned conductive layer 22 more can comprise that a gate line (not shown) and grid G are electrically connected, or for example common line (not shown) of other necessary wire.In the present embodiment, the first conductive layer 18 that removal patterned shielding 20 exposes utilizes patterned shielding 20 as etch shield and utilizes etch process to be realized using the step that forms patterned insulation layer 24 with the insulating barrier 16 that removal patterned shielding 20 is exposed to form the first patterned conductive layer 22.For example, etch process can be selected such as dry etching process of anisotropic etch process, and therefore the pattern of grid G can equate in fact with the pattern of gate insulator GI, that is to say, the sidewall of the sidewall of grid G and gate insulator GI can trim in fact, but not as limit.
As shown in 4 figure, on the substrate 10 exposing in patterned shielding 20 subsequently, upper one second conductive layer 26 that forms of upper surface 14Y upper surface 14Z upper and the second contact zone 142 of the first contact zone 141 of oxide semiconductor layer 14.That is to say, on the upper surface 14Y of the first contact zone 141 of the oxide semiconductor layer 14 that the first shielding layer 201 exposes and on the upper surface of a part of the storage capacitors bottom electrode 14B that the upper surface 14Z of the second contact zone 142 is upper, the second shielding layer 202 exposes, and can form the second conductive layer 26 on substrate 10 (or resilient coating 12).The material of the second conductive layer 26 can comprise transparent conductive material, for example: metal conductive oxide material (for example tin indium oxide), opaque electric conducting material, for example: metal alloy or other applicable metal or alloy that for example aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, above-mentioned metal form, but not as limit.The second conductive layer 26 can be single layer structure or lamination layer structure.The thickness visual material difference of the second conductive layer 26 is adjusted.For example, if the such as molybdenum of material selection metal of the second conductive layer 26, its thickness in fact can be between 50 dusts (angstrom) and 200 dusts, but not as limit; If the material selection transparent conductive material of the second conductive layer 26, for example tin indium oxide, its thickness can be thick compared with metal, for example, be greater than 200 dusts, but not as limit.
As shown in Figure 5, then carry out one and lift off (lift-off) technique, remove patterned shielding 20 simultaneously and be positioned at the second conductive layer 26 in patterned shielding 20 to form one second patterned conductive layer 28.The second patterned conductive layer 28 comprises one first connecting electrode 281 and one second connecting electrode 282, the upper surface 14Y that is formed at respectively the first contact zone 141 in (self-align) mode of aiming at voluntarily upper surface 14Z upper and the second contact zone 142 is upper, and the first connecting electrode 281 and the second connecting electrode 282 not overlapping on upright projection direction Z with gate insulator GI.Speak by the book, the sidewall of the sidewall of the first connecting electrode 281 and the second connecting electrode 282 can trim respectively and cover completely respectively in fact the upper surface 14Z of upper and the second contact zone 142 of the upper surface 14Y of the first contact zone 141 with the sidewall of gate insulator GI.In addition, the second patterned conductive layer 28 separately comprises a conductive pattern 283, and at least one side (for example both sides also) the part that are arranged at capacitance dielectric layer CD cover storage capacitors bottom electrode 14B, can reduce by this resistance of storage capacitors bottom electrode 14B.When the material selection metal oxide of the second conductive layer 26 is for example when tin indium oxide, the first connecting electrode 281 and the second connecting electrode 282 are for example indium oxide thing electrode of metal conductive oxide electrode; In the time of the material selection metal or alloy of the second conductive layer 26, the first connecting electrode 281 and the second connecting electrode 282 are for example aluminium electrode, titanium/aluminium/titanium electrode, molybdenum electrode or molybdenum/aluminium/molybdenum electrode of metal electrode.From the above, because the first connecting electrode 281 and the utilization of the second connecting electrode 282 lift off, (lift-off) technique removes patterned shielding 20 simultaneously and the second conductive layer 26 of being positioned in patterned shielding 20 forms, and patterned shielding 20 itself also has definition grid G and the pattern of gate insulator GI and the effect of position, therefore, the practice of the present embodiment has the effect of aiming at voluntarily, that is the relative position of grid G and gate insulator GI and the first connecting electrode 281 and the second connecting electrode 282 is fixed, and can guarantee that the first connecting electrode 281 can cover the upper surface 14Y of the first contact zone 141 completely, the second connecting electrode 282 can cover the upper surface 14Z of the second contact zone 142 completely, and the first connecting electrode 281 and the second connecting electrode 282 can be not overlapping on upright projection direction Z with gate insulator GI or gate pole G.
As shown in Figure 6, retain after the first connecting electrode 281, the second connecting electrode 282 and conductive pattern 283, and remove the second patterned conductive layer 28 other do not need part, be for example positioned at the second patterned conductive layer 28 on substrate 10 or resilient coating 12.Subsequently, on grid G, the first connecting electrode 281 and the second connecting electrode 282, form a dielectric layer 30, and in dielectric layer 30, form one first contact hole TH1 and expose at least partly the upper surface 281S of the first connecting electrode 281, and one second contact hole TH2 exposes the upper surface 282S of the second connecting electrode 282 at least partly.Dielectric layer 30 can have a planarized surface, in order to the formation of subsequent film.The material of dielectric layer 30 can be organic dielectric materials or Inorganic Dielectric Material, and dielectric layer 30 can be single layer structure or lamination layer structure.
As shown in Figure 7, on dielectric layer 30, form subsequently one the 3rd patterned conductive layer 32.The 3rd patterned conductive layer 30 comprises one source pole S and a drain D, wherein source S contacts and is electrically connected with the first connecting electrode 281 via the first contact hole TH1, and drain D contacts and is electrically connected with the second connecting electrode 282 via the second contact hole TH2, to produce the thin-film transistor element TFT of the present embodiment.The material of the 3rd patterned conductive layer 32 can comprise transparent conductive material, for example: metal conductive oxide material (for example tin indium oxide), opaque electric conducting material, for example: metal alloy or other applicable metal or alloy that for example aluminium, titanium/aluminium/titanium, molybdenum, molybdenum/aluminium/molybdenum, above-mentioned metal form, but not as limit.In addition, the 3rd patterned conductive layer 32 can be single layer structure or lamination layer structure.In addition, the 3rd patterned conductive layer 32 more can comprise that data wire (not shown) and source S are electrically connected, or other necessary wire.On dielectric layer 30, form subsequently one first protective layer 34, wherein the first protective layer 34 has one the 3rd contact hole TH3, exposes at least partly drain D.The first protective layer 34 can have a planarized surface, in order to the formation of subsequent film.The material of the first protective layer 34 can be organic insulating material or inorganic insulating material, and the first protective layer 34 can be single layer structure or lamination layer structure.
As shown in Figure 8; on the first protective layer 34, form one first pixel electrode 36 to form the dot structure 50 of the present embodiment, wherein the first pixel electrode 36 is positioned at pixel region 10P and extends to switch element district 10S and contact hole TH3 via the 3rd and contact and be electrically connected with the drain D of thin-film transistor element TFT.In the present embodiment, dot structure 50 is applied to organic electric-excitation luminescent displaying panel, therefore more can further comprise the following steps.On the first protective layer 34, form one second protective layer 38, wherein the second protective layer 38 has an opening 38A, is positioned at pixel region 10P and exposes at least partly the first pixel electrode 36.The material of the second protective layer 38 can be organic insulating material or inorganic insulating material, and the second protective layer 38 can be single layer structure or lamination layer structure.After, in the opening 38A of the second protective layer 38, form a display dielectric layer 40, wherein display dielectric layer 40 is an organic electric-excitation luminescent layer.Finally, on display dielectric layer 40, form one second pixel electrode 42.The first pixel electrode 36 and the second pixel electrode 42 be for example anode of conduct and negative electrode respectively, and forms display element 44 with display dielectric layer 40, and wherein display element 44 is such as organic light-emitting diode element of organic electroluminescent element.The wherein one of the first pixel electrode 36 and the second pixel electrode 42 is through electrode, and another one can be reflecting electrode or through electrode.For example, if display element 44 is upper light emitting-type display elements, the first pixel electrode 36 is reflecting electrode, and the second pixel electrode 42 is through electrode; If display element 44 is end light emitting-type display elements, the first pixel electrode 36 is through electrode, and the second pixel electrode 42 is reflecting electrode; If display element 44 is dual-side luminescent type display elements, the first pixel electrode 36 and the second pixel electrode 42 can be through electrode.In addition, between the first pixel electrode 36 and the second pixel electrode 42, separately can optionally optionally form the retes such as electric hole implanted layer, electric hole transport layer, electron injecting layer and electron transfer layer.
The dot structure 50 of the present embodiment is not limited to be applied on organic electric-excitation luminescent displaying panel and can be applicable on other various emissive type or non-emissive type display floater, for example, on display panels, electrophoretic display panel, Electrowetting display panel or other various applicable display floater.If dot structure 50 is wanted to be applied on the display floater of other type, can select solid-state or liquid rete for example liquid crystal layer, electrophoretic layer or the hydrophilic/hydrophobic mixing material of other correspondence.Wherein, in the time that display dielectric layer 40 is non-light emitting-type material or other emissive type material, the second protective layer 38 and the second pixel electrode 42 wherein at least one, alternative does not arrange.
Dot structure of the present invention and preparation method thereof is not limited with above-described embodiment.Below dot structure of other preferred embodiment of the present invention and preparation method thereof will sequentially be introduced, and for the ease of deviation the simplified illustration of more each embodiment, use in the following embodiments identical symbol to mark identical element, and the deviation mainly for each embodiment describes, and no longer repeating part is repeated.
Please refer to Fig. 9 and Figure 10.Fig. 9 and Figure 10 have illustrated the schematic diagram of the making dot structure of the second embodiment of the present invention.Be different from the first embodiment, in the present embodiment, the sidewall of grid G is recessed in the sidewall of gate insulator GI.Please hookup 2 rear with reference to figure 9, as shown in Figure 9, in the present embodiment, forming the first patterned conductive layer 22 utilizes patterned shielding 20 as etch shield and utilizes for example wet etching process of isotropic etching technique to be realized with the step that forms patterned insulation layer 24.Although therefore the pattern of grid G and gate insulator GI use patterned shielding 20 as etch shield, the pattern of the pattern of grid G and gate insulator GI can be different.That is to say, because grid G is positioned at the upper of gate insulator GI, therefore the etching period of grid G is length compared with the etching period of gate insulator GI, therefore a part of sidewall of grid G can be etched in the continuation of etching grid insulating barrier GI, and can be recessed in the sidewall of gate insulator GI at the sidewall of etched rear grid G.In like manner, the sidewall of storage capacitors top electrode 22T also can be recessed in the sidewall of capacitance dielectric layer CD.Then sequentially carry out the step that the 4th figure to Fig. 8 discloses, can form the dot structure 60 of the present embodiment, as shown in figure 10.What deserves to be explained is, because the first connecting electrode 281 and the utilization of the second connecting electrode 282 lift off, technique removes patterned shielding 20 simultaneously and the second conductive layer 26 of being positioned in patterned shielding 20 forms, therefore the inside contracting sidewall and can more effectively guarantee can not produce short circuit between grid G and the first connecting electrode 281/ second connecting electrode 282 lifting after lifting technique of grid G.
The method of making dot structure of the present invention has following advantages:
1. source S contacts with the second contact zone 142 with the first contact zone 141 of patterning oxide semiconductor layer 14 with the second connecting electrode 282 via the first connecting electrode 281 respectively with drain D, therefore can select with patterning oxide semiconductor layer 14 and there is the better material contacting, to reduce resistance, and then increase the electron mobility of thin-film transistor element TFT.
2. because the first connecting electrode 281 and the second connecting electrode 282 are to utilize to lift to lift technique and form, therefore there is voluntarily alignment result and can not produce bit errors, and source S contacts with the second contact zone 142 with the first contact zone 141 of patterning oxide semiconductor layer 14 with the second connecting electrode 282 via the first connecting electrode 281 respectively with drain D, even if therefore the first contact hole TH1 contacts hole TH2 and produces process shifts with second, also can not affect because of the asymmetric of the contact position of the first contact zone 141 of source S/drain D and patterning oxide semiconductor layer 14 and the second contact zone 142 element characteristic.
3. because contacting hole TH2 with second, the first contact hole TH1 exposes the first connecting electrode 281 and the second connecting electrode 282, instead of exposure pattern oxide semiconductor layer 14, therefore patterning oxide semiconductor layer 14 can not sustain damage in the process of etching dielectric layer 30, and the material of dielectric layer 30 is selected not to be limited to the etching selectivity of itself and patterning oxide semiconductor layer 14 and has larger elasticity.
4. manufacture method of the present invention is used the practice of three layer pattern conductive layers (comprising the first patterned conductive layer 22, the second patterned conductive layer 28 and the 3rd patterned conductive layer 32) to use the practice of two-layer patterned conductive layer to have larger design flexibility compared to known manufacture method.
Please refer to Figure 11.Figure 11 has illustrated the schematic diagram of the dot structure of a control Example of the present invention.As shown in figure 11, in the dot structure 70 of this control Example, the first contact hole TH1 contacts hole TH2 with second and directly exposes patterning oxide semiconductor layer 14, and source S and drain D contact hole TH1 via first respectively and contact hole TH2 with second and directly contact with the second contact zone 142 with the first contact zone 141.The dot structure 70 of this control Example has following shortcoming:
1. source S/drain D is directly to contact with patterning oxide semiconductor layer 14, and therefore source S/drain D is poor with contacting of patterning oxide semiconductor layer 14.
At etching dielectric layer 30 when forming the first contact hole TH1 and second contact hole TH2, cannot use dry ecthing, otherwise can cause the damage of patterning oxide semiconductor layer 14, and in the situation that using wet etching, also to dielectric layer 30, the selection on material causes restriction, for example, cannot use the material that utilizes hydrofluoric acid etch.
3. in the time that the first contact hole TH1 contacts hole TH2 position with second is offset to some extent because of process deviation, the corresponding grid G of source S/drain D can form dissymmetrical structure, affects very for the element characteristic of thin-film transistor element.
Refer again to Figure 12 and Figure 13.Figure 12 has illustrated the grid voltage VG of thin-film transistor element and the graph of a relation of drain current ID of the dot structure of control Example of the present invention, and Figure 13 has illustrated the grid voltage VG of thin-film transistor element and the graph of a relation of drain current ID of dot structure of the present invention.Figure 12 has shown the grid voltage VG of sample and the relation of drain current ID of the thin-film transistor element of three same sizes of control Example, the result that wherein curve A measures at drain voltage VD=0.1V for sample 1, curve A ' result that measures at drain voltage VD=10V for sample 1, the result that curve B measures at drain voltage VD=0.1V for sample 2, curve B ' result that measures at drain voltage VD=10V for sample 2, the result that curve C measures at drain voltage VD=0.1V for sample 3, curve C ' result that measures at drain voltage VD=10V for sample 3.As shown in figure 12, can significantly be found out by curve A-C, even under identical drain voltage VD=0.1V, the grid voltage VG of the thin-film transistor element of sample 1-3 and the relation of drain current ID have obvious difference.Similarly, by curve A '-C ' can significantly find out, even under identical drain voltage VD=10V, the grid voltage VG of the thin-film transistor element of sample 1-3 and the relation of drain current ID also have obvious difference.In addition, the critical voltage of the thin-film transistor element of sample 1-3 (threshold voltage) also has obvious difference.Therefore, by the measurement of Figure 12 can confirm control Example thin-film transistor element do not arranging under the situation of connecting electrode, its element uniformity and element characteristic are all not good.Figure 13 has shown the grid voltage VG of sample and the relation of drain current ID of two thin-film transistor elements of the present embodiment, wherein sample 4 uses the molybdenum of thickness=50 dust (angstrom) as connecting electrode, and sample 5 uses the molybdenum of thickness=100 dust as connecting electrode, the result that curve D measures at drain voltage VD=0.1V for sample 4, curve D ' result that measures at drain voltage VD=5V for sample 4, the result that curve E measures at drain voltage VD=0.1V for sample 5, the result that curve E ' measures at drain voltage VD=5V for sample 5.As shown in figure 13, for example, under different drain voltage (VD) (VD=5V or VD=0.1V), the critical voltage (threshold voltage) of the thin-film transistor element of sample 4-5 is almost consistent, has confirmed that the thin-film transistor element of the present embodiment has good element uniformity and element characteristic.In addition, because the thickness of the connecting electrode of sample 5 is greater than the thickness of the connecting electrode of sample 4, therefore the resistance of the connecting electrode of sample 5 is lower than the resistance of the connecting electrode of sample 4, and also can be found out under identical grid voltage VG and drain voltage VD by Figure 13, the drain current ID of sample 5 (curve E or curve E ') significantly higher than the drain current ID of sample 4 (curve E or curve E ').Confirmed the element characteristic that can change thin-film transistor element that arranges of connecting electrode, and the resistance of connecting electrode is less, drain current ID is larger.What deserves to be explained is, in the time selecting the thickness of connecting electrode, except the impact of its drain current ID on thin-film transistor element, should consider in the lump whether the second conductive layer is easily removed lifting off in technique.
In sum, dot structure of the present invention utilizes connecting electrode to connect source/drain and oxide semiconductor layer, can effectively avoid the direct shortcoming contacting with oxide semiconductor layer of source/drain, effectively promotes the element characteristic of thin-film transistor element.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. a dot structure, comprising:
One substrate;
One thin-film transistor element, is arranged on this substrate, and this thin-film transistor element comprises:
Monoxide semiconductor layer, is arranged on this substrate, and this oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone lay respectively at the two opposite sides of this channel region;
One gate insulator, is arranged on this oxide semiconductor layer, and this gate insulator covers a upper surface of this channel region and exposes a upper surface of this first contact zone and this second contact zone
One upper surface;
One grid, is arranged on this gate insulator;
One first connecting electrode and one second connecting electrode, be arranged at respectively the both sides of this gate insulator, this first connecting electrode covers this upper surface of this first contact zone and contacts with this upper surface of this first contact zone, and this second connecting electrode covers this upper surface of this second contact zone and contacts with this upper surface of this second contact zone, and wherein this first connecting electrode and this second connecting electrode are not overlapping in a upright projection direction with this gate insulator;
One dielectric layer, be arranged on this grid, this first connecting electrode and this second connecting electrode, wherein this dielectric layer has one first contact hole and exposes at least partly a upper surface of this first connecting electrode, and one second contact hole exposes a upper surface of this second connecting electrode at least partly; And
One source pole and a drain electrode, be arranged on this dielectric layer, and wherein this source electrode is electrically connected via this first contact hole and this first connecting electrode, and this drain electrode is electrically connected via this second contact hole and this second connecting electrode;
One first protective layer, is arranged on this dielectric layer, and wherein this first protective layer has one the 3rd contact hole, exposes at least partly this drain electrode; And
One first pixel electrode, is arranged on this first protective layer, and wherein this first pixel electrode is electrically connected via this drain electrode of the 3rd contact hole and this thin-film transistor element.
2. dot structure as claimed in claim 1, is characterized in that, this first connecting electrode and this second connecting electrode are not overlapping in this upright projection direction with this grid.
3. dot structure as claimed in claim 1, is characterized in that, a sidewall of this grid is recessed in a sidewall of this gate insulator.
4. dot structure as claimed in claim 1, is characterized in that, this first connecting electrode and this second connecting electrode comprise metal electrode.
5. dot structure as claimed in claim 1, is characterized in that, this first connecting electrode and this second connecting electrode comprise metal conductive oxide electrode.
6. dot structure as claimed in claim 1, more comprises:
One display dielectric layer, is arranged on this first pixel electrode; And
One second pixel electrode, is arranged on this display dielectric layer.
7. dot structure as claimed in claim 6, is characterized in that, this display dielectric layer is an organic electric-excitation luminescent layer.
8. dot structure as claimed in claim 6, is characterized in that, separately comprises one second protective layer; be arranged on this first protective layer; wherein this second protective layer has an opening, exposes at least partly this first pixel electrode, and this display dielectric layer is arranged in this opening of this second protective layer.
9. dot structure as claimed in claim 1, is characterized in that, separately comprises that a storage capacitors element is arranged on this substrate, and wherein this storage capacitors element comprises:
One storage capacitors bottom electrode, is arranged on this substrate;
One capacitance dielectric layer, is arranged at a upper surface that also partly covers this storage capacitors bottom electrode on this storage capacitors bottom electrode;
One storage capacitors top electrode, is arranged on this capacitance dielectric layer; And
One conductive pattern, at least one side that is arranged at this capacitance dielectric layer also partly covers this upper surface of this storage capacitors bottom electrode.
10. dot structure as claimed in claim 9, it is characterized in that, this storage capacitors bottom electrode and this oxide semiconductor layer are made up of same layer patterning oxide semiconductor layer, this capacitance dielectric layer and this gate insulator are made up of same layer patterned insulation layer, this storage capacitors top electrode and this grid are made up of same layer patterned conductive layer, and this conductive pattern, this first connecting electrode and this second connecting electrode are made up of same layer patterned conductive layer.
Make the method for dot structure for 11. 1 kinds, it is characterized in that, comprising:
One substrate is provided;
On this substrate, form a patterning oxide semiconductor layer, wherein this patterning oxide semiconductor layer comprises monoxide semiconductor layer, and this oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone lay respectively at the two opposite sides of this channel region;
On this substrate and this patterning oxide semiconductor layer, sequentially form an insulating barrier and one first conductive layer;
On this first conductive layer, form a patterned shielding, wherein this patterned shielding part covers this first conductive layer;
Remove this first conductive layer that this patterned shielding exposes to form one first patterned conductive layer, and remove this insulating barrier that this patterned shielding exposes to form a patterned insulation layer, wherein this patterned insulation layer comprises a gate insulator, this gate insulator covers a upper surface of this channel region and exposes a upper surface of this first contact zone and a upper surface of this second contact zone, and this first patterned conductive layer comprises that a grid is positioned on this gate insulator;
On this substrate exposing in this patterned shielding, form one second conductive layer on this upper surface of on this upper surface of this first contact zone of this oxide semiconductor layer and this second contact zone;
Carry out one and lift off (lift-off) technique, remove this patterned shielding simultaneously and be positioned at this second conductive layer in this patterned shielding to form one second patterned conductive layer, wherein this second patterned conductive layer comprises one first connecting electrode and one second connecting electrode, be formed at respectively to aim at voluntarily (self-align) mode on this upper surface of this first contact zone and on this upper surface of this second contact zone, and this first connecting electrode and this second connecting electrode not overlapping in a upright projection direction with this gate insulator;
On this grid, this first connecting electrode and this second connecting electrode, form a dielectric layer, wherein this dielectric layer has one first contact hole and exposes at least partly a upper surface of this first connecting electrode, and one second contact hole exposes a upper surface of this second connecting electrode at least partly; And
On this dielectric layer, form one the 3rd patterned conductive layer, wherein the 3rd patterned conductive layer comprises one source pole and a drain electrode, this source electrode is electrically connected via this first contact hole and this first connecting electrode, and this drain electrode is electrically connected via this second contact hole and this second connecting electrode;
On this dielectric layer, form one first protective layer, wherein this first protective layer has one the 3rd contact hole, exposes at least partly this drain electrode; And
On this first protective layer, form one first pixel electrode.
The method of 12. making dot structures as claimed in claim 11, is characterized in that, this first connecting electrode and this second connecting electrode and this grid are underlapped in this upright projection direction.
The method of 13. making dot structures as claimed in claim 11, it is characterized in that, remove this first conductive layer that this patterned shielding exposes and comprise that to form the step of this first patterned conductive layer a sidewall that utilizes an isotropic etching to make this grid is recessed in a sidewall of this gate insulator.
The method of 14. making dot structures as claimed in claim 11, is characterized in that, this first connecting electrode and this second connecting electrode comprise metal electrode.
The method of 15. making dot structures as claimed in claim 11, is characterized in that, this first connecting electrode and this second connecting electrode comprise metal conductive oxide electrode.
The method of 16. making dot structures as claimed in claim 11, is characterized in that, more comprises:
On this first protective layer, form one second protective layer, wherein this second protective layer has an opening, exposes at least partly this first pixel electrode;
In this opening of this second protective layer, form a display dielectric layer; And
On this display dielectric layer, form one second pixel electrode.
The method of 17. making dot structures as claimed in claim 16, is characterized in that, this display dielectric layer is an organic electric-excitation luminescent layer.
The method of 18. making dot structures as claimed in claim 11, it is characterized in that, this patterning oxide semiconductor layer separately comprises that a storage capacitors bottom electrode, this patterned insulation layer separately comprise that a capacitance dielectric layer is arranged on this storage capacitors bottom electrode, this first patterned conductive layer separately comprises that a storage capacitors top electrode is arranged on this capacitance dielectric layer, and this second patterned conductive layer separately comprises a conductive pattern, at least one side the part that are arranged at this capacitance dielectric layer cover this storage capacitors bottom electrode.
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| CN105789217A (en) * | 2016-01-19 | 2016-07-20 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| CN107369717A (en) * | 2017-05-09 | 2017-11-21 | 友达光电股份有限公司 | Thin film transistor and photoelectric device thereof |
| WO2021120974A1 (en) * | 2019-12-17 | 2021-06-24 | Tseng Shih Hsien | Display apparatus, pixel array and manufacturing method thereof |
| TWI740806B (en) * | 2014-10-16 | 2021-10-01 | 南韓商三星顯示器有限公司 | Thin film transistor array substrate, method of manufacturing the same, and organic light-emitting display apparatus including the same |
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| TWI688802B (en) | 2017-11-03 | 2020-03-21 | 曾世憲 | Pixel array and manufacturing method thereof |
| US10930631B2 (en) | 2017-11-03 | 2021-02-23 | Shih-Hsien Tseng | Display apparatus, pixel array and manufacturing method thereof |
| WO2019193463A1 (en) * | 2018-04-04 | 2019-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor device, and semiconductor device manufacturing method |
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| TWI483344B (en) * | 2011-11-28 | 2015-05-01 | Au Optronics Corp | Array substrate and manufacturing method thereof |
| TW201338173A (en) * | 2012-02-28 | 2013-09-16 | Sony Corp | Transistor, method of manufacturing the transistor, display, and electronic apparatus |
| CN103296034A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
| CN103346093B (en) * | 2013-06-13 | 2015-12-23 | 北京大学深圳研究生院 | Top grid self-aligned thin film transistor that source/drain region is raised and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI740806B (en) * | 2014-10-16 | 2021-10-01 | 南韓商三星顯示器有限公司 | Thin film transistor array substrate, method of manufacturing the same, and organic light-emitting display apparatus including the same |
| CN105789217A (en) * | 2016-01-19 | 2016-07-20 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| CN105789217B (en) * | 2016-01-19 | 2019-04-19 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| US10615188B2 (en) | 2016-01-19 | 2020-04-07 | Au Optronics Corporation | Array substrate and manufacturing method thereof |
| CN107369717A (en) * | 2017-05-09 | 2017-11-21 | 友达光电股份有限公司 | Thin film transistor and photoelectric device thereof |
| US10475826B2 (en) | 2017-05-09 | 2019-11-12 | Au Optronics Corporation | Thin film transistor and photoelectric device thereof |
| CN107369717B (en) * | 2017-05-09 | 2020-05-19 | 友达光电股份有限公司 | Thin film transistor and photoelectric device thereof |
| WO2021120974A1 (en) * | 2019-12-17 | 2021-06-24 | Tseng Shih Hsien | Display apparatus, pixel array and manufacturing method thereof |
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| TW201537730A (en) | 2015-10-01 |
| CN104009043B (en) | 2017-05-10 |
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