CN103296034A - Array substrate, production method thereof and display device - Google Patents
Array substrate, production method thereof and display device Download PDFInfo
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- CN103296034A CN103296034A CN2013102039124A CN201310203912A CN103296034A CN 103296034 A CN103296034 A CN 103296034A CN 2013102039124 A CN2013102039124 A CN 2013102039124A CN 201310203912 A CN201310203912 A CN 201310203912A CN 103296034 A CN103296034 A CN 103296034A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention belongs to the technical field of display and relates to an array substrate, a production method thereof and a display device. The array substrate comprises a substrate body, a thin film transistor and a storage capacitor. The thin film transistor and the storage capacitor are formed on the substrate body. The thin film transistor comprises a grid electrode, a source electrode, a drain electrode and a grid insulating layer which is arranged among the source electrode, the drain electrode and the grid electrode. The storage capacitor comprises a first electrode plate, a second electrode plate and a dielectric layer arranged between the first electrode plate and the second electrode plate. The dielectric constant of a portion, closely adjacent to the source electrode and the drain electrode, of the grid insulating layer, is smaller than that of the dielectric layer. The array substrate has the advantages that although the thickness of the dielectric layer of the storage capacitor in the array substrate is small, the capacity of the storage capacitor is high, the size of the storage capacitor is greatly reduced and the size of a pixel structure of the storage capacitor is reduced, so that a guarantee is provided for manufacturing of high-resolution display panels.
Description
Technical field
The invention belongs to the Display Technique field, relate to a kind of array base palte, preparation method and display unit.
Background technology
Along with the development of Display Technique, people are growing to the demand that shows image quality, and the demand of high image quality, high-resolution panel display apparatus is more and more general, also more and more obtains the attention of display floater producer.
Thin-film transistor (Thin Film Transistor is called for short TFT) is the main driving element of present panel display board, is directly connected to the developing direction of high-performance panel display apparatus.Thin-film transistor has multiple structure, the material of the thin-film transistor of preparation corresponding construction also has multiple, wherein, low temperature polycrystalline silicon is because its mobility can reach tens even hundred times of amorphous silicon, therefore, adopt the low temperature polycrystalline silicon material to form the less thin-film transistor of size, can obtain to adopt relatively the bigger driving force of thin-film transistor of amorphous silicon material formation, therefore low-temperature polysilicon film transistor has also obtained the concern of research institution and display floater producer.Can provide high image quality, high-resolution low-temperature polysilicon film transistor to begin to occur in market gradually not broken hair exhibition, be liquid crystal indicator (Liquid Crystal Display: be called for short LCD) or organic electroluminescence display device and method of manufacturing same (Organic Light-Emitting Diode: abbreviation OLED) provide better demonstration image quality.
Though low-temperature polysilicon film transistor has above-mentioned advantage, but, driving force in order to realize continuing in the low-temperature polysilicon film transistor array base palte, also need to arrange simultaneously storage capacitance (Storing Capacity: be called for short Cs), especially in the high-resolution display panel, usually need be equipped with the storage capacitance of larger capacity for low-temperature polysilicon film transistor, could satisfy driving needs.The process of the normal preparation storage capacitance that adopts is at present, in the preparation thin-film transistor, directly adopt the conductive metallic material that forms grid and source/drain to form two pole plates of storage capacitance respectively, directly adopt one deck interlayer insulating film or one deck gate insulation layer as the dielectric layer of storage capacitance then, thereby form storage capacitance.Yet, consider the electrology characteristic of thin-film transistor, be that interlayer insulating film or gate insulation layer all can't be done thinly as far as possible; Simultaneously, interlayer insulating film will play passivation, protective effect, and gate insulation layer is in order to form the excellent contact interface with polysilicon layer, and therefore, interlayer insulating film or gate insulation layer all can adopt the less silica material of dielectric constant to form usually.
The capacity of storage capacitance is calculated by following formula (1):
Cs=εS/4πkd………………（1）
In formula (1), ε is dielectric constant, S be capacitor plate over against area, k is the electrostatic force constant, d is the distance (or thickness) between capacitor plate.
As seen, the thickness that above-mentioned interlayer insulating film or gate insulation layer are bigger and less dielectric constant have all limited the capacity of storage capacitance, and the capacity of storage capacitance is directly restricting the performance of high resolution ratio array substrate, and then has limited further developing of high-definition display device.
Therefore, how to improve the capacity of storage capacitance in the array base palte, the thin-film transistor that acquisition simultaneously has stable driving force, the size that reduces the size of storage capacitance and comprise the dot structure of storage capacitance, the display quality that improves panel display apparatus is present problem demanding prompt solution.
Summary of the invention
Technical problem to be solved by this invention is at above shortcomings in the prior art, a kind of array base palte, preparation method and display unit are provided, though the dielectric layer thickness of the storage capacitance in this array base palte is less, but the capacity of storage capacitance is higher, has significantly reduced the storage capacitance size.
The technical scheme that solution the technology of the present invention problem adopts is this a kind of array base palte, comprise substrate and be formed on thin-film transistor and storage capacitance on the described substrate, described thin-film transistor comprises grid, source electrode, drain electrode and be arranged at described source electrode, gate insulation layer between described drain electrode and the described grid, described storage capacitance comprises first pole plate, dielectric layer between second pole plate and described first pole plate and described second pole plate, wherein said gate insulation layer is close to described source electrode, the dielectric constant of the gate insulation layer of described drain electrode part is smaller or equal to the dielectric constant of described dielectric layer.
Preferably, described gate insulation layer comprises first grid insulating barrier and second gate insulation layer, the dielectric constant of described first grid insulating barrier is less than the dielectric constant of described second gate insulation layer, described first grid insulating barrier is close to described source electrode, described drain electrode, described first pole plate and the described second pole plate branch are located at the both sides up and down of described second gate insulation layer, and described dielectric layer is the part that the described second gate insulation layer correspondence described first pole plate and described second pole plate.
A kind of preferred version is, described source electrode, described drain electrode and described first pole plate arrange with layer, and described first grid insulating barrier covers described source electrode and described drain electrode fully and do not cover described first pole plate; Described second gate insulation layer covers described first grid insulating barrier and described first pole plate fully; Described grid is arranged at the described second gate insulation layer correspondence and the top in the zone between described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate is arranged at above described second gate insulation layer and is at least part of overlapping on the orthographic projection direction with described first pole plate;
Perhaps, described source electrode, described drain electrode and described first pole plate arrange with layer, and described first grid insulating barrier covers described source electrode and described drain electrode fully and do not cover described first pole plate; Described second gate insulation layer cover described first pole plate fully and do not cover described source electrode corresponding with described drain electrode the zone; Described grid is arranged at described first grid insulating barrier correspondence and the top in the zone between described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate is arranged at above described second gate insulation layer and is at least part of overlapping on the orthographic projection direction with described first pole plate.
A kind of preferred version is, described grid and described second pole plate arrange with layer, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate; Described second gate insulation layer covers described first grid insulating barrier and described second pole plate fully; Described source electrode and described drain electrode be arranged at described second gate insulation layer corresponding the top at two ends of described grid and overlapping on orthographic projection direction top with described grid respectively, described first pole plate is arranged at the top that the described second gate insulation layer correspondence described second pole plate;
Perhaps, described grid and described second pole plate arrange with layer, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate; Described second gate insulation layer covers described second pole plate fully and does not cover the zone that described grid correspondence; Described source electrode and described drain electrode be arranged at described first grid insulating barrier corresponding the top at two ends of described grid and overlapping on orthographic projection direction top with described grid respectively, described first pole plate is arranged at the top that the described second gate insulation layer correspondence described second pole plate.
Preferably, described first grid insulating barrier adopts silica material to form, and described first grid insulating barrier is single layer structure; Described second gate insulation layer adopts at least a formation in silica material, the silicon nitride material, and described second gate insulation layer is the laminated construction of single layer structure or a plurality of sublayers.
Preferably, the thickness range of described first grid insulating barrier is
The thickness range of described second gate insulation layer is
Preferably, described source electrode, described drain electrode and described first pole plate adopt the low temperature polycrystalline silicon material to form, and the thickness range of described source electrode, described drain electrode and described first pole plate is
Described grid and described second pole plate adopt at least a material in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium and the copper to form, and the thickness range of described grid and described second pole plate is
Preferably, also comprise resilient coating, described resilient coating is the laminated construction of single layer structure or a plurality of sublayers, described resilient coating adopts at least a formation in silica material, the silicon nitride material, and described resilient coating is arranged between described substrate and described source electrode, described drain electrode, described first pole plate; Perhaps, described resilient coating is arranged between described substrate and described grid, described second pole plate.
Preferably, also comprise interlayer insulating film and extraction electrode in the described array base palte, described extraction electrode comprises first electrode and second electrode, described interlayer insulating film is arranged on the top of described thin-film transistor and described storage capacitance, the zone that described interlayer insulating film correspondence described source electrode and described drain electrode offers first via hole and second via hole respectively, described source electrode is electrically connected with described first electrode by described first via hole, and described drain electrode is electrically connected with described second electrode by second via hole.
A kind of display unit comprises above-mentioned array base palte.
A kind of preparation method of array base palte, be included in the step that forms thin-film transistor and storage capacitance on the substrate, the step that forms described thin-film transistor comprises the formation grid, source electrode, the drain electrode step and at described source electrode, form the step of gate insulation layer between described drain electrode and the described grid, the step that forms described storage capacitance comprises formation first pole plate, second pole plate and the step that between described first pole plate and described second pole plate, forms dielectric layer, wherein, form the described source electrode of next-door neighbour, the dielectric constant of the described gate insulation layer of described drain electrode part is smaller or equal to the dielectric constant that forms described dielectric layer.
Preferably, the step that forms described gate insulation layer comprises the step that forms first grid insulating barrier and second gate insulation layer, the dielectric constant of described first grid insulating barrier is less than the dielectric constant of described second gate insulation layer, described first grid insulating barrier is close to described source electrode, described drain electrode, described first pole plate and described second pole plate are formed on the both sides up and down of described second gate insulation layer, and described dielectric layer is the part that the described second gate insulation layer correspondence described first pole plate and described second pole plate.
A kind of preferred version is that this preparation method specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form amorphous silicon layer at described resilient coating, described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, form the figure that comprises active layer silicon island and pole plate silicon island;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, described first grid insulating barrier covers described source electrode and described drain electrode fully and does not cover described first pole plate, and forms described first pole plate by the ion injection mode in described pole plate silicon island;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described first pole plate fully;
Perhaps, step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first pole plate fully and do not cover described source electrode and described corresponding the zone that drains;
Step S5): at completing steps S4 on the described substrate), above described second gate insulation layer, form the figure that comprises grid and second pole plate, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction;
Perhaps, step S5): at completing steps S4 on the described substrate), form the figure comprise grid above described first grid insulating barrier, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode; Form the figure that comprises second pole plate above described second gate insulation layer, described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction;
Step S6): at completing steps S5 on the described substrate), form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island.
A kind of preferred version is that this preparation method specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form the figure that comprises grid and second pole plate at described resilient coating;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, and described first grid insulating barrier covers described grid fully and do not cover the figure of described second pole plate;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described second pole plate fully;
Perhaps, step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described second pole plate fully and do not cover the zone that described grid correspondence;
Step S5): at completing steps S4 described substrate) forms amorphous silicon layer, and described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, forms the figure that comprises active layer silicon island and pole plate silicon island;
Step S6): form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island, described source electrode and described drain electrode are at least part of overlapping with described grid on the orthographic projection direction; Form first pole plate by the ion injection mode in described pole plate silicon island, described first pole plate and described second pole plate are overlapping on the orthographic projection direction.
Further preferably, also further comprise step S7): above described thin-film transistor and described storage capacitance, form the figure that comprises interlayer insulating film and extraction electrode, described extraction electrode comprises first electrode and second electrode, the zone of corresponding described source electrode and described drain electrode forms first via hole and second via hole respectively above described interlayer insulating film, described source electrode is electrically connected by described first via hole with described first electrode, and described drain electrode is electrically connected by described second via hole with described second electrode.
Preferably, form described resilient coating at described substrate and comprise that using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode or sputter mode, the thickness range of described resilient coating is
Depositing temperature is smaller or equal to 600 ℃.
Preferably, form described first grid insulating barrier and second gate insulation layer and comprise that using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode or the sputter mode forms corresponding first grid insulating layer film and second layer gate insulating film, the thickness range of described first grid insulating barrier is
The thickness range of described second gate insulation layer is
Preferably, form described grid and comprise that employing sputter mode, thermal evaporation mode, plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode form gate electrode film, form the figure that comprises grid and described second pole plate by a composition technology, the thickness range of described grid and described second pole plate is
Preferably, form described amorphous silicon layer and comprise plasma enhanced chemical vapor deposition mode or low-pressure chemical vapor deposition mode, depositing temperature is smaller or equal to 600 ℃, and the thickness range of described polysilicon layer is
Described amorphous silicon layer is carried out crystallization comprise employing excimer laser crystallization mode, metal-induced crystallization mode or solid phase crystallization mode, perhaps also further comprise: in crystallization process, increase the heat treatment dehydrogenating technology, deposit the activation technology of inducing smithcraft, heat treatment crystallization process or excimer laser irradiation crystallization process, impurity doping and impurity.
Preferably, described ion injection mode comprises the ion injection mode with mass-synchrometer, the ion cloud formula injection mode that does not have mass-synchrometer, plasma injection mode or solid-state diffusion formula injection mode, wherein, injected media is for containing boron element and/or phosphorus element-containing gas, the injection energy range is 10-200keV, and the implantation dosage scope is 1x10
11-1x10
20Atoms/cm
3
Preferably, ion activates thin-film transistor by flash annealing mode, quasi-molecule laser annealing mode or furnace annealing mode after injecting, and annealing region is 300 ℃-600 ℃, and the annealing time scope is 0.5-4 hour.
The invention has the beneficial effects as follows: in the described array base palte, by changing the source electrode that forms thin-film transistor, gate insulation layer between drain electrode and the grid, the pole plate of storage capacitance and the material of dielectric layer, and adopt the preparation method of corresponding array base palte, adopt the mask plate of existing formation storage capacitance and the insulating material of the big dielectric constant of collocation, both reduced dielectric layer thickness in the storage capacitance, effectively improved the capacity of storage capacitance again, significantly reduced the storage capacitance size, reduced to comprise the size of the dot structure of storage capacitance, thereby solved big and the problem that resolution limiting promotes of storage capacitance size in the preparation of low-temperature polysilicon film transistor array base palte, for the preparation of high-resolution display panel provides assurance, also be preparation high-resolution liquid crystal display unit and organic electroluminescence display device and method of manufacturing same assurance is provided.
Description of drawings
Fig. 1 is the cutaway view of array base palte in the prior art;
Fig. 2 is the cutaway view of array base palte in the embodiment of the invention 1;
Fig. 3 is preparation method's flow chart of array base palte among Fig. 2;
Fig. 4 is the cutaway view of each step in the array base palte preparation process among Fig. 2;
Wherein:
Fig. 4 A is for forming the cutaway view of resilient coating;
Fig. 4 B(4B-1 is 4B-2) for forming the cutaway view of polysilicon layer;
Fig. 4 C is for forming the cutaway view of first grid insulating barrier and mask layer;
Fig. 4 D is for forming the cutaway view of second gate insulation layer;
Fig. 4 E(4E-1 is 4E-2) for forming the cutaway view of the figure that comprises grid, second pole plate;
Fig. 4 F is for forming the cutaway view of source electrode and drain electrode;
Fig. 4 G is for forming the cutaway view that comprises interlayer insulating film and comprise the figure of extraction electrode;
Fig. 5 is the cutaway view of array base palte in the embodiment of the invention 2;
Fig. 6 is the cutaway view of array base palte in the embodiment of the invention 3;
Fig. 7 is the cutaway view of array base palte in the embodiment of the invention 4;
Among the figure: the 1-substrate; The 2-resilient coating; The 31-source electrode; The 32-drain electrode; The 33-polysilicon layer; 33a-active layer silicon island; 33b-pole plate silicon island; 33c-treats injection zone; The 34-grid; The 340-the first metal layer; The 4-gate insulation layer; 41-first grid insulating barrier; The 41a-mask layer; 41b-zone to be etched; 42-second gate insulation layer; 61-first pole plate; 62-second pole plate; The 7-interlayer insulating film; 81-first electrode; 82-second electrode.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments array base palte of the present invention, preparation method and display unit are described in further detail.
A kind of array base palte, comprise substrate and be formed on thin-film transistor and storage capacitance on the described substrate, described thin-film transistor comprises grid, source electrode, drains and is arranged at the gate insulation layer between described source electrode, described drain electrode and the described grid, described storage capacitance comprises the dielectric layer between first pole plate, second pole plate and described first pole plate and described second pole plate, wherein, described gate insulation layer is close to the dielectric constant of described source electrode, described drain electrode gate insulation layer partly smaller or equal to the dielectric constant of described dielectric layer.
A kind of display unit comprises above-mentioned array base palte.
A kind of preparation method of array base palte, be included in the step that forms thin-film transistor and storage capacitance on the substrate, the step that forms described thin-film transistor comprises the formation grid, source electrode, the drain electrode step and at described source electrode, form the step of gate insulation layer between described drain electrode and the described grid, the step that forms described storage capacitance comprises formation first pole plate, second pole plate and the step that between described first pole plate and described second pole plate, forms dielectric layer, wherein, form the described source electrode of next-door neighbour, the dielectric constant of the described gate insulation layer of described drain electrode part is smaller or equal to the dielectric constant that forms described dielectric layer.
Embodiment 1:
As shown in Figure 2, a kind of array base palte, comprise substrate 1, be formed on resilient coating 2 on the described substrate 1, and the thin-film transistor and the storage capacitance that are formed on described resilient coating 2 tops, described thin-film transistor comprises grid 34, source electrode 31, drain electrode 32 and be arranged at described source electrode 31, gate insulation layer 4 between described drain electrode 32 and the described grid 34, described storage capacitance comprises first pole plate 61, dielectric layer between second pole plate 62 and described first pole plate and described second pole plate, described gate insulation layer 4 comprises first grid insulating barrier 41 and second gate insulation layer 42, the dielectric constant of described first grid insulating barrier 41 is less than the dielectric constant of described second gate insulation layer 42, the described source electrode 31 of described first grid insulating barrier 41 next-door neighbours, described drain electrode 32, described first pole plate 61 and described second pole plate were located at the both sides up and down of described second gate insulation layer 42 in 62 minutes, and described dielectric layer is the part that described second gate insulation layer, 42 correspondences described first pole plate 61 and described second pole plate 62.
For to thin-film transistor with storage capacitance is carried out insulation protection and signal is drawn; also comprise interlayer insulating film 7 and extraction electrode in the described array base palte; described extraction electrode comprises first electrode 81 and second electrode 82; described interlayer insulating film 7 is arranged on the top of described thin-film transistor and described storage capacitance; the zone that described interlayer insulating film 7 correspondences described source electrode 31 and described drain electrode 32 offers first via hole and second via hole respectively; described source electrode 31 is electrically connected with described first electrode 81 by described first via hole, and described drain electrode 32 is electrically connected with described second electrode 82 by second via hole.
Wherein, described source electrode 31, described drain electrode 32 arrange with layer with described first pole plate 61, and described first grid insulating barrier 41 covers described source electrode 31 fully with described drain electrode 32 and do not cover described first pole plate 61; Described second gate insulation layer 42 covers described first grid insulating barrier 31 and described first pole plate 61 fully; Described grid 34 is arranged at described second gate insulation layer, 42 correspondences and the top in the zone between described source electrode 31 and the described drain electrode 32 and overlapping on orthographic projection direction top with described drain electrode 32 with described source electrode 31 simultaneously, and described second pole plate 62 is arranged at described second gate insulation layer, 42 tops and at least part of overlapping on the orthographic projection direction with described first pole plate 61.
In the present embodiment, described first grid insulating barrier 41 adopts silica material to form, and described first grid insulating barrier 41 is single layer structure; At least a formation that described second gate insulation layer 42 adopts in silica material, the silicon nitride material, described second gate insulation layer 42 is the laminated construction of single layer structure or a plurality of sublayers.The thickness range of described first grid insulating barrier 41 is
The thickness range of described second gate insulation layer 42 is
In the present embodiment, described source electrode 31, described drain electrode 32 adopt the low temperature polycrystalline silicon material to form with described first pole plate 61, and described source electrode 31, described drain electrode 32 with the thickness range of described first pole plate 61 are
Described grid 34 adopts at least a material in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium and the copper to form with described second pole plate 62, and described grid 34 with the thickness range of described second pole plate 62 is
In the present embodiment, described resilient coating 2 is the laminated construction of single layer structure or a plurality of sublayers, at least a formation that described resilient coating 2 adopts in silica material, the silicon nitride material.In the present embodiment, thin-film transistor is the top gate type structure, and described resilient coating 2 is arranged between described substrate 1 and described source electrode 31, described drain electrode 32, described first pole plate 61.
Accordingly, a kind of preparation method of array base palte, be included in the step that forms thin-film transistor and storage capacitance on the substrate, the step that forms described thin-film transistor comprises the formation grid, source electrode, the drain electrode step and at described source electrode, form the step of gate insulation layer between described drain electrode and the described grid, the step that forms described storage capacitance comprises the step that forms first pole plate and second pole plate, wherein, the step that forms described gate insulation layer comprises the step that forms first grid insulating barrier and second gate insulation layer, the dielectric constant of described first grid insulating barrier is less than the dielectric constant of described second gate insulation layer, described first grid insulating barrier is close to described source electrode, described drain electrode, described first pole plate and described second pole plate are formed on the both sides up and down of described second gate insulation layer, and described dielectric layer is the part that the described second gate insulation layer correspondence described first pole plate and described second pole plate.
Preferably, as shown in Figure 3, this preparation method specifically comprises the steps:
Step S1): form resilient coating at described substrate.
Shown in Fig. 4 A, in this step, on described substrate 1, using plasma strengthens chemical vapour deposition (CVD) (Plasma Enhanced: be called for short PECVD) mode, low-pressure chemical vapor deposition mode (Low Pressure Chemical Vapor Deposition: be called for short LPCVD), atmospheric pressure chemical vapour deposition (Atmospheric Pressure Chemical Vapor Deposition: be called for short APCVD) mode or electron cyclotron resonance chemical vapour deposition (CVD) (Electron Cyclotron Resonance Chemical Vapor Deposition: be called for short ECR-CVD) mode or sputter mode form resilient coating 2.Described resilient coating 2 can be silica, silicon nitride or the lamination of the two of individual layer, and its thickness range is
Preferred thickness range is
Depositing temperature is smaller or equal to 600 ℃.
Wherein, described substrate 1 adopts transparent material such as glass to make and through cleaning in advance.Described resilient coating 2 is used for stopping that substrate 1 contained impurity diffuses in the active layer of thin-film transistor (TFT), prevents from characteristics such as the threshold voltage of TFT and leakage current are exerted an influence.Except introducing resilient coating 2, higher because of metals content impurities such as aluminium, barium and sodium in traditional alkali glass, the diffusion of metal impurities takes place easily, so preferable substrate 1 adopts alkali-free glass to make in high-temperature processing technology.
Step S2): form amorphous silicon layer at described resilient coating, and described amorphous silicon layer is carried out crystallization to form polysilicon layer, described polysilicon layer is carried out composition technology, form the figure that comprises active layer silicon island and pole plate silicon island.
Shown in Fig. 4 B, in this step, form described amorphous silicon layer by depositional mode at described resilient coating 2, depositional mode comprises plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, depositing temperature is smaller or equal to 600 ℃, and the thickness range of described amorphous silicon layer is
Preferred thickness range is
Described amorphous silicon layer is carried out crystallization comprise excimer laser crystallization mode, metal-induced crystallization mode or the solid phase crystallization mode of adopting, change amorphous silicon layer into polysilicon layer 33(Fig. 4 B-1), need to prove, adopt different crystallization modes, the technical process that it is concrete and the structure of thin-film transistor can be different.Perhaps, according to concrete production technology, also further comprise: increase the heat treatment dehydrogenating technology in crystallization process, deposit the activation technology of inducing smithcraft, heat treatment crystallization process, excimer laser irradiation crystallization process, impurity doping and impurity, wherein the impurity doping mainly is the doping (the P type mixes or N-type is mixed) of source drain region.
After crystallization process is finished, adopt composition technology in polysilicon layer 33, to form the figure (Fig. 4 B-2) that comprises active layer silicon island 33a and pole plate silicon island 33b.Wherein, composition technology can include only photoetching process, or, comprising photoetching process and etch step, other are used to form the technology of predetermined pattern can also to comprise printing, ink-jet etc. simultaneously; Photoetching process refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise technical processs such as film forming, exposure, development form the technology of figure.The corresponding composition technology of formed structure choice in can be according to the present invention.
In the present embodiment, form one deck photoresist at polysilicon layer 33, photoresist is exposed and develops, then polysilicon layer 33 is carried out dry etching, the figure that comprises active layer silicon island 33a and pole plate silicon island 33b with formation, 33a zone, described active layer silicon island is used to form the active layer of TFT, and 33b zone, described pole plate silicon island is used to form first pole plate 61 of storage capacitance.
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, described first grid insulating barrier covers described source electrode and described drain electrode fully and does not cover described first pole plate, and forms described first pole plate by the ion injection mode in described pole plate silicon island.
In this step, using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode or the sputter mode forms first grid insulating layer film above active layer silicon island 33a and pole plate silicon island 33b, and depositing temperature is smaller or equal to 600 ℃.
Then, shown in Fig. 4 C, above described first grid insulating layer film, form one deck photoresist, photoresist is exposed and develops, form mask layer 41a, this mask layer 41a the photoresist of described pole plate silicon island 33b except the zone, edge in correspondence and is removed, thereby expose corresponding the first grid insulating layer film zone that will form the zone of first pole plate, the corresponding first grid insulating layer film of this exposed region partly is that regional 41b(to be etched namely defines the district to be etched in the first grid insulating layer film), 33b zone, the corresponding pole plate of this exposed region silicon island treats that namely injection zone 33c(namely defines the ion implanted region that forms first pole plate 61 in the polysilicon layer 33).Mask plate in this photoetching process can directly adopt the storage capacitance mask plate in the common technology and needn't design in addition, thereby does not need to increase extra mask plate design and cost of manufacture.
Wherein, described first grid insulating barrier 41 can adopt the silica material of individual layer to form, and silica material can form good interface with active layer (active layer silicon island 33a) in the bottom and contact, and improves the electric property of thin-film transistor.The thickness of described first grid insulating barrier 41 is
Or according to the suitable thickness of concrete arts demand selection.
Then, to pole plate silicon island 33b treat that injection zone 33c carries out ion and injects, treat that injection zone 33c injects through ion and namely form first pole plate 61 to form the first pole plate 61().Described ion injection mode comprises the ion injection mode with mass-synchrometer, the ion cloud formula injection mode that does not have mass-synchrometer, plasma injection mode or solid-state diffusion formula injection mode.In the present embodiment, preferably adopt the ion cloud formula injection mode of main flow, treat injection zone 33c and carry out first pole plate that the heavy prescription amount injects to form storage capacitance.According to the design needs, injected media is the gas that contains boron element and/or phosphorus element-containing, and a kind of optimal way contains boron element, for example B for adopting
2H
6/ H
2The mist of (ratio is between 5%-15%) is as injected media; The injection energy range is 10-200keV, and preferred energy range is 40-100keV; The implantation dosage scope is 1x10
11-1x10
20Atoms/cm
3, preferred implantation dosage scope is 1x10
13-8x10
15Atoms/cm
3Perhaps, also can adopt phosphorus element-containing, for example PH
3/ H
2Mist as injected media, it injects energy and implantation dosage and above-mentioned B
2H
6/ H
2Mode similar, no longer describe in detail here.
And then, the to be etched regional 41b of first grid insulating layer film is carried out dry etching or wet etching, to form first grid insulating barrier 41.During dry etching, can adopt the gas that contains fluorine element, as SF
6, CF
4, CHF
3Deng gas or aforementioned gas and O
2Mist as the etching medium, in reactive ion etching machine, plasma etching machine or reaction coupled plasma etching machine etc., carry out etching.During wet etching, the hydrofluoric acid solution etc. that can adopt hydrofluoric acid or add corrosion inhibiter is as the etching medium, and etching is removed the first grid insulating layer film of regional 41b part to be etched under normal temperature or high temperature.Above-mentioned two kinds of etching modes all can obtain etching effect preferably in the present embodiment, and etching can adopt common stripping technology that remaining photoresist lift off is removed after finishing.
Here it should be understood that in this step and can change by ion injection formation first pole plate and by the process sequence of etching formation first grid insulating barrier, in actual production process, can adjust flexibly process sequence as required.
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described first pole plate fully.
Shown in Fig. 4 D, in this step, using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode or the sputter mode forms second gate insulation layer 42, and depositing temperature is smaller or equal to 600 ℃.
Described second gate insulation layer 42 can adopt silica material, silicon nitride material or at least a material in the two of individual layer to form the lamination of a plurality of sublayers, for the capacity that makes storage capacitance increases, the thickness of described second gate insulation layer 42 can be thin as much as possible, and preferably adopt the bigger silicon nitride material of dielectric constant to form.The thickness range of described second gate insulation layer 42 is
Or according to the suitable thickness of concrete arts demand selection.
Step S5): at completing steps S4 on the described substrate), above described second gate insulation layer, form the figure that comprises grid and second pole plate, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction.
Shown in Fig. 4 E, in this step, above described second gate insulation layer 42, adopt sputter mode, thermal evaporation mode, plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode to form the first metal layer 340(Fig. 4 E-1), by a composition technology (film forming, exposure, development, wet etching or dry etching), form the figure (Fig. 4 E-2) that comprises grid 34 and described second pole plate 62 simultaneously.Described the first metal layer 340 adopts metal, metal alloy, as: electric conducting materials such as molybdenum, molybdenum alloy form, and described grid 34 with the thickness range of described second pole plate 62 is
Preferred thickness range is
So far, storage capacitance has just formed, and wherein: described first pole plate 61 and described second pole plate 62 form two pole plates of storage capacitance respectively, and second gate insulation layer 42 between described first pole plate 61 and described second pole plate 62 forms dielectric layers.In the present embodiment, because second gate insulation layer 42 can be accomplished thin as much as possible and dielectric constant is bigger, according to formula (1), make storage capacitance under reduced size, can obtain bigger capacitance (can improve more than 2 times at least compared to existing technology), and, also reduced storage capacitance effectively in the size that array base palte takies, the density of the pixel region in the array base palte can further be improved, for the preparation high-resolution display panel provides assurance.
Step S6): at completing steps S5 on the described substrate), form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island.
Shown in Fig. 4 F, in this step, form described source electrode 31 and described drain electrode 32 in the both sides on described active layer silicon 33a island.Described ion injection mode comprises the ion injection mode with mass-synchrometer, the ion cloud formula injection mode that does not have mass-synchrometer, plasma injection mode or solid-state diffusion formula injection mode.According to the design needs, injected media is the gas that contains boron element and/or phosphorus element-containing, and preferred the employing contains boron element, for example B
2H
6/ H
2The mist of (ratio is between 5%-15%) is as injected media; The injection energy range is 10-200keV, and preferred energy range is 40-100keV; The implantation dosage scope is 1x10
11-1x10
20Atoms/cm
3, preferred implantation dosage scope is 1x10
13-8x10
15Atoms/cm
3
Can activate thin-film transistor by flash annealing mode (Rapid Thermal Annealer: be called for short RTA), quasi-molecule laser annealing mode (Excimer Laser Annealer: be called for short ELA) or furnace annealing mode after the ion implantation technology.In the present embodiment, preferred furnace annealing mode is carried out the activation heat processing to thin-film transistor, and the furnace annealing mode has economy, the simple and preferable advantage of uniformity, and annealing region is 300 ℃-600 ℃, the annealing time scope is 0.5-4 hour, and further preferred time range is 1-3 hour.
Here it should be understood that, step S4), step S5) with step S6) in process sequence can change, namely, in the present embodiment, also can form source electrode and drain electrode by the ion injection mode, and then form second gate insulation layer earlier by composition technology, then form the figure that comprises grid and first pole plate, in actual production process, can adjust flexibly process sequence as required.
For thin-film transistor and storage capacitance are carried out insulation protection, described this preparation method also further comprises step S7): above described thin-film transistor and described storage capacitance, form interlayer insulating film; For being carried out signal, thin-film transistor draws, described this preparation method also further comprises: the zone that described source electrode and described drain electrode in described interlayer insulating film correspondence forms the figure that comprises first via hole, second via hole and extraction electrode respectively, described extraction electrode comprises first electrode and second electrode, described source electrode is electrically connected by described first via hole with described first electrode, and described drain electrode is electrically connected by described second via hole with described second electrode.
Shown in Fig. 4 G, deposition interlayer insulating film 7 above described thin-film transistor and described storage capacitance, the thickness range of described interlayer insulating film 7 is
Preferred thickness range is
Identical with the mode of deposition first grid insulating barrier and second gate insulation layer, but using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode deposits formation interlayer insulating film 7, and depositing temperature is smaller or equal to 600 ℃.Described interlayer insulating film 7 can adopt the silica material of individual layer or silica material, silicon nitride material to form the lamination of a plurality of sublayers.
Then, above described interlayer insulating film 7, adopt photoetching process to form mask layer, and adopt dry etching to form first via hole and second via hole.Dry etching can adopt multiple modes such as plasma etching, reactive ion etching, inductively coupled plasma etching, and etching gas can adopt gas fluorine-containing, chlorine is as CF
4, CHF
3, SF
6, CCl
2F
2Deng gas or above-mentioned gas and O
2The mist that forms.
Then, above interlayer insulating film 7, adopt sputter mode, thermal evaporation mode or plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode to deposit second metal level.Above second metal level, adopt photoetching process to form mask layer, and adopt wet etching or dry etching to form the figure that comprises first electrode 81 and second electrode 82, described first electrode 81 runs through first via hole and is electrically connected with described source electrode 31, and described second electrode 82 runs through second via hole and is electrically connected with described drain electrode 32.Further, first electrode 81 is electrically connected with data wire in the array base palte, and second electrode 82 is electrically connected with pixel electrode in the array base palte.Second metal level adopts metal, metal alloy, as: electric conducting materials such as molybdenum, molybdenum alloy, aluminium, aluminium alloy, titanium form, and thickness range is
Preferred thickness range is
In the present embodiment, in two pole plates of storage capacitance, one of them pole plate adopts the low temperature amorphous silicon materials (need mix) identical with drain electrode with the source electrode of thin-film transistor to form, and another pole plate adopts the conductive metallic material identical with the grid that forms thin-film transistor to form; And the gate insulation layer of thin-film transistor adopts the substep depositional mode to form, the employing of first grid insulating barrier and source electrode and drain electrode have that good interface contacts and dielectric constant materials with smaller (for example silica) forms, second gate insulation layer adopts the bigger material (for example silicon nitride) of dielectric constant to form, and second gate insulation layer between two pole plates of storage capacitance is dielectric layer.Like this, under identical capacitance condition, compare existing storage capacitance, dielectric layer thickness is thinner, the size of storage capacitance is littler, make to adopt the small size storage capacitance can reach the capacitance of design requirement, reduced to comprise the size of the dot structure of storage capacitance, for the preparation of high-resolution display floater provides assurance.
Embodiment 2:
Thin-film transistor in the array base palte of present embodiment and embodiment 1 is all top gate type.Difference is that the structure of first grid insulating barrier is different with embodiment 1 in the present embodiment array base palte.
As shown in Figure 5, in the present embodiment, described source electrode 31, described drain electrode 32 arrange with layer with described first pole plate 61, and described first grid insulating barrier 41 covers described source electrode 31 fully with described drain electrode 32 and do not cover described first pole plate 61; Described second gate insulation layer 42 cover described first pole plate 61 fully and do not cover described source electrode 31 and described drain electrode 32 corresponding the zone; Described grid 34 is arranged at described first grid insulating barrier 41 correspondences and the top in the zone between described source electrode 31 and the described drain electrode 32 and overlapping on orthographic projection direction top with described drain electrode 32 with described source electrode 31 simultaneously, and described second pole plate 62 is arranged at described second gate insulation layer, 42 tops and at least part of overlapping on the orthographic projection direction with described first pole plate 61.
Accordingly, the preparation method of the array base palte of present embodiment specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form amorphous silicon layer at described resilient coating, described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, form the figure that comprises active layer silicon island and pole plate silicon island;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, described first grid insulating barrier covers described source electrode and described drain electrode fully and does not cover described first pole plate, and forms described first pole plate by the ion injection mode in described pole plate silicon island;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first pole plate fully and do not cover described source electrode and described corresponding the zone that drains;
Step S5): at completing steps S4 on the described substrate), form the figure comprise grid above described first grid insulating barrier, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode; Form the figure that comprises second pole plate above described second gate insulation layer, described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction;
Step S6): at completing steps S5 on the described substrate), form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island.
Other structures of array base palte are identical with embodiment 1 in the present embodiment, but the preparation method of the concrete technology in its preparation process or technological parameter reference example 1 repeats no more here.
Embodiment 3:
Present embodiment and embodiment 1,2 difference are that the thin-film transistor in the present embodiment array base palte is bottom gate type.
As shown in Figure 6, in the present embodiment, a kind of array base palte, comprise substrate 1, be formed on resilient coating 2 on the described substrate 1, and the thin-film transistor and the storage capacitance that are formed on described resilient coating 2 tops, described thin-film transistor comprises grid 34, source electrode 31, drain electrode 32 and be arranged at described source electrode 31, gate insulation layer 4 between described drain electrode 32 and the described grid 34, described storage capacitance comprises first pole plate 61 and second pole plate 62, described gate insulation layer 4 comprises first grid insulating barrier 41 and second gate insulation layer 42, the dielectric constant of described first grid insulating barrier 41 is less than the dielectric constant of described second gate insulation layer 42, and described first pole plate 61 and described second pole plate were located at the both sides of described second gate insulation layer 42 in 62 minutes.
In the present embodiment, because thin-film transistor is the bottom gate type structure, described resilient coating 2 is arranged between described substrate 2 and described grid 34, described second pole plate 62.Described grid 34 arranges with layer with described second pole plate 62, and described first grid insulating barrier 41 covers described grid 34 fully and do not cover described second pole plate 62; Described second gate insulation layer 42 covers described first grid insulating barrier 41 and described second pole plate 62 fully; Described source electrode 31 and described drain electrode 32 be arranged at described second gate insulation layer 42 corresponding the top at two ends of described grid 34 and overlapping on orthographic projection direction top with described grid 34 respectively, described first pole plate 61 is arranged at the top that described second gate insulation layer, 42 correspondences described second pole plate 62.
Accordingly, the preparation method of array base palte specifically comprises the steps: in the present embodiment
Step S1): form resilient coating at described substrate;
Step S2): form the figure that comprises grid and second pole plate at described resilient coating;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described second pole plate fully;
Step S5): at completing steps S4 described substrate) forms amorphous silicon layer, and described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, forms the figure that comprises active layer silicon island and pole plate silicon island;
Step S6): form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island, described source electrode and described drain electrode are at least part of overlapping with described grid on the orthographic projection direction; Form first pole plate by the ion injection mode in described pole plate silicon island, described first pole plate and described second pole plate are overlapping on the orthographic projection direction.
Other structures of array base palte are identical with embodiment 1 in the present embodiment, but the preparation method of the concrete technology in its preparation process or technological parameter reference example 1 repeats no more here.
Embodiment 4:
Thin-film transistor in the array base palte of present embodiment and embodiment 3 is all bottom gate type.Difference is that the structure of second gate insulation layer is different with embodiment 3 in the present embodiment array base palte.
As shown in Figure 7, in the present embodiment, described grid 34 arranges with layer with described second pole plate 62, and described first grid insulating barrier 41 covers described grid 34 fully and do not cover described second pole plate 62; Described second gate insulation layer 42 covers described second pole plate 62 fully and does not cover the zone that described grid 34 correspondences; Described source electrode 31 and described drain electrode 32 be arranged at described first grid insulating barrier 41 corresponding the top at two ends of described grid 34 and overlapping on orthographic projection direction top with described grid 34 respectively, described first pole plate 62 is arranged at the top that described second gate insulation layer, 42 correspondences described second pole plate 62.
Accordingly, the preparation method of the array base palte of present embodiment specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form the figure that comprises grid and second pole plate at described resilient coating;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described second pole plate fully and do not cover the zone that described grid correspondence;
Step S5): at completing steps S4 described substrate) forms amorphous silicon layer, and described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, forms the figure that comprises active layer silicon island and pole plate silicon island;
Step S6): form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island, described source electrode and described drain electrode are at least part of overlapping with described grid on the orthographic projection direction; Form first pole plate by the ion injection mode in described pole plate silicon island, described first pole plate and described second pole plate are overlapping on the orthographic projection direction.
Other structures of array base palte are identical with embodiment 3 in the present embodiment, but the preparation method of the concrete technology in its preparation process or technological parameter reference example 1 repeats no more here.
The present invention also provides a kind of display unit, comprises array base palte arbitrary among the embodiment 1-4.Described display unit can be liquid crystal indicator or el display device, for example liquid crystal panel, LCD TV, mobile phone, LCD etc., and it comprises the array base palte in color membrane substrates and above-described embodiment; Except liquid crystal indicator, described display unit can also be the display unit of other types, and such as electronic reader etc., it does not comprise color membrane substrates, but comprises the array base palte in above-described embodiment.
In the array base palte of the present invention, by changing the source electrode that forms thin-film transistor, gate insulation layer between drain electrode and the grid, the pole plate of storage capacitance and the material of dielectric layer, and adopt the preparation method of corresponding array base palte, adopt the mask plate of existing formation storage capacitance and the insulating material of the big dielectric constant of collocation, both reduced dielectric layer thickness in the storage capacitance, effectively improved the capacity of storage capacitance again, significantly reduced the storage capacitance size, reduced to comprise the size of the dot structure of storage capacitance, thereby solved big and the problem that resolution limiting promotes of storage capacitance size in the preparation of low-temperature polysilicon film transistor array base palte, for the preparation of high-resolution display panel provides assurance, also be preparation high-resolution liquid crystal display unit and organic electroluminescence display device and method of manufacturing same assurance is provided.
Be understandable that above execution mode only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement also are considered as protection scope of the present invention.
Claims (17)
1. array base palte, comprise substrate and be formed on thin-film transistor and storage capacitance on the described substrate, described thin-film transistor comprises grid, source electrode, drains and is arranged at the gate insulation layer between described source electrode, described drain electrode and the described grid, described storage capacitance comprises the dielectric layer between first pole plate, second pole plate and described first pole plate and described second pole plate, it is characterized in that described gate insulation layer is close to the dielectric constant of described source electrode, described drain electrode gate insulation layer partly smaller or equal to the dielectric constant of described dielectric layer.
2. array base palte according to claim 1, it is characterized in that, described gate insulation layer comprises first grid insulating barrier and second gate insulation layer, the dielectric constant of described first grid insulating barrier is less than the dielectric constant of described second gate insulation layer, described first grid insulating barrier is close to described source electrode, described drain electrode, described first pole plate and the described second pole plate branch are located at the both sides up and down of described second gate insulation layer, and described dielectric layer is the part that the described second gate insulation layer correspondence described first pole plate and described second pole plate.
3. array base palte according to claim 2 is characterized in that, described source electrode, described drain electrode and described first pole plate arrange with layer, and described first grid insulating barrier covers described source electrode and described drain electrode fully and do not cover described first pole plate; Described second gate insulation layer covers described first grid insulating barrier and described first pole plate fully; Described grid is arranged at the described second gate insulation layer correspondence and the top in the zone between described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate is arranged at above described second gate insulation layer and is at least part of overlapping on the orthographic projection direction with described first pole plate;
Perhaps, described source electrode, described drain electrode and described first pole plate arrange with layer, and described first grid insulating barrier covers described source electrode and described drain electrode fully and do not cover described first pole plate; Described second gate insulation layer cover described first pole plate fully and do not cover described source electrode corresponding with described drain electrode the zone; Described grid is arranged at described first grid insulating barrier correspondence and the top in the zone between described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate is arranged at above described second gate insulation layer and is at least part of overlapping on the orthographic projection direction with described first pole plate.
4. array base palte according to claim 2 is characterized in that, described grid and described second pole plate arrange with layer, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate; Described second gate insulation layer covers described first grid insulating barrier and described second pole plate fully; Described source electrode and described drain electrode be arranged at described second gate insulation layer corresponding the top at two ends of described grid and overlapping on orthographic projection direction top with described grid respectively, described first pole plate is arranged at the top that the described second gate insulation layer correspondence described second pole plate;
Perhaps, described grid and described second pole plate arrange with layer, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate; Described second gate insulation layer covers described second pole plate fully and does not cover the zone that described grid correspondence; Described source electrode and described drain electrode be arranged at described first grid insulating barrier corresponding the top at two ends of described grid and overlapping on orthographic projection direction top with described grid respectively, described first pole plate is arranged at the top that the described second gate insulation layer correspondence described second pole plate.
5. according to claim 3 or 4 described array base paltes, it is characterized in that described first grid insulating barrier adopts silica material to form, described first grid insulating barrier is single layer structure; Described second gate insulation layer adopts at least a formation in silica material, the silicon nitride material, and described second gate insulation layer is the laminated construction of single layer structure or a plurality of sublayers.
6. array base palte according to claim 5 is characterized in that, the thickness range of described first grid insulating barrier is
The thickness range of described second gate insulation layer is
7. array base palte according to claim 6 is characterized in that, described source electrode, described drain electrode and described first pole plate adopt the low temperature polycrystalline silicon material to form, and the thickness range of described source electrode, described drain electrode and described first pole plate is
Described grid and described second pole plate adopt at least a material in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium and the copper to form, and the thickness range of described grid and described second pole plate is
8. array base palte according to claim 7, it is characterized in that, described array base palte also comprises resilient coating, described resilient coating is the laminated construction of single layer structure or a plurality of sublayers, described resilient coating adopts at least a formation in silica material, the silicon nitride material, and described resilient coating is arranged between described substrate and described source electrode, described drain electrode, described first pole plate; Perhaps, described resilient coating is arranged between described substrate and described grid, described second pole plate.
9. array base palte according to claim 8, it is characterized in that, described array base palte also comprises interlayer insulating film and extraction electrode, described extraction electrode comprises first electrode and second electrode, described interlayer insulating film is arranged on the top of described thin-film transistor and described storage capacitance, the zone that described interlayer insulating film correspondence described source electrode and described drain electrode offers first via hole and second via hole respectively, described source electrode is electrically connected with described first electrode by described first via hole, and described drain electrode is electrically connected with described second electrode by second via hole.
10. a display unit is characterized in that, comprises each described array base palte of claim 1-9.
11. the preparation method of an array base palte, be included in the step that forms thin-film transistor and storage capacitance on the substrate, the step that forms described thin-film transistor comprises the formation grid, source electrode, the drain electrode step and at described source electrode, form the step of gate insulation layer between described drain electrode and the described grid, the step that forms described storage capacitance comprises formation first pole plate, second pole plate and the step that between described first pole plate and described second pole plate, forms dielectric layer, it is characterized in that, form the described source electrode of next-door neighbour, the dielectric constant of the described gate insulation layer of described drain electrode part is smaller or equal to the dielectric constant that forms described dielectric layer.
12. preparation method according to claim 11, it is characterized in that, the step that forms described gate insulation layer comprises the step that forms first grid insulating barrier and second gate insulation layer, the dielectric constant of described first grid insulating barrier is less than the dielectric constant of described second gate insulation layer, described first grid insulating barrier is close to described source electrode, described drain electrode, described first pole plate and described second pole plate are formed on the both sides up and down of described second gate insulation layer, and described dielectric layer is the part that the described second gate insulation layer correspondence described first pole plate and described second pole plate.
13. preparation method according to claim 12 is characterized in that, this preparation method specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form amorphous silicon layer at described resilient coating, described amorphous silicon layer is carried out crystallization with the formation polysilicon layer, and described polysilicon layer is carried out composition technology, form the figure that comprises active layer silicon island and pole plate silicon island;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, described first grid insulating barrier covers described source electrode and described drain electrode fully and does not cover described first pole plate, and forms described first pole plate by the ion injection mode in described pole plate silicon island;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described first pole plate fully;
Perhaps, step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first pole plate fully and do not cover described source electrode and described corresponding the zone that drains;
Step S5): at completing steps S4 on the described substrate), above described second gate insulation layer, form the figure that comprises grid and second pole plate, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode, and described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction;
Perhaps, step S5): at completing steps S4 on the described substrate), form the figure comprise grid above described first grid insulating barrier, described grid is formed on zone between corresponding described source electrode and the described drain electrode and simultaneously overlapping on orthographic projection direction top with described source electrode and described drain electrode; Form the figure that comprises second pole plate above described second gate insulation layer, described second pole plate and described first pole plate are at least part of overlapping on the orthographic projection direction;
Step S6): at completing steps S5 on the described substrate), form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island.
14. preparation method according to claim 12 is characterized in that, this preparation method specifically comprises the steps:
Step S1): form resilient coating at described substrate;
Step S2): form the figure that comprises grid and second pole plate at described resilient coating;
Step S3): at completing steps S2 described substrate) forms the figure that comprises first grid insulating barrier, and described first grid insulating barrier covers described grid fully and do not cover described second pole plate;
Step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described first grid insulating barrier and described second pole plate fully;
Perhaps, step S4): at completing steps S3 described substrate) forms the figure that comprises second gate insulation layer, and described second gate insulation layer covers described second pole plate fully and do not cover the zone that described grid correspondence;
Step S5): at completing steps S4 described substrate) forms amorphous silicon layer, and described amorphous silicon layer is carried out crystallization to form polysilicon layer, and described polysilicon layer is carried out composition technology, forms the figure that comprises active layer silicon island and pole plate silicon island;
Step S6): form described source electrode and described drain electrode by the ion injection mode in the both sides of described active layer silicon island, described source electrode and described drain electrode are at least part of overlapping with described grid on the orthographic projection direction; Form first pole plate by the ion injection mode in described pole plate silicon island, described first pole plate and described second pole plate are overlapping on the orthographic projection direction.
15. according to claim 13 or 14 described preparation methods, it is characterized in that, also further comprise step S7): above described thin-film transistor and described storage capacitance, form the figure that comprises interlayer insulating film and extraction electrode, described extraction electrode comprises first electrode and second electrode, the zone of corresponding described source electrode and described drain electrode forms first via hole and second via hole respectively above described interlayer insulating film, described source electrode is electrically connected by described first via hole with described first electrode, and described drain electrode is electrically connected by described second via hole with described second electrode.
16. preparation method according to claim 15, it is characterized in that, form described first grid insulating barrier and second gate insulation layer and comprise that using plasma strengthens chemical vapour deposition (CVD) mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode or the sputter mode forms corresponding first grid insulating layer film and second layer gate insulating film, the thickness range of described first grid insulating barrier is
The thickness range of described second gate insulation layer is
17. preparation method according to claim 16, it is characterized in that, form described grid and comprise that employing sputter mode, thermal evaporation mode, plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, atmospheric pressure chemical vapour deposition mode or electron cyclotron resonance chemical vapour deposition (CVD) mode form gate electrode film, form the figure that comprises grid and described second pole plate by a composition technology, the thickness range of described grid and described second pole plate is
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| CN2013102039124A CN103296034A (en) | 2013-05-28 | 2013-05-28 | Array substrate, production method thereof and display device |
| PCT/CN2013/086497 WO2014190669A1 (en) | 2013-05-28 | 2013-11-04 | Array substrate, manufacturing method, and display apparatus |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103584A (en) * | 2014-06-25 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate fabrication method |
| WO2014190669A1 (en) * | 2013-05-28 | 2014-12-04 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display apparatus |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1928683A (en) * | 2005-09-09 | 2007-03-14 | 群康科技(深圳)有限公司 | Thin-film transistor array substrate and its making method |
| CN101064322A (en) * | 2006-04-26 | 2007-10-31 | 爱普生映像元器件有限公司 | Electro-optical device and electronic apparatus |
| CN101071242A (en) * | 2006-05-10 | 2007-11-14 | 三星电子株式会社 | Display substrate, method for manufacturing the same and display apparatus having the same |
| CN103081079A (en) * | 2010-08-30 | 2013-05-01 | 夏普株式会社 | Semiconductor device and process for production thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1020920B1 (en) * | 1999-01-11 | 2010-06-02 | Sel Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a driver TFT and a pixel TFT on a common substrate |
| KR101243809B1 (en) * | 2006-06-30 | 2013-03-18 | 엘지디스플레이 주식회사 | Method For Fabricating Thin Film Transistor And Method For Fabricating Thin Film Transistor Array Substrate By Applying Said Method |
| KR101747341B1 (en) * | 2010-11-02 | 2017-06-15 | 엘지디스플레이 주식회사 | Array substrate for organic electro luminescent device and method of fabricating the same |
| CN103296034A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
-
2013
- 2013-05-28 CN CN2013102039124A patent/CN103296034A/en active Pending
- 2013-11-04 WO PCT/CN2013/086497 patent/WO2014190669A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1928683A (en) * | 2005-09-09 | 2007-03-14 | 群康科技(深圳)有限公司 | Thin-film transistor array substrate and its making method |
| CN101064322A (en) * | 2006-04-26 | 2007-10-31 | 爱普生映像元器件有限公司 | Electro-optical device and electronic apparatus |
| CN101071242A (en) * | 2006-05-10 | 2007-11-14 | 三星电子株式会社 | Display substrate, method for manufacturing the same and display apparatus having the same |
| CN103081079A (en) * | 2010-08-30 | 2013-05-01 | 夏普株式会社 | Semiconductor device and process for production thereof |
Cited By (20)
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