CN106997903A - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
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- CN106997903A CN106997903A CN201610974692.9A CN201610974692A CN106997903A CN 106997903 A CN106997903 A CN 106997903A CN 201610974692 A CN201610974692 A CN 201610974692A CN 106997903 A CN106997903 A CN 106997903A
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- 239000010409 thin film Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 291
- 239000010410 layer Substances 0.000 claims description 375
- 238000005530 etching Methods 0.000 claims description 59
- 238000000059 patterning Methods 0.000 claims description 51
- 238000009413 insulation Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 29
- 238000002360 preparation method Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 27
- 239000011229 interlayer Substances 0.000 claims description 26
- 239000012212 insulator Substances 0.000 claims description 24
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 12
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 12
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 229910052733 gallium Inorganic materials 0.000 claims description 12
- 229910052738 indium Inorganic materials 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 12
- 229910052725 zinc Inorganic materials 0.000 claims description 12
- 239000011701 zinc Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 239000005300 metallic glass Substances 0.000 claims description 4
- 235000006408 oxalic acid Nutrition 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000007788 liquid Substances 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 229910021389 graphene Inorganic materials 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- ZGHDMISTQPRNRG-UHFFFAOYSA-N dimolybdenum Chemical compound [Mo]#[Mo] ZGHDMISTQPRNRG-UHFFFAOYSA-N 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- FAHBNUUHRFUEAI-UHFFFAOYSA-M hydroxidooxidoaluminium Chemical compound O[Al]=O FAHBNUUHRFUEAI-UHFFFAOYSA-M 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
Abstract
The invention discloses a thin film transistor and a manufacturing method thereof, wherein the thin film transistor is provided with a first patterned semiconductor layer with lower resistance value and a second patterned semiconductor layer with higher resistance value, the first patterned semiconductor layer is closer to a grid electrode, and the second patterned semiconductor layer is closer to a drain electrode, so that the number of extra carriers generated by a back channel influenced by the drain electrode can be reduced, and the change range of the critical voltage of the thin film transistor along with different drain electrode voltages is reduced.
Description
Technical field
The present invention relates to a kind of thin film transistor (TFT) and preparation method thereof, there are two layers of different resistance values more particularly, to one kind
The thin film transistor (TFT) of patterned semiconductor layer and preparation method thereof.
Background technology
In recent years, the application development of various flat-panel screens is rapid, all kinds of daily necessitiess such as TV, mobile phone, vapour
Locomotive, even refrigerator, all visible application being combined with each other with flat-panel screens.In flat-panel screens technology, film crystal
It is a kind of semiconductor element being widely used to manage (thin film transistor, TFT), for example, apply in liquid crystal display
(liquid crystal display, LCD), Organic Light Emitting Diode (organic light emitting diode,
OLED) in the flat-panel screens such as display and Electronic Paper (electronic paper, E-paper).Thin film transistor (TFT) is to utilize
To provide the switching of voltage or electric current, to cause the display pixel in various displays can show bright, dark and GTG aobvious
Show effect.
The thin film transistor (TFT) that current display industry is used can be distinguished according to the semiconductor layer material used, including non-
Polycrystal silicon film transistor (amorphous silicon TFT, a-Si TFT), polycrystalline SiTFT (poly silicon
) and oxide semiconductor thin-film transistor (metal oxide semiconductor TFT) TFT.It is thin compared to polysilicon
Film transistor, oxide semiconductor thin-film transistor has the advantages that electron mobility is higher and manufacture craft is more simplified, therefore
It is considered as the amorphous silicon film transistor for having an opportunity to may replace current main flow.However, in bottom gate thin film transistor, due to half
Back of the body passage (back channel) closer drain electrode in conductor layer, therefore can when applying voltages to drain electrode to carry on the back passage
Region produces extra carrier, and the critical voltage (threshold voltage) of thin film transistor (TFT) can be caused to change, and then
Reduce the control ability of the prepass (front channel) of close grid in semiconductor layer so that control thin film transistor (TFT)
Difficulty rises.
The content of the invention
One of main object of the present invention is to provide a kind of thin film transistor (TFT) and preparation method thereof, by setting two layers of tool
There is the patterned semiconductor layer of different resistance values, to avoid the problem of critical voltage changes.
For up to above-mentioned purpose, one embodiment of the invention provides a kind of thin film transistor (TFT), it include a substrate, a grid,
One drain electrode, a source electrode, a gate insulator, one first patterned semiconductor layer and one second patterned semiconductor layer.Grid is set
It is placed on substrate, and gate insulator is arranged on grid.First patterned semiconductor layer is set with the second patterned semiconductor layer
It is placed on gate insulator, wherein grid is arranged between substrate and the first patterned semiconductor layer, the first patterned semiconductor
Layer is arranged between the second patterned semiconductor layer and gate insulator, and the area of the first patterned semiconductor layer is more than second
The area of patterned semiconductor layer.Drain electrode is arranged in the first patterned semiconductor layer with source electrode, and is partly led with the first patterning
Body layer electrical connection.
For up to above-mentioned purpose, one embodiment of the invention provides a kind of preparation method of thin film transistor (TFT), and it includes following
Step.A grid is first formed on a substrate, and forms a gate insulator on grid, then on gate insulator sequentially
One first semiconductor layer and one second semiconductor layer are formed, wherein to be arranged at the second semiconductor layer exhausted with grid for the first semiconductor layer
Between edge layer.Then, a patterned insulation layer is formed on the second semiconductor layer, an erosion is used as followed by patterned insulation layer
Mask is carved, and the second semiconductor layer is carried out one first etching process to form one second patterned semiconductor layer.Then,
Patterned first semiconductor layer is to form one first patterned semiconductor layer, wherein the area of the first patterned semiconductor layer is more than
The area of second patterned semiconductor layer, and a drain electrode and a source electrode are formed on patterned insulation layer, wherein drain electrode and source
Pole is electrically connected with the first patterned semiconductor layer.
For up to above-mentioned purpose, another embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), under it includes
Row step.First form a grid on a substrate, then form a gate insulator on grid, then on gate insulator according to
Sequence one first semiconductor layer of formation and one second semiconductor layer, wherein the first semiconductor layer is arranged at the second semiconductor layer and grid
Between insulating barrier.Then, patterned first semiconductor layer and the second semiconductor layer with formed one first patterned semiconductor layer with
One second prepatterned semiconductor layer, then patterns interlayer dielectric layer in formation one on the second prepatterned semiconductor layer, its
There is middle patterning interlayer dielectric layer one first contact hole to contact hole with one second.Then, using pattern interlayer dielectric layer make
For an etching mask, and an etching process is carried out to the second prepatterned semiconductor layer partly led with forming one second patterning
There is body layer, the second patterned semiconductor layer one the 3rd contact hole to contact hole with one the 4th, wherein the first contact hole connects with the 3rd
Tactile hole is connected, and the second contact hole contacts hole with the 4th and is connected, and the area of the first patterned semiconductor layer is more than the second figure
The area of case semiconductor layer.Then, a drain electrode and a source electrode are formed on patterning interlayer dielectric layer, drain electrode is inserted with source electrode
First contact hole, the second contact hole, the 3rd contact hole contact in hole with the 4th and electrically connect the first patterned semiconductor layer.
Brief description of the drawings
Fig. 1 is the partial cutaway schematic view of the first embodiment of thin film transistor (TFT) of the present invention；
Fig. 2 to Fig. 4 is the manufacture craft schematic diagram of the first embodiment of the preparation method of thin film transistor (TFT) of the present invention；
Fig. 5 is the partial cutaway schematic view of the second embodiment of thin film transistor (TFT) of the present invention；
Fig. 6 to Fig. 8 is the manufacture craft schematic diagram of the second embodiment of the preparation method of thin film transistor (TFT) of the present invention.
Symbol description
1st, 2 thin film transistor (TFT)
100 substrates
102 grids
104 drain electrodes
106 source electrodes
108 gate insulators
110 first patterned semiconductor layers
112 second patterned semiconductor layers
114 patterned insulation layers
116 first semiconductor layers
118 second semiconductor layers
120th, 122 photoresist
124 patterning interlayer dielectric layers
126 second prepatterned semiconductor layers
128 first etching process
130 second etching process
132 etching process
V1 first contacts hole
V2 second contacts hole
V3 the 3rd contacts hole
V4 the 4th contacts hole
Z upright projections direction
Embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy enumerates
Presently preferred embodiments of the present invention, and coordinate appended diagram, describe thin film transistor (TFT) of the present invention and preparation method thereof and institute in detail
The effect to be reached.
Fig. 1 is refer to, it is the partial cutaway schematic view of the first embodiment of thin film transistor (TFT) of the present invention.The present embodiment
Thin film transistor (TFT) is not limited by taking the thin film transistor (TFT) that can be applied to display panel as an example.As shown in figure 1, the present embodiment
Thin film transistor (TFT) 1 include substrate 100, grid 102, drain electrode 104, source electrode 106, gate insulator 108, first patterning partly lead
The 110, second patterned semiconductor layer of body layer 112 and patterned insulation layer 114.Grid 102 is arranged on substrate 100, and grid
Insulating barrier 108 is arranged on grid 102 and complete covering grid 102.Substrate 100 may include such as glass substrate and ceramic substrate
Hard substrate, the flexible substrate (flexible substrate) of such as plastic substrate or other be adapted to materials and formed
Substrate, the substrate 100 of the present embodiment is by taking glass substrate as an example.Grid 102 is arranged at the patterned semiconductor layer of substrate 100 and first
Between 110, therefore thin film transistor (TFT) 1 is bottom gate thin film transistor.First patterned semiconductor layer 110 and the second patterning half
Conductor layer 112 is arranged on gate insulator 108, is partly led wherein the first patterned semiconductor layer 110 is arranged at the second patterning
Between body layer 112 and gate insulator 108.First patterned semiconductor layer 110 is with the second patterned semiconductor layer 112 in vertical
Overlapping with the grid 102 of part on projecting direction Z, wherein upright projection direction Z refers to the direction perpendicular to the surface of substrate 100.
The area of first patterned semiconductor layer 110 is more than the area of the second patterned semiconductor layer 112, therefore the second patterning is partly led
Body layer 112 exposes the two ends of the first patterned semiconductor layer 110.In the present embodiment, the first patterned semiconductor layer 110 is
Indium tin zinc oxide (ITZO), and the second patterned semiconductor layer 112 is indium gallium zinc (IGZO), wherein aluminic acid is to indium gallium
The etch-rate of zinc is very fast, and indium tin zinc oxide can aluminum-resistant etching solution (Al etchant), therefore the first patterned semiconductor layer
110 and second patterned semiconductor layer 112 for aluminium etching solution have high selection etching ratio, when using aluminium etching solution to the second figure
When case semiconductor layer 112 is etched, the first patterned semiconductor layer 110 can't be influenceed by aluminium etching solution, or by
Influence to aluminium etching solution is limited so that when being etched manufacture craft using aluminium etching night, can produce with different pattern
The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112.In addition, the oxygen of the first patterned semiconductor layer 110
Change resistance value of the resistance value less than the indium gallium zinc of the second patterned semiconductor layer 112 of indium tin zinc.In other words, the present embodiment
The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 except with high selection etching than in addition to, the first pattern
The resistance value for changing semiconductor layer 110 is less than the resistance value of the second patterned semiconductor layer 112.
In addition, the present embodiment the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 material not
It is limited with indium tin zinc oxide and indium gallium zinc.For example, the first patterned semiconductor layer 110 and the second patterned semiconductor layer
112 material may include indium tin zinc oxide, indium gallium zinc or other kinds of metal-oxide semiconductor (MOS), and first respectively
As long as the material selection of the patterned semiconductor layer 112 of patterned semiconductor layer 110 and second can meet above-mentioned first patterning
The patterned semiconductor layer 112 of semiconductor layer 110 and second has the condition of high selection etching ratio, and the first patterned semiconductor
Condition of the resistance value of layer 110 less than the resistance value of the second patterned semiconductor layer 112.In other alternate embodiments,
When the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 include the metal-oxide semiconductor (MOS) of identical type
During material, the first patterned semiconductor layer 110 can each have different crystal structures from the second patterned semiconductor layer 112,
Such as crystalline metal-oxide semiconductor layer and amorphous metal oxide semiconductor layer.For example, the first patterned semiconductor
Layer 110 can be crystallization indium tin zinc oxide and the second patterned semiconductor layer 112 is amorphous oxide indium tin zinc, but be not limited.
In the present embodiment, patterned insulation layer 114 is arranged in the second patterned semiconductor layer 112, wherein patterning
The patterned semiconductor layer 112 of insulating barrier 114 and second has substantially the same area and pattern, and patterned insulation layer 114
It is less than the area of the first patterned semiconductor layer 110 with the area of the second patterned semiconductor layer 112.In other words, pattern exhausted
First patterned semiconductor layer 110 of the patterned semiconductor layer 112 of edge layer 114 and second only covering part, and expose first
The two ends of patterned semiconductor layer 100.In addition, drain electrode 104 is arranged in the first patterned semiconductor layer 110 with source electrode 106, and
Electrically connected with the first patterned semiconductor layer 110, and drain electrode 104 and the electrically isolation each other of source electrode 106.Specifically, leak
Pole 104 is covered each by and directly contacted the top surface and side wall at the two ends of the first patterned semiconductor layer 110 with source electrode 106, drain electrode
104 separately extend and are arranged on patterned insulation layer 114 with source electrode 106, because the second patterned semiconductor layer 112 is patterned
Insulating barrier 114 is covered, therefore 104 top surface with source electrode 106 not with the second patterned semiconductor layer 112 of drain electrode is contacted.It is logical
The area for crossing the patterned semiconductor layer 112 of patterned insulation layer 114 and second is less than the area of the first patterned semiconductor layer 110
Design, drain electrode 104 directly can contact directly with source electrode 106 with the first patterned semiconductor layer 110 compared with low-resistance value,
Therefore the drain electrode 104 of the present embodiment can have relatively low contact resistance with source electrode 106.Due to the first patterned semiconductor layer 110
It is relatively near apart from grid 102, therefore the first patterned semiconductor layer 110 can be considered the prepass of thin film transistor (TFT) 1, and the second pattern
Change semiconductor layer 112 and can be considered back of the body passage.In addition, because the second patterned semiconductor layer 112 has higher resistance value, therefore
Back of the body passage can be reduced is influenceed the quantity of produced additional carriers by drain electrode 104, to reduce the critical electricity of thin film transistor (TFT) 1
The change amplitude of pressure.On the other hand, because the first patterned semiconductor layer 110 is relatively near from grid 102 and resistance value is compared with the second figure
Case semiconductor layer 112 is low, so carrier circulates in the first patterned semiconductor layer 110 mostly, and then it is brilliant to increase film
The control ability of the prepass of body pipe 1.
Fig. 2 to Fig. 4 is refer to, it shows for the manufacture craft of the first embodiment of the preparation method of thin film transistor (TFT) of the present invention
It is intended to.As shown in Fig. 2 according to the first embodiment of the present invention, substrate 100 being provided first, grid is formed on substrate 100
102, and in formation gate insulator 108 on grid 102.The mode of grid 102 is formed for example prior to forming whole face on substrate 100
Metal level (not shown), then patterning manufacture craft is carried out to metal level, for example, carries out photoetching and etching process, with
Grid 102 is formed on substrate 100.The material of above-mentioned metal level may include aluminium (aluminum), copper (copper), silver
(silver), chromium (chromium), titanium (titanium), the one or more of which of molybdenum (molybdenum), above-mentioned material
The alloy of composite bed or above-mentioned material, but be not limited thereto.The material of gate insulator 108 may include inorganic insulating material example
Such as silica, silicon nitride, silicon oxynitride, graphene oxide, nitridation graphene, nitrogen oxidation graphene, or organic insulation material
Material or organic/inorganic blend together insulating materials, and can be single layer structure or lamination layer structure, but are not limited.Then, in grid
First semiconductor layer 116 and the second semiconductor layer 118 in whole face are sequentially formed on insulating barrier 108, wherein the first semiconductor layer 116
It is arranged between the second semiconductor layer 118 and gate insulator 108.In the present embodiment, the first semiconductor layer 116 is indium oxide
Tin zinc (ITZO), and the second semiconductor layer 118 is indium gallium zinc (IGZO), but be not limited.First semiconductor layer 116 with
The material of second semiconductor layer 118 may include indium tin zinc oxide, indium gallium zinc or other kinds of metal oxide half respectively
Conductor, as long as and the first semiconductor layer 116 and the second semiconductor layer 118 material selection can cause the first semiconductor layer
116 and second semiconductor layer 118 there is high selection to etch compare, and the resistance value of the first semiconductor layer 116 is led less than the second half
The resistance value of body layer 118.In other alternate embodiments, the first semiconductor layer 116 can be included with the second semiconductor layer 118
The metal oxide semiconductor material of identical type, but each there is different crystal structures, such as the first semiconductor layer 116 is
It is amorphous oxide indium tin zinc to crystallize indium tin zinc oxide and the second semiconductor layer 118, but is not limited.
Then, patterned insulation layer 114 is formed on the second semiconductor layer 118.The method for forming patterned insulation layer 114
A layer insulating (not shown) for example is formed prior to whole face on the second semiconductor layer 118, photoresist 120 is reused and defines
The position of patterned insulation layer 114 to be formed, is then etched manufacture craft (such as dry ecthing manufacture craft) to produce
Patterned insulation layer 114.Photoresist 120 can use photoresist release agent after the formation of patterned insulation layer 114
(stripper) remove, but be not limited.The material of patterned insulation layer 114 may include that inorganic insulating material is for example aoxidized
Silicon, silicon nitride, silicon oxynitride, graphene oxide, nitridation graphene, nitrogen oxidation graphene etc., but be not limited.Patterning is exhausted
The material of edge layer 114 may also comprise organic insulation or organic/inorganic blendes together insulating materials, and can be single layer structure or compound
Rotating fields.In addition, the thickness of patterned insulation layer 114 is exemplified as about 500 angstroms, but it is not limited.
As shown in figure 3, followed by patterned insulation layer 114 as etching mask, and the second semiconductor layer 118 is carried out
First etching process 128 is to form the second patterned semiconductor layer 112.It is to be come using the first etching solution in the present embodiment
The first etching process 128 is carried out, and the first etching solution is aluminium etching solution, so the first etching process 128 is wet corrosion
Manufacture craft is carved, but is not limited.Because aluminium etching solution is very fast to the etch-rate of indium gallium zinc, and indium tin zinc oxide can
Aluminum-resistant etching solution, therefore in the first etching process 128, the second semiconductor layer 118 can be etched to form the second pattern
Change semiconductor layer 112, while the first semiconductor layer 116 is influenceed substantially without by the first etching solution.Further, since
It is directly to use patterned insulation layer 114 as etching mask in one etching process 128, therefore the second pattern formed
Changing semiconductor layer 112 has the pattern and area substantially the same with patterned insulation layer 114.In other words, the present embodiment is logical
Patterned insulation layer 114 is crossed to define the pattern of the second patterned semiconductor layer 112.
Partly led as shown in figure 4, then carrying out patterning manufacture craft to the first semiconductor layer 116 with forming the first patterning
Body layer 110.Patterning manufacture craft may be, for example, photoetching and etching process, first can whole face be coated with one layer of photoresist
Layer, then is intended to produce the first patterned semiconductor layer 110 to photoresist layer exposure using photomask to define
Position, then by being developed to the photoresist 122 of patterning, it has the first patterned semiconductor layer to be produced
110 pattern, then carries out the second etching process 130 to form the first patterned semiconductor layer 110 with the second etching solution,
Second etching solution of the present embodiment is oxalic acid, but is not limited.In the present embodiment, photoresist 122 is formed at second
The position of patterned semiconductor layer 112, and photoresist 112 has the area bigger than the second patterned semiconductor layer 112, and
The second patterned semiconductor layer 112 and patterned insulation layer 114 can be coated, but is not limited.Thus, made by the second etching
The area for making the first patterned semiconductor layer 110 that technique 130 is formed is more than the area of the second patterned semiconductor layer 112.
In addition, photoresist 122 can be removed after the formation of the first patterned semiconductor layer 110 using photoresist release agent, but
It is not limited.
Fig. 1 is refer again to, photoresist 122 is then removed, exposes and be not patterned the pattern of insulating barrier 114 and second
Change the two ends for the first patterned semiconductor layer 110 that semiconductor layer 112 is covered.Then, formed on patterned insulation layer 114
Drain electrode 104 and source electrode 106, wherein drain electrode 104 is also formed in the first patterned semiconductor layer 110 with source electrode 106 and covered respectively
Cover and be directly contacted with the top surface and side wall at the two ends of the first patterned semiconductor layer 110 so that the first patterned semiconductor layer
110 electrically connect with drain electrode 104 and source electrode 106.Further, since the second patterned semiconductor layer 112 is patterned the institute of insulating barrier 114
Cover, therefore 104 top surface with source electrode 106 not with the second patterned semiconductor layer 112 of drain electrode is contacted.Formed drain electrode 104 with
The method of source electrode 106 can be identical with forming the method for grid 102, but is not limited.The material of drain electrode 104 and source electrode 106 can
Including aluminium (aluminum), copper (copper), silver-colored (silver), chromium (chromium), titanium (titanium), molybdenum
(molybdenum) alloy of one or more of which, the composite bed of above-mentioned material or above-mentioned material, but be not limited thereto.
According to the present embodiment, due to being directly to use patterned insulation layer 114 as etching mask in the first etching process 128
To make the second patterned semiconductor layer 112, therefore compared to the preparation method of existing making bottom gate thin film transistor, this reality
Apply example and do not need extra photomask to make the first patterned semiconductor layer 110 for providing different pattern and area and
Two patterned semiconductor layers 112.
Thin film transistor (TFT) of the present invention and preparation method thereof is not limited with above-described embodiment.It will hereafter continue to disclose this hair
Bright other embodiments, so for the purpose of simplifying the description and are highlighted the difference between each embodiment, are hereinafter marked using identical label
Similar elements, and no longer counterweight is partly repeated again.
Fig. 5 is refer to, it is the partial cutaway schematic view of the second embodiment of thin film transistor (TFT) of the present invention.As shown in figure 5,
The place that the thin film transistor (TFT) 2 of the present embodiment is different from first embodiment is that thin film transistor (TFT) 2 includes patterning interlayer dielectric
Layer 124 is arranged in the second patterned semiconductor layer 112, and drain electrode 104 is arranged at patterning interlayer dielectric layer with source electrode 106
On 124.About 3000 angstroms of the thickness citing of the patterning interlayer dielectric layer 124 of the present embodiment, but be not limited.Patterned layer
Between dielectric layer 124 material can be organic dielectric materials or Inorganic Dielectric Material, and patterning interlayer dielectric layer 124 can be individual layer
Structure or lamination layer structure, associated materials may be selected from the material of patterned insulation layer 114 as the aforementioned, will not be repeated here.This
Outside, there is patterning interlayer dielectric layer 124 first contact hole V1 hole V2 is contacted with second, and the second patterned semiconductor layer 112 has
There is the 3rd contact hole V3 to contact hole V4 with the 4th, wherein the first contact hole V1 contacts hole V3 with the 3rd and is connected, the second contact hole
V2 contacts hole V4 with the 4th and is connected, and the 3rd contact hole V3 contacts hole V4 with the 4th and do not cover the first patterned semiconductor respectively
Two parts of 110 top surface of layer.In addition, source electrode 106 is also inserted in addition to being arranged on patterning interlayer dielectric layer 124 simultaneously
First contact hole V1 contacts hole V3 with the 3rd, and is directly contacted with the top surface of the first patterned semiconductor layer 110 of a part, and
Drain electrode 104 is in addition to being arranged on patterning interlayer dielectric layer 124, and also insert the second contact hole V2 contacts hole with the 4th simultaneously
V4, and directly contacted with the top surface of first patterned semiconductor layer 110 of another part.Due to second patterning of the present embodiment
Semiconductor layer 112 has contact hole, therefore the area of the second patterned semiconductor layer 112 is less than the first patterned semiconductor layer
110, and by the design of the present embodiment, drain electrode 104 can be directly with the first patterning with compared with low-resistance value partly with source electrode 106
Conductor layer 110 is directly contacted, therefore the drain electrode 104 of the present embodiment can have relatively low contact resistance with source electrode 106.The opposing party
Face, because thin film transistor (TFT) 2 has different the first patterned semiconductor layers 110 and the second patterned semiconductor layer of resistance value
112, therefore back of the body passage can be reduced 104 influenceed the quantity of produced additional carriers by drain electrode, to reduce thin film transistor (TFT) 2
Critical voltage change amplitude, and then increase the prepass of thin film transistor (TFT) 2 control ability.The thin film transistor (TFT) of the present embodiment
2 remaining feature is roughly the same with first embodiment, refers to the setting of Fig. 1 related elements and the narration of material, no longer goes to live in the household of one's in-laws on getting married herein
State.
Fig. 6 to Fig. 8 is refer to, it shows for the manufacture craft of the second embodiment of the preparation method of thin film transistor (TFT) of the present invention
It is intended to.As shown in fig. 6, the difference of second embodiment of the invention and first embodiment be in, formed the first semiconductor layer with
Second semiconductor layer (such as the first semiconductor layer 116 and the second semiconductor layer 118 shown in Fig. 2) is afterwards i.e. to the first semiconductor layer
Patterning manufacture craft is first carried out with the second semiconductor layer, to form the first patterned semiconductor layer 110 and the second prepatterned
Semiconductor layer 126.First patterned semiconductor layer 110 and the second prepatterned semiconductor layer 126 can be for example with photoetching and etchings
Manufacture craft is formed.For example, first semiconductor layer of the present embodiment is indium tin zinc oxide, and the second semiconductor layer is oxidation
Indium gallium zinc, and used etching solution includes oxalic acid, it can be etched to the first semiconductor layer and the second semiconductor layer simultaneously,
But it is not limited.As shown in fig. 7, then in formation patterning interlayer dielectric layer on the second prepatterned semiconductor layer 126
124, wherein there is patterning interlayer dielectric layer 124 first contact hole V1 to contact hole V2 with second.Form patterning interlayer dielectric
The mode of layer 124 for example first forms dielectric layer (not shown) by entire surface, then dielectric layer progress patterning manufacture craft (is for example entered
Row photoetching and etching process), contact hole V1 to form first in dielectric layer and contact hole V2 with second, but not as
Limit.
As shown in figure 8, followed by patterning interlayer dielectric layer 124 as etching mask, and to the second prepatterned half
Conductor layer 126 is etched manufacture craft 132 to form the second patterned semiconductor layer 112, wherein in etching process 132
Middle use aluminium etching solution patterns the second prepatterned semiconductor layer 126.After etching process 132, the second figure
There is case semiconductor layer 112 the 3rd contact hole V3 hole V4 is contacted with the 4th, wherein the first contact hole V1 contacts hole V3 with the 3rd
It is connected, the second contact hole V2 contacts hole V4 with the 4th and is connected, therefore the 3rd contact hole V3 contacts hole V4 with the 4th and exposed respectively
Expose two parts of the top surface of the first patterned semiconductor layer 110.Because second patterned semiconductor layer 112 of the present embodiment has
There is the 3rd contact hole V3 to contact hole V4 with the 4th, therefore the area of the first patterned semiconductor layer 110 is more than the second patterning half
The area of conductor layer 112.Please continue to refer to Fig. 5, then in formation drain electrode 104 and source electrode on patterning interlayer dielectric layer 124
106, drain electrode 104 inserts the second contact hole V2 and contacts hole V4 with the 4th and be electrically connected to the first patterned semiconductor layer 110, and source
Pole 106 inserts the first contact hole V1 and is contacted with the 3rd in the V3 of hole and be electrically connected to the first patterned semiconductor layer 110.It is another due to the
The top surface of one patterned semiconductor layer 110 has contacts two parts that hole V4 is exposed with the 4th by the 3rd contact hole V3, because
This drain electrode 104 via the second contact hole V2 can contact hole V4 with the 4th and with the first a part of patterned semiconductor layer 110
Top surface is directly contacted, and source electrode 106 via the first contact hole V1 can contact hole V3 with the 3rd and with first figure of another part
The top surface of case semiconductor layer 110 is directly contacted.According to the present embodiment, due to being directly to use in etching process 132
Interlayer dielectric layer 124 is patterned as etching mask, therefore compared to the preparation method of existing making bottom gate thin film transistor,
And do not need extra photomask to be formed with different area and the first patterned semiconductor layer 110 of pattern and the second figure
Case semiconductor layer 112.Other manufacture crafts of the preparation method of the thin film transistor (TFT) 2 of the present embodiment and condition and each element
Material can be substantially identical with first embodiment, will not be repeated here.
In summary, the second patterned semiconductor layer of thin film transistor (TFT) disclosed by the invention has higher resistance value,
Therefore back of the body passage, which can be reduced, is influenceed the quantity of produced additional carriers by drain electrode, to reduce the critical electricity of thin film transistor (TFT)
The change amplitude of pressure.On the other hand, due to the first patterned semiconductor layer from grid relatively near and resistance value compared with the second patterning partly
Conductor layer is low, so carrier circulates in the first patterned semiconductor layer mostly, and then can increase thin film transistor (TFT) prepass
Control ability.In addition, the preparation method of thin film transistor (TFT) disclosed by the invention, is forming the mistake of the second patterned semiconductor layer
It is directly to use patterned insulation layer or patterning interlayer dielectric layer as etching mask in journey, therefore is formed with different area
The first patterned semiconductor layer and the second patterned semiconductor layer, compared to the making of existing making bottom gate thin film transistor
Method does not simultaneously need extra photomask.
Presently preferred embodiments of the present invention is the foregoing is only, all equivalent changes done according to the claims in the present invention are with repairing
Decorations, should all belong to the covering scope of the present invention.
Claims (25)
1. a kind of thin film transistor (TFT), including：
Substrate；
Grid, is arranged on the substrate；
Gate insulator, is arranged on the grid；
First patterned semiconductor layer and the second patterned semiconductor layer, are arranged on the gate insulator, wherein the grid is set
It is placed between the substrate and first patterned semiconductor layer, first patterned semiconductor layer is arranged at second patterning half
Between conductor layer and the gate insulator, and the area of first patterned semiconductor layer is more than second patterned semiconductor layer
Area；And
Drain electrode and source electrode, are arranged in first patterned semiconductor layer, and electrically connected with first patterned semiconductor layer.
2. thin film transistor (TFT) as claimed in claim 1, separately including patterned insulation layer, is arranged at second patterned semiconductor
On layer, wherein the patterned insulation layer has substantially the same area with second patterned semiconductor layer.
3. thin film transistor (TFT) as claimed in claim 2, the wherein patterned insulation layer are sudden and violent with second patterned semiconductor layer
Expose the two ends of first patterned semiconductor layer.
4. thin film transistor (TFT) as claimed in claim 3, the wherein drain electrode are separately arranged on the patterned insulation layer with the source electrode,
The drain electrode directly contacts the top surface at the two ends of first patterned semiconductor layer with the source electrode respectively, and the drain electrode and the source electrode are not
Contact the top surface of second patterned semiconductor layer.
5. thin film transistor (TFT) as claimed in claim 1, another to include patterning interlayer dielectric layer, second patterning half is arranged at
In conductor layer, wherein there is the patterning interlayer dielectric layer the first contact hole to contact hole with second, second patterned semiconductor
There is layer the 3rd contact hole contact hole with the 4th, and the first contact hole contacts hole with the 3rd and is connected, this second contact hole and
4th contact hole is connected, and the 3rd contact hole contacts hole with the 4th and do not cover first patterned semiconductor layer.
6. thin film transistor (TFT) as claimed in claim 5, the wherein drain electrode are arranged at the patterning interlayer dielectric layer with the source electrode
Go up and insert the first contact hole, the second contact hole, the 3rd contact hole contacted with the 4th in hole and with first pattern
Change semiconductor layer contact.
7. thin film transistor (TFT) as claimed in claim 1, wherein first patterned semiconductor layer are partly led with second patterning
The material of body layer is partly led including indium tin zinc oxide (ITZO), indium gallium zinc (IGZO) or other kinds of metal oxide respectively
Body.
8. thin film transistor (TFT) as claimed in claim 7, the wherein resistance value of first patterned semiconductor layer less than this second
The resistance value of patterned semiconductor layer.
9. thin film transistor (TFT) as claimed in claim 7, wherein first patterned semiconductor layer are partly led with second patterning
Body layer includes identical material, but first patterned semiconductor layer is crystalline metal-oxide semiconductor layer and second pattern
Change semiconductor layer is amorphous metal oxide semiconductor layer.
10. a kind of preparation method of thin film transistor (TFT), comprises the following steps：
A grid is formed on a substrate；
A gate insulator is formed on the gate；
One first semiconductor layer and one second semiconductor layer are sequentially formed on the gate insulator, wherein first semiconductor layer
It is arranged between second semiconductor layer and the gate insulator；
A patterned insulation layer is formed on second semiconductor layer；
By the use of the patterned insulation layer as an etching mask, and one first etching process is carried out to second semiconductor layer
To form one second patterned semiconductor layer；
Pattern first semiconductor layer to form one first patterned semiconductor layer, wherein first patterned semiconductor layer
Area is more than the area of second patterned semiconductor layer；And
A drain electrode and a source electrode are formed on the patterned insulation layer, the wherein drain electrode is partly led with the source electrode with first patterning
Body layer electrical connection.
11. the preparation method of thin film transistor (TFT) as claimed in claim 10, the wherein patterned insulation layer and second pattern
Changing semiconductor layer has substantially the same area.
12. the preparation method of thin film transistor (TFT) as claimed in claim 11, the wherein patterned insulation layer and second pattern
Change the two ends that semiconductor layer exposes first patterned semiconductor layer.
13. the preparation method of thin film transistor (TFT) as claimed in claim 12, the wherein drain electrode are directly contacted respectively with the source electrode
The top surface at the two ends of first patterned semiconductor layer, and the drain electrode and the source electrode are not in contact with second patterned semiconductor layer
Top surface.
14. the preparation method of thin film transistor (TFT) as claimed in claim 10, wherein first etching process including the use of
One first etching solution is carried out, and first etching solution includes aluminium etching solution (Al etchant).
15. the preparation method of thin film transistor (TFT) as claimed in claim 10, wherein in the patterning first semiconductor layer
One second etching process that step is carried out including the use of one second etching solution, and second etching solution includes oxalic acid.
16. the preparation method of thin film transistor (TFT) as claimed in claim 10, wherein first patterned semiconductor layer with this
The material of two patterned semiconductor layers includes indium tin zinc oxide (ITZO), indium gallium zinc (IGZO) or other kinds of gold respectively
Belong to oxide semiconductor.
17. thin film transistor (TFT) as claimed in claim 16, the wherein resistance value of first patterned semiconductor layer less than this
The resistance value of two patterned semiconductor layers.
18. thin film transistor (TFT) as claimed in claim 16, wherein first patterned semiconductor layer and second patterning half
Conductor layer includes identical material, but first patterned semiconductor layer is crystalline metal-oxide semiconductor layer and second figure
Case semiconductor layer is amorphous metal oxide semiconductor layer.
19. a kind of preparation method of thin film transistor (TFT), comprises the following steps：
A grid is formed on a substrate；
A gate insulator is formed on the gate；
One first semiconductor layer and one second semiconductor layer are sequentially formed on the gate insulator, wherein first semiconductor layer
It is arranged between second semiconductor layer and the gate insulator；
First semiconductor layer is patterned with second semiconductor layer to form one first patterned semiconductor layer and one second pre-
Patterned semiconductor layer；
One is formed on the second prepatterned semiconductor layer and patterns interlayer dielectric layer, the wherein patterning interlayer dielectric layer has
There is one first contact hole to contact hole with one second；
By the use of the patterning interlayer dielectric layer as an etching mask, and an etching is carried out to the second prepatterned semiconductor layer
Manufacture craft is to form one second patterned semiconductor layer, and second patterned semiconductor layer has one the 3rd contact hole and one the
Four contact holes, wherein the first contact hole contact hole with the 3rd and are connected, and the second contact hole contacts hole with the 4th and is connected
It is logical, and area of the area more than second patterned semiconductor layer of first patterned semiconductor layer；And
Form a drain electrode and a source electrode on the patterning interlayer dielectric layer, the drain electrode and the source electrode insert this first contact hole,
The second contact hole, the 3rd contact hole contact in hole with the 4th and electrically connect first patterned semiconductor layer.
20. the preparation method of thin film transistor (TFT) as claimed in claim 19, the wherein the 3rd contact hole contacts hole with the 4th
Do not cover first patterned semiconductor layer, and the drain electrode and the source electrode respectively via this first contact hole, the second contact hole,
3rd contact hole contacts hole with the 4th and directly contacted with first patterned semiconductor layer.
21. the preparation method of thin film transistor (TFT) as claimed in claim 19, the wherein etching process are lost including the use of aluminium
Liquid (Al etchant) is carved to pattern the second prepatterned semiconductor layer.
22. the preparation method of thin film transistor (TFT) as claimed in claim 19, wherein in the patterning first semiconductor layer with
The step of second semiconductor layer, is used as etching solution including the use of oxalic acid.
23. the preparation method of thin film transistor (TFT) as claimed in claim 19, wherein first patterned semiconductor layer with this
The material of two patterned semiconductor layers includes indium tin zinc oxide (ITZO), indium gallium zinc (IGZO) or other kinds of gold respectively
Belong to oxide semiconductor.
24. thin film transistor (TFT) as claimed in claim 23, the wherein resistance value of first patterned semiconductor layer less than this
The resistance value of two patterned semiconductor layers.
25. thin film transistor (TFT) as claimed in claim 23, wherein first patterned semiconductor layer and second patterning half
Conductor layer includes identical material, but first patterned semiconductor layer is crystalline metal-oxide semiconductor layer and second figure
Case semiconductor layer is amorphous metal oxide semiconductor layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105128844A TWI609496B (en) | 2016-09-07 | 2016-09-07 | Thin film transistor and manufacturing method thereof |
| TW105128844 | 2016-09-07 |
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| CN106997903A true CN106997903A (en) | 2017-08-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054102A (en) * | 2017-11-13 | 2018-05-18 | 友达光电股份有限公司 | Pixel structure, manufacturing method of semiconductor structure and manufacturing method of semiconductor element |
| WO2020088368A1 (en) * | 2018-10-29 | 2020-05-07 | 京东方科技集团股份有限公司 | Thin film transistor and fabrication method therefor, array substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010073881A (en) * | 2008-09-18 | 2010-04-02 | Fujifilm Corp | Thin-film field-effect transistor, and display device using the same |
| CN102751240A (en) * | 2012-05-18 | 2012-10-24 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
| TW201436231A (en) * | 2012-12-28 | 2014-09-16 | Idemitsu Kosan Co | Thin film field effect transistor |
-
2016
- 2016-09-07 TW TW105128844A patent/TWI609496B/en not_active IP Right Cessation
- 2016-11-03 CN CN201610974692.9A patent/CN106997903A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010073881A (en) * | 2008-09-18 | 2010-04-02 | Fujifilm Corp | Thin-film field-effect transistor, and display device using the same |
| CN102751240A (en) * | 2012-05-18 | 2012-10-24 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
| TW201436231A (en) * | 2012-12-28 | 2014-09-16 | Idemitsu Kosan Co | Thin film field effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054102A (en) * | 2017-11-13 | 2018-05-18 | 友达光电股份有限公司 | Pixel structure, manufacturing method of semiconductor structure and manufacturing method of semiconductor element |
| WO2020088368A1 (en) * | 2018-10-29 | 2020-05-07 | 京东方科技集团股份有限公司 | Thin film transistor and fabrication method therefor, array substrate and display device |
| US11244965B2 (en) | 2018-10-29 | 2022-02-08 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Thin film transistor and manufacturing method therefor, array substrate and display device |
Also Published As
| Publication number | Publication date |
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| TWI609496B (en) | 2017-12-21 |
| TW201810682A (en) | 2018-03-16 |
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