TW201810682A - Thin film transistor and manufacturing method thereof - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 321
- 239000010410 layer Substances 0.000 claims description 414
- 238000000034 method Methods 0.000 claims description 67
- 238000005530 etching Methods 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 31
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 24
- 229910044991 metal oxide Inorganic materials 0.000 claims description 16
- 150000004706 metal oxides Chemical class 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 12
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 12
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
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- 238000012986 modification Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
本發明係關於一種薄膜電晶體及其製作方法，尤指一種具有兩層不同電阻值之圖案化半導體層的薄膜電晶體及其製作方法。The invention relates to a thin film transistor and a manufacturing method thereof, in particular to a thin film transistor having two patterned semiconductor layers with different resistance values and a manufacturing method thereof.
近年來，各種平面顯示器之應用發展迅速，各類生活用品例如電視、行動電話、汽機車、甚至是冰箱，都可見與平面顯示器互相結合之應用。在平面顯示器技術中，薄膜電晶體(thin film transistor, TFT)係一種被廣泛應用之半導體元件，例如應用在液晶顯示器(liquid crystal display, LCD)、有機發光二極體(organic light emitting diode, OLED)顯示器及電子紙(electronic paper, E-paper)等平面顯示器中。薄膜電晶體係利用來提供電壓或電流的切換，以使得各種顯示器中的顯示畫素可呈現出亮、暗以及灰階的顯示效果。In recent years, the application of various flat-panel displays has developed rapidly, and various daily necessities such as televisions, mobile phones, automobiles, and even refrigerators have seen the application of the combination of flat-panel displays. In flat-panel display technology, thin film transistor (TFT) is a widely used semiconductor element, such as liquid crystal display (LCD), organic light emitting diode (OLED) ) Displays and flat displays such as electronic paper (e-paper). The thin film transistor system is used to provide voltage or current switching, so that the display pixels in various displays can display bright, dark and grayscale display effects.
目前顯示器業界使用之薄膜電晶體可根據使用之半導體層材料來做區分，包括非晶矽薄膜電晶體(amorphous silicon TFT, a-Si TFT)、多晶矽薄膜電晶體(poly silicon TFT)以及氧化物半導體薄膜電晶體(metal oxide semiconductor TFT)。相較於多晶矽薄膜電晶體，氧化物半導體薄膜電晶體具有電子遷移率較高以及製程較簡化等優點，故被視為有機會可取代目前主流之非晶矽薄膜電晶體。然而，在底閘型薄膜電晶體中，由於半導體層中的背通道(back channel)較靠近汲極，因此當施加電壓至汲極時會使得背通道的區域產生額外的載子，並會造成薄膜電晶體的臨界電壓(threshold voltage)改變，進而減少半導體層中靠近閘極之前通道(front channel)的控制能力，使得控制薄膜電晶體的難度上升。The thin film transistors currently used in the display industry can be differentiated according to the semiconductor layer materials used, including amorphous silicon TFTs (a-Si TFTs), poly silicon TFTs (poly silicon TFTs), and oxide semiconductors. Thin film transistor (metal oxide semiconductor TFT). Compared with polycrystalline silicon thin film transistors, oxide semiconductor thin film transistors have the advantages of higher electron mobility and simpler manufacturing processes, so they are considered to have the opportunity to replace the mainstream amorphous silicon thin film transistors. However, in a bottom-gate thin-film transistor, since the back channel in the semiconductor layer is closer to the drain, when a voltage is applied to the drain, additional carriers will be generated in the back channel region, and it will cause The threshold voltage of the thin film transistor is changed, thereby reducing the control capability of the front channel in the semiconductor layer close to the gate, making it difficult to control the thin film transistor.
本發明之主要目的之一在於提供一種薄膜電晶體及其製作方法，藉由設置兩層具有不同電阻值之圖案化半導體層，以避免臨界電壓改變的問題發生。One of the main objects of the present invention is to provide a thin film transistor and a method for manufacturing the same. By providing two patterned semiconductor layers with different resistance values, the problem of changing the threshold voltage can be avoided.
為達上述目的，本發明之一實施例提供一種薄膜電晶體，其包括一基板、一閘極、一汲極、一源極、一閘極絕緣層、一第一圖案化半導體層與一第二圖案化半導體層。閘極設置於基板上，且閘極絕緣層設置於閘極上。第一圖案化半導體層與第二圖案化半導體層設置於閘極絕緣層上，其中閘極設置於基板與第一圖案化半導體層之間，第一圖案化半導體層設置於第二圖案化半導體層與閘極絕緣層之間，且第一圖案化半導體層的面積大於第二圖案化半導體層的面積。汲極與源極設置於第一圖案化半導體層上，並與第一圖案化半導體層電性連接。To achieve the above object, an embodiment of the present invention provides a thin film transistor, which includes a substrate, a gate, a drain, a source, a gate insulating layer, a first patterned semiconductor layer, and a first Two patterned semiconductor layers. The gate is disposed on the substrate, and the gate insulation layer is disposed on the gate. The first patterned semiconductor layer and the second patterned semiconductor layer are disposed on the gate insulating layer, wherein the gate is disposed between the substrate and the first patterned semiconductor layer, and the first patterned semiconductor layer is disposed on the second patterned semiconductor. Between the layer and the gate insulating layer, and an area of the first patterned semiconductor layer is larger than an area of the second patterned semiconductor layer. The drain and source are disposed on the first patterned semiconductor layer and are electrically connected to the first patterned semiconductor layer.
為達上述目的，本發明之一實施例提供一種薄膜電晶體的製作方法，其包括下列步驟。先於一基板上形成一閘極，並於閘極上形成一閘極絕緣層，接著於閘極絕緣層上依序形成一第一半導體層與一第二半導體層，其中第一半導體層設置於第二半導體層與閘極絕緣層之間。然後，於第二半導體層上形成一圖案化絕緣層，接著利用圖案化絕緣層作為一蝕刻遮罩，並對第二半導體層進行一第一蝕刻製程以形成一第二圖案化半導體層。然後，圖案化第一半導體層以形成一第一圖案化半導體層，其中第一圖案化半導體層的面積大於第二圖案化半導體層的面積，以及於圖案化絕緣層上形成一汲極與一源極，其中汲極與源極與第一圖案化半導體層電性連接。To achieve the above object, an embodiment of the present invention provides a method for manufacturing a thin film transistor, which includes the following steps. A gate is formed on a substrate, a gate insulating layer is formed on the gate, and then a first semiconductor layer and a second semiconductor layer are sequentially formed on the gate insulating layer. The first semiconductor layer is disposed on Between the second semiconductor layer and the gate insulating layer. Then, a patterned insulating layer is formed on the second semiconductor layer, and then the patterned insulating layer is used as an etching mask, and a second etching process is performed on the second semiconductor layer to form a second patterned semiconductor layer. Then, the first semiconductor layer is patterned to form a first patterned semiconductor layer, wherein the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer, and a drain electrode and a drain electrode are formed on the patterned insulating layer. The source, wherein the drain and the source are electrically connected to the first patterned semiconductor layer.
為達上述目的，本發明之另一實施例提供一種薄膜電晶體的製作方法，其包括下列步驟。先於一基板上形成一閘極，接著於閘極上形成一閘極絕緣層，再於閘極絕緣層上依序形成一第一半導體層與一第二半導體層，其中第一半導體層設置於第二半導體層與閘極絕緣層之間。然後，圖案化第一半導體層與第二半導體層以形成一第一圖案化半導體層與一第二預圖案化半導體層，接著於第二預圖案化半導體層上形成一圖案化層間介電層，其中圖案化層間介電層具有一第一接觸洞與一第二接觸洞。然後，利用圖案化層間介電層作為一蝕刻遮罩，並對第二預圖案化半導體層進行一蝕刻製程以形成一第二圖案化半導體層，第二圖案化半導體層具有一第三接觸洞與一第四接觸洞，其中第一接觸洞與第三接觸洞相連通，第二接觸洞與第四接觸洞相連通，且第一圖案化半導體層的面積大於第二圖案化半導體層的面積。接著，於圖案化層間介電層上形成一汲極與一源極，汲極與源極填入第一接觸洞、第二接觸洞、第三接觸洞與第四接觸洞中而電性連接第一圖案化半導體層。To achieve the above object, another embodiment of the present invention provides a method for manufacturing a thin film transistor, which includes the following steps. A gate is formed on a substrate, a gate insulating layer is formed on the gate, and a first semiconductor layer and a second semiconductor layer are sequentially formed on the gate insulating layer. The first semiconductor layer is disposed on Between the second semiconductor layer and the gate insulating layer. Then, the first semiconductor layer and the second semiconductor layer are patterned to form a first patterned semiconductor layer and a second pre-patterned semiconductor layer, and then a patterned interlayer dielectric layer is formed on the second pre-patterned semiconductor layer. The patterned interlayer dielectric layer has a first contact hole and a second contact hole. Then, the patterned interlayer dielectric layer is used as an etching mask, and an etching process is performed on the second pre-patterned semiconductor layer to form a second patterned semiconductor layer. The second patterned semiconductor layer has a third contact hole. And a fourth contact hole, wherein the first contact hole is in communication with the third contact hole, the second contact hole is in communication with the fourth contact hole, and the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer . Next, a drain electrode and a source electrode are formed on the patterned interlayer dielectric layer, and the drain electrode and the source electrode are filled in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole to be electrically connected. The first patterned semiconductor layer.
為使熟習本發明所屬技術領域之一般技藝者能更進一步瞭解本發明，下文特列舉本發明之較佳實施例，並配合所附圖示，詳細說明本發明的薄膜電晶體及其製作方法及所欲達成的功效。In order to make a person skilled in the art in the technical field to further understand the present invention, the preferred embodiments of the present invention are enumerated below, and the accompanying drawings are used to describe the thin film transistor of the present invention and its manufacturing method and The desired effect.
請參考第1圖，其為本發明薄膜電晶體之第一實施例的部分剖面示意圖。本實施例的薄膜電晶體係以可應用於顯示面板之薄膜電晶體為例，但不以此為限。如第1圖所示，本實施例的薄膜電晶體1包括基板100、閘極102、汲極104、源極106、閘極絕緣層108、第一圖案化半導體層110、第二圖案化半導體層112與圖案化絕緣層114。閘極102設置於基板100上，而閘極絕緣層108設置於閘極102上且完整覆蓋閘極102。基板100可包括例如玻璃基板與陶瓷基板之硬質基板、例如塑膠基板之可撓式基板(flexible substrate)或其他適合材料所形成之基板，本實施例之基板100係以玻璃基板為例。閘極102設置於基板100與第一圖案化半導體層110之間，因此薄膜電晶體1為底閘型薄膜電晶體。第一圖案化半導體層110與第二圖案化半導體層112設置於閘極絕緣層108上，其中第一圖案化半導體層110設置於第二圖案化半導體層112與閘極絕緣層108之間。第一圖案化半導體層110與第二圖案化半導體層112於垂直投影方向Z上與部分的閘極102重疊，其中垂直投影方向Z係指垂直於基板100表面的方向。第一圖案化半導體層110的面積大於第二圖案化半導體層112的面積，因此第二圖案化半導體層112暴露出第一圖案化半導體層110之兩端。在本實施例中，第一圖案化半導體層110為氧化銦錫鋅(ITZO)，而第二圖案化半導體層112為氧化銦鎵鋅(IGZO)，其中鋁酸對氧化銦鎵鋅的蝕刻速率較快，而氧化銦錫鋅可抗鋁蝕刻液(Al etchant)，因此第一圖案化半導體層110與第二圖案化半導體層112對於鋁蝕刻液具有高選擇蝕刻比，當使用鋁蝕刻液對第二圖案化半導體層112進行蝕刻時，第一圖案化半導體層110並不會受鋁蝕刻液的影響，或是受到鋁蝕刻液的影響有限，使得使用鋁蝕刻夜進行蝕刻製程時，可製作出具有不同圖案的第一圖案化半導體層110與第二圖案化半導體層112。此外，第一圖案化半導體層110的氧化銦錫鋅的電阻值低於第二圖案化半導體層112的氧化銦鎵鋅的電阻值。換言之，本實施例的第一圖案化半導體層110與第二圖案化半導體層112除了具有高選擇蝕刻比外，第一圖案化半導體層110的電阻值是低於第二圖案化半導體層112的電阻值。Please refer to FIG. 1, which is a schematic partial cross-sectional view of a first embodiment of a thin film transistor of the present invention. The thin film transistor system of this embodiment is exemplified by a thin film transistor that can be applied to a display panel, but is not limited thereto. As shown in FIG. 1, the thin film transistor 1 of this embodiment includes a substrate 100, a gate 102, a drain 104, a source 106, a gate insulating layer 108, a first patterned semiconductor layer 110, and a second patterned semiconductor. The layer 112 and the patterned insulating layer 114. The gate electrode 102 is disposed on the substrate 100, and the gate insulation layer 108 is disposed on the gate electrode 102 and completely covers the gate electrode 102. The substrate 100 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate, or a substrate formed of other suitable materials. The substrate 100 in this embodiment is a glass substrate as an example. The gate electrode 102 is disposed between the substrate 100 and the first patterned semiconductor layer 110, so the thin film transistor 1 is a bottom gate type thin film transistor. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 are disposed on the gate insulating layer 108, and the first patterned semiconductor layer 110 is disposed between the second patterned semiconductor layer 112 and the gate insulating layer 108. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 overlap part of the gate electrode 102 in a vertical projection direction Z, where the vertical projection direction Z refers to a direction perpendicular to the surface of the substrate 100. The area of the first patterned semiconductor layer 110 is larger than the area of the second patterned semiconductor layer 112, so the second patterned semiconductor layer 112 exposes both ends of the first patterned semiconductor layer 110. In this embodiment, the first patterned semiconductor layer 110 is indium tin zinc oxide (ITZO), and the second patterned semiconductor layer 112 is indium gallium zinc oxide (IGZO). The etching rate of indium gallium zinc oxide by aluminate It is faster, and indium tin zinc oxide is resistant to aluminum etchant. Therefore, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have a high selective etching ratio for the aluminum etchant. When the second patterned semiconductor layer 112 is etched, the first patterned semiconductor layer 110 is not affected by the aluminum etching solution, or is limited by the aluminum etching solution. When the aluminum pattern is used for the etching process, it can be produced. A first patterned semiconductor layer 110 and a second patterned semiconductor layer 112 having different patterns are obtained. In addition, the resistance value of the indium tin zinc oxide of the first patterned semiconductor layer 110 is lower than the resistance value of the indium gallium zinc oxide of the second patterned semiconductor layer 112. In other words, in addition to the high selective etching ratio of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 in this embodiment, the resistance value of the first patterned semiconductor layer 110 is lower than that of the second patterned semiconductor layer 112. resistance.
此外，本實施例之第一圖案化半導體層110與第二圖案化半導體層112的材料並不以氧化銦錫鋅及氧化銦鎵鋅為限。例如，第一圖案化半導體層110與第二圖案化半導體層112的材料分別可包括氧化銦錫鋅、氧化銦鎵鋅或其他種類的金屬氧化物半導體，並且第一圖案化半導體層110與第二圖案化半導體層112的材料選擇只要可以符合上述第一圖案化半導體層110與第二圖案化半導體層112具有高選擇蝕刻比的條件，以及第一圖案化半導體層110的電阻值低於第二圖案化半導體層112的電阻值的條件即可。在其他變化實施例中，當第一圖案化半導體層110與第二圖案化半導體層112包含相同種類的金屬氧化物半導體材料時，第一圖案化半導體層110與第二圖案化半導體層112可各自具有不同的晶體結構，例如結晶金屬氧化物半導體層及非晶金屬氧化物半導體層。舉例而言，第一圖案化半導體層110可為結晶氧化銦錫鋅而第二圖案化半導體層112為非晶氧化銦錫鋅，但不以此為限。In addition, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 in this embodiment are not limited to indium tin zinc oxide and indium gallium zinc oxide. For example, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 may include indium tin zinc oxide, indium gallium zinc oxide, or other types of metal oxide semiconductors, and the first patterned semiconductor layer 110 and the first As long as the material selection of the two patterned semiconductor layers 112 can meet the conditions that the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have a high selective etching ratio, and the resistance value of the first patterned semiconductor layer 110 is lower than that of the first patterned semiconductor layer 110, The conditions of the resistance value of the two patterned semiconductor layers 112 may be sufficient. In other variant embodiments, when the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 include the same kind of metal oxide semiconductor material, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 may be Each has a different crystal structure, such as a crystalline metal oxide semiconductor layer and an amorphous metal oxide semiconductor layer. For example, the first patterned semiconductor layer 110 may be a crystalline indium tin oxide and the second patterned semiconductor layer 112 is an amorphous indium tin zinc oxide, but is not limited thereto.
在本實施例中，圖案化絕緣層114設置於第二圖案化半導體層112上，其中圖案化絕緣層114與第二圖案化半導體層112具有實質上相同的面積與圖案，而圖案化絕緣層114與第二圖案化半導體層112的面積小於第一圖案化半導體層110的面積。換言之，圖案化絕緣層114與第二圖案化半導體層112僅覆蓋部分的第一圖案化半導體層110，並暴露出第一圖案化半導體層100的兩端。此外，汲極104與源極106設置於第一圖案化半導體層110上，並與第一圖案化半導體層110電性連接，且汲極104與源極106彼此之間電性隔絕。詳細而言，汲極104與源極106分別覆蓋並直接接觸第一圖案化半導體層110之兩端的頂面及側壁，汲極104與源極106另延伸並設置於圖案化絕緣層114上，由於第二圖案化半導體層112被圖案化絕緣層114所覆蓋，因此汲極104與源極106並未與第二圖案化半導體層112的頂面接觸。藉由圖案化絕緣層114與第二圖案化半導體層112的面積小於第一圖案化半導體層110的面積的設計，汲極104與源極106可直接與具有較低電阻值的第一圖案化半導體層110直接接觸，因此本實施例的汲極104與源極106可具有較低的接觸電阻。由於第一圖案化半導體層110距離閘極102較近，因此第一圖案化半導體層110可視為薄膜電晶體1之前通道，而第二圖案化半導體層112可視為背通道。此外，因為第二圖案化半導體層112具有較高的電阻值，因此可以減少背通道受汲極104影響所產生的額外載子的數量，以降低薄膜電晶體1之臨界電壓的改變幅度。另一方面，由於第一圖案化半導體層110離閘極102較近且電阻值較第二圖案化半導體層112低，所以載子大多在第一圖案化半導體層110裡流通，進而增加薄膜電晶體1前通道的控制能力。In this embodiment, the patterned insulating layer 114 is disposed on the second patterned semiconductor layer 112, wherein the patterned insulating layer 114 and the second patterned semiconductor layer 112 have substantially the same area and pattern, and the patterned insulating layer The areas of 114 and the second patterned semiconductor layer 112 are smaller than the areas of the first patterned semiconductor layer 110. In other words, the patterned insulating layer 114 and the second patterned semiconductor layer 112 only cover a part of the first patterned semiconductor layer 110 and expose both ends of the first patterned semiconductor layer 100. In addition, the drain 104 and the source 106 are disposed on the first patterned semiconductor layer 110 and are electrically connected to the first patterned semiconductor layer 110, and the drain 104 and the source 106 are electrically isolated from each other. In detail, the drain electrode 104 and the source electrode 106 respectively cover and directly contact the top surface and the sidewall of both ends of the first patterned semiconductor layer 110, and the drain electrode 104 and the source electrode 106 are further extended and disposed on the patterned insulating layer 114. Since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114, the drain 104 and the source 106 are not in contact with the top surface of the second patterned semiconductor layer 112. By designing that the area of the patterned insulating layer 114 and the second patterned semiconductor layer 112 is smaller than the area of the first patterned semiconductor layer 110, the drain 104 and the source 106 can be directly patterned with the first pattern having a lower resistance value. The semiconductor layer 110 is in direct contact, so the drain 104 and the source 106 of this embodiment may have a lower contact resistance. Since the first patterned semiconductor layer 110 is closer to the gate 102, the first patterned semiconductor layer 110 can be regarded as a front channel of the thin film transistor 1, and the second patterned semiconductor layer 112 can be regarded as a back channel. In addition, because the second patterned semiconductor layer 112 has a higher resistance value, the number of extra carriers generated by the back channel affected by the drain 104 can be reduced, so as to reduce the variation range of the threshold voltage of the thin film transistor 1. On the other hand, since the first patterned semiconductor layer 110 is closer to the gate electrode 102 and has a lower resistance value than the second patterned semiconductor layer 112, most of the carriers circulate in the first patterned semiconductor layer 110, thereby increasing the thin-film electricity. Control ability of front channel of crystal 1.
請參考第2圖至第4圖，其為本發明薄膜電晶體之製作方法之第一實施例的製程示意圖。如第2圖所示，根據本發明之第一實施例，首先提供基板100，再於基板100上形成閘極102，並於閘極102上形成閘極絕緣層108。形成閘極102的方式例如先於基板100上形成整面的金屬層(圖未示)，再對金屬層進行圖案化製程，例如進行微影暨蝕刻製程，以於基板100上形成閘極102。上述金屬層之材料可包括鋁(aluminum)、銅(copper)、銀(silver)、鉻(chromium)、鈦(titanium)、鉬(molybdenum)之其中一種或多種、上述材料之複合層或上述材料之合金，但並不以此為限。閘極絕緣層108的材料可包括無機絕緣材料例如氧化矽、氮化矽、氮氧化矽、氧化石墨烯、氮化石墨烯、氮氧化石墨烯等，或是有機絕緣材料或有機/無機混成絕緣材料，並可為單層結構或複合層結構，但不以此為限。接著，於閘極絕緣層108上依序形成整面的第一半導體層116與第二半導體層118，其中第一半導體層116設置於第二半導體層118與閘極絕緣層108之間。在本實施例中，第一半導體層116為氧化銦錫鋅(ITZO)，而第二半導體層118為氧化銦鎵鋅(IGZO)，但不以此為限。第一半導體層116與第二半導體層118的材料分別可包括氧化銦錫鋅、氧化銦鎵鋅或其他種類的金屬氧化物半導體，並且第一半導體層116與第二半導體層118的材料選擇只要可以使得第一半導體層116與第二半導體層118具有高選擇蝕刻比，以及第一半導體層116的電阻值低於第二半導體層118的電阻值即可。在其他變化實施例中，第一半導體層116與第二半導體層118可包含相同種類的金屬氧化物半導體材料，但各自具有不同的晶體結構，例如第一半導體層116為結晶氧化銦錫鋅而第二半導體層118為非晶氧化銦錫鋅，但不以此為限。Please refer to FIG. 2 to FIG. 4, which are process schematic diagrams of a first embodiment of a method for manufacturing a thin film transistor of the present invention. As shown in FIG. 2, according to a first embodiment of the present invention, a substrate 100 is first provided, a gate electrode 102 is formed on the substrate 100, and a gate insulating layer 108 is formed on the gate electrode 102. The method of forming the gate electrode 102 is, for example, forming a metal layer (not shown) on the entire surface of the substrate 100, and then performing a patterning process on the metal layer, such as a lithography and etching process, to form the gate electrode 102 on the substrate 100. . The material of the metal layer may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, a composite layer of the above materials, or the above materials Alloy, but not limited to this. The material of the gate insulating layer 108 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, graphene oxide, graphene nitride, graphene oxynitride, or the like, or an organic insulating material or an organic / inorganic hybrid insulating material. The material can be a single layer structure or a composite layer structure, but it is not limited thereto. Next, the entire first semiconductor layer 116 and the second semiconductor layer 118 are sequentially formed on the gate insulating layer 108, and the first semiconductor layer 116 is disposed between the second semiconductor layer 118 and the gate insulating layer 108. In this embodiment, the first semiconductor layer 116 is indium tin zinc oxide (ITZO), and the second semiconductor layer 118 is indium gallium zinc oxide (IGZO), but not limited thereto. The materials of the first semiconductor layer 116 and the second semiconductor layer 118 may include indium tin zinc oxide, indium gallium zinc oxide, or other types of metal oxide semiconductors, and the materials of the first semiconductor layer 116 and the second semiconductor layer 118 may be selected as long as The first semiconductor layer 116 and the second semiconductor layer 118 may have a high selective etching ratio, and the resistance value of the first semiconductor layer 116 may be lower than that of the second semiconductor layer 118. In other modified embodiments, the first semiconductor layer 116 and the second semiconductor layer 118 may include the same kind of metal oxide semiconductor material, but each have a different crystal structure. For example, the first semiconductor layer 116 is crystalline indium tin oxide and The second semiconductor layer 118 is an amorphous indium tin oxide, but is not limited thereto.
然後，於第二半導體層118上形成圖案化絕緣層114。形成圖案化絕緣層114的方法例如先於第二半導體層118上整面形成一層絕緣層(圖未示)，再使用光阻120定義出欲形成圖案化絕緣層114的位置，接著進行蝕刻製程(例如乾蝕刻製程)以製作出圖案化絕緣層114。光阻120可在圖案化絕緣層114形成後使用光阻剝離劑(stripper)去除，但不以此為限。圖案化絕緣層114的材料可包括無機絕緣材料例如氧化矽、氮化矽、氮氧化矽、氧化石墨烯、氮化石墨烯、氮氧化石墨烯等，但不以此為限。圖案化絕緣層114的材料也可包括有機絕緣材料或有機/無機混成絕緣材料，並可為單層結構或複合層結構。此外，圖案化絕緣層114的厚度舉例為約500埃，但不以此為限。Then, a patterned insulating layer 114 is formed on the second semiconductor layer 118. The method for forming the patterned insulating layer 114 is, for example, forming an insulating layer (not shown) on the entire surface of the second semiconductor layer 118, and then using a photoresist 120 to define a position where the patterned insulating layer 114 is to be formed, and then performing an etching process. (Eg, a dry etching process) to form a patterned insulating layer 114. The photoresist 120 may be removed using a photoresist stripper after the patterned insulating layer 114 is formed, but is not limited thereto. The material of the patterned insulating layer 114 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, graphene oxide, graphene nitride, graphene oxynitride, and the like, but is not limited thereto. The material of the patterned insulating layer 114 may also include an organic insulating material or an organic / inorganic hybrid insulating material, and may have a single-layer structure or a composite-layer structure. In addition, the thickness of the patterned insulating layer 114 is, for example, about 500 angstroms, but is not limited thereto.
如第3圖所示，接著利用圖案化絕緣層114作為蝕刻遮罩，並對第二半導體層118進行第一蝕刻製程128以形成第二圖案化半導體層112。在本實施例中係使用第一蝕刻液來進行第一蝕刻製程128，且第一蝕刻液為鋁蝕刻液，所以第一蝕刻製程128為濕蝕刻製程，但不以此為限。由於鋁蝕刻液對氧化銦鎵鋅的蝕刻速率較快，而氧化銦錫鋅可抗鋁蝕刻液，因此在第一蝕刻製程128中，第二半導體層118可被蝕刻而形成第二圖案化半導體層112，同時第一半導體層116大體上不會受到第一蝕刻液的影響。此外，由於在第一蝕刻製程128中係直接使用圖案化絕緣層114作為蝕刻遮罩，因此所形成之第二圖案化半導體層112具有與圖案化絕緣層114實質上相同的圖案及面積。換言之，本實施例係藉由圖案化絕緣層114來定義第二圖案化半導體層112的圖案。As shown in FIG. 3, the patterned insulating layer 114 is then used as an etching mask, and the second semiconductor layer 118 is subjected to a first etching process 128 to form a second patterned semiconductor layer 112. In this embodiment, the first etching process 128 is performed using a first etching solution, and the first etching solution is an aluminum etching solution. Therefore, the first etching process 128 is a wet etching process, but is not limited thereto. Because the etching rate of aluminum etching solution to indium gallium zinc oxide is fast, and the indium tin zinc oxide is resistant to aluminum etching solution, in the first etching process 128, the second semiconductor layer 118 can be etched to form a second patterned semiconductor. Layer 112, while the first semiconductor layer 116 is substantially unaffected by the first etchant. In addition, since the patterned insulating layer 114 is directly used as an etching mask in the first etching process 128, the second patterned semiconductor layer 112 formed has substantially the same pattern and area as the patterned insulating layer 114. In other words, in this embodiment, the pattern of the second patterned semiconductor layer 112 is defined by the patterned insulating layer 114.
如第4圖所示，接著對第一半導體層116進行圖案化製程以形成第一圖案化半導體層110。圖案化製程可例如為微影暨蝕刻製程，首先可整面塗佈一層光阻層，接著可利用光罩對光阻層曝光以定義出欲製作出第一圖案化半導體層110的位置，再經過顯影以形成圖案化之光阻122，其具有欲製作出之第一圖案化半導體層110的圖案，接著用第二蝕刻液進行第二蝕刻製程130以形成第一圖案化半導體層110，本實施例之第二蝕刻液為草酸，但不以此為限。在本實施例中，光阻122係形成於第二圖案化半導體層112的位置，且光阻112具有比第二圖案化半導體層112大的面積，並可包覆第二圖案化半導體層112與圖案化絕緣層114，但不以此為限。藉此，經過第二蝕刻製程130所形成的第一圖案化半導體層110的面積係大於第二圖案化半導體層112的面積。另外，光阻122可在第一圖案化半導體層110形成後使用光阻剝離劑去除，但不以此為限。As shown in FIG. 4, a patterning process is performed on the first semiconductor layer 116 to form a first patterned semiconductor layer 110. The patterning process may be, for example, a lithography and etching process. First, a photoresist layer may be coated on the entire surface, and then the photoresist layer may be exposed using a photomask to define the position where the first patterned semiconductor layer 110 is to be produced. It is developed to form a patterned photoresist 122 having a pattern of the first patterned semiconductor layer 110 to be produced, and then a second etching process 130 is performed with a second etchant to form the first patterned semiconductor layer 110. The second etching solution in the embodiment is oxalic acid, but is not limited thereto. In this embodiment, the photoresist 122 is formed at the position of the second patterned semiconductor layer 112, and the photoresist 112 has a larger area than the second patterned semiconductor layer 112 and can cover the second patterned semiconductor layer 112. And patterned insulating layer 114, but not limited thereto. Accordingly, the area of the first patterned semiconductor layer 110 formed by the second etching process 130 is larger than the area of the second patterned semiconductor layer 112. In addition, the photoresist 122 may be removed using a photoresist stripper after the first patterned semiconductor layer 110 is formed, but is not limited thereto.
請再參考第1圖，接著移除光阻122，曝露出未被圖案化絕緣層114與第二圖案化半導體層112所覆蓋的第一圖案化半導體層110之兩端。然後，於圖案化絕緣層114上形成汲極104與源極106，其中汲極104與源極106亦形成於第一圖案化半導體層110上並分別覆蓋且直接接觸於第一圖案化半導體層110之兩端的頂面及側壁，使得第一圖案化半導體層110與汲極104及源極106電性連接。此外，由於第二圖案化半導體層112係被圖案化絕緣層114所覆蓋，因此汲極104與源極106並未與第二圖案化半導體層112的頂面接觸。形成汲極104與源極106的方法可與形成閘極102的方法相同，但不以此為限。汲極104與源極106之材料可包括鋁(aluminum)、銅(copper)、銀(silver)、鉻(chromium)、鈦(titanium)、鉬(molybdenum)之其中一種或多種、上述材料之複合層或上述材料之合金，但並不以此為限。根據本實施例，由於在第一蝕刻製程128中係直接使用圖案化絕緣層114作為蝕刻遮罩來製作第二圖案化半導體層112，因此相較於習知製作底閘型薄膜電晶體的製作方法，本實施例並不需要額外的光罩即可製作出具不同圖案與面積的第一圖案化半導體層110與第二圖案化半導體層112。Please refer to FIG. 1 again, and then remove the photoresist 122 to expose both ends of the first patterned semiconductor layer 110 not covered by the patterned insulating layer 114 and the second patterned semiconductor layer 112. Then, a drain electrode 104 and a source electrode 106 are formed on the patterned insulating layer 114, wherein the drain electrode 104 and the source electrode 106 are also formed on the first patterned semiconductor layer 110 and cover and directly contact the first patterned semiconductor layer, respectively. The top surfaces and sidewalls of the two ends of 110 make the first patterned semiconductor layer 110 be electrically connected to the drain 104 and the source 106. In addition, since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114, the drain electrode 104 and the source electrode 106 are not in contact with the top surface of the second patterned semiconductor layer 112. The method of forming the drain electrode 104 and the source electrode 106 may be the same as the method of forming the gate electrode 102, but is not limited thereto. The materials of the drain 104 and the source 106 may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, and a combination of the foregoing materials. Layers or alloys of the above materials, but not limited to this. According to this embodiment, since the patterned insulating layer 114 is directly used as an etching mask to fabricate the second patterned semiconductor layer 112 in the first etching process 128, compared with the conventional fabrication of a bottom-gate thin-film transistor, In this method, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different patterns and areas can be fabricated without an additional photomask.
本發明之薄膜電晶體及其製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例，然為了簡化說明並突顯各實施例之間的差異，下文中使用相同標號標注相同元件，並不再對重覆部分作贅述。The thin film transistor and the manufacturing method thereof of the present invention are not limited to the above embodiments. The following will continue to disclose other embodiments of the present invention, but in order to simplify the description and highlight the differences between the embodiments, the same elements are labeled with the same reference numerals in the following, and repeated details will not be repeated.
請參考第5圖，其為本發明薄膜電晶體之第二實施例的部分剖面示意圖。如第5圖所示，本實施例之薄膜電晶體2與第一實施例不同的地方在於，薄膜電晶體2包括圖案化層間介電層124設置於第二圖案化半導體層112上，且汲極104與源極106係設置於圖案化層間介電層124上。本實施例之圖案化層間介電層124的厚度舉例約為3000埃，但不以此為限。圖案化層間介電層124的材料可為有機介電材料或無機介電材料，且圖案化層間介電層124可為單層結構或複合層結構，相關材料可選自如前述之圖案化絕緣層114的材料，在此不再贅述。此外，圖案化層間介電層124具有第一接觸洞V1與第二接觸洞V2，第二圖案化半導體層112具有第三接觸洞V3與第四接觸洞V4，其中第一接觸洞V1與第三接觸洞V3相連通，第二接觸洞V2與第四接觸洞V4相連通，且第三接觸洞V3與第四接觸洞V4分別未覆蓋第一圖案化半導體層110頂面的兩個部分。另外，源極106除了設置於圖案化層間介電層124上外，也同時填入第一接觸洞V1與第三接觸洞V3，並與一部分的第一圖案化半導體層110之頂面直接接觸，而汲極104除了設置於圖案化層間介電層124上外，也同時填入第二接觸洞V2與第四接觸洞V4，並與另一部分的第一圖案化半導體層110之頂面直接接觸。由於本實施例之第二圖案化半導體層112具有接觸洞，因此第二圖案化半導體層112的面積係小於第一圖案化半導體層110，且藉由本實施例的設計，汲極104與源極106可直接與具有較低電阻值的第一圖案化半導體層110直接接觸，因此本實施例的汲極104與源極106可具有較低的接觸電阻。另一方面，由於薄膜電晶體2具有電阻值不同的第一圖案化半導體層110與第二圖案化半導體層112，因此可以減少背通道受汲極104影響所產生的額外載子的數量，以降低薄膜電晶體2之臨界電壓的改變幅度，進而增加薄膜電晶體2前通道的控制能力。本實施例之薄膜電晶體2的其餘特徵與第一實施例大致相同，可參考第1圖相關元件設置與材料之敘述，在此不再贅述。Please refer to FIG. 5, which is a schematic partial cross-sectional view of a second embodiment of a thin film transistor of the present invention. As shown in FIG. 5, the thin film transistor 2 of this embodiment is different from the first embodiment in that the thin film transistor 2 includes a patterned interlayer dielectric layer 124 disposed on the second patterned semiconductor layer 112, and The electrode 104 and the source electrode 106 are disposed on the patterned interlayer dielectric layer 124. The thickness of the patterned interlayer dielectric layer 124 in this embodiment is, for example, about 3000 angstroms, but is not limited thereto. The material of the patterned interlayer dielectric layer 124 may be an organic dielectric material or an inorganic dielectric material, and the patterned interlayer dielectric layer 124 may be a single-layer structure or a composite layer structure. The related material may be selected from the aforementioned patterned insulating layer. The material of 114 is not repeated here. In addition, the patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2, and the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 and the first contact hole V1 The three contact holes V3 are in communication, the second contact hole V2 is in communication with the fourth contact hole V4, and the third contact hole V3 and the fourth contact hole V4 respectively do not cover two portions of the top surface of the first patterned semiconductor layer 110. In addition, in addition to being disposed on the patterned interlayer dielectric layer 124, the source electrode 106 is also filled with the first contact hole V1 and the third contact hole V3 at the same time, and directly contacts a part of the top surface of the first patterned semiconductor layer 110. In addition to being disposed on the patterned interlayer dielectric layer 124, the drain 104 is also filled with the second contact hole V2 and the fourth contact hole V4 at the same time, and directly with the top surface of the first patterned semiconductor layer 110 in another part contact. Since the second patterned semiconductor layer 112 in this embodiment has a contact hole, the area of the second patterned semiconductor layer 112 is smaller than that of the first patterned semiconductor layer 110. According to the design of this embodiment, the drain 104 and the source 106 can be in direct contact with the first patterned semiconductor layer 110 having a lower resistance value. Therefore, the drain 104 and the source 106 in this embodiment can have a lower contact resistance. On the other hand, since the thin film transistor 2 has the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 with different resistance values, the number of extra carriers generated by the back channel affected by the drain 104 can be reduced, so that The change of the threshold voltage of the thin film transistor 2 is reduced, thereby increasing the control ability of the front channel of the thin film transistor 2. The remaining features of the thin-film transistor 2 of this embodiment are substantially the same as those of the first embodiment, and reference may be made to the description of related component settings and materials in FIG. 1, which will not be repeated here.
請參考第6圖至第8圖，其為本發明薄膜電晶體之製作方法之第二實施例的製程示意圖。如第6圖所示，本發明第二實施例與第一實施例的不同處在於，在形成第一半導體層與第二半導體層（例如第2圖所示之第一半導體層116與第二半導體層118）後即對第一半導體層與第二半導體層先進行圖案化製程，以形成第一圖案化半導體層110與第二預圖案化半導體層126。第一圖案化半導體層110與第二預圖案化半導體層126可例如係以微影暨蝕刻製程所形成。舉例而言，本實施例的第一半導體層為氧化銦錫鋅，第二半導體層為氧化銦鎵鋅，而所使用的蝕刻液包括草酸，其可同時對第一半導體層與第二半導體層進行蝕刻，但不以此為限。如第7圖所示，接著於第二預圖案化半導體層126上形成圖案化層間介電層124，其中圖案化層間介電層124具有第一接觸洞V1與第二接觸洞V2。形成圖案化層間介電層124的方式例如先整面地形成介電層(圖未示)，再對介電層進行圖案化製程(例如進行微影暨蝕刻製程)，以於介電層中形成第一接觸洞V1與第二接觸洞V2，但不以此為限。Please refer to FIG. 6 to FIG. 8, which are process schematic diagrams of a second embodiment of a method for manufacturing a thin film transistor of the present invention. As shown in FIG. 6, the second embodiment of the present invention is different from the first embodiment in that a first semiconductor layer and a second semiconductor layer (such as the first semiconductor layer 116 and the second semiconductor layer shown in FIG. 2) are formed. After the semiconductor layer 118), a patterning process is performed on the first semiconductor layer and the second semiconductor layer to form a first patterned semiconductor layer 110 and a second pre-patterned semiconductor layer 126. The first patterned semiconductor layer 110 and the second pre-patterned semiconductor layer 126 may be formed by, for example, a photolithography and etching process. For example, the first semiconductor layer in this embodiment is indium tin zinc oxide, the second semiconductor layer is indium gallium zinc oxide, and the etching solution used includes oxalic acid, which can simultaneously align the first semiconductor layer and the second semiconductor layer. Etching is performed, but not limited thereto. As shown in FIG. 7, a patterned interlayer dielectric layer 124 is formed on the second pre-patterned semiconductor layer 126. The patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2. The method of forming the patterned interlayer dielectric layer 124 is, for example, firstly forming a dielectric layer (not shown) on the entire surface, and then performing a patterning process (such as a lithography and etching process) on the dielectric layer so that the dielectric layer is formed in the dielectric layer. The first contact hole V1 and the second contact hole V2 are formed, but not limited thereto.
如第8圖所示，接著利用圖案化層間介電層124作為蝕刻遮罩，並對第二預圖案化半導體層126進行蝕刻製程132以形成第二圖案化半導體層112，其中在蝕刻製程132中係使用鋁蝕刻液來圖案化第二預圖案化半導體層126。在經過蝕刻製程132後，第二圖案化半導體層112具有第三接觸洞V3與第四接觸洞V4，其中第一接觸洞V1與第三接觸洞V3相連通，第二接觸洞V2與第四接觸洞V4相連通，因此第三接觸洞V3與第四接觸洞V4分別曝露出第一圖案化半導體層110頂面的兩個部分。由於本實施例的第二圖案化半導體層112具有第三接觸洞V3與第四接觸洞V4，因此第一圖案化半導體層110的面積係大於第二圖案化半導體層112的面積。請繼續參考第5圖，接著於圖案化層間介電層124上形成汲極104與源極106，汲極104填入第二接觸洞V2與第四接觸洞V4並電性連接於第一圖案化半導體層110，而源極106填入第一接觸洞V1與第三接觸洞V3中並電性連接於第一圖案化半導體層110。另由於第一圖案化半導體層110的頂面具有被第三接觸洞V3與第四接觸洞V4所暴露的兩個部分，因此汲極104可經由第二接觸洞V2與第四接觸洞V4而與一部分的第一圖案化半導體層110的頂面直接接觸，以及源極106可經由第一接觸洞V1與第三接觸洞V3而與另一部分的第一圖案化半導體層110的頂面直接接觸。根據本實施例，由於在蝕刻製程132中係直接使用圖案化層間介電層124作為蝕刻遮罩，因此相較於習知製作底閘型薄膜電晶體的製作方法，並不需要額外的光罩即可形成具有不同面積與圖案的第一圖案化半導體層110與第二圖案化半導體層112。本實施例之薄膜電晶體2之製作方法的其他製程與條件以及各元件之材料可大致與第一實施例相同，在此不再贅述。As shown in FIG. 8, the patterned interlayer dielectric layer 124 is then used as an etching mask, and the second pre-patterned semiconductor layer 126 is subjected to an etching process 132 to form a second patterned semiconductor layer 112, where the etching process 132 The middle system uses an aluminum etchant to pattern the second pre-patterned semiconductor layer 126. After the etching process 132, the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 is in communication with the third contact hole V3, and the second contact hole V2 and the fourth The contact hole V4 is communicated, so the third contact hole V3 and the fourth contact hole V4 respectively expose two portions of the top surface of the first patterned semiconductor layer 110. Since the second patterned semiconductor layer 112 in this embodiment has a third contact hole V3 and a fourth contact hole V4, the area of the first patterned semiconductor layer 110 is larger than the area of the second patterned semiconductor layer 112. Please continue to refer to FIG. 5, and then form a drain electrode 104 and a source electrode 106 on the patterned interlayer dielectric layer 124. The drain electrode 104 is filled in the second contact hole V2 and the fourth contact hole V4 and is electrically connected to the first pattern. The semiconductor layer 110 is patterned, and the source electrode 106 is filled in the first contact hole V1 and the third contact hole V3 and is electrically connected to the first patterned semiconductor layer 110. In addition, since the top surface of the first patterned semiconductor layer 110 has two portions exposed by the third contact hole V3 and the fourth contact hole V4, the drain electrode 104 can pass through the second contact hole V2 and the fourth contact hole V4. In direct contact with a portion of the top surface of the first patterned semiconductor layer 110, and the source electrode 106 may be in direct contact with the top surface of the other portion of the first patterned semiconductor layer 110 via the first contact hole V1 and the third contact hole V3. . According to this embodiment, since the patterned interlayer dielectric layer 124 is directly used as an etching mask in the etching process 132, compared to the conventional method for manufacturing a bottom-gate thin film transistor, an additional photomask is not required. That is, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different areas and patterns can be formed. The other processes and conditions of the method for manufacturing the thin film transistor 2 of this embodiment and the materials of each component may be substantially the same as those of the first embodiment, and details are not described herein again.
綜上所述，本發明揭露之薄膜電晶體的第二圖案化半導體層具有較高的電阻值，因此可以減少背通道受汲極影響所產生的額外載子的數量，以降低薄膜電晶體之臨界電壓的改變幅度。另一方面，由於第一圖案化半導體層離閘極較近且電阻值較第二圖案化半導體層低，所以載子大多在第一圖案化半導體層裡流通，進而可增加薄膜電晶體前通道的控制能力。此外，本發明揭露之薄膜電晶體的製作方法，在形成第二圖案化半導體層的過程中係直接使用圖案化絕緣層或圖案化層間介電層作為蝕刻遮罩，因此形成具有不同面積的第一圖案化半導體層與第二圖案化半導體層，相較於習知製作底閘型薄膜電晶體的製作方法並不需要額外的光罩。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In summary, the second patterned semiconductor layer of the thin film transistor disclosed by the present invention has a higher resistance value, so the number of extra carriers generated by the back channel affected by the drain can be reduced, so as to reduce the thickness of the thin film transistor. The magnitude of the change in threshold voltage. On the other hand, since the first patterned semiconductor layer is closer to the gate and has a lower resistance than the second patterned semiconductor layer, most of the carriers flow in the first patterned semiconductor layer, which can increase the front channel of the thin film transistor. Control. In addition, in the manufacturing method of the thin-film transistor disclosed in the present invention, in the process of forming the second patterned semiconductor layer, a patterned insulating layer or a patterned interlayer dielectric layer is directly used as an etching mask, so a first electrode having a different area is formed. A patterned semiconductor layer and a second patterned semiconductor layer do not require an additional photomask compared to the conventional method for manufacturing a bottom-gate thin film transistor. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.
1、2‧‧‧薄膜電晶體
100‧‧‧基板
102‧‧‧閘極
104‧‧‧汲極
106‧‧‧源極
108‧‧‧閘極絕緣層
110‧‧‧第一圖案化半導體層
112‧‧‧第二圖案化半導體層
114‧‧‧圖案化絕緣層
116‧‧‧第一半導體層
118‧‧‧第二半導體層
120、122‧‧‧光阻
124‧‧‧圖案化層間介電層
126‧‧‧第二預圖案化半導體層
128‧‧‧第一蝕刻製程
130‧‧‧第二蝕刻製程
132‧‧‧蝕刻製程
V1‧‧‧第一接觸洞
V2‧‧‧第二接觸洞
V3‧‧‧第三接觸洞
V4‧‧‧第四接觸洞
Z‧‧‧垂直投影方向1, 2‧‧‧ thin film transistor
100‧‧‧ substrate
102‧‧‧Gate
104‧‧‧ Drain
106‧‧‧Source
108‧‧‧Gate insulation
110‧‧‧first patterned semiconductor layer
112‧‧‧Second patterned semiconductor layer
114‧‧‧ patterned insulation layer
116‧‧‧First semiconductor layer
118‧‧‧Second semiconductor layer
120, 122‧‧‧Photoresist
124‧‧‧ patterned interlayer dielectric layer
126‧‧‧Second pre-patterned semiconductor layer
128‧‧‧First Etching Process
130‧‧‧Second etching process
132‧‧‧etching process
V1‧‧‧First contact hole
V2‧‧‧Second contact hole
V3‧‧‧Third contact hole
V4‧‧‧ Fourth contact hole
Z‧‧‧ vertical projection direction
第1圖為本發明薄膜電晶體之第一實施例的部分剖面示意圖。 第2圖至第4圖為本發明薄膜電晶體之製作方法之第一實施例的製程示意圖。 第5圖為本發明薄膜電晶體之第二實施例的部分剖面示意圖。 第6圖至第8圖為本發明薄膜電晶體之製作方法之第二實施例的製程示意圖。FIG. 1 is a schematic partial cross-sectional view of a first embodiment of a thin film transistor of the present invention. FIG. 2 to FIG. 4 are process schematic diagrams of the first embodiment of the method for manufacturing a thin film transistor of the present invention. FIG. 5 is a schematic partial cross-sectional view of a second embodiment of a thin film transistor of the present invention. FIG. 6 to FIG. 8 are process schematic diagrams of a second embodiment of a method for manufacturing a thin film transistor of the present invention.
1‧‧‧薄膜電晶體 1‧‧‧ thin film transistor
100‧‧‧基板 100‧‧‧ substrate
102‧‧‧閘極 102‧‧‧Gate
104‧‧‧汲極 104‧‧‧ Drain
106‧‧‧源極 106‧‧‧Source
108‧‧‧閘極絕緣層 108‧‧‧Gate insulation
110‧‧‧第一圖案化半導體層 110‧‧‧first patterned semiconductor layer
112‧‧‧第二圖案化半導體層 112‧‧‧Second patterned semiconductor layer
114‧‧‧圖案化絕緣層 114‧‧‧ patterned insulation layer
Z‧‧‧垂直投影方向 Z‧‧‧ vertical projection direction
Claims (25)
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