CN105990332B - Thin film transistor base plate and its display panel - Google Patents
Thin film transistor base plate and its display panel Download PDFInfo
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- CN105990332B CN105990332B CN201510085288.1A CN201510085288A CN105990332B CN 105990332 B CN105990332 B CN 105990332B CN 201510085288 A CN201510085288 A CN 201510085288A CN 105990332 B CN105990332 B CN 105990332B
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Abstract
It includes: substrate that the present invention, which discloses a kind of thin film transistor base plate and its display panel, the display panel,；The first metal layer is located on substrate, including grid, and the grid line of connection grid；First insulating layer is located on the first metal layer；Planarization layer is located on the first insulating layer；Opening, is defined by the surface of the side wall and the first insulating layer of planarization layer, opening and gate overlap；Active layer is located on opening and planarization layer；And second metal layer, it is located on active layer, the source electrode including contacting active layer, and the data line of connection source electrode；Wherein planarization layer and the first insulating layer are between data line and grid line.
Description
Technical field
The present invention relates to thin film transistor (TFT)s, and more particularly to thin film transistor base plate and display.
Background technique
In current thin film transistor base plate manufacture craft, after forming grid and grid line, that is, it is corresponding to define active layer
Grid, using as channel layer.Be subsequently formed another metal layer, it includes on active layer two sides source electrode and drain electrode, and connection
To the data line of source electrode.Above-mentioned data line and data line overlapping are only separated with gate dielectric.In order to reduce thin film transistor (TFT)
Driving current need to reduce the thickness of gate dielectric.However gate dielectric is thinner, the capacitor between data line and grid line is got over
Burden that is big and increasing the two confluce.In other words, above structure can not reduce the driving current and drop of thin film transistor (TFT) simultaneously
Capacitor between low data line and grid line.
In conclusion need new thin film transistor base plate at present, to when reducing the driving current of thin film transistor (TFT),
The capacitor between data line and grid line can also be reduced.
Summary of the invention
The display panel that one embodiment of the invention provides, comprising: substrate；The first metal layer is located on substrate, including grid
Pole, and the grid line of connection grid；First insulating layer is located on the first metal layer；Planarization layer is located at the first insulating layer
On；Opening, is defined by the surface of the side wall and the first insulating layer of planarization layer, opening and gate overlap；Active layer is located at flat
On smoothization layer and covering is open；And second metal layer, it is located on active layer, the source electrode including contacting active layer, and connection
The data line of source electrode；Wherein planarization layer and the first insulating layer are between data line and grid line.
The thin film transistor base plate that one embodiment of the invention provides, comprising: substrate；The first metal layer is located on substrate, packet
Include grid, and the grid line of connection grid；First insulating layer is located on the first metal layer；Planarization layer is located at the first insulation
On layer；Opening, is defined by the surface of the side wall and the first insulating layer of planarization layer, opening and gate overlap；Active layer is located at
On planarization layer and covering is open；And second metal layer, it is located on active layer, the source electrode including contacting active layer, Yi Jilian
Connect the data line of source electrode；Wherein planarization layer and the first insulating layer are between data line and grid line.
Detailed description of the invention
Figure 1A to Fig. 1 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention；
Fig. 2A to Fig. 2 D is the top view of corresponding diagram 1A to Fig. 1 D；
Fig. 3 A to Fig. 3 C is the manufacture craft cross-sectional view of the thin film transistor base plate in one embodiment of the invention；
Fig. 4 A to Fig. 4 C is the top view of corresponding diagram 3A to Fig. 3 C；
Fig. 5 A and Fig. 5 B are the cross-sectional view of thin film transistor base plate in the embodiment of the present invention；
Fig. 6 A to Fig. 6 B is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention；
Fig. 7 A to Fig. 7 B is the top view of corresponding diagram 6A to Fig. 6 B；
Fig. 8 A to Fig. 8 C is the manufacture craft cross-sectional view of the thin film transistor base plate in one embodiment of the invention；
Fig. 9 A to Fig. 9 C is the top view of corresponding diagram 8A to Fig. 8 C；
Figure 10 A to Figure 10 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention；
Figure 11 A to Figure 11 D is the top view of corresponding diagram 10A to Figure 10 D；
Figure 12 A to Figure 12 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention；
Figure 13 A to Figure 13 D is the top view of corresponding diagram 12A to Figure 12 D；
Figure 14 is the schematic diagram of display in one embodiment of the invention.
Symbol description
10 substrates
11 grid lines
11A grid
13,51 insulating layer
15,15 ' planarization layer
17 openings
19 active layers
19 ' conductor metal oxide layers
21 data lines
21A source electrode
21B drain electrode
31 etching stopping layers
33,103 contact hole
101 protective layers
1401 thin film transistor base plates
1403 display mediums
1405 opposite substrates
Specific embodiment
Figure 1A to Fig. 1 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Figure 1A extremely schemes
1D is respectively the cross-sectional view at the dotted line of the top views such as Fig. 2A to Fig. 2 D.It is worth noting that, the production of thin film transistor base plate
Technique can also be completed by other modes, however it is not limited to following step.In addition, before forming thin film transistor base plate, among or
Other additional steps can be carried out, later to define other nonwoven fabric from filaments among or on thin film transistor base plate.Firstly, forming gold
Belong to layer on substrate 10, then patterned metal layer is to define grid line 11 and coupled grid 11A.Implement in the present invention one
In example, substrate 10 can be glass, plastic cement or other common baseplate materials.In an embodiment of the present invention, metal layer can be
The metal or alloy of the single-layer or multi-layers such as molybdenum, aluminium, copper, titanium combination, forming method can be physical vaporous deposition (PVD), splash
Plating method, or the like.The method of patterned metal layer can be lithographic fabrication process and etching process.Lithographic fabrication process
Include following step: painting photoresist such as spin-coating method, soft baking, alignment of photomask, exposure, postexposure bake, development, punching
It washes, dry as toasted firmly, other suitable fabrication techniques or combinations of the above.In addition, the step of exposure of lithographic fabrication process can change
With other methods, such as unglazed mask lithography, electron-beam direct writing or ion beam direct write.After lithographic fabrication process, it can be lost
Manufacture craft such as dry ecthing, wet etching or combinations of the above are carved with patterned metal layer.Light can be removed after etching process
Cause resist pattern, method can for ashing, strip or combinations of the above.
Then insulating layer 13 and planarization layer 15 are sequentially formed on grid line 11 and grid 11A.Insulating layer 13 can be to have
Machine silicon oxide compound or inorganic such as silicon nitride, silica, silicon oxynitride, silicon carbide, aluminium oxide, hafnium oxide or above-mentioned material
The multilayered structure of matter, forming method can be chemical vapour deposition technique (CVD) such as plasma enhancing formula CVD (PECVD), low pressure
CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), physical vapour deposition (PVD) (PVD) or similar techniques.In an embodiment of the present invention,
The thickness of insulating layer 13 betweenBetween.If the thickness of insulating layer 13 is excessively thin, though transistor charging ability
The electric leakage of high but gate insulating layer is excessively high.If the thickness of insulating layer 13 is blocked up, transistor charging ability is too low.It is real in the present invention one
It applies in example, planarization layer 15 can be organic insulation layer material or inorganic insulating layer material, and forming method can be physical deposition
Or chemical vapor deposition.In an embodiment of the present invention, the composition of planarization layer 15 is different from insulating layer 13.In the present invention one
In embodiment, the thickness of planarization layer 15 betweenBetween.If the thickness of planarization layer 15 is excessively thin, after
The continuous data line and the distance between grid line 11 electricity that is too short, and can not being effectively reduced between data line and grid line 11 formed
Hold.If the thickness of planarization layer 15 is blocked up, influences it and pattern difficulty.This must it should be noted that, the top view of Fig. 2A
Insulating layer 13 and planarization layer 15 is omitted to simplify attached drawing.
Then as shown in Figure 1B and Fig. 2 B, planarization layer 15 is patterned to form opening 17, to expose corresponding grid 11A's
The upper surface of insulating layer 13.The method of above-mentioned formation opening 17 can be lithographic fabrication process and etching process it has been observed that In
This is not repeated.
Then as shown in Fig. 1 C and Fig. 2 C, active layer is formed after above structure, is patterned with active layer to define active layer
19 side wall and bottom in opening 17.As shown in Figure 1 C, active layer 19 may be slightly larger than opening 17, that is, extend to part planarization layer
On 15 surface.In an embodiment of the present invention, active layer 19 can be polysilicon or metal-oxide semiconductor (MOS) such as indium gallium zinc oxygen
Compound (IGZO).The forming method of active layer can for CVD such as PECVD, LPCVD or SACVD, physics and vapor deposition (PVD),
Solution synthesis mode deposition, or the like.It is worth noting that, when active layer 19 is metal-oxide semiconductor (MOS), it is flat
Changing layer 15 can not be silicon nitride or the insulating materials rich in hydrogen, to avoid side wall and the bottom that will be located at opening 17 in manufacture craft
The active layer 19 in portion is converted to conductor.The method for being patterned with active layer can be lithographic fabrication process and etching process as before
It states, this will not be repeated here.
Then as shown in Fig. 1 D and Fig. 2 D, metal layer is formed on above structure, then patterned metal layer is to define data
Line 21, source electrode 21A and drain electrode 21B.In an embodiment of the present invention, above-mentioned metal layer can be the single layers or more such as molybdenum, aluminium, copper, titanium
The metal or alloy of layer combination, forming method can be physical vapour deposition (PVD) (PVD) or sputter.The method of patterned metal layer can
It is lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 and 11 overlapping of grid line every
There are planarization layer 15 and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.Source electrode 21A and drain electrode 21B are located at opening
It is not attached on active layer 19 in 17 opposite side walls and each other.It is worth noting that, if source electrode 21A is only positioned at drain electrode 21B
It does not extend on part active layer 19 on planarization layer 15 on the active layer 19 on the side wall of opening 17, then active layer 19
Passage length (channel length) is difficult to drive by too long.
Fig. 3 A to Fig. 3 C is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Fig. 3 A extremely schemes
3C is respectively the cross-sectional view at the dotted lines of top views such as Fig. 4 A to Fig. 4 C.After the structure for completing Fig. 1 C and Fig. 2 C, etching is formed
Stop-layer 31 is thereon to form structure shown in Fig. 3 A and Fig. 4 A.In an embodiment of the present invention, etching stopping layer 31 can be
The inorganic insulation layers such as silica, aluminium oxide, titanium oxide, forming method can be heavy for chemical vapor deposition, atomic layer deposition, physics
The methods of product.In an embodiment of the present invention, the thickness of etching stopping layer 31 betweenBetween.If etching
The thickness of stop-layer 31 is excessively thin, then inadequate for active layer protective capability.If the thickness of etching stopping layer 31 is blocked up, influence to make
Make the process time and patterning difficulty increases.This must it should be noted that, the top view of Fig. 3 A be omitted insulating layer 13, planarization
Layer 15 and etching stopping layer 31 are to simplify attached drawing.
Then as shown in Fig. 3 B and Fig. 4 B, patterned etch stop 31 is to form contact hole 33, to expose opening 17
Active layer 19 on side wall and the part active layer 19 on the bottom of opening 17.The method of above-mentioned formation contact hole 33 can be photoetching
Manufacture craft and etching process are it has been observed that this will not be repeated here.
Then as shown in Fig. 3 C and Fig. 4 C, metal layer is formed on above structure, then patterned metal layer is to define data
Line 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal layer and forming method are with aforementioned, and the method for patterned metal layer
It can be lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 and 11 overlapping of grid line
It is separated with etching stopping layer 31, planarization layer 15 and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.Source electrode 21A and leakage
Pole 21B is via contact hole 33, and contact is located at the active layer 19 in the opposite side walls of opening 17 and is not attached to each other respectively.This is implemented
The nonwoven fabric from filaments being separated by between the data line 21 and grid line 11 of example is more, therefore can further decrease capacitor between the two.Separately
On the one hand, it is open between the source electrode 21A and drain electrode 21B of 17 bottoms and is separated with etching stopping layer 31, can further avoid because making work
Skill error causes the two to be electrical connected.
Fig. 5 A is the cross-sectional view of thin film transistor base plate in one embodiment of the invention.The knot of structure and Fig. 1 D in Fig. 5 A
Structure is similar, and difference is initially formed another insulating layer 51 after forming opening 17 and before formation active layer 19.Insulating layer 51 and active layer
There is preferable interfacial property between 19.In an embodiment of the present invention, insulating layer 51 can be silica, aluminium oxide or oxidation
Titanium, forming method can be the methods of chemical vapor deposition, atomic layer deposition or physical deposition.In one embodiment of the invention
In, the thickness of insulating layer 51 betweenBetween.If the thickness of insulating layer 51 is excessively thin, insulating layer electric leakage is excessively high.
If the thickness of insulating layer 51 is blocked up, transistor charging ability is influenced.
Fig. 5 B is the cross-sectional view of thin film transistor base plate in one embodiment of the invention.The knot of structure and Fig. 3 C in Fig. 5 B
Structure is similar, and difference is initially formed another insulating layer 51 after forming opening 17 and before formation active layer 19.Insulating layer 51 and active layer
There is preferable interfacial property between 19.As for the composition of insulating layer 51, forming method and thickness with aforementioned, this will not be repeated here.
Fig. 6 A to Fig. 6 B is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Fig. 6 A extremely schemes
6B is respectively the cross-sectional view at the dotted lines of top views such as Fig. 7 A to Fig. 7 B.The structure of Fig. 6 A is similar with the structure of Fig. 1 C, and difference exists
The active layer 19 of Fig. 6 A be metal-oxide semiconductor (MOS) such as IGZO, it includes have be located at opening 17 bottom on first part,
And the second part on planarization layer 15, and the planarization layer 15 of Fig. 1 C is changed to that metal-oxide semiconductor (MOS) can be converted
For the planarization layer 15 ' of conductor.In an embodiment of the present invention, planarization layer 15 ' be silicon nitride or the insulating layer rich in hydrogen,
Hydrogen content need to be greater than 10 atom %.In this way, which the second part for the active layer 19 being formed on planarization layer 15 ' is converted into
Conductor metal oxide layer 19 '.This must it should be noted that, insulating layer 13 and planarization layer 15 ' is omitted in the top view of Fig. 7 A
To simplify attached drawing.
Then as shown in Fig. 6 B and Fig. 7 B, metal layer is formed on above structure, then patterned metal layer is to define data
Line 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal layer and forming method are with aforementioned, and the method for patterned metal layer
It can be lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 and 11 overlapping of grid line
It is separated with planarization layer 15 ' and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.Source electrode 21A is located at drain electrode 21B
It is not attached on the conductor metal oxide layer 19 ' of 19 two sides of active layer and each other.Due to the active layer 19 on planarization layer 15 '
It is converted into conductor metal oxide layer 19 ', source electrode 21A and drain electrode 21B only need the metal oxide on contact planarization layer 15 '
Conductor layer 19 ' can further reduce the size of opening 17 and avoid making because of manufacture craft error without extending in opening 17
It is electrical connected at the two.
Fig. 8 A to Fig. 8 C is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Fig. 8 A extremely schemes
8C is respectively the cross-sectional view at the dotted lines of top views such as Fig. 9 A to Fig. 9 C.After completing the structure of Fig. 6 A and Fig. 7 A, etching is formed
Stop-layer 31 is thereon to form structure shown in Fig. 8 A and Fig. 9 A.It is the composition of etching stopping layer 31, forming method, same with thickness
Aforementioned, this will not be repeated here.At this, it should be noted that, insulating layer 13, planarization layer 15 ' and erosion is omitted in the top view of Fig. 9 A
Stop-layer 31 is carved to simplify attached drawing.
Then as shown in Fig. 8 B and Fig. 9 B, patterned etch stop 31 is to form contact hole 81, to expose planarization layer
Conductor metal oxide layer 19 ' on 15 '.The method of above-mentioned formation contact hole 81 can be lithographic fabrication process and etching production work
Skill is it has been observed that this will not be repeated here.
Then as shown in Fig. 8 C and Fig. 9 C, metal layer is formed on above structure, then patterned metal layer is to define data
Line 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal layer and forming method are with aforementioned, and the method for patterned metal layer
It can be lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 and 11 overlapping of grid line
It is separated with etching stopping layer 31, planarization layer 15 ' and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.Source electrode 21A and leakage
Pole 21B via contact hole 81, lead by the metal oxide on planarization layer 15 ' that contact is located on the two opposite sides of opening 17 respectively
It body layer 19 ' and is not attached to each other.The nonwoven fabric from filaments being separated by between the data line 21 and grid line 11 of this embodiment is more, therefore can be into
One step reduces capacitor between the two.On the other hand, source electrode 21A and drain electrode 21B are not required to extend in opening 17, can further contract
The size of small opening 17 is simultaneously electrical connected both caused by avoiding because of manufacture craft error.
Figure 10 A to Figure 10 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Figure 10 A is extremely
Figure 10 D is respectively the cross-sectional view at the dotted lines of top views such as Figure 11 A to Figure 11 D.The pattern etched after the structure for completing Fig. 3 A
Stop-layer 31, at least reservation etching stopping layer 31 are in as shown in Figure 10 A on the active layer 19 of the bottom of opening 17.It must say at this
Bright, insulating layer 13 and planarization layer 15 is omitted to simplify attached drawing in the top view of Figure 11 A.
Then as shown in Figure 10 B, protective layer 101 is deposited on above structure.In this embodiment, active layer 19 is metal
Oxide semiconductor.Above-mentioned etching stopping layer 31 can not be silicon nitride or the insulating layer rich in hydrogen with insulating layer 13, to avoid inciting somebody to action
The active layer 19 of 17 bottoms of being open is converted to conductor.Above-mentioned protective layer 101 is silicon nitride or the insulating layer rich in hydrogen, formation side
Method can be the methods of chemical vapor deposition or physical deposition.Above-mentioned protective layer 101 can make be open 17 bottoms other than other have
Active layer 19 is converted to conductor metal oxide layer 19 '.
Then it as shown in Figure 10 C and Figure 11 C, forms contact hole 103 and passes through protective layer 101, to expose on planarization layer 15
Conductor metal oxide layer 19 '.The method of above-mentioned formation contact hole 103 can be for lithographic fabrication process and etching process such as
Aforementioned, this will not be repeated here.
Then as shown in Figure 10 D and Figure 11 D, metal layer is formed on above structure, then patterned metal layer is to define number
According to line 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal layer and forming method are with aforementioned, and the side of patterned metal layer
Method can be lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 is Chong Die with grid line 11
Place is separated with protective layer 101, planarization layer 15 and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.Source electrode 21A and drain electrode
21B is contacted on the conductor metal oxide layer 19 ' of two sides respectively via contact hole 103 and is not attached to each other.Due to protective layer 101
There is etching stopping layer 31 between 17 bottoms of opening, can avoid the active layer 19 for 17 bottoms that are open being converted to conductor.
Figure 12 A to Figure 12 D is the manufacture craft cross-sectional view of thin film transistor base plate in one embodiment of the invention.Figure 12 A is extremely
Figure 12 D is respectively the cross-sectional view at the dotted lines of top views such as Figure 13 A to Figure 13 D.The pattern etched after the structure for completing Fig. 3 A
Stop-layer 31, with retain etching stopping layer 31 in opening 17 bottom active layer 19 on and active layer 19 other than other
On region, as shown in Figure 12 A and Figure 13 A.This must it should be noted that, the top view of Figure 13 A be omitted insulating layer 13 with it is flat
Change layer 15 to simplify attached drawing.
Then as shown in Figure 12 B, protective layer 101 is deposited on above structure.In this embodiment, active layer 19 is metal
Oxide semiconductor.Above-mentioned etching stopping layer 31 can not be silicon nitride or the insulating layer rich in hydrogen with insulating layer 13, to avoid inciting somebody to action
The active layer 19 of 17 bottoms of being open is converted to conductor.Above-mentioned protective layer 101 is silicon nitride or the insulating layer rich in hydrogen, formation side
Method can be the methods of chemical vapor deposition or physical deposition.Above-mentioned protective layer 101 can make be open 17 bottoms other than other have
Active layer 19 is converted to conductor metal oxide layer 19 '.
Then as shown in Figure 12 C and Figure 13 C, protective layer 101 is patterned to form contact hole 103, to expose planarization layer
Conductor metal oxide layer 19 ' on 15.The method of above-mentioned formation contact hole 103 can be lithographic fabrication process and etching production work
Skill is it has been observed that this will not be repeated here.
Then as shown in Figure 12 D and Figure 13 D, metal layer is formed on above structure, then patterned metal layer is to define number
According to line 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal layer and forming method are with aforementioned, and the side of patterned metal layer
Method can be lithographic fabrication process and etching process it has been observed that this will not be repeated here.Above-mentioned data line 21 is Chong Die with grid line 11
Place is separated with protective layer 101, etching stopping layer 31, planarization layer 15 and insulating layer 13.Above-mentioned source electrode 21A is connected to data line 21.
Source electrode 21A contacts the conductor metal oxide layer 19 ' of two sides via contact hole 103 with drain electrode 21B respectively and is not attached to each other.This
The nonwoven fabric from filaments being separated by between the data line 21 and grid line 11 of embodiment is more, therefore can further decrease electricity between the two
Hold.
Thin film transistor base plate shown in above-mentioned Fig. 1 D, Fig. 3 C, Fig. 5 A, Fig. 5 B, Fig. 6 B, Fig. 8 C, Figure 10 D and Figure 12 D
Drain electrode 21B can further be connected with pixel electrode, to control the light and shade of pixel region.Pixel region can further include common electrode.
The design of pixel electrodes and common electrode is common in thin film transistor base plate, and this will not be repeated here.
Figure 14 is the cross-sectional view of the display of one embodiment of the invention.In Figure 14, display includes thin film transistor (TFT) base
Plate 1401, opposite substrate 1405 and the display medium being sandwiched between thin film transistor base plate 1401 and opposite substrate 1405
1403.Thin film transistor base plate 1401 can be for shown in Fig. 1 D, Fig. 3 C, Fig. 5 A, Fig. 5 B, Fig. 6 B, Fig. 8 C, Figure 10 D or Figure 12 D
Thin film transistor base plate, display medium 1030 can be liquid crystal layer or organic luminous layer.Opposite substrate 1020 can be colorized optical filtering base
Plate or transparent substrate.
Claims (11)
1. a kind of display panel, comprising:
Substrate；
The first metal layer is located on the substrate, including grid, and connects the grid line of the grid；
First insulating layer is located on the first metal layer；
Planarization layer is located on first insulating layer；
Opening, is defined by the surface of the side wall and first insulating layer of the planarization layer, the opening and the gate overlap；
Active layer on the planarization layer and covers the opening；And
Second metal layer is located on the active layer, including contacting the source electrode of the active layer, and connects the data line of the source electrode；
Wherein the planarization layer and first insulating layer are located between the data line and the grid line,
Wherein the active layer includes the first part on the surface of first insulating layer, and on the planarization layer
Second part, wherein the second metal layer contacts the second part of the active layer,
Wherein the first part of the active layer is metal-oxide semiconductor (MOS), and the second part of the active layer is metal oxide
Conductor；
Wherein the planarization layer is by silicon nitride or the insulating materials rich in hydrogen is formed.
2. display panel as described in claim 1, wherein the second metal layer contacts the active layer in the opening.
3. display panel as claimed in claim 2 further includes second insulating layer, it is located on the planarization layer, and the active layer
In the second insulating layer, and the second insulating layer, the planarization layer and first insulating layer are located at the data line and the grid
Between polar curve.
4. display panel as claimed in claim 2 further includes etching stopping layer, it is located on the active layer and the planarization layer,
And there are the etching stopping layer multiple contact holes to expose part active layer in the opening, wherein the source electrode is via those contacts
One of hole contacts the active layer,
Wherein the etching stopping layer, the planarization layer and first insulating layer are located between the data line and the grid line.
5. display panel as claimed in claim 4 further includes second insulating layer, it is located on the planarization layer, and the active layer
In the second insulating layer, and the etching stopping layer, the second insulating layer, the planarization layer, it is located at first insulating layer
Between the data line and the grid line.
6. display panel as described in claim 1 further includes etching stopping layer, it is located on the active layer and the planarization layer,
And the etching stopping layer has the second part of multiple contact hole exposed portion active layer, wherein the source electrode is via those contacts
One of hole contacts the second part of the active layer,
Wherein the etching stopping layer, the planarization layer and first insulating layer are located between the data line and the grid line.
7. display panel as described in claim 1, further includes:
Etching stopping layer is located on the active layer；And
Protective layer, positioned at the etching stopping layer, the second part of the active layer, on the planarization layer, and the protective layer has
The second part of multiple contact hole exposed portion active layer, the source electrode contact the of the active layer via one of those contact holes
Two parts；
Wherein the protective layer, the planarization layer and first insulating layer are located between the data line and the grid line.
8. display panel as claimed in claim 7, wherein the protective layer is by silicon nitride or the institute of the insulating materials rich in hydrogen group
At.
9. display panel as claimed in claim 7, wherein the etching stopping layer is also located on the planarization layer, and the protection
Layer, the etching stopping layer, the planarization layer and first insulating layer are located between the data line and the grid line.
10. display panel as described in claim 1, further includes:
Opposite substrate；And
Display medium, between the substrate and the opposite substrate.
11. a kind of thin film transistor base plate, comprising:
Substrate；
The first metal layer is located on the substrate, including grid, and connects the grid line of the grid；
First insulating layer is located on the first metal layer；
Planarization layer is located on first insulating layer；
Opening, is defined by the surface of the side wall and first insulating layer of the planarization layer, the opening and the gate overlap；
Active layer on the planarization layer and covers the opening；And
Second metal layer is located on the active layer, including contacting the source electrode of the active layer, and connects the data line of the source electrode；
Wherein the planarization layer and first insulating layer are located between the data line and the grid line,
Wherein the active layer includes the first part on the surface of first insulating layer, and on the planarization layer
Second part, wherein the second metal layer contacts the second part of the active layer,
Wherein the first part of the active layer is metal-oxide semiconductor (MOS), and the second part of the active layer is metal oxide
Conductor；
Wherein the planarization layer is by silicon nitride or the insulating materials rich in hydrogen is formed.
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| CN201510085288.1A CN105990332B (en) | 2015-02-17 | 2015-02-17 | Thin film transistor base plate and its display panel |
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| US10191345B2 (en) | 2016-11-01 | 2019-01-29 | Innolux Corporation | Display device |
| US10319880B2 (en) * | 2016-12-02 | 2019-06-11 | Innolux Corporation | Display device |
| US10726758B2 (en) | 2018-12-04 | 2020-07-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| CN109493726A (en) * | 2018-12-04 | 2019-03-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Citations (4)
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| CN101800229A (en) * | 2009-02-09 | 2010-08-11 | 株式会社日立显示器 | Display unit |
| CN104022156A (en) * | 2014-05-20 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, corresponding manufacturing method and display device |
| CN104347727A (en) * | 2013-07-23 | 2015-02-11 | 三星显示有限公司 | Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element |
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| JP2009049340A (en) * | 2007-08-23 | 2009-03-05 | Epson Imaging Devices Corp | Electrooptical device and method of manufacturing the same |
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| CN101800229A (en) * | 2009-02-09 | 2010-08-11 | 株式会社日立显示器 | Display unit |
| CN104347727A (en) * | 2013-07-23 | 2015-02-11 | 三星显示有限公司 | Thin film transistor and method of manufacturing same, storage capacitor and semiconductor element |
| CN104022156A (en) * | 2014-05-20 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, corresponding manufacturing method and display device |
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