CN109860306A - A kind of transistor, array substrate, display panel and its manufacturing method - Google Patents
A kind of transistor, array substrate, display panel and its manufacturing method Download PDFInfo
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- CN109860306A CN109860306A CN201910058531.9A CN201910058531A CN109860306A CN 109860306 A CN109860306 A CN 109860306A CN 201910058531 A CN201910058531 A CN 201910058531A CN 109860306 A CN109860306 A CN 109860306A
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Abstract
The present invention provides a kind of transistor, array substrate, display panel and its manufacturing method.Transistor includes gate electrode layer structure and the source-drain electrode layer in the gate electrode layer structure, and gate electrode layer structure includes the substrate stacked gradually, First Transition layer and the first copper film layer, and First Transition layer is constituted using indium tin oxide material.Array substrate includes above-mentioned transistor.Display panel includes above-mentioned array substrate.The manufacturing method of display panel is comprising steps of production light shield layer, production buffer layer, production active layer, production gate insulating layer, production gate electrode layer structure, graphical treatment, corona treatment active layer, production interlayer insulating film, production source-drain electrode layer, production passivation layer, the flat organic layer of production, production anode, production organic light emitting diodde desplay device.Use tin indium oxide as First Transition layer, be effectively improved gate electrode layer structure undercut problem, this structure improves as source-drain electrode layer and overlaps situation with interlayer insulating film, reduces short-circuit generation.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of transistor, array substrate, display panel and its manufacturers
Method.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT), is the widely used semiconductor device of electronics industry
Part, the multi-purpose drive for making active matrix LCDs (AMLCD) and active matrix organic light-emitting diode (AMOLED) screen
Dynamic circuit core element.Oxide TFT is using active channel layer of the metal oxide semiconductor material as TFT device, phase
Than traditional silicon-based semiconductor TFT device, has the characteristics that low in cost, carrier mobility is high, uniformity is good, be future
The Main way of TFT development.
Currently, due to the resistivity that there is fine copper low-resistivity (2.3 μ Ω cm) can reduce TFT device, it is excellent with its
The price of low-resistivity and relative moderate, therefore use copper film as device electrode material.But fine copper is as device electrode, mainly
Face following difficulty: (1) only one electron outside nucleus of outermost layer, chemical activity are weak in Cu atomic structure, it is difficult to substrate bonding,
Lead to the poor bonding strength of copper electrode and substrate.(2) copper atom, which occurs to spread, causes Cu-W ore deposit, and insulating layer or semiconductor is caused to have
Deep energy level acceptor impurity is formed in active layer, makes device performance degeneration.
Based on problem above, a kind of current solution is to add one layer or more between copper film electrode and insulating layer
Other metals of layer stop the diffusion of copper atom as transition zone and improve bond strength.As now it is common using Mo/Cu
Gate electrode layer structure of the lamination as thin film transistor (TFT).This processing mode, the Mo intermediate metal of addition and the quarter of fine copper film
Erosion characteristic has differences, and exists after causing in etching process electrochemical reaction to will cause grid and source-drain electrode etching and seriously stings
Side (undercut, or undercutting) problem, the presence of undercut will cause some bad of follow-up process, such as interlayer insulating film covers
Lid is poor, be easy to cause grid and source-drain electrode short circuit.
Therefore, it is necessary to design a kind of new material structure, while meeting the diffusion of blocking copper atom, increasing adhesive force,
Undercut problem can be improved, solving has grid caused by undercut and source-drain electrode short circuit in production.
Summary of the invention
In place of the above shortcoming and defect of the existing technology, the primary purpose of the present invention is that providing a kind of crystal
Pipe, array substrate, display panel.
Another object of the present invention is to provide the preparation methods of above-mentioned display panel.
The object of the invention is achieved through the following technical solutions:
A kind of transistor is provided in one embodiment of the invention, including gate electrode layer structure and is located at the gate electrode layer structure
On source-drain electrode layer, the gate electrode layer structure includes the substrate stacked gradually, First Transition layer and the first copper film layer, described
One transition zone is constituted using indium tin oxide material.Indium tin oxide material is used to replace prior art Mo material as the first copper film layer
First Transition layer, be effectively improved gate electrode layer structure undercut problem, and then improve and overlap situation with gate insulating layer, and make
Gate electrode layer structure has the advantages of high bond strength, high electrical stability, low-resistivity, etching good compatibility.
Further, wherein the source-drain electrode layer includes the second transition zone and the second copper film layer stacked gradually, described
Two transition zones are constituted using indium tin oxide material.Use indium tin oxide material as the second transition zone of the second copper film layer, effectively
Improve and overlap situation with interlayer insulating film, reduces gate electrode layer structure and source-drain electrode layer short circuit probability of happening.
Further, wherein the First Transition layer with a thickness ofAnd/or the first copper film layer thickness
ForThe range of its thickness can effectively realize the combination of gate electrode layer structure and gate insulating layer, avoid undercut
The appearance of problem.
Further, wherein second transition region thickness isAnd/or the second copper film layer thickness
ForThe range of its thickness can effectively realize the combination of gate electrode layer structure and interlayer insulating film, avoid undercut
The appearance of problem.
A kind of array substrate is provided in further embodiment of this invention, including transistor described in any of the above-described kind.The array
The gate electrode layer structure of substrate has the advantages of high bond strength, high electrical stability, low-resistivity, etching good compatibility.
Further, wherein the substrate from bottom to up successively include substrate of glass, light shield layer, buffer layer, active layer and
Gate insulating layer；It successively include interlayer insulating film in the gate electrode layer structure, the source-drain electrode layer, passivation layer, flat
Organic layer and anode.
Further, wherein the material that the light shield layer uses includes any or combinations thereof of Mo, Al, Cu or Ti；With/
Or, the material that the buffer layer uses includes SiOx material, the buffer layer with a thickness ofAnd/or it is described
Active layer use material include metal oxide semiconductor material, the active layer with a thickness ofAnd/or institute
The material for stating interlayer insulating film use includes SiOx material, the interlayer insulating film with a thickness ofAnd/or
The material that the passivation layer uses includes SiOx material, the passivation layer with a thickness ofAnd/or it is described flat
The material that smooth organic layer uses includes photoresist, the flat organic layer with a thickness ofAnd/or institute
State anode use material include transparent oxide material, the anode with a thickness of
A kind of display panel, array substrate described in any of the above-described kind are provided in another embodiment of the present invention.
Further, wherein the display panel further includes the pixel defining layer being located in the array substrate, shines
Layer and cathode；The material that the pixel defining layer uses includes photoresist, the pixel defining layer with a thickness of
A kind of manufacturing method of above-mentioned display panel is provided in yet another embodiment of the invention, comprising steps of
S1 makes light shield layer step, provides a substrate of glass and cleans, and deposits one layer of metal on the glass substrate and makees
For light shield layer；
S2 makes buffer layer step, and one layer of SiOx material is deposited on the light shield layer as buffer layer；
S3 makes active layer step, and one layer of metal oxide semiconductor material is deposited on the buffer layer as active
Layer, is patterned processing to the active layer；
S4 makes gate insulating layer step, deposits one layer of SiOx material on the active layer as gate insulating layer；
S5 makes gate electrode layer configuration steps, deposits indium oxide layer tin material on the gate insulating layer as first
Transition zone, the First Transition layer with a thickness ofOne layer of fine copper is deposited on the First Transition layer as first
Copper film layer, first copper film layer with a thickness of
S6 graphical treatment step forms photoresist layer on first copper film layer, etches the photoresist layer using yellow light
It is patterned processing；The first copper film layer described in copper acid etching is closed using tetrahydroxy, etches the First Transition layer using oxalic acid,
Etching forms the gate electrode layer structure graph twice；The gate electrode layer structure graph autoregistration is recycled, the grid are etched
The exposed active layer both ends of pole insulating layer；Remove the photoresist layer；
S7 corona treatment active layer step carries out corona treatment to the active layer both ends and oxidizes metal object
Semiconductor forms conductor layer, as source electrode and drain electrode contact jaw；
S8 makes interlayer insulating film step, and one layer of SiOx material is deposited in the gate electrode layer structure as layer insulation
Layer；
S9 makes source-drain electrode layer step, carries out aperture using yellow light in the interlayer insulating film, and deposit indium oxide layer
Tin material is as the second transition zone, second transition region thicknessOne is deposited on second transition zone
Layer fine copper as the second copper film layer, second copper film layer with a thickness ofSource electricity is graphically made using yellow light
Pole and drain electrode；
S10 makes passivation layer step, one layer of SiOx material is deposited on the source-drain electrode layer as passivation layer, and etch
First via hole, the bottom hole of first via hole are the drain electrode；
S11 makes flat organic layer step, and one layer of photoresist is made on the passivation layer as flat organic layer, is led to
It crosses yellow light and makes the second via hole, second via hole is overlapped with first via hole；
S12 production anode simultaneously completes array substrate making step, is deposited described in one layer of filling on the flat organic layer
The transparent oxide of first via hole and the second via hole is as anode, and complete array substrate；
S13 production organic light emitting diodde desplay device simultaneously completes display panel making step, in the array substrate
Pixel defining layer, luminescent layer and cathode are successively made as the machine light emitting diodde desplay device, complete display panel.
The technical effects of the invention are that providing a kind of transistor, array substrate, display panel and its manufacturing method, lead to
It crosses and uses indium tin oxide material replacement prior art Mo material as the First Transition layer of the first copper film layer, be effectively improved gate electrode
Layer structure undercut problem, improves and overlaps situation with gate insulating layer, and gate electrode layer structure is made to have high bond strength, high electricity
The advantages of stability, low-resistivity, etching good compatibility.Further, the source-drain electrode layer in the gate electrode layer structure makes
Indium tin oxide material is used as the second transition zone of the second copper film layer, is effectively improved and overlaps situation with interlayer insulating film, reduce
Gate electrode layer structure and source-drain electrode layer short circuit probability of happening.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the gate electrode layer structure of first embodiment of the invention；
Fig. 2 is the structural schematic diagram of the array substrate of second embodiment of the invention；
Fig. 3 is the structural schematic diagram of the display panel of third embodiment of the invention；
Fig. 4 is the manufacturing flow chart of the display panel of four embodiment of the invention；
Fig. 5 is the manufacturing flow chart of the manufacturing step S13 of the display panel of fifth embodiment of the invention；
Fig. 6 is the structural schematic diagram of the manufacturing step S6-S8 of the display panel of sixth embodiment of the invention；
Fig. 7 is the structural schematic diagram of the manufacturing step S11 of the display panel of seventh embodiment of the invention.
Component mark is as follows in figure:
100 gate electrode layer structures, 200 array substrates,
10 substrates, 11 substrate of glass, 12 light shield layers, 13 buffer layers, 14 active layers, 15 gate insulating layers,
20 First Transition layers, 30 first copper film layers, 40 interlayer insulating films, 50 source-drain electrode layers,
60 passivation layers, 70 flat organic layers, 80 anodes, 90 organic light emitting diodde desplay devices,
31 photoresist layers, 51 source electrodes, 52 drain electrodes, 53 second transition zones, 54 second copper film layers,
61 first via holes, 71 second via holes, 91 pixel defining layers, 92 luminescent layers, 93 cathodes.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
Refering to Figure 1, providing a kind of transistor in one embodiment of the invention, including gate electrode layer structure 100 and position
Source-drain electrode layer 50 in the gate electrode layer structure 100, the gate electrode layer structure 100 include stack gradually substrate 10,
First Transition layer 20 and the first copper film layer 30, the First Transition layer 20 are constituted using indium tin oxide material.Use tin indium oxide
Material replaces First Transition layer 20 of the prior art Mo material as the first copper film layer 30, is effectively improved gate electrode layer structure 100
Undercut problem, so improve with 15 overlap joint situation of gate insulating layer, and make gate electrode layer structure 100 have high bond strength,
The advantages of high electrical stability, low-resistivity, etching good compatibility.
It please referring to shown in Fig. 2, the source-drain electrode layer 50 includes the second transition zone 53 and the second copper film layer 54 stacked gradually,
Second transition zone 53 is constituted using indium tin oxide material.Use indium tin oxide material as the second mistake of the second copper film layer 54
Cross layer 53, be effectively improved with 40 overlap joint situation of interlayer insulating film, reduce gate electrode layer structure 100 and the short circuit of source-drain electrode layer 50 sent out
Raw probability.
Wherein, the First Transition layer 20 with a thickness ofAnd/or first copper film layer 30 with a thickness ofThe range of its thickness can effectively realize the combination of gate electrode layer structure 100 and gate insulating layer 15, avoid stinging
The appearance of side problem.
Wherein, second transition zone 53 with a thickness ofAnd/or second copper film layer 54 with a thickness ofThe range of its thickness can effectively realize the combination of gate electrode layer structure 100 and interlayer insulating film 40, avoid
The appearance of undercut problem.
A kind of array substrate 200 is provided in one embodiment of the invention, including gate electrode layer structure described in any of the above-described kind
100.The gate electrode layer structure 100 of the array substrate 200 has high bond strength, high electrical stability, and low-resistivity etches simultaneous
The good advantage of capacitive.
Wherein, the substrate 10 successively includes substrate of glass 11, light shield layer 12, buffer layer 13, active layer 14 from bottom to up
With gate insulating layer 15.It successively include interlayer insulating film 40, the source-drain electrode layer 50, passivation in the gate electrode layer structure
Layer 60, flat organic layer 70 and anode 80.
Wherein, the material that the light shield layer 12 uses includes any or combinations thereof of Mo, Al, Cu or Ti；And/or institute
The material for stating the use of buffer layer 13 includes SiOx material；The buffer layer 13 with a thickness ofAnd/or it is described
The material that active layer uses includes metal oxide semiconductor material；The active layer with a thickness ofAnd/or institute
Stating on the first copper film layer 30 further includes interlayer insulating film 40；The material that the interlayer insulating film 40 uses includes SiOx material；Institute
State interlayer insulating film 40 with a thickness ofAnd/or the material that the passivation layer uses includes SiOx material, institute
State passivation layer with a thickness ofAnd/or the material that the flat organic layer uses includes photoresist, it is described
Flat organic layer with a thickness ofAnd/or the material that the anode uses includes transparent oxide material,
The anode with a thickness of
It please refers to shown in Fig. 3, a kind of display panel is provided in one embodiment of the invention, including battle array described in any of the above-described kind
Column substrate 200.
Wherein, the display panel further includes the pixel defining layer 91 being located in the array substrate 200, luminescent layer 92
And cathode 93.The material that the pixel defining layer 91 uses includes photoresist；The pixel defining layer 91 with a thickness of
It please refers to shown in Fig. 4, a kind of manufacturing method of display panel is provided in one embodiment of the invention, comprising steps of
S1 makes 12 step of light shield layer, provides a substrate of glass 11 and cleans, and one layer is deposited in the substrate of glass 11For the metal of thickness as light shield layer 12, the material that the light shield layer 12 uses includes appointing for Mo, Al, Cu or Ti
One kind or combinations thereof.
S2 makes 13 step of buffer layer, and one layer of SiOx material of deposition is described as buffer layer 13 on the light shield layer 12
Buffer layer 13 with a thickness of
S3 makes 14 step of active layer, and one layer of metal oxide semiconductor material is deposited on the buffer layer 13
(Oxide) it is used as active layer 14, the active layer 14 includes IGZO, IZTO or IGZTO；The active layer 14 with a thickness ofProcessing is patterned to the active layer 14.
S4 makes 15 step of gate insulating layer, and one layer of SiOx material is deposited on the active layer 14 as gate insulating layer
15, the gate insulating layer 15 with a thickness of
S5 makes 100 step of gate electrode layer structure, and indium oxide layer tin material is deposited on the gate insulating layer 15 and is made
For First Transition layer 20, the First Transition layer 20 with a thickness ofOne layer is deposited on the First Transition layer 20
Fine copper as the first copper film layer 30, first copper film layer 30 with a thickness of
S6 graphical treatment step forms photoresist layer 31 on first copper film layer 30, etches the light using yellow light
Resistance layer 31 is patterned processing；The first copper film layer 30 described in copper acid etching is closed using tetrahydroxy, etches described the using oxalic acid
One transition zone 20, etching forms 100 figure of gate electrode layer structure twice；Recycle 100 figure of gate electrode layer structure
Autoregistration etches exposed 14 both ends of active layer of the gate insulating layer 15；Remove the photoresist layer 31.
14 step of S7 corona treatment active layer, carrying out corona treatment to 14 both ends of active layer makes exposed metal
The resistance of oxide semiconductor material is substantially reduced to form conductor layer, as 52 contact jaw of source electrode 51 and drain electrode.
S8 makes 40 step of interlayer insulating film, and one layer of SiOx material is deposited in the gate electrode layer structure 100 as layer
Between insulating layer 40, the interlayer insulating film 40 with a thickness of
It please refers to shown in Fig. 6, is the structural schematic diagram during step S6-S8.
S9 makes 50 step of source-drain electrode layer, carries out aperture using yellow light in the interlayer insulating film 40, and deposit one layer of oxygen
Change indium tin material as the second transition zone 53, second transition zone 53 with a thickness ofIn second transition zone
One layer of fine copper is deposited on 53 as the second copper film layer 54, second copper film layer 54 with a thickness ofUtilize yellow light
Graphically make source electrode 51 and drain electrode 52.
S10 makes 60 step of passivation layer, and one layer of SiOx material is deposited on the source-drain electrode layer 50 as passivation layer 60, institute
State passivation layer 60 with a thickness ofAnd the first via hole 61 is etched, the bottom hole of first via hole 61 is described
Drain electrode 52.
S11 makes flat 70 step of organic layer, and one layer of photoresist is made on the passivation layer 60 as flat organic
Layer 70, the flat organic layer 70 with a thickness ofThe second via hole 71 is made by yellow light, described second
Via hole 71 is overlapped with first via hole 61.
It please refers to shown in Fig. 7, for the structural schematic diagram for completing step S11.
S12 production anode 80 simultaneously completes 200 making step of array substrate, deposits one layer on the flat organic layer 70 and fills out
The transparent oxide of first via hole 61 and the second via hole 71 is filled as anode 80, the preferred tin indium oxide material of the anode 80
Material, the anode 80 with a thickness ofThe array substrate that completes 200.
S13 production organic light emitting diodde desplay device 90 simultaneously completes display panel making step, in the array substrate
Pixel defining layer 91, luminescent layer 92 and cathode 93 are successively made on 200 is used as the machine light emitting diodde desplay device 90, production
Complete display panel.
It please refers to shown in Fig. 5, step S13 specifically comprises the following steps:
S131 makes 91 step of pixel defining layer, and one layer of photoresist is made in the array substrate 200 as pixel
Definition layer 91, the pixel defining layer 91 with a thickness ofLuminous zone is defined by yellow light, completes backboard production；
S132 makes 92 step of luminescent layer, and the pixel defining layer 91 on the backboard utilizes vapor deposition or inkjet printing
Mode makes luminescent layer 92；
S133 makes 93 step of cathode, and one layer of metal is made on the luminescent layer 92 as cathode 93, that is, completes display
The production of panel.
The technical effects of the invention are that providing a kind of transistor, array substrate, display panel and its manufacturing method, lead to
It crosses and uses indium tin oxide material replacement prior art Mo material as the First Transition layer of the first copper film layer, be effectively improved gate electrode
Layer structure undercut problem, improves and overlaps situation with gate insulating layer, and gate electrode layer structure is made to have high bond strength, high electricity
The advantages of stability, low-resistivity, etching good compatibility.Further, the source-drain electrode layer in the gate electrode layer structure makes
Indium tin oxide material is used as the second transition zone of the second copper film layer, is effectively improved and overlaps situation with interlayer insulating film, reduce
Gate electrode layer structure and source-drain electrode layer short circuit probability of happening.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of transistor, the source-drain electrode layer including gate electrode layer structure and in the gate electrode layer structure, feature exist
In the gate electrode layer structure includes the substrate stacked gradually, First Transition layer and the first copper film layer, and the First Transition layer is adopted
It is constituted with indium tin oxide material.
2. transistor according to claim 1, which is characterized in that the source-drain electrode layer includes the second transition stacked gradually
Layer and the second copper film layer, second transition zone are constituted using indium tin oxide material.
3. transistor according to claim 1, which is characterized in that
The First Transition layer with a thickness ofAnd/or
First copper film layer with a thickness of
4. transistor according to claim 2, which is characterized in that
Second transition region thickness isAnd/or
Second copper film layer with a thickness of
5. a kind of array substrate, including the transistor any one of as described in claim 1-4.
6. array substrate according to claim 5, which is characterized in that the substrate successively includes glass base from bottom to up
Bottom, light shield layer, buffer layer, active layer and gate insulating layer；In the gate electrode layer structure successively include interlayer insulating film,
The source-drain electrode layer, passivation layer, flat organic layer and anode.
7. array substrate according to claim 6, which is characterized in that the material that the light shield layer uses includes Mo, Al, Cu
Or Ti's is any or combinations thereof；And/or
The material that the buffer layer uses includes SiOx material, the buffer layer with a thickness ofAnd/or
The material that the active layer uses includes metal oxide semiconductor material, the active layer with a thickness of
And/or
The material that the interlayer insulating film uses includes SiOx material, the interlayer insulating film with a thickness of
And/or
The material that the passivation layer uses includes SiOx material, the passivation layer with a thickness ofAnd/or
The material that the flat organic layer uses includes photoresist, the flat organic layer with a thickness ofAnd/or
The material that the anode uses includes transparent oxide material, the anode with a thickness of
8. a kind of display panel, including array substrate as claimed in claim 5.
9. display panel according to claim 8, which is characterized in that further include that the pixel being located in the array substrate is determined
Adopted layer, luminescent layer and cathode；The material that the pixel defining layer uses includes photoresist, the pixel defining layer with a thickness of
10. a kind of manufacturing method of the display panel as described in claim 8 or 9, which is characterized in that comprising steps of
S1 makes light shield layer step, provides a substrate of glass and cleans, and deposits one layer of metal on the glass substrate as screening
Photosphere；
S2 makes buffer layer step, and one layer of SiOx material is deposited on the light shield layer as buffer layer；
S3 makes active layer step, and one layer of metal oxide semiconductor material of deposition is right as active layer on the buffer layer
The active layer is patterned processing；
S4 makes gate insulating layer step, deposits one layer of SiOx material on the active layer as gate insulating layer；
S5 makes gate electrode layer configuration steps, deposits indium oxide layer tin material on the gate insulating layer as First Transition
Layer, the First Transition layer with a thickness ofOne layer of fine copper is deposited on the First Transition layer as the first copper film
Layer, first copper film layer with a thickness of
S6 graphical treatment step forms photoresist layer on first copper film layer, etches the photoresist layer using yellow light and carries out
Graphical treatment；The first copper film layer described in copper acid etching is closed using tetrahydroxy, etches the First Transition layer using oxalic acid, twice
Etching forms the gate electrode layer structure graph；The gate electrode layer structure graph autoregistration is recycled, it is exhausted to etch the grid
The exposed active layer both ends of edge layer；Remove the photoresist layer；
S7 corona treatment active layer step oxidizes metal object to active layer both ends progress corona treatment and partly leads
Body forms conductor layer, as source electrode and drain electrode contact jaw；
S8 makes interlayer insulating film step, and one layer of SiOx material is deposited in the gate electrode layer structure as interlayer insulating film；
S9 makes source-drain electrode layer step, carries out aperture using yellow light in the interlayer insulating film, and deposit indium oxide layer tin material
Material is used as the second transition zone, and second transition region thickness isOne layer of deposition is pure on second transition zone
Copper as the second copper film layer, second copper film layer with a thickness ofGraphically made using yellow light source electrode and
Drain electrode；
S10 makes passivation layer step, one layer of SiOx material is deposited on the source-drain electrode layer as passivation layer, and etch first
Via hole, the bottom hole of first via hole are the drain electrode；
S11 makes flat organic layer step, and one layer of photoresist is made on the passivation layer as flat organic layer, passes through Huang
Light makes the second via hole, and second via hole is overlapped with first via hole；
S12 production anode simultaneously completes array substrate making step, and one layer of filling described first is deposited on the flat organic layer
The transparent oxide of via hole and the second via hole is as anode, and complete array substrate；
S13 production organic light emitting diodde desplay device simultaneously completes display panel making step, in the array substrate successively
Pixel defining layer, luminescent layer and cathode are made as the machine light emitting diodde desplay device, complete display panel.
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| CN111403488A (en) * | 2020-03-31 | 2020-07-10 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, substrate for display and display device |
| CN111403488B (en) * | 2020-03-31 | 2024-03-29 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, display substrate and display device |
| CN113064298A (en) * | 2021-03-01 | 2021-07-02 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
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