TWI569421B - Pixel structure and method of making the same - Google Patents

Description

Pixel structure and its making method

The present invention relates to a pixel structure and a method of fabricating the same, and more particularly to a pixel structure in which a source/drain and an oxide semiconductor layer are connected by a connection electrode and a fabrication method thereof.

A thin film transistor (TFT) device is a semiconductor component widely used in display panels, for example, a liquid crystal display panel (LCD panel), an organic light emitting diode display (organic light emitting diode display) Panel, OLED display panel) and electronic paper (E-paper) and other display panels. The electron mobility of the thin film transistor element directly affects the switching speed of the thin film transistor element, and thus has a large influence on the display picture quality.

At present, the thin film transistor component of the display panel can be mainly divided into an amorphous silicon TFT (a-Si TFT) device, a polycrystalline silicon transistor (poly silicon TFT) device, and the like according to the semiconductor layer material used. An oxide semiconductor thin film transistor element. Amorphous germanium thin film transistor components are limited to the use of amorphous germanium semiconductor materials, so their electron mobility is low (currently, the amorphous germanium thin film transistor components have an electron mobility of about 1 cm 2 /Vs or less), so they cannot be seen at present. The future needs for higher specification displays. Polycrystalline germanium thin film transistors benefit from the properties of their polycrystalline germanium materials and have a significant improvement in electron mobility (the electron mobility of polycrystalline germanium thin film transistors is optimally up to about 100 cm 2 /Vs). However, the process of polycrystalline germanium thin film transistor components is complicated (relatively costly), and there is a problem of poor uniformity of crystallinity in the application of large-sized panels. Therefore, polycrystalline germanium thin film transistor components are still applied in small-sized panels. Mainly. The oxide semiconductor thin film transistor element is a newly emerging oxide semiconductor material in recent years, and such a material is generally an amorphous crystal lattice structure, and is not applied to the problem of poor uniformity on a large-sized panel, and Films can be formed in a variety of ways, such as sputtering, spin-on, and printing, so that the process is more flexible than the amorphous germanium film transistor. The electron mobility of the oxide semiconductor thin film transistor element is generally 10 times higher than that of the amorphous germanium thin film transistor (the electron mobility of the oxide semiconductor thin film transistor is generally between 10 cm 2 /Vs and 50 cm 2 /Vs), This level has met the needs of the currently available high-profile display panels.

However, in an oxide semiconductor thin film transistor element, if the contact resistance between the source/drain and the oxide semiconductor layer is too large, the performance of the thin film transistor element is lowered and the high electron mobility property cannot be effectively exhibited. It is necessary to lower the contact resistance between the oxide semiconductor layer and the source/drain electrodes so that the oxide semiconductor thin film transistor element exhibits characteristics of high electron mobility.

One of the objects of the present invention is to provide a pixel structure and a method of fabricating the same to enhance the element characteristics of a thin film transistor element having a pixel structure.

One embodiment of the present invention provides a pixel structure including a substrate, a thin film transistor element, a first protective layer, and a first pixel electrode. The thin film transistor component is disposed on the substrate, and the thin film transistor component comprises an oxide semiconductor layer, a gate insulating layer, a gate, a first connection electrode, a second connection electrode, a dielectric layer, and a source. Extreme and a bungee. The oxide semiconductor layer is disposed on the substrate, and the oxide semiconductor layer has a channel region, and a first contact region and a second contact region are respectively located on opposite sides of the channel region. The gate insulating layer is disposed on the oxide semiconductor layer, and the upper surface of the gate insulating layer covering the channel region does not cover an upper surface of the first contact region and an upper surface of the second contact region. The gate is disposed on the gate insulating layer. First connecting electrode and second The connection electrodes are respectively disposed on two sides of the gate insulating layer, the first connection electrode covers the upper surface of the first contact region and is in contact with the upper surface of the first contact region, and the second connection electrode covers the upper surface of the second contact region and Contacting the upper surface of the second contact region, wherein the first connection electrode and the second connection electrode are not overlapped with the gate insulating layer in a vertical projection direction. The dielectric layer is disposed on the gate, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially covering an upper surface of the first connection electrode, and a second contact hole is at least partially The upper surface of one of the second connection electrodes is not covered. The source and the drain are disposed on the dielectric layer, wherein the source is electrically connected to the first connection electrode via the first contact hole, and the drain is electrically connected to the second connection electrode via the second contact hole. The first protective layer is disposed on the dielectric layer, wherein the first protective layer has a third contact hole, at least partially not covering the drain. The first pixel electrode is disposed on the first protective layer, wherein the first pixel electrode is electrically connected to the drain of the thin film transistor element via the third contact hole.

Another embodiment of the present invention provides a method of fabricating a pixel structure comprising the following steps. Providing a substrate, and forming a patterned oxide semiconductor layer on the substrate, wherein the patterned oxide semiconductor layer comprises an oxide semiconductor layer, and the oxide semiconductor layer has a channel region, and a first contact region and a first The two contact areas are respectively located on opposite sides of the channel area. An insulating layer and a first conductive layer are sequentially formed on the substrate and the patterned oxide semiconductor layer. Forming a patterned masking layer on the first conductive layer, wherein the patterned masking layer partially covers the first conductive layer. Removing the first conductive layer exposed by the patterned shielding layer to form a first patterned conductive layer, and removing the insulating layer exposed by the patterned shielding layer to form a patterned insulating layer, wherein the patterned insulating layer comprises a a gate insulating layer, the gate insulating layer covers an upper surface of the channel region and exposes an upper surface of the first contact region and an upper surface of the second contact region, and the first patterned conductive layer includes a gate at the gate On the pole insulation layer. A second conductive layer is formed on the substrate exposed by the patterned shielding layer, the upper surface of the first contact region of the oxide semiconductor layer, and the upper surface of the second contact region. Performing a detachment process while removing the patterned shielding layer and the second conductive layer on the patterned shielding layer to form a second patterned conductive layer, wherein the second patterned conductive layer includes a first connecting electrode and a second Connecting electrodes are respectively formed on the upper surface of the first contact region and the upper surface of the second contact region in a self-aligning manner, and the first connection electrode and the second connection electrode are not in a vertical projection direction with the gate insulating layer Overlap. Forming a dielectric layer on the gate, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially exposing an upper surface of the first connection electrode, and a second contact hole A portion of the upper surface of the second connection electrode is partially exposed. Forming a third patterned conductive layer on the dielectric layer, wherein the third patterned conductive layer includes a source and a drain, the source is electrically connected to the first connection electrode via the first contact hole, and the drain is via The second contact hole is electrically connected to the second connection electrode. A first protective layer is formed on the dielectric layer, wherein the first protective layer has a third contact hole, at least partially exposing the drain. A first pixel electrode is formed on the first protective layer.

10‧‧‧Substrate

10S‧‧‧Switching element area

10C‧‧‧ Storage Capacitor Area

10P‧‧‧Photo District

12‧‧‧ Buffer layer

14‧‧‧ patterned oxide semiconductor layer

14S‧‧‧Oxide semiconductor layer

14C‧‧‧Channel area

141‧‧‧First contact area

142‧‧‧Second contact area

14B‧‧‧ storage capacitor lower electrode

16‧‧‧Insulation

161‧‧‧First insulating film

162‧‧‧Second insulation film

18‧‧‧First conductive layer

20‧‧‧ patterned masking layer

201‧‧‧First masking layer

202‧‧‧Second shelter

22‧‧‧First patterned conductive layer

24‧‧‧ patterned insulation

GI‧‧‧ gate insulation

CD‧‧‧capacitor dielectric layer

14X‧‧‧ upper surface

14Y‧‧‧Upper surface

14Z‧‧‧ upper surface

G‧‧‧ gate

22T‧‧‧ storage capacitor upper electrode

Cst‧‧‧ storage capacitor components

26‧‧‧Second conductive layer

28‧‧‧Second patterned conductive layer

281‧‧‧First connecting electrode

282‧‧‧Second connection electrode

Z‧‧‧Vertical projection direction

283‧‧‧ conductive pattern

30‧‧‧Dielectric layer

TH1‧‧‧ first contact hole

TH2‧‧‧Second contact hole

32‧‧‧ Third patterned conductive layer

S‧‧‧ source

D‧‧‧汲

TFT‧‧‧thin film transistor components

34‧‧‧First protective layer

TH3‧‧‧ third contact hole

36‧‧‧ first pixel electrode

50‧‧‧ pixel structure

38‧‧‧Second protective layer

38A‧‧‧ openings

40‧‧‧Display media layer

42‧‧‧Second pixel electrode

44‧‧‧ Display elements

60‧‧‧ pixel structure

70‧‧‧ pixel structure

A‧‧‧ curve

A’‧‧‧ Curve

B‧‧‧ Curve

B’‧‧‧ Curve

C‧‧‧ Curve

C’‧‧‧ Curve

D‧‧‧ Curve

D’‧‧‧ Curve

E‧‧‧ curve

E’‧‧‧ Curve

1 to 8 are schematic views showing a method of fabricating a pixel structure according to a first embodiment of the present invention.

9 and 10 illustrate schematic views of a pixel structure for fabricating a second embodiment of the present invention.

Figure 11 is a schematic view showing the pixel structure of a comparative embodiment of the present invention.

Fig. 12 is a view showing the relationship between the gate voltage V _G and the gate current I _D of the thin film transistor device of the pixel structure of the comparative example of the present invention.

Figure 13 is a graph showing the relationship between the gate voltage V _G and the drain current I _D of the thin film transistor device of the pixel structure of the present invention.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, .

Please refer to Figures 1 to 8. 1 to 8 are schematic views showing a method of fabricating a pixel structure according to a first embodiment of the present invention. As shown in Fig. 1, a substrate 10 is first provided. The substrate 10 may be a transparent substrate, and may be a rigid substrate or a flexible substrate such as a glass substrate, a quartz substrate or a plastic substrate, but is not limited thereto. The substrate 10 may have a switching element region 10S, a storage capacitor region 10C, and a pixel region 10P. Next, a buffer layer 12 can be selectively formed on the substrate 10. The buffer layer 12 may have an insulating property, and the material thereof may be an inorganic insulating material such as cerium oxide, tantalum nitride or cerium oxynitride, but not limited thereto, the material of the buffer layer 12 may also be an organic insulating material. Further, the buffer layer 12 may be a single layer structure or a composite layer structure. Subsequently, a patterned oxide semiconductor layer 14 is formed on the substrate 10. If the buffer layer 12 is present, the patterned oxide semiconductor layer 14 is formed on the buffer layer 12. The material of the patterned oxide semiconductor layer 14 may include, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide. (indium tin oxide, ITO), zinc oxide (ZnO), indium oxide (InO), (indium tin zinc oxide, ITZO), gallium oxide (GaO) or other suitable oxide semiconductor material. The patterned oxide semiconductor layer 14 may have an amorphous structure, and it may be formed using, for example, sputtering, spin coating, printing, or other suitable means. The patterned oxide semiconductor layer 14 includes an oxide semiconductor layer 14S disposed in the switching element region 10S, wherein the oxide semiconductor layer 14S has a channel region 14C, and a first contact region 141 and a second contact region 142 are respectively Located on opposite sides of the channel region 14C. In this embodiment, the channel region 14C, the first contact region 141, and the second contact region 142 are located on the same plane, and the two ends of the channel region 14C are respectively structurally connected to the first contact region 141 and the second contact region 142. The connection, that is, the channel region 14C, the first contact region 141, and the second contact region 142 are respectively a part of the oxide semiconductor layer 14S. In addition, the patterned oxide semiconductor layer 14 further includes a storage capacitor lower electrode 14B disposed in the storage capacitor region 10C of the substrate 10.

As shown in FIG. 2, an insulating layer 16 and a first conductive layer 18 are sequentially formed on the substrate 10 and the patterned oxide semiconductor layer 14. The material of the insulating layer 16 may be an inorganic insulating material such as cerium oxide, cerium nitride or cerium oxynitride, but is not limited thereto. In this embodiment, the insulating layer 16 may be a composite insulating layer, which may include a first insulating film 161 and a second insulating film 162, wherein the first insulating film 161 is formed on the patterned oxide semiconductor layer 14, and the second insulating film 162 Then formed on the first insulating film 161. The first insulating film 161 and the second insulating film 162 may be composed of the same material, wherein the first insulating film 161 may be formed using a low temperature process, whereby the patterned oxide semiconductor layer 14 may be prevented from being destroyed by high temperature, and the second insulating film 162 may be avoided. It can be formed by a high temperature process, whereby it can have better insulation properties and structural strength. In a variant embodiment, the insulating layer 16 can also be a single insulating layer. In addition, the material of the first conductive layer 18 may include a transparent conductive material, such as a metal oxide conductive material (such as indium tin oxide), an opaque conductive material, such as: metal such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum / molybdenum, an alloy of the above metals or other suitable metal or alloy, but not limited thereto. The first conductive layer 18 may be a single layer structure or a composite layer structure.

As shown in FIG. 3, a patterned masking layer 20 is then formed on the first conductive layer 18 to partially cover the first conductive layer 18. The patterned masking layer 20 can be, for example, a photoresist layer, which can be patterned by an exposure and development process, but is not limited thereto. The patterned shielding layer 20 can include a first shielding layer 201 and a second shielding layer 202, wherein the first shielding layer 201 is located in the switching element region 10S of the substrate 10 and covers the channel corresponding to the patterned oxide semiconductor layer 14. The first conductive layer 18 is above the region 14C, and the second shielding layer 202 is located in the storage capacitor region 10C of the substrate 10 and covers the first conductive layer 18 corresponding to the upper portion of the storage capacitor lower electrode 14B. In this embodiment, the size of the first shielding layer 201 is substantially equal to the size of the channel region 14C of the patterned oxide semiconductor layer 14, and the size of the second shielding layer 202 is slightly smaller than the size of the storage capacitor lower electrode 14B, but not This is limited to this. For example, in a variant embodiment, the size of the second masking layer 202 can be equal to the size of the storage capacitor lower electrode 14B. Subsequently, the first conductive layer 18 exposed by the patterned masking layer 20 is removed to form a first patterned conductive layer 22, and the insulating layer 16 exposed by the patterned masking layer 20 is removed to form a patterned insulating layer 24. . The patterned insulating layer 24 includes a gate insulating layer GI and a capacitor dielectric layer CD, wherein the gate insulating layer GI is located in the switching element region 10S and covers the upper surface 14X of the channel region 14C and exposes the first contact region 141. Upper surface 14Y and second contact area 142 above Face 14Z; the capacitor dielectric layer CD is located in the storage capacitor region 10C and partially covers the storage capacitor lower electrode 14B. In this embodiment, the gate insulating layer GI and the capacitor dielectric layer CD are respectively stacked by the first insulating film 161 and the second insulating film 162, but not limited thereto. The first patterned conductive layer 22 includes a gate G and a storage capacitor upper electrode 22T, wherein the gate G is located in the switching element region 10S and is located on the gate insulating layer GI; the storage capacitor upper electrode 22T is located in the storage capacitor region 10C. It is located on the storage capacitor lower electrode 14B. The storage capacitor lower electrode 14B, the storage capacitor upper electrode 22T, and the capacitor dielectric layer CD interposed between the storage capacitor lower electrode 14B and the storage capacitor upper electrode 22T constitute a storage capacitor element Cst. In addition, the first patterned conductive layer 22 may further include a gate line (not shown) electrically connected to the gate G, or other necessary wires such as a common line (not shown). In this embodiment, the first conductive layer 18 exposed by the patterned shielding layer 20 is removed to form the first patterned conductive layer 22 and the insulating layer 16 exposed by the patterned masking layer 20 is removed to form a patterned insulating layer. The step of 24 is performed using the patterned masking layer 20 as an etch mask and using an etching process. For example, the etching process may use an anisotropic etching process such as a dry etching process, so that the pattern of the gate G and the pattern of the gate insulating layer GI are substantially equal, that is, the sidewall of the gate G and the gate insulating layer GI The side walls will be substantially aligned, but not limited to this.

As shown in FIG. 4, subsequently formed on the substrate 10 exposed by the patterned shielding layer 20, the upper surface 14Y of the first contact region 141 of the oxide semiconductor layer 14, and the upper surface 14Z of the second contact region 142. A second conductive layer 26. That is, the upper surface 14Y of the first contact region 141 of the oxide semiconductor layer 14 exposed by the first shielding layer 201 and the upper surface 14Z of the second contact region 142 are exposed by the second shielding layer 202. A second conductive layer 26 is formed on a portion of the upper surface of the storage capacitor lower electrode 14B and on the substrate 10 (or the buffer layer 12). The material of the second conductive layer 26 may include a transparent conductive material such as a metal oxide conductive material (for example, indium tin oxide), an opaque conductive material such as a metal such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum/molybdenum. The alloy of the above metal or other suitable metal or alloy, but not limited thereto. The second conductive layer 26 may be a single layer structure or a composite layer structure. The thickness of the second conductive layer 26 can be adjusted depending on the material. Example For example, if the material of the second conductive layer 26 is made of a metal such as molybdenum, the thickness may be substantially between 50 angstroms and 200 angstroms, but not limited thereto; if the material of the second conductive layer 26 is A transparent conductive material, such as indium tin oxide, may be used to be thicker than metal, for example, greater than 200 angstroms, but not limited thereto.

As shown in FIG. 5, a lift-off process is then performed while removing the patterned masking layer 20 and the second conductive layer 26 on the patterned masking layer 20 to form a second patterned conductive layer. 28. The second patterned conductive layer 28 includes a first connection electrode 281 and a second connection electrode 282 formed on the upper surface 14Y of the first contact region 141 and the second contact region in a self-aligning manner. 142 is on the upper surface 14Z, and the first connection electrode 281 and the second connection electrode 282 are not overlapped with the gate insulating layer GI in the vertical projection direction Z. To be precise, the sidewalls of the first connection electrode 281 and the sidewalls of the second connection electrode 282 may be substantially aligned with the sidewalls of the gate insulating layer GI and completely cover the upper surface 14Y of the first contact region 141 and the second The upper surface 14Z of the contact region 142. In addition, the second patterned conductive layer 28 further includes a conductive pattern 283 disposed on at least one side (eg, both sides) of the capacitor dielectric layer CD and partially covering the storage capacitor lower electrode 14B, thereby reducing the storage capacitor lower electrode 14B. The resistance. When the material of the second conductive layer 26 is selected from a metal oxide such as indium tin oxide, the first connection electrode 281 and the second connection electrode 282 are metal oxide conductive electrodes such as indium oxide electrodes; when the second conductive layer 26 is When the material is a metal or an alloy, the first connection electrode 281 and the second connection electrode 282 are metal electrodes such as an aluminum electrode, a titanium/aluminum/titanium electrode, a molybdenum electrode, or a molybdenum/aluminum/molybdenum electrode. As can be seen from the above, the first connection electrode 281 and the second connection electrode 282 are formed by simultaneously removing the patterned shielding layer 20 and the second conductive layer 26 on the patterned shielding layer 20 by a lift-off process. The patterned shielding layer 20 itself also has the function of defining the pattern and position of the gate G and the gate insulating layer GI. Therefore, the method of the embodiment has the effect of self-alignment, that is, the gate G and the gate are insulated. The layer GI and the relative positions of the first connection electrode 281 and the second connection electrode 282 are fixed, and can ensure that the first connection electrode 281 completely covers the upper surface 14Y of the first contact region 141, and the second connection electrode 282 is completely covered. second The upper surface 14Z of the contact region 142 does not overlap the first connection electrode 281 and the second connection electrode 282 with the gate insulating layer GI or the gate G in the vertical projection direction Z.

As shown in FIG. 6, after the first connection electrode 281, the second connection electrode 282 and the conductive pattern 283 are left, and other unnecessary portions of the second patterned conductive layer 28 are removed, for example, on the substrate 10 or the buffer layer 12. The second patterned conductive layer 28. Then, a dielectric layer 30 is formed on the gate G, the first connection electrode 281 and the second connection electrode 282, and a first contact hole TH1 is formed in the dielectric layer 30 to at least partially expose the first connection electrode 281. The upper surface 281S, and a second contact hole TH2 at least partially expose the upper surface 282S of the second connection electrode 282. The dielectric layer 30 can have a planarized surface to facilitate subsequent film formation. The material of the dielectric layer 30 may be an organic dielectric material or an inorganic dielectric material, and the dielectric layer 30 may be a single layer structure or a composite layer structure.

As shown in FIG. 7, a third patterned conductive layer 32 is then formed over the dielectric layer 30. The third patterned conductive layer 32 includes a source S and a drain D, wherein the source S is in contact with and electrically connected to the first connection electrode 281 via the first contact hole TH1, and the drain D is via the second contact hole TH2. The second connection electrode 282 is in contact with and electrically connected to form the thin film transistor element TFT of the present embodiment. The material of the third patterned conductive layer 32 may include a transparent conductive material such as a metal oxide conductive material (such as indium tin oxide), an opaque conductive material such as a metal such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum / molybdenum, an alloy of the above metals or other suitable metal or alloy, but not limited thereto. In addition, the third patterned conductive layer 32 may be a single layer structure or a composite layer structure. In addition, the third patterned conductive layer 32 may further include a data line (not shown) electrically connected to the source S, or other necessary wires. A first protective layer 34 is then formed on the dielectric layer 30, wherein the first protective layer 34 has a third contact hole TH3 that at least partially exposes the drain D. The first protective layer 34 can have a planarized surface to facilitate subsequent film formation. The material of the first protective layer 34 may be an organic insulating material or an inorganic insulating material, and the first protective layer 34 may be a single layer structure or a composite layer structure.

As shown in FIG. 8, a first pixel electrode 36 is formed on the first protective layer 34 to form the pixel structure 50 of the present embodiment, wherein the first pixel electrode 36 is located in the pixel region 10P and extends to the switch. The element region 10S is in contact with and electrically connected to the drain D of the thin film transistor element TFT via the third contact hole TH3. In the present embodiment, the pixel structure 50 is applied to an organic electroluminescent display panel, and thus may further include the following steps. A second protective layer 38 is formed on the first protective layer 34, wherein the second protective layer 38 has an opening 38A located in the pixel region 10P and at least partially exposing the first pixel electrode 36. The material of the second protective layer 38 may be an organic insulating material or an inorganic insulating material, and the second protective layer 38 may be a single layer structure or a composite layer structure. Thereafter, a display dielectric layer 40 is formed in the opening 38A of the second protective layer 38, wherein the display dielectric layer 40 is an organic electroluminescent layer. Finally, a second pixel electrode 42 is formed on the display dielectric layer 40. The first pixel electrode 36 and the second pixel electrode 42 may respectively form, for example, an anode and a cathode, and form a display element 44 with the display medium layer 40, wherein the display element 44 is an organic electroluminescent element such as an organic light emitting diode element. One of the first pixel electrode 36 and the second pixel electrode 42 is a penetrating electrode, and the other may be a reflective electrode or a penetrating electrode. For example, if the display element 44 is an upper illumination type display element, the first pixel electrode 36 is a reflective electrode and the second pixel electrode 42 is a penetration electrode; if the display element 44 is a bottom emission type display element, the first The pixel electrode 36 is a penetrating electrode, and the second pixel electrode 42 is a reflective electrode. If the display element 44 is a double-sided light emitting type display element, the first pixel electrode 36 and the second pixel electrode 42 may both be worn. Through the electrode. Further, a film layer such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer may be selectively formed between the first pixel electrode 36 and the second pixel electrode 42 as needed.

The pixel structure 50 of the embodiment is not limited to be applied to an organic electroluminescent display panel, and can be applied to other self-illuminating or non-self-illuminating display panels, such as a liquid crystal display panel, an electrophoretic display panel, and an electric Wet the display panel or other suitable display panels. If the pixel structure 50 is to be applied to other types of display panels, other corresponding solid or liquid film layers such as a liquid crystal layer, an electrophoretic layer or a hydrophilic/hydrophobic mixed liquid may be selected. Wherein, when the display medium layer 40 is In the case of a non-emissive material or other self-luminous material, at least one of the second protective layer 38 and the second pixel electrode 42 may be selectively disposed.

The pixel structure of the present invention and the method of fabricating the same are not limited to the above embodiments. The pixel structure of the other preferred embodiments of the present invention and its manufacturing method will be sequentially described below, and the same symbols are used in the following embodiments for the convenience of comparing the differences of the embodiments and simplifying the description. The components are mainly described for the differences between the embodiments, and the repeated portions are not described again.

Please refer to Figure 9 and Figure 10. 9 and 10 illustrate schematic views of a pixel structure for fabricating a second embodiment of the present invention. Unlike the first embodiment, in the present embodiment, the sidewall of the gate G is shrunk to the sidewall of the gate insulating layer GI. Referring to FIG. 9 and FIG. 9 , as shown in FIG. 9 , in the embodiment, the steps of forming the first patterned conductive layer 22 and forming the patterned insulating layer 24 are performed by using the patterned shielding layer 20 as an etching. The mask is implemented using an isotropic etching process such as a wet etch process. Therefore, although both the pattern of the gate G and the gate insulating layer GI use the patterned mask layer 20 as an etch mask, the pattern of the gate G and the pattern of the gate insulating layer GI may be different. That is, since the gate G is located above the gate insulating layer GI, the etching time of the gate G is longer than the etching time of the gate insulating layer GI, so a part of the sidewall of the gate G is in the etching gate insulating layer. The GI continues to be etched away, and the sidewall of the gate G is shrunk to the sidewall of the gate insulating layer GI after etching. Similarly, the sidewall of the storage capacitor upper electrode 22T is also constricted to the sidewall of the capacitor dielectric layer CD. Then, the steps disclosed in FIGS. 4 to 8 are sequentially performed to form the pixel structure 60 of the present embodiment, as shown in FIG. It should be noted that, since the first connection electrode 281 and the second connection electrode 282 are formed by using the lift-off process to simultaneously remove the patterned shielding layer 20 and the second conductive layer 26 on the patterned shielding layer 20, the gate is formed. The retracting side wall of G can more effectively ensure that no short circuit occurs between the gate G and the first connection electrode 281 / the second connection electrode 282 after the detachment process.

The method of making a pixel structure of the present invention has the following advantages:

1. The source S and the drain D are respectively in contact with the first contact region 141 of the patterned oxide semiconductor layer 14 and the second contact region 142 via the first connection electrode 281 and the second connection electrode 282, and thus are selectable and patterned. The oxide semiconductor layer 14 has a material that is preferably in contact to reduce the resistance, thereby increasing the electron mobility of the thin film transistor element TFT.

2. Since the first connection electrode 281 and the second connection electrode 282 are formed by the detachment process, the self-alignment effect is obtained without a registration error, and the source S and the drain D are respectively connected via the first connection electrode. 281 and the second connection electrode 282 and the first contact region 141 of the patterned oxide semiconductor layer 14 are in contact with the second contact region 142, so even if the first contact hole TH1 and the second contact hole TH2 generate a process offset, The element characteristics are affected because of the asymmetry of the contact positions of the source S/drain D and the first contact region 141 of the patterned oxide semiconductor layer 14 and the second contact region 142.

3. Since the first contact hole TH1 and the second contact hole TH2 expose the first connection electrode 281 and the second connection electrode 282 instead of exposing the patterned oxide semiconductor layer 14, the patterned oxide semiconductor layer 14 does not The process of etching the dielectric layer 30 is damaged, and the material of the dielectric layer 30 is not limited by its greater selectivity to the etching selectivity of the patterned oxide semiconductor layer 14.

4. The fabrication method of the present invention uses three layers of patterned conductive layers (including the first patterned conductive layer 22, the second patterned conductive layer 28 and the third patterned conductive layer 32) as compared to conventional fabrication methods. The two layers of patterned conductive layer have greater design flexibility.

Please refer to Figure 11. Figure 11 is a schematic view showing the pixel structure of a comparative embodiment of the present invention. As shown in Fig. 11, in the pixel structure 70 of the comparative embodiment, the first contact The hole TH1 and the second contact hole TH2 directly expose the patterned oxide semiconductor layer 14, and the source S and the drain D are in contact with the second contact via the first contact hole TH1 and the second contact hole TH2 and the first contact region 141, respectively. Zone 142 is in direct contact. The pixel structure 70 of this comparative embodiment has the following disadvantages:

1. The source S/dip D is directly in contact with the patterned oxide semiconductor layer 14, and thus the source S/drain D is in poor contact with the patterned oxide semiconductor layer 14.

2. When the dielectric layer 30 is etched to form the first contact hole TH1 and the second contact hole TH2, dry etching cannot be used, otherwise the patterned oxide semiconductor layer 14 may be damaged, and also in the case of using wet etching. The choice of material for dielectric layer 30 is limited, for example, materials that are etched using hydrofluoric acid cannot be used.

3. When the positions of the first contact hole TH1 and the second contact hole TH2 are offset due to process variation, the source S/drain D corresponding to the gate G may form an asymmetrical structure for the thin film transistor element. Component characteristics have a great impact.

Please refer to Figure 12 and Figure 13 again. 12 is a diagram showing a relationship between a gate voltage V _G and a gate current I _D of a pixel transistor device of a pixel structure according to a comparative example of the present invention, and FIG. 13 is a view showing a pixel structure of the present invention. A plot of the gate voltage V _{G of the} thin film transistor element and the drain current I _D . Figure 12 is a graph showing the relationship between the gate voltage V _G and the drain current I _D of a sample of three identically sized thin film transistor elements of the comparative example, wherein the curve A is the sample 1 at the drain voltage V _D = 0.1V. As a result of the measurement, the curve A' is the result of the sample 1 measured at the drain voltage V _D = 10 V, and the curve B is the result of the sample 2 measured at the drain voltage V _D = 0.1 V, and the curve B' is Sample 2 is the result measured at the drain voltage V _D =10V, curve C is the result of sample 3 measured at the drain voltage V _D =0.1V, and curve C' is the sample 3 at the drain voltage V _D =10V The measured result. As shown in Fig. 12, it can be clearly seen from the curve AC that the gate voltage V _G and the drain current I of the thin film transistor element of the sample 1-3 even at the same drain voltage V _D = 0.1 V The relationship of _D has significant differences. Similarly, it can be clearly seen from the curve A'-C' that the gate voltage V _G and the drain current I _D of the thin film transistor element of the sample 1-3 even at the same gate voltage V _D = 10 V The relationship also has significant differences. In addition, the threshold voltage of the thin film transistor element of Samples 1-3 also had a significant difference. Therefore, it can be confirmed from the measurement results of Fig. 12 that the thin film transistor element of the comparative example is inferior in element uniformity and element characteristics in the case where the connection electrode is not provided. Fig. 13 is a view showing the relationship between the gate voltage V _G and the gate current I _D of the samples of the two thin film transistor elements of the present embodiment, wherein the sample 4 is made of molybdenum having a film thickness of 50 angstroms as a connection electrode. While sample 5 uses molybdenum with film thickness = 100 angstroms as the connection electrode, curve D is the result of sample 4 measured at the drain voltage V _D = 0.1 V, and curve D' is the sample 4 at the drain voltage V _D = The result measured by 5V, curve E is the result of sample 5 measured at the drain voltage V _D = 0.1V, and curve E' is the result of sample 5 measured at the drain voltage V _D = 5V. As shown in Figure 13, at different drain voltages (V _D ) (for example, V _D = 5V or V _D = 0.1V), the threshold voltage of the thin film transistor elements of samples 4-5 is almost identical. It was confirmed that the thin film transistor element of the present embodiment has good element uniformity and element characteristics. Further, since the film thickness of the connection electrode of the sample 5 is larger than the film thickness of the connection electrode of the sample 4, the resistance of the connection electrode of the sample 5 is lower than that of the connection electrode of the sample 4, and it can be seen from the same in Fig. 13 The gate current I _D of sample 5 (curve E or curve E') is significantly higher than the gate current I of sample 4 (curve E or curve E') at the gate voltage V _G and the drain voltage V _{D D.} It was confirmed that the arrangement of the connection electrodes can change the element characteristics of the thin film transistor element, and the smaller the resistance of the connection electrode, the larger the gate current I _D . It is worth noting that when selecting the film thickness of the connection electrode, in addition to its influence on the gate current I _D of the thin film transistor element, it should be considered together whether the second conductive layer is easily removed during the separation process. .

In summary, the pixel structure of the present invention utilizes a connection electrode to connect the source/drain and the oxide semiconductor layer, thereby effectively avoiding the disadvantage that the source/drain directly contacts the oxide semiconductor layer, thereby effectively improving the thin film transistor component. Component characteristics.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Substrate

10S‧‧‧Switching element area

10C‧‧‧ Storage Capacitor Area

10P‧‧‧Photo District

12‧‧‧ Buffer layer

14‧‧‧ patterned oxide semiconductor layer

14S‧‧‧Oxide semiconductor layer

14C‧‧‧Channel area

141‧‧‧First contact area

142‧‧‧Second contact area

14B‧‧‧ storage capacitor lower electrode

16‧‧‧Insulation

161‧‧‧First insulating film

162‧‧‧Second insulation film

22‧‧‧First patterned conductive layer

24‧‧‧ patterned insulation

GI‧‧‧ gate insulation

CD‧‧‧capacitor dielectric layer

14X‧‧‧ upper surface

14Y‧‧‧Upper surface

14Z‧‧‧ upper surface

G‧‧‧ gate

22T‧‧‧ storage capacitor upper electrode

Cst‧‧‧ storage capacitor components

28‧‧‧Second patterned conductive layer

281‧‧‧First connecting electrode

282‧‧‧Second connection electrode

Z‧‧‧Vertical projection direction

283‧‧‧ conductive pattern

30‧‧‧Dielectric layer

TH1‧‧‧ first contact hole

TH2‧‧‧Second contact hole

32‧‧‧ Third patterned conductive layer

S‧‧‧ source

D‧‧‧汲

TFT‧‧‧thin film transistor components

34‧‧‧First protective layer

TH3‧‧‧ third contact hole

36‧‧‧ first pixel electrode

38‧‧‧Second protective layer

38A‧‧‧ openings

40‧‧‧Display media layer

42‧‧‧Second pixel electrode

44‧‧‧ Display elements

60‧‧‧ pixel structure

Claims (18)

A pixel structure includes: a substrate; a thin film transistor component disposed on the substrate, the thin film transistor component comprising: an oxide semiconductor layer disposed on the substrate, the oxide semiconductor layer having a channel region And a first contact region and a second contact region are respectively located on opposite sides of the channel region; a gate insulating layer is disposed on the oxide semiconductor layer, and the gate insulating layer covers one of the channel regions The surface does not cover an upper surface of the first contact region and an upper surface of the second contact region; a gate is disposed on the gate insulating layer; a first connecting electrode and a second connecting electrode respectively Provided on both sides of the gate insulating layer, the first connection electrode covers the upper surface of the first contact region and is in contact with the upper surface of the first contact region, and the second connection electrode covers the second contact The upper surface of the region is in contact with the upper surface of the second contact region, wherein the first connection electrode and the second connection electrode are not overlapped with the gate insulating layer in a vertical projection direction; a dielectric layer, Set on a gate, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially covering an upper surface of the first connection electrode, and a second contact hole is at least partially An upper surface of the second connection electrode is disposed; and a source and a drain are disposed on the dielectric layer, wherein the source is electrically connected to the first connection electrode via the first contact hole, and the The first protective layer is disposed on the dielectric layer, wherein the first protective layer has a third contact hole, at least partially not covering the Bungee jumping; A first pixel electrode is disposed on the first protective layer, wherein the first pixel electrode is electrically connected to the drain of the thin film transistor element via the third contact hole. The pixel structure of claim 1, wherein the first connection electrode and the second connection electrode do not overlap the gate in the vertical projection direction. The pixel structure of claim 1, wherein one of the sidewalls of the gate is recessed to a sidewall of the gate insulating layer. The pixel structure of claim 1, wherein the first connection electrode and the second connection electrode comprise metal electrodes. The pixel structure of claim 1, wherein the first connection electrode and the second connection electrode comprise metal oxide conductive electrodes. The pixel structure of claim 1, further comprising: a display medium layer disposed on the first pixel electrode; and a second pixel electrode disposed on the display medium layer. The pixel structure of claim 6, wherein the display medium layer is an organic electroluminescent layer. The pixel structure of claim 6, further comprising a second protective layer disposed on the first protective layer, wherein the second protective layer has an opening at least partially covering the first pixel electrode, and The display medium layer is disposed in the opening of the second protective layer. The pixel structure of claim 1, further comprising a storage capacitor element disposed on the substrate, wherein the storage capacitor element comprises: a storage capacitor lower electrode is disposed on the substrate; a capacitor dielectric layer is disposed on the lower electrode of the storage capacitor and partially covers an upper surface of the storage capacitor lower electrode; a storage capacitor upper electrode is disposed on the capacitor And a conductive pattern disposed on at least one side of the capacitor dielectric layer and partially covering the upper surface of the storage capacitor lower electrode. The pixel structure of claim 9, wherein the storage capacitor lower electrode and the oxide semiconductor layer are composed of the same patterned oxide semiconductor layer, and the capacitor dielectric layer and the gate insulating layer are the same a patterned insulating layer, wherein the storage capacitor upper electrode and the gate are formed by the same patterned conductive layer, and the conductive pattern, the first connecting electrode and the second connecting electrode are patterned by the same layer The conductive layer is composed of. A method for fabricating a pixel structure, comprising: providing a substrate; forming a patterned oxide semiconductor layer on the substrate, wherein the patterned oxide semiconductor layer comprises an oxide semiconductor layer, and the oxide semiconductor layer has a The channel region, and a first contact region and a second contact region are respectively located on opposite sides of the channel region; an insulating layer and a first conductive layer are sequentially formed on the substrate and the patterned oxide semiconductor layer; Forming a patterned shielding layer on the first conductive layer, wherein the patterned shielding layer partially covers the first conductive layer; removing the first conductive layer exposed by the patterned shielding layer to form a first patterned a conductive layer, and removing the insulating layer exposed by the patterned shielding layer to form a patterned insulating layer, wherein the patterned insulating layer comprises a gate insulating layer covering one of the channel regions Surface and exposing an upper surface of the first contact region and the second connection An upper surface of the contact region, and the first patterned conductive layer includes a gate on the gate insulating layer; the first of the oxide semiconductor layer on the substrate exposed by the patterned shielding layer Forming a second conductive layer on the upper surface of the contact region and the upper surface of the second contact region; performing a lift-off process while removing the patterned mask layer and located in the patterned mask The second conductive layer on the layer to form a second patterned conductive layer, wherein the second patterned conductive layer comprises a first connecting electrode and a second connecting electrode, respectively, in a self-aligning manner Formed on the upper surface of the first contact region and the upper surface of the second contact region, and the first connection electrode and the second connection electrode are not overlapped with the gate insulating layer in a vertical projection direction Forming a dielectric layer on the gate, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially exposing an upper surface of the first connection electrode, and a second contact hole is at least partially violent Exposing an upper surface of the second connection electrode; and forming a third patterned conductive layer on the dielectric layer, wherein the third patterned conductive layer comprises a source and a drain, the source a contact hole is electrically connected to the first connection electrode, and the drain is electrically connected to the second connection electrode via the second contact hole; a first protection layer is formed on the dielectric layer, wherein the first layer The protective layer has a third contact hole at least partially exposing the drain; and a first pixel electrode is formed on the first protective layer. The method of fabricating a pixel structure according to claim 11, wherein the first connection electrode and the second connection electrode system and the gate do not overlap in the vertical projection direction. The method of fabricating a pixel structure according to claim 11, wherein the step of removing the first conductive layer exposed by the patterned shielding layer to form the first patterned conductive layer comprises using an isotropic The etching etches a sidewall of one of the gates to a sidewall of the gate insulating layer. The method of fabricating a pixel structure according to claim 11, wherein the first connection electrode and the second connection electrode comprise metal electrodes. The method of fabricating a pixel structure according to claim 11, wherein the first connection electrode and the second connection electrode comprise a metal oxide conductive electrode. The method for fabricating a pixel structure according to claim 11, further comprising: forming a second protective layer on the first protective layer, wherein the second protective layer has an opening at least partially exposing the first pixel An electrode is formed in the opening of the second protective layer; and a second pixel electrode is formed on the display dielectric layer. The method of fabricating a pixel structure according to claim 16, wherein the display medium layer is an organic electroluminescent layer. The method of fabricating a pixel structure according to claim 11, wherein the patterned oxide semiconductor layer further comprises a storage capacitor lower electrode, the patterned insulating layer further comprising a capacitor dielectric layer disposed on the storage capacitor lower electrode The first patterned conductive layer further includes a storage capacitor upper electrode disposed on the capacitor dielectric layer, and the second patterned conductive layer further includes a conductive pattern disposed on at least one side of the capacitor dielectric layer Partially covering the lower electrode of the storage capacitor.