CN103346093A - Top grid self-alignment thin-film transistor with source/drain areas raised and manufacturing method thereof - Google Patents
Top grid self-alignment thin-film transistor with source/drain areas raised and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a top grid self-alignment thin-film transistor with source/drain areas raised and a manufacturing method of the top grid self-alignment thin-film transistor with the source/drain areas raised. The manufacturing method includes the steps that an oxide semiconductor active layer, a grid dielectric layer and a grid electrode are sequentially formed on glass or a flexible substrate, and the thickness of the oxide semiconductor active layer is 5-20 nanometers in order to reduce influences of short-wavelength light on off-state characteristics of the thin-film transistor; then grid dielectric is corroded with the grid electrode as a stopping layer, the active layer corresponding to the grid dielectric is made to serve as a channel region, the active layers on the two sides are a source area and a drain area respectively, and self-alignment is achieved; next, low-resistivity conductive thin films are deposited, and the raised source area and the raised drain area are formed after photoetching, stripping or corrosion. The thin channels are adopted and the source area and the drain area are raised, not only are the influences of the light on the channels reduced, but also the resistance of the source area and the resistance of the drain area are reduced, and performance of the thin-film transistor is improved.
Description
Technical field
The present invention relates to top-gate thin-film transistors and preparation method thereof, especially the top grid autoregistration thin-film transistor raised of source/drain region relates generally to the manufacture method of raising source region and drain region.
Background technology
Thin-film transistor is the core devices in the flat panel display as the integrated component of switch control element or peripheral driving circuit.The thin-film transistor that is widely adopted at present mainly contains amorphous silicon film transistor and polycrystalline SiTFT.Amorphous silicon (a-Si) thin-film transistor be widely used in the flat panel display drive circuit or as switch control device.But the mobility of amorphous silicon is low, is usually less than 1cm
2/ VS, the polysilicon uniformity is poor, and complex process cost height to the visible light sensitivity, is worked under the radiation of visible light again, is difficult to large scale and high-resolution flat panel display.In recent years, oxide semiconductor thin-film transistor receives much concern, indium gallium zinc oxide (IGZO) semi-conducting material especially, and its mobility ratio is bigger, good uniformity, technological temperature is low, at visible region light transmittance height, and is applicable to flexible the demonstration.
At present, amorphous oxide semiconductor (AOS) is paid close attention to widely and is studied, as indium tin oxide (ITO), aluminium zinc oxide (AZO), indium-zinc oxide (IZO), indium gallium zinc oxide (IGZO), wherein indium gallium zinc oxide (IGZO) is that be studied more also is more potential.Mainly there are two problems in the thin-film transistor of bottom grating structure; the one, the control of back of the body channel etching (BCE); back of the body channel etching influences channel device because of over etching easily; unfavorable to thin-film transistor performance; though can adopt etching protective layer (ES) to solve this problem, adopt the etching protective layer can increase the complexity of technology.The 2nd, bottom gate thin film transistor is difficult for realizing autoregistration, there is compatibility issue in the back-exposure technology with present technology, and traditional manufacture method can cause existing in the bottom gate thin film transistor bigger overlapping region, produce bigger overlap capacitance, not in order to reducing channel dimensions, big overlap capacitance also can reduce the operating rate of drive circuit, is difficult to use in to drive high-resolution active matrix organic light-emitting diode (AMOLED) display.
Top-gate thin-film transistors can solve the problem and shortage that bottom gate thin film transistor exists; at first; there is not the over etching damage problem in top-gate thin-film transistors, and the gate dielectric layer in the top-gate thin-film transistors can play the effect of protection active layer on active layer.Secondly, top gate structure has the self aligned advantage of realization, technology is simple relatively, plasma treatment is carried out in pair source/leakage that has commonly used, in source/drain region, mix hydrogen with the conductivity in increase source/drain region, adopt self-alignment structure can avoid overlapping region, do not have overlap capacitance, the channel dimensions of thin-film transistor can be controlled more accurately, and short raceway groove can be realized.
But when in top gate structure, being active layer with the oxide semiconductor, when penetrating the channel region oxide semiconductor layer, the short illumination of wavelength can cause that the off-state current of thin-film transistor increases problem.Though the oxide semiconductor of broad stopband is to visible transparent, but when being reduced to ultraviolet region, optical wavelength still has the absorption problem, oxide semiconductor can cause the film transistor device off-state current obviously to increase to the absorption of short-wavelength light, reduce the switching characteristic of thin-film transistor, increase energy consumption.
Summary of the invention
In order to address the above problem, can adopt the thin channel minimizing to the absorption of short-wavelength light, make the charge carrier of channel layer depleted easily simultaneously, thin-film transistor can better be turn-offed, cut-off current is less.But when adopting thin channel in the thin-film transistor of top grid self-alignment structure, it is very thin that source/drain region can become equally, and thinner source/drain region can increase the resistance in source region and drain region, reduces output current.
In order in the grid self-alignment structure of top, to adopt thin channel to reduce the resistance in source/drain region simultaneously, the invention provides thin-film transistor of the top grid self-alignment structure of raising in one provenance/drain region and preparation method thereof.This method can guarantee to form autoregistration between grid and the source/drain region, and raises source/drain region to reduce the resistance in source region and drain region.
The thin-film transistor of the top grid self-alignment structure that raise in source/drain region that the inventive method is made possesses: be formed at the oxide semiconductor thin-film on the substrate (substrate), as active layer; Cover the gate dielectric layer of aforesaid semiconductor film; The gate electrode that forms on aforementioned gate dielectric layer, gate electrode are the metal oxide of metal or conduction; The source region links to each other with raceway groove with the drain region, is all the active layer oxide semiconductor thin-film, lays respectively at left side and the right side of channel region; Finish aforesaid oxide semiconductor thin-film, gate medium, after the grid, the conductive film of deposit one deck low-resistivity, conductive film can be the metal oxide of metal or low-resistivity, utilizes the method for wet etching or dry etching to remove low-resistivity conductive film outside source region and the drain region, therefore, the conductive film that remains in source region and drain region has been raised source region and drain region, reduces source region and drain region resistance.
The manufacture method of above-mentioned thin-film transistor may further comprise the steps:
1) at substrate growth one deck oxide semiconductor thin-film, as active layer, through removing corresponding to the part that forms outside the thin-film transistor after photoetching and the etching, forms island areas then;
2) growth one deck gate medium on active layer;
3) the opaque metal of deposit one deck on gate dielectric layer forms grid;
4) be that etching is carried out to gate dielectric layer in the barrier layer with the grid, make gate dielectric layer identical with gate patterns, then the active layer of grid correspondence is channel region, and the left and right sides is respectively source region and drain region;
5) conductive film of growth one deck low-resistivity by the part outside wet etching or the method removal source region of peeling off and the drain region, only keeps the low-resistivity conductive layer in source region and drain region, raises source region and drain region;
6) enter the later process of transistor fabrication at last, generally comprise deposit passivation layer, opening contact hole, growing metal, photoetching and etching metal form contact electrode then.
In the above-mentioned manufacture method, the substrate of step 1) can be glass substrate or flexible substrate.
In the above-mentioned manufacture method, the active layer of step 1) can be indium gallium zinc oxide (IGZO), aluminium zinc oxide (AZO), indium-zinc oxide oxide semiconductors such as (IZO), and film is amorphous state or polycrystalline attitude, adopts the magnetron sputtering technique growth.Target is ceramic target, and purity is 99.99%.
In the above-mentioned manufacture method, step 2) gate dielectric layer of growing can be dielectrics such as silicon nitride and/or silica, is formed by plasma reinforced chemical vapor deposition (PECVD) method; Also can be metal oxide dielectric such as aluminium oxide and/or hafnium oxide, be formed by magnetically controlled sputter method.
In the above-mentioned manufacture method, the metallic film that step 3) is grown is generally molybdenum, chromium, titanium or aluminium etc., is formed by magnetically controlled sputter method or thermal evaporation method
In the above-mentioned manufacture method, the low-resistivity conductive film that step 5) is grown can be metal such as titanium, aluminium, chromium, molybdenum, the employing dc magnetron sputtering method forms, also can be the metal oxide of low-resistivity such as tin indium oxide (ITO), aluminum zinc oxide (AZO), boron oxide zinc transparent conductive oxides such as (BZO), adopt radio frequency magnetron sputtering method to form.
In the above-mentioned manufacture method, the later process of step 6) is one deck passivation dielectric layer of growing earlier, photoetching and etching form the fairlead of grid, source and leakage, the layer of conductive film of growing then, photoetching and etching form electrode, the conductive film of wherein growing, can be general metal material, as molybdenum, chromium, titanium or aluminium etc., also can be transparent conductive film, as tin indium oxide (ITO) etc.
The objective of the invention is to utilize thin channel to reduce the oxide semiconductor channel layer to the absorption of light, reduce short wavelength's light to the influence of oxide semiconductor thin-film transistor off-state current, raise source/drain region simultaneously to reduce the resistance in source region and drain region, be conducive to obtain big output current.
In order to reach the purpose that source-drain area is raised, according to the present invention, in aforementioned thin-film transistor manufacturing process steps, the technology of step 5) can be realized by following method.
Method one, in previous process steps 4) finish after, performing step 5) method is as follows: the conductive film of deposit one deck low-resistivity at first, apply photoresist, utilize the reticle identical with active area, the method of employing wet etching or etching is removed the conductive film outside the active area figure, apply negative photoresist again, be that the mask version is exposed by the glass substrate back side with opaque grid, after the development, the photoresist of top portions of gates is removed, and remainder is covered by photoresist, utilizes wet etching that conductive film is handled then, erode cover on grid and the part gate dielectric layer conductive film, do not contact with grid until conductive film, the conductive film that then retains has just realized that source/leakage raises, and has reduced the resistance in source region and drain region.
Method two, performing step 5) method is as follows: after step 4) is finished, apply one deck positive photoresist at device surface, expose by the glass substrate back side, the photoresist of top portions of gates is kept, removing of remainder, heat the regular hour at a certain temperature, make photoresist be subjected to thermal softening, has certain fluidity, photoresist can be along grid, gate dielectric layer is dirty, by control heating-up temperature and time, can make photoresist flow down part effectively cover gate and part gate dielectric layer, conductive film of deposit one deck low-resistivity on this along grid and gate dielectric layer, peel off the photoresist that is covered in grid and gate dielectric layer then, expose grid.Apply photoresist on this basis again, adopt the source-drain area reticle, source-drain area is covered by photoresist, utilize wet etching or dry etching to remove not by the conductive film of the photoresist area of coverage then, then the conductive film in source region and drain region remains, effectively raise source/drain region height, reduced the resistance in source region and drain region.
Advantage of the present invention and good effect: the thin-film transistor that preparation method of the present invention makes can be realized the autoregistration in source/drain region, be the both sides that are distributed in raceway groove of source region and drain region symmetry, channel region is to be determined by grid technology, grid and source/drain region do not have overlapping, there is not parasitic capacitance, ghost effect can be effectively avoided, also the short channel thin-film transistor can be made.The thin-film transistor of the present invention's preparation adopts thin channel, can reduce the oxide semiconductor raceway groove effectively to the absorption of short-wavelength light, effectively reduced the influence of short-wavelength light to the thin-film transistor off-state current, improve the pass step response of thin-film transistor, avoided illumination to cause that off-state current increases and the problem of energy consumption increase.Simultaneously, source region and drain region are raised, can reduce the resistance in source region and drain region effectively, when adopting thin channel and do not increase the resistance in source/drain region.
Description of drawings
Fig. 1-Figure 13 shows the main manufacturing process steps among two embodiment of the present invention successively.Wherein,
Fig. 1 has illustrated the processing step that oxide semiconductor active layer forms.
Fig. 2 has illustrated the processing step that gate dielectric layer forms.
Fig. 3 has illustrated the processing step that grid forms.
Fig. 4 has illustrated autoregistration to form the processing step in source region and drain region.
Fig. 5 has illustrated deposit low-resistivity conductive film and form the processing step of figure.
It is that the mask version is carried out back-exposure to negative photoresist that Fig. 6 has illustrated among the embodiment one with the grid, removes the processing step of top portions of gates photoresist after the development.
Fig. 7 has illustrated the processing step of wet etching low-resistivity conductive film among the embodiment one.
It is that the mask version is carried out back-exposure to positive photoetching rubber that Fig. 8 has illustrated among the embodiment two with the grid, and the back of developing forms the processing step of photoresist figure at top portions of gates.
Fig. 9 has illustrated photoresist among the embodiment two to be subjected to form after the thermal softening processing step of figure.
Figure 10 has illustrated the processing step of deposit low-resistivity conductive film among the embodiment two.
Figure 11 has illustrated to remove the processing step that raise in photoresist opisthogenesis/drain region among embodiment one, the embodiment two.
Figure 12 has illustrated the processing step of deposit passivation layer and opening contact hole among embodiment one, the embodiment two.
Figure 13 has illustrated deposited metal among embodiment one, the embodiment two and draw the processing step of contact electrode.
Embodiment
Below by embodiment, further describe the present invention by reference to the accompanying drawings.
Embodiment one:
In the present embodiment its profile of the thin-film transistor of made as shown in figure 11, this thin-film transistor is produced on the glass substrate 1, comprises an active layer 2, one gate dielectric layers 3, one gate electrodes 4, the source region 7 of raising and drain region 8.Wherein, the corresponding active layer of grid district is channel region, and the channel region left and right sides is respectively source region and drain region, source region and drain region raise the part on active layer, lay respectively at the left and right sides of gate dielectric layer.Active layer 2 is positioned on the glass substrate 1, and active layer comprises the channel region of gate electrode correspondence and source region and the drain region of channel region both sides; Gate dielectric layer 3 is positioned on the active layer 2; Gate electrode 4 is positioned on the gate dielectric layer 3; The source region 7 of raising and the drain region 8 of raising lay respectively on active layer source region and the drain region left and right sides of gate dielectric layer 3.
Thin-film transistor manufacture method instantiation described in the present embodiment as Fig. 1-Fig. 7 and Figure 11-shown in Figure 13, comprises following manufacturing process steps successively:
As shown in Figure 1, used substrate is transparency glass plate, utilizes the indium gallium zinc oxide (IGZO) of magnetron sputtering method growth 5～10 nanometer thickness at glass plate, and used target is that purity is 99.99% ceramic target, utilizes photoetching and etching to form active layer 2 then.
As shown in Figure 2, on active layer and glass substrate, adopt the silicon oxide film of plasma-reinforced chemical vapor deposition (PECVD) method growth one deck 150-300 nanometer thickness, as gate medium 3.
As shown in Figure 3, on the gate medium silica, adopt the metal titanium membrane of magnetron sputtering method growth one deck 100～200 nanometer thickness, photoetching and etching form gate electrode 4 then.
As shown in Figure 4, be the method etching gate dielectric layer 3 that plasma etching (RIE) is adopted on the barrier layer with the gate electrode, make the figure of gate medium identical with grid, then active layer 2 zones that covered by gate medium 3 are channel region, while gate electrode and source region and drain region do not have overlapping, form self-alignment structure.
As shown in Figure 5, adopt the transparent conductive film tin indium oxide (ITO) of magnetron sputtering method deposit one deck 50～100 nanometer thickness, and carry out photoetching with the active area reticle, obtain the figure identical with active area 5, target is that purity is 99.99% ceramic target.
As shown in Figure 6, on indium and tin oxide film, apply one deck negative photoresist, be the mask version with opaque grid, from glass back expose (the arrow direction is the exposure light incident direction Fig. 6), the photoresist of top portions of gates is removed after developing, and remainder is covered by photoresist 6.
As shown in Figure 7, utilize finite concentration watery hydrochloric acid corrosion oxidation indium tin transparent conductive film, the tin indium oxide that is covered on grid and the part gate dielectric layer is corroded, and the tin indium oxide conductive film that remains has formed source region 7 and the drain region 8 of raising, and does not contact with grid.
As shown in figure 11, adopt the ultrasonic removal of acetone to raise photoresist 6 on the source-drain area, expose the source region 7 of raising and the drain region 8 of raising.
As shown in figure 12, the passivation layer silica 9 of plasma-reinforced chemical vapor deposition (PECVD) growth one deck 100～300 nanometers, photoetching and etching form the contact hole of grid, source electrode, drain electrode then.
As shown in figure 13, with the metal titanium membrane of magnetically controlled sputter method deposit one deck 100～300 nanometer thickness, photoetching and be etched into the metal extraction electrode 10,11,12 of each electrode of thin-film transistor then.
Embodiment two:
In the present embodiment its profile of the thin-film transistor of made as shown in figure 11, with identical among the embodiment one, as previously mentioned.
The instantiation of the manufacture craft of thin-film transistor is successively as Fig. 1-Fig. 4 and Fig. 8-shown in Figure 13 in the present embodiment.The technology manufacture method of Fig. 1-Fig. 4 and Figure 12-Figure 13 describes in detail in embodiment one.Different among the manufacture craft of Fig. 8 in the present embodiment-shown in Figure 11 and the embodiment one, describe in detail below:
As shown in Figure 8, at surface-coated one deck positive photoresist, advance as mask with opaque grid, expose from the back side of glass substrate (the arrow direction is the exposure light incident direction Fig. 8), the photoresist 6 that is positioned at top portions of gates after the development remains.This photoresist 6 is positive glue, has certain thermal endurance and flowability.
As shown in Figure 9, sheet glass is placed baking oven, heat the regular hour at a certain temperature, make photoresist 6 softening flowing, photoresist flows downward to gate dielectric layer along gate side, and the gate dielectric layer of cover part.
As shown in figure 10, adopt the transparent conductive film tin indium oxide thing (ITO) 5 of magnetron sputtering method deposit one deck 50～100 nanometer thickness, target is that purity is 99.99% ceramic target.
As shown in figure 11, adopt the ultrasonic photoresist that peels off top portions of gates and side of acetone, remove indium tin oxide outside the source-drain area with photoetching and etch again, the indium tin oxide that retains is the source region 7 of raising and the drain region 8 of raising.
Although disclose specific embodiments of the invention and accompanying drawing for the purpose of illustration, its purpose is to help to understand content of the present invention and implement according to this, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.The present invention should not be limited to this specification most preferred embodiment and the disclosed content of accompanying drawing, and the scope of protection of present invention is as the criterion with the scope that claims define.
Claims (10)
1. the manufacture method of a top grid autoregistration thin-film transistor, its step comprises:
1) grows the monoxide semiconductor layer as active layer in substrate, after photoetching and etching, form island areas;
2) gate dielectric layer of on active layer, growing;
3) deposit one deck opaque metal on gate dielectric layer forms grid;
4) be that etching is carried out to gate dielectric layer in the barrier layer with the grid, make gate dielectric layer identical with gate patterns, the active layer of grid correspondence is channel region, and the active layer of channel region both sides is respectively source region and drain region;
5) conductive film of growth one deck low-resistivity, and remove its part outside source region and drain region, realize raising source region and drain region;
6) carry out the subsequent handling of transistor fabrication.
2. the method for claim 1, it is characterized in that, the implementation method of described step 5) is: apply photoresist at the conductive film that forms, utilize the reticle identical with active area then, the method for employing wet etching or dry etching is removed the conductive film outside the active area figure; Applying negative photoresist again, is that the mask version is exposed from backside of substrate with opaque grid, and the photoresist of the back top portions of gates that develops is removed, and remainder is covered by photoresist; Utilize wet etching to remove to cover the conductive film on grid and the part gate dielectric layer then, do not contact with grid until conductive film.
3. the method for claim 1 is characterized in that, the implementation method of described step 5) is: apply one deck positive photoresist at device surface, expose from backside of substrate then, the photoresist of the back top portions of gates that develops is retained; Make photoresist be subjected to thermal softening and dirty along grid, gate dielectric layer, cover gate and part gate dielectric layer by heating; The conductive film of deposit one deck low-resistivity peels off the photoresist that is covered in grid and gate dielectric layer then, exposes grid; Apply photoresist again, adopt the source-drain area reticle, source-drain area is covered by photoresist; Utilize wet etching or dry etching to remove the conductive film that is not covered by photoresist then.
4. as each described method in the claim 1 to 3, it is characterized in that: the described oxide semiconductor layer of step 1) is the metal oxide semiconductor films of amorphous or polycrystalline, adopts the magnetron sputtering technique growth, and its thickness is 5～20 nanometers.
5. as each described method in the claim 1 to 3, it is characterized in that: step 2) using plasma strengthens the chemical vapor deposition method grown silicon nitride and/or silica forms described gate dielectric layer, perhaps adopts magnetically controlled sputter method growth aluminium oxide and/or hafnium oxide to form described gate dielectric layer.
6. as each described method in the claim 1 to 3, it is characterized in that: the described metal of step 3) is molybdenum, chromium, titanium or aluminium, adopts the growth of thermal evaporation or magnetically controlled sputter method.
7. as each described method in the claim 1 to 3, it is characterized in that: the conductive film of the described low-resistivity of step 5) is the transparent conductive metal oxide that adopts the magnetically controlled sputter method growth, or adopts the metal of magnetically controlled sputter method growth.
8. as each described method in the claim 1 to 3, it is characterized in that: in the step 5) source region and drain region raise the part thickness be 50～150 nanometers.
9. as each described method in the claim 1 to 3, it is characterized in that the described subsequent handling of step 6) comprises: the deposit passivation layer, opening contact hole forms contact electrode and interconnection.
10. the top grid autoregistration thin-film transistor raised of the source/drain region that makes according to each described method in the claim 1 to 9.
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