CN109993243A - A kind of commodity counterfeit prevention traceability system based on transparent membrane RFID chip - Google Patents
A kind of commodity counterfeit prevention traceability system based on transparent membrane RFID chip Download PDFInfo
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- CN109993243A CN109993243A CN201910164029.6A CN201910164029A CN109993243A CN 109993243 A CN109993243 A CN 109993243A CN 201910164029 A CN201910164029 A CN 201910164029A CN 109993243 A CN109993243 A CN 109993243A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
- G06K17/0022—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisious for transferring data to distant stations, e.g. from a sensing device
- G06K17/0029—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisious for transferring data to distant stations, e.g. from a sensing device the arrangement being specially adapted for wireless interrogation of grouped or bundled articles tagged with wireless record carriers
Abstract
The invention discloses a kind of commodity counterfeit prevention traceability systems based on transparent membrane RFID chip.RFID chip includes transparent membrane substrate and the chip layout in transparent membrane substrate, chip layout includes rectification circuit, modulation circuit, Digital Logical Circuits, antenna and tuning circuit, all-transparent thin film transistor (TFT) in the circuit of chip layout is all made of ZnO-TFT device, bridging commodity seal both ends after label is made in RFID chip, label is destroyed while commodity packaging convenient for opening, the identification code that RFID chip is written in advance can by dedicated reader or have NFC function mobile phone read, and the encapsulation of commodity is carried out by network data base, storage, outbound, the record of the information such as sale and inquiry.The present invention applies stable transparent RFID chip, and technical barrier is high, it is difficult to copy；Transparent membrane substrate easily ruins unrepairable and does not influence exterior of commodity, and dedicated reader uses cryptographic protocol and algorithm, is complete set, difficult duplication, the not reproducible anti-counterfeiting system utilized, can be applied to the anti-fake of all kinds of commodity.
Description
Technical field
The present invention relates to anti-fake and RFID chip designing techniques, are based on transparent membrane substrate RFID core more particularly, to one kind
The commodity counterfeit prevention traceability system of piece.
Background technique
RFID chip is widely used in the fields such as gate inhibition, payment, logistics, identification, anti-fake in recent years.Currently on the market
RFID chip mostly be silicon chip, transparent membrane chip belongs to newer field, and the mechanism or company studied in the world are few.
Commodity counterfeit prevention is broadly divided into destructive anti-counterfeit, honorable optically variable anti-counterfeiting and the several types such as RFID chip is anti-fake at present.
Destructive anti-counterfeit refers to that the movement for opening sealing can destroy commodity packaging or the appendicular technology of packaging simultaneously, can effectively prevent packing
Be recycled, do not need yet additionally increase consumer learning cost, but be unfavorable for commodity preservation and safety coefficient it is low.Light
Color optically variable anti-counterfeiting refers to prints light popular form of narrative literature flourishing in the Tang Dynasty word or pattern in packaging, and difference can be presented under different angle, different illumination conditions
Color, technical difficulty is lower, easily forges, the method and feature that consumer needs additional studies anti-fake.Anti-fake RFID chip is to wrap
Dress seals attached RFID chip, and with card reader or handset identity chip information with anti-fake, RFID chip mostly uses papery chip, holds
Destructible, can be simultaneously as a part of destructive anti-counterfeit.But existing RFID label tag is due to using silicon base chip, although antenna
It is easily destroyed, but chip is difficult to destroyed, therefore exists and is read hidden danger with secondary use.Generally using more in practical application
The mode of the anti-pseudocaustics method of kind increases reliability.
Summary of the invention
In order to solve the problems in background technique, the present invention provides a kind of quotient based on transparent membrane substrate RFID chip
The anti-fake traceability system of product, the present invention apply stable transparent RFID chip, and technical barrier is high, it is difficult to copy；Transparent membrane substrate
Easily ruin unrepairable and do not influence exterior of commodity, dedicated reader uses cryptographic protocol and algorithm, be complete set, difficult duplication,
The not reproducible anti-counterfeiting system utilized, can be applied to the anti-fake of all kinds of commodity.
The present invention adopts the following technical scheme:
RFID chip of the invention includes transparent membrane substrate and the chip layout in transparent membrane substrate, chip version
Figure includes rectification circuit, modulation circuit, Digital Logical Circuits, antenna and tuning circuit, and rectification circuit is connected by tuning circuit
Antenna, rectification circuit are connected through Digital Logical Circuits with modulation circuit；
All-transparent thin film transistor (TFT) in the circuit of chip layout is all made of ZnO-TFT device, ZnO-TFT device include according to
The secondary ITO source region layer being formed in transparent membrane substrate, the drain region ITO layer, ZnO layer, the first Al2O3Layer, the 2nd Al2O3Layer, ITO
Grid region layer and barrier layer, ITO source region layer, the drain region ITO layer are located at ZnO-TFT bottom device two sides and in same layer；ZnO
Layer middle section, which is embedded in downwards between ITO source region layer and the drain region ITO layer, forms rectangle recess, and ZnO layer two sides sink respectively
Product is in ITO source region layer, the drain region ITO layer upper surface；First Al2O3Layer is deposited on ZnO layer upper surface and equally also has rectangle recessed
It falls into, twoth Al identical as ZnO layer structure2O3Layer middle section is covered in the first Al2O3Layer upper surface and the 2nd Al2O3Layer is intermediate
The first Al of the downwardly convex covering of portion lower surface2O3Layer intermediate recess, the 2nd Al2O3Layer two sides extend respectively into ITO source region layer,
The drain region ITO layer upper surface；ITO source region layer and the drain region ITO layer upper surface middle part are respectively from the 2nd Al2O3Distinguish after being pierced by layer two sides
In the first Al2O3Inverted L shape protrusion is formed on layer；The grid region ITO layer is laid in the 2nd Al2O3Among layer upper surface；The grid region ITO layer two
The side side barrier layer Jun You, barrier layer are isolated with the grid region ITO layer, and the inverted L shape that two barrier layers are located at ITO source region layer is convex
Rise and the 2nd Al2O3The upper surface of layer, the inverted L shape protrusion of the drain region ITO layer and the 2nd Al2O3The upper surface of layer, two barrier layers are leaned on
The inside of the nearly grid region ITO layer respectively with the first Al2O3The two sides of layer are vertically concordant.
The transparent membrane substrate uses the materials such as glass, PET, PI.
The preparation process of the ZnO-TFT device is as follows:
S1: the ITO of one layer of 200nm is deposited in transparent membrane substrate after cleaning as source-drain electrode layer, in source-drain electrode layer
Upper surface spin coating photoresist, in source after being denaturalized using on photo-etching machine exposal transition diagram to transparent membrane substrate, photoresist dissolves
Etching forms a part of ITO source region layer and the drain region ITO layer on drain electrode layer；
S2: atomic layer deposition ALD equipment is used to deposit ZnO film as ZnO layer on ITO source region layer and the drain region ITO layer；
Annealing and depositing Al in ZnO layer upper surface2O3Film is as the first Al2O3Layer etches ZnO layer and first using photoetching process
Al2O3Layer, so that ZnO layer and the first Al2O3Layer two sides form channel；
S3: in the first Al2O3The upper surface of layer upper surface and ITO source region layer and the drain region ITO layer deposits one layer of Al2O3As
2nd Al2O3Layer, the 2nd Al2O3Layer two sides extend respectively into ZnO layer and the first Al2O3In the channel of layer two sides, 1% is then used
HF solution is in the 2nd Al2O3Layer two sides form channel close to edge chemical wet etching, so that the 2nd Al2O3Layer is not by ITO source region
Layer and the drain region ITO layer upper surface are completely covered；
S4: the ITO layer of one layer of 100nm is deposited in the structure upper surface that step S3 is obtained, ITO layer two sides extend to second
Al2O3Layer both sides of the edge and part deposition is to the 2nd Al2O3In two wing passage of layer, then by the 2nd Al2O3Two side through hole of layer are to the
Two Al2O3ITO layer removing between layer middle part, is retained in the 2nd Al after removing2O3The ITO layer of layer upper surface is as the grid region ITO
Layer, the ITO layer that two sides are retained in after removing are prepared respectively as another part and step S2 of ITO source region layer and the drain region ITO layer
ITO source region layer, the drain region ITO layer a part collectively constitute ITO source region layer, the drain region ITO layer；
S5: a layer photoresist is coated as Resistance in ITO source region layer upper surface, is etched and is located at by photoetching process
The grid region ITO layer two sides barrier layer, and barrier layer close to the grid region ITO layer inside respectively with the first Al2O3The two sides of layer are vertical
Concordantly；
S6: deuterium doping: the upper area using deuterium between two barrier layers carries out ion implantation doping at room temperature,
The ion under the barrier effect on barrier layer of lower zone corresponding to barrier layer can not inject doping.
The deuterium adulterates the variation for controlling ZnO-TFT threshold voltage.
First Al2O3Layer is protective layer, the 2nd Al2O3Layer is used as grid oxide layer, and the grid region ITO layer is used as grid, the source ITO
Region layer and the drain region ITO layer are respectively as source electrode and drain electrode.
Each RFID chip has a corresponding identification code, this identification code is affixed on envelope as label in RFID chip
It is written before at mouthful, wireless telecom equipment energizes when close to RFID chip for RFID chip, and circuit is intrinsic in RFID chip
Frequency obtains energy from wireless telecom equipment by tuning circuit resonance to specific frequency, antenna, and rectification circuit rectifies energy
It is power digital logic circuitry at direct current, the identification code signal that Digital Logical Circuits generates in RFID chip is exported to modulation electricity
Road, modulation circuit will be emitted by antenna to wireless telecom equipment after identification code signal modulation to specific frequency, and wireless communication is set
Standby that modulated signal demodulation is reverted to identification code signal, wireless telecom equipment reads and shows the merchandise news in RFID chip,
Network data base is written into this read access time simultaneously.
The network data base is used to record encapsulation, storage, outbound when and where, sales situation and the consumer of commodity
Inquiry record, consumer can be read from network data base by reader and inquire bought merchandise news.
The specific frequency is 13.56MHz.
The wireless telecom equipment uses dedicated reader or has the mobile phone of NFC function.
The wireless telecom equipment is provided with the function that a key burns RFID chip, passes through when starting wireless telecom equipment
RFID chip can be burnt by increasing its power, prevented chip to be recycled and counterfeited merchandise.
Element in the circuit of the chip layout is transparent element, element include all-transparent thin film transistor (TFT), capacitor,
Conducting wire, wherein capacitor is mainly made of upper layer and lower layer ITO layer and the insulating layer among two layers of ITO layer.
Inverter structure in the circuit of the chip layout selects depletion load phase inverter.
The Digital Logical Circuits is mainly by ring oscillator, counter, decoder, memory, Manchester encoder
It is formed with d type flip flop, Digital Logical Circuits generates global clock by ring oscillator, and counter is according to the clock frequency of global clock
Rate counts, and the same address signal counted to get is transferred to two decoders by counter respectively, and two decoders obtain respectively
Wordline in read-only memory, the address signal on bit line are obtained, and takes out identification code data from read-only memory, decoder will be only
The data read on the bit line and wordline of memory are sent to Manchester encoder, Manchester's code after d type flip flop shaping
Device is exported the data after coding as identification code signal to modulation circuit.
The RFID label tag is mainly made of transparent zinc oxide thin-film transistor, and ZnO-TFT device uses bottom grating structure.
The transparent membrane substrate thickness is 100-700 μm.
The antenna is printed in RFID chip circuit peripheral, and rectangular or round, rectangular day can be divided into according to sealing part shape
Line periphery side length 1-4cm, circular antenna peripheral diameter 2cm.
The RFID chip is affixed on sealing part, bridging sealing two sides after label is made.
The invention has the advantages that:
1) all-transparent chip of the invention is all worldwide a new field, is able to achieve transparent radio frequency mark at present
Few therefore of the invention compared with the traditional die all-transparent chip appearance identification of the study group of label chip is high and extremely difficult imitative
It makes, adulterator can be effectively prevent by forging chip to cheat consumer.
2) RFID chip of the invention is different from traditional commodity counterfeit prevention traceability system, using transparent membrane as substrate,
Chip all-transparent and destructible, can be covered in two dimensional code etc. needs not influencing existing goods appearance, and be placed in except visible label
When sealing part, consumer Kaifeng can destroy chip, to achieve the effect that anti-fake.
3) this anti-fake traceability system identification is high, applied widely, and safety coefficient is high, and antifalse effect is good, low in cost, disappears
The learning cost of the person of expense is low, can be applied to the various occasions for needing anti-counterfeiting system such as drinks, drug, tealeaves.
Detailed description of the invention
Fig. 1 is system structure diagram of the invention.
Fig. 2 is the structure chart of ZnO-TFT device and process flow used in the present invention；Fig. 2 (a) is source-drain electrode layer and thin transparent
The structure chart of film substrate；Fig. 2 (b) is the structure chart of ITO source region layer, the drain region ITO layer and transparent membrane substrate；Fig. 2 (c) is to scheme
The structure chart of ZnO layer is deposited in 2 (b) structures；Fig. 2 (d) is that the first Al is deposited in Fig. 2 (c) structure2O3The structure chart of layer；Fig. 2
It (e) is the structure chart by Fig. 2 (d) structure Jing Guo photoetching；Fig. 2 (f) is that the 2nd Al is deposited in Fig. 2 (e) structure2O3The structure of layer
Figure；Fig. 2 (g) is the structure chart by Fig. 2 (e) structure Jing Guo photoetching；Fig. 2 (h) is deposited, photoetching, stripping in Fig. 2 (g) structure
From the structure chart after operation；Fig. 2 (i) is the structure chart in Fig. 2 (h) structure after deposited, photoetching, deuterium doping operation.
Fig. 3 is chip layout of the invention.
Fig. 4 is Digital Logical Circuits structure chart of the invention.
Fig. 5 is test result waveform diagram of the invention.
Fig. 6 is the structural schematic diagram that the present invention is applied to red wine bottle.
Fig. 7 is the structural schematic diagram that the present invention is applied to White Spirit Bottle.
Fig. 8 is the structural schematic diagram that the present invention is applied to drug tank.
Fig. 9 is the structural schematic diagram that the present invention is applied to tea can or cigarette case.
Figure 10 is the structural schematic diagram that the present invention is applied to salt bag.
Figure 11 is the structural schematic diagram that the present invention is applied to casket.
In figure: 1: transparent membrane substrate；2:ZnO layers；3: the one Al2O3Layer；4: the two Al2O3Layer；5:ITO source region layer；6:
The drain region ITO layer；The grid region 7:ITO layer；8: barrier layer；9: source-drain electrode layer；10: label；11: envelope modeling；12: two dimensional code；13 corks；
14: bottleneck；15: tank mouth；16: sealing.
Specific embodiment
With reference to the accompanying drawing to and embodiment the invention will be further described.
As shown in Figure 1, anti-counterfeiting system of the invention includes using label made of RFID chip, reads the special of label information
With the network data base of reader and record commodity circulation information.Label bridging sealing both ends, 100-700 μm of thickness, convenient for beating
Label is destroyed while opening commodity packaging.The circuit of RFID chip is printed on transparent membrane, the full impregnated in RFID chip circuit
Bright thin film transistor (TFT) uses ZnO-TFT device, and RFID chip includes counter, decoding and ROM storage, trigger, ring oscillation
The parts such as device, buffer.
As shown in Fig. 2 (i), ZnO-TFT device includes ITO source region layer 5, the ITO being sequentially formed in transparent membrane substrate 1
Drain region layer 6, ZnO layer 2, the first Al2O3The 3, the 2nd Al of layer2O3Layer 4, the grid region ITO layer 7 and barrier layer 8, ITO source region layer 5, ITO leakage
Region layer 6 is located at ZnO-TFT bottom device two sides and in same layer；2 middle section of ZnO layer is embedded in downwards ITO source region
Form rectangle recess between the layer of layer 5 and ITO drain region, 2 two sides of ZnO layer are deposited on ITO source region layer 5, on the layer of the drain region ITO
Surface；First Al2O3Layer 3 is deposited on 2 upper surface of ZnO layer and equally also has rectangle recess, identical as 2 structure of ZnO layer, and second
Al2O34 middle section of layer are covered in the first Al2O33 upper surface of layer and the 2nd Al2O3The 4 downwardly convex overlay in middle section lower surface of layer
The first Al of lid2O33 intermediate recess of layer, the 2nd Al2O34 two sides of layer extend respectively into ITO source region layer 5, the drain region ITO layer upper surface；
ITO source region layer 5 and the drain region ITO 6 upper surface middle part of layer are respectively from the 2nd Al2O3Layer 4 two sides be pierced by after respectively in the first Al2O3Layer 3
Upper formation inverted L shape protrusion；The grid region ITO layer 7 is laid in the 2nd Al2O3Among 4 upper surface of layer；The grid region ITO 7 two sides side of layer have
Barrier layer 8, the grid region barrier layer 8 and ITO layer 7 are isolated, two barrier layers 8 be located at ITO source region layer 5 inverted L shape protrusion and
2nd Al2O3The upper surface of layer 4, the inverted L shape protrusion of the drain region ITO layer 6 and the 2nd Al2O3The upper surface of layer 4, two barrier layers 8 are leaned on
The inside of the nearly grid region ITO layer 7 respectively with the first Al2O3The two sides of layer 3 are vertically concordant.
Specific embodiment:
The preparation process of ZnO-TFT device is as follows:
S1: the ITO of one layer of 200nm is deposited as shown in Fig. 2 (a), in transparent membrane substrate 1 after cleaning as source-drain electrode
Layer, in source-drain electrode layer upper surface spin coating photoresist, using on photo-etching machine exposal transition diagram to transparent membrane substrate 1；Such as Fig. 2
(b) shown in, etching forms a part of ITO source region layer 5 and the drain region ITO layer 6 on source-drain electrode layer after photoresist dissolution denaturation；
S2: as shown in Fig. 2 (c), use ALD equipment ITO source region layer 5 and the drain region ITO layer 6 on deposition ZnO film as
ZnO layer 2；As shown in Fig. 2 (d), annealing and depositing Al in 2 upper surface of ZnO layer2O3Film is as the first Al2O3Layer 3；Such as Fig. 2 (e)
It is shown, ZnO layer 2 and the first Al are etched using photoetching process2O3Layer 3, so that ZnO layer 2 and the first Al2O33 two sides of layer form ditch
Road；
S3: as shown in Fig. 2 (f), in the first Al2O3The upper surface of 3 upper surface of layer and ITO source region layer 5 and the drain region ITO layer 6 is heavy
One layer of Al of product2O3As the 2nd Al2O3Layer 4, the 2nd Al2O34 two sides of layer extend respectively into ZnO layer 2 and the first Al2O33 two sides of layer
In channel；As shown in Fig. 2 (g), then using volume fraction is 1% HF solution in the 2nd Al2O34 two sides of layer are close to edge
Chemical wet etching forms channel, so that the 2nd Al2O3ITO source region layer 5 and the drain region ITO 6 upper surface of layer are not completely covered for layer 4；
S4: as shown in Fig. 2 (h), the ITO layer of one layer of 100nm, ITO layer two are deposited in the structure upper surface that step S3 is obtained
Side extends to the 2nd Al2O34 both sides of the edge of layer and part deposition is to the 2nd Al2O3In 4 liang of wing passage of layer, then by the 2nd Al2O3
4 liang of side through hole of layer are to the 2nd Al2O3ITO layer removing between 4 middle part of layer, is retained in the 2nd Al after removing2O34 upper surface of layer
ITO layer is retained in the ITO layers of two sides respectively as the another of ITO source region layer 5 and the drain region ITO layer 6 as the grid region ITO layer 7 after removing
A part and a part of the ITO source region layer 5 of step S2 preparation, the drain region ITO layer 6 collectively constitute ITO source region layer 5, the drain region ITO layer
6；
S5: a layer photoresist is coated as Resistance in 5 upper surface of ITO source region layer, etches in place by photoetching process
In the grid region ITO layer 7 two sides barrier layer 8, and barrier layer 8 close to the grid region ITO layer 7 inside respectively with the first Al2O3The two of layer 3
Side is concordant vertically；
S6: deuterium doping: as shown in Fig. 2 (i), at room temperature use upper area of the deuterium between two barrier layers 8 into
Row ion implantation doping, lower zone ion under the barrier effect on barrier layer 8 corresponding to barrier layer 8 can not inject doping.
The materials such as glass, PET, PI can be used in transparent membrane substrate 1 used.A specific embodiment of the invention uses wafer
As transparent membrane substrate 1
As shown in figure 3, chip layout includes rectification circuit, modulation circuit, Digital Logical Circuits, antenna and tuning circuit,
Antenna is connected with tuning circuit, rectification circuit, modulation circuit respectively, and rectification circuit is through Digital Logical Circuits and modulation circuit phase
Even；Each RFID chip has a corresponding identification code, this identification code is affixed on sealing part as label in RFID chip
It is written before, reader energizes when close to RFID chip for RFID chip, and the intrinsic frequency of circuit passes through tune in RFID chip
For humorous circuit resonance to 13.56MHz, antenna obtains energy from reader, and energy is rectified into direct current and patrolled for number by rectification circuit
Circuit power supply is collected, the identification code signal that Digital Logical Circuits generates in RFID chip is exported to modulation circuit, and modulation circuit will be known
Other code signal is emitted by antenna to reader after modulating to 13.56MHz, and modulated signal demodulation is reverted to identification code by reader
Signal, reader reads and shows the merchandise news in RFID chip, while network data base is written in this read access time.It reads
It reads device and uses cryptographic protocol and algorithm, 14443 agreement of protocol-compliant.
As shown in figure 4, Digital Logical Circuits is mainly by ring oscillator, counter, decoder, memory, Manchester
Encoder and d type flip flop composition, Digital Logical Circuits generate global clock by ring oscillator, and counter is according to global clock
Clock frequency counts, and the same address signal counted to get is transferred to two decoders, two decoders by counter respectively
Wordline in read-only memory, the address signal on bit line are obtained respectively, and takes out identification code data from read-only memory, are decoded
Data on the bit line and wordline of read-only memory are sent to Manchester encoder, Man Chesi by device after d type flip flop shaping
Special encoder is exported the data after coding as identification code signal to modulation circuit
It is illustrated in figure 5 test voltage VDDTest result waveform when for 10V, data rate 18.4kbit/s.In figure
Shown waveform uses Manchester's code, and Manchester code as shown in the figure is 011001010101100110010101010101
10, decoding obtains data 1011110101111110.
If Fig. 6 is that the exemplary diagram for being applied to red wine after label is made of the present invention, label 10 is pasted on red wine bottle cork
14 outside of plug 13 and bottleneck, bridges cork 13 and body, two dimensional code 12 or brilliance can be added between glass label 10 and bottleneck
Optically variable anti-counterfeiting etc. needs visible verifying means, and label 10 has chip and antenna side towards bottle to prevent from being destroyed, label 10
Outside is packaged using envelope modeling 11.
If Fig. 7 is that the exemplary diagram for being applied to white wine after label is made of the present invention, label 10 is pasted on White Spirit Bottle bottleneck
14 outsides can add two dimensional code 12 or honorable light if the modeling 11 of 14 envelope of white wine bottleneck is transparent between glass label 10 and bottleneck 14
Becoming anti-fake wait needs visible verifying means, and label 10 has chip and antenna side towards bottle to prevent from being destroyed, on the outside of label
It is packaged using envelope modeling 11.
If Fig. 8 is that the exemplary diagram for being applied to drug tank after label is made of the present invention, label 10 is pasted on drug tank mouth
15 outsides can add two dimensional code 12 or honorable light if the modeling 11 of 15 envelope of drug tank mouth is transparent between glass label 10 and tank mouth 15
Become anti-fake and wait the visible verifying means that need, label 10 has chip and antenna side towards drug tank inside to prevent from being destroyed, mark
10 outside of label is packaged using envelope modeling 11.
If Fig. 9 is that the exemplary diagram for being applied to tea can or cigarette case after label is made of the present invention, label 10 is pasted on tea
At leaf tank or cigarette case sealing 16, two dimensional code or honorable optically variable anti-counterfeiting etc. can be added on the inside of label 10 needs visible verifying means, mark
Label 10 have chip and antenna side towards tea can or cigarette case inside to prevent from being destroyed, conventional using envelope modeling etc. on the outside of label 10
Encapsulation means are packaged.
If Figure 10 is that the exemplary diagram for being applied to salt bag after label is made of the present invention, label 10 is pasted on salt bag envelope
At mouthfuls 16, two dimensional code or honorable optically variable anti-counterfeiting etc. can be added on the inside of label 10 needs visible verifying means, label 10 have chip and
Antenna side is towards salt bag inside to prevent from being destroyed.
If Figure 11 is that the exemplary diagram for being applied to casket after label is made of the present invention, label 10 is pasted on casket and opens
Mouthful place, two dimensional code 12 or honorable optically variable anti-counterfeiting etc. can be added on the inside of label 10 needs visible verifying means, label 10 have chip with
Antenna side is towards salt bag inside to prevent from being destroyed.
The above is only preferred embodiments of the present invention on the commodity counterfeit preventions such as food, beverage, not to this hair
The bright restriction done in any form, any person skilled in the art are become possibly also with the technology contents of the disclosure above
More or it is modified to the equivalent example of equivalent variations, but without departing from the technical solutions of the present invention, skill according to the present invention
Any simple modification, equivalent change and modification that art substantially does the above example, still falls within protection scope of the present invention
Within.
Claims (9)
1. a kind of commodity counterfeit prevention traceability system based on transparent membrane substrate RFID chip, it is characterised in that: RFID chip includes
Transparent membrane substrate (1) and the chip layout being located on transparent membrane substrate (1), chip layout include rectification circuit, modulation electricity
Road, Digital Logical Circuits, antenna and tuning circuit, rectification circuit connect antenna by tuning circuit, and rectification circuit is patrolled through number
Circuit is collected to be connected with modulation circuit；
All-transparent thin film transistor (TFT) in the circuit of chip layout is all made of ZnO-TFT device, and ZnO-TFT device includes successively shape
At in the ITO source region layer (5) on transparent membrane substrate (1), the drain region ITO layer (6), ZnO layer (2), the first Al2O3Layer (3), second
Al2O3Layer (4), the grid region ITO layer (7) and barrier layer (8), ITO source region layer (5), the drain region ITO layer (6) are located at ZnO-TFT device
Part two sides of the bottom and be in same layer；ZnO layer (2) middle section is embedded in downwards between ITO source region layer (5) and the drain region ITO layer
Rectangle recess is formed, ZnO layer (2) two sides are deposited on ITO source region layer (5), the drain region ITO layer upper surface；First Al2O3
Layer (3) is deposited on ZnO layer (2) upper surface and equally also has rectangle recess, the 2nd Al2O3Layer (4) middle section is covered in first
Al2O3Layer (3) upper surface and the 2nd Al2O3The first Al of the layer downwardly convex covering in (4) middle section lower surface2O3Layer (3) middle concave
It falls into, the 2nd Al2O3Layer (4) two sides extend respectively into ITO source region layer (5), the drain region ITO layer upper surface；ITO source region layer (5) and ITO
Drain region layer (6) upper surface middle part is respectively from the 2nd Al2O3Layer (4) two sides be pierced by after respectively in the first Al2O3Inverted L is formed on layer (3)
Type protrusion；The grid region ITO layer (7) is laid in the 2nd Al2O3Among layer (4) upper surface；There is blocking in the grid region ITO layer (7) two sides side
Layer (8), barrier layer (8) are isolated with the grid region ITO layer (7), and two barrier layers (8) are located at the inverted L shape of ITO source region layer (5)
Protrusion and the 2nd Al2O3The upper surface of layer (4), the inverted L shape protrusion of the drain region ITO layer (6) and the 2nd Al2O3The upper surface of layer (4),
Two barrier layers (8) close to the inside of the grid region ITO layer (7) respectively with the first Al2O3The two sides of layer (3) are vertically concordant.
2. the commodity counterfeit prevention traceability system according to claim 1 based on transparent membrane substrate RFID chip, feature exist
In: the preparation process of the ZnO-TFT device is as follows:
S1: one layer of ITO is deposited in transparent membrane substrate (1) after cleaning as source-drain electrode layer (9), on source-drain electrode layer (9)
Surface spin coating photoresist, in source after being denaturalized using on photo-etching machine exposal transition diagram to transparent membrane substrate (1), photoresist dissolves
Etching forms a part of ITO source region layer (5) and the drain region ITO layer (6) on drain electrode layer；
S2: atomic layer deposition apparatus is used to deposit ZnO film on ITO source region layer (5) and the drain region ITO layer (6) as ZnO layer
(2)；Annealing and depositing Al in ZnO layer (2) upper surface2O3Film is as the first Al2O3Layer (3) etches ZnO using photoetching process
Layer (2) and the first Al2O3Layer (3), so that ZnO layer (2) and the first Al2O3Layer (3) two sides form channel；
S3: in the first Al2O3The upper surface of layer (3) upper surface and ITO source region layer (5) and the drain region ITO layer (6) deposits one layer of Al2O3
As the 2nd Al2O3Layer (4), the 2nd Al2O3Layer (4) two sides extend respectively into ZnO layer (2) and the first Al2O3The ditch of layer (3) two sides
In road, then using HF solution in the 2nd Al2O3Layer (4) two sides form channel close to edge chemical wet etching, so that second
Al2O3ITO source region layer (5) and the drain region ITO layer (6) upper surface are not completely covered for layer (4)；
S4: one layer of ITO layer is deposited in the structure upper surface that step S3 is obtained, ITO layer two sides extend to the 2nd Al2O3Layer (4) two sides
Edge and part deposition is to the 2nd Al2O3In (4) two wing passage of layer, then by the 2nd Al2O3(4) two side through hole of layer are to second
Al2O3ITO layer removing between in the middle part of layer (4), is retained in the 2nd Al after removing2O3The ITO layer of layer (4) upper surface is as ITO grid
Region layer (7), be retained in after removing the ITO layers of two sides respectively as another part of ITO source region layer (5) and the drain region ITO layer (6) and
The ITO source region layer (5) of step S2 preparation, a part of the drain region ITO layer (6) collectively constitute ITO source region layer (5), the drain region ITO layer
(6)；
S5: a layer photoresist is coated as Resistance in ITO source region layer (5) upper surface, is etched and is located at by photoetching process
The grid region ITO layer (7) two sides barrier layer (8), and barrier layer (8) close to the grid region ITO layer (7) inside respectively with the first Al2O3Layer
(3) two sides are concordant vertically；
S6: ion implantation doping deuterium doping: is carried out using upper area of the deuterium between two barrier layers (8).
3. the commodity counterfeit prevention traceability system according to claim 1 based on transparent membrane substrate RFID chip, feature exist
In: the first Al2O3Layer (3) is protective layer, the 2nd Al2O3Layer (4) is used as grid oxide layer, and the grid region ITO layer (7) is used as grid,
ITO source region layer (5) and the drain region ITO layer (6) are respectively as source electrode and drain electrode.
4. the commodity counterfeit prevention traceability system according to claim 1 based on transparent membrane substrate RFID chip, feature exist
In: each RFID chip has a corresponding identification code, and wireless telecom equipment is RFID core when close to RFID chip
Piece energy supply, the intrinsic frequency of circuit is by tuning circuit resonance to specific frequency in RFID chip, and antenna is from wireless telecom equipment
Energy is obtained, it is power digital logic circuitry that energy is rectified into direct current by rectification circuit, and Digital Logical Circuits generates RFID core
Identification code signal in piece is exported to modulation circuit, and modulation circuit will be sent out after identification code signal modulation to specific frequency by antenna
It is incident upon wireless telecom equipment, modulated signal demodulation is reverted to identification code signal by wireless telecom equipment, and wireless telecom equipment is read
And show the merchandise news in RFID chip.
5. the commodity counterfeit prevention traceability system according to claim 4 based on transparent membrane substrate RFID chip, feature exist
In: the specific frequency is 13.56MHz.
6. the commodity counterfeit prevention traceability system according to claim 4 based on transparent membrane substrate RFID chip, feature exist
In: the wireless telecom equipment uses dedicated reader or has the mobile phone of NFC function.
7. the commodity counterfeit prevention traceability system according to claim 4 based on transparent membrane substrate RFID chip, feature exist
Being provided with a key in: the wireless telecom equipment and burn the function of RFID chip prevents from chip to be recycled counterfeiting merchandise.
8. the commodity counterfeit prevention traceability system according to claim 1 based on transparent membrane substrate RFID chip, feature exist
It is transparent element in: the element in the circuit of the chip layout, element includes all-transparent thin film transistor (TFT), capacitor, conducting wire,
Wherein capacitor is mainly made of upper layer and lower layer ITO layer and the insulating layer among two layers of ITO layer.
9. the commodity counterfeit prevention traceability system according to claim 1 based on transparent membrane substrate RFID chip, feature exist
In: the inverter structure in the circuit of the chip layout selects depletion load phase inverter.
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