CN106355234A - 100% demodulation circuit for NFC tag - Google Patents
100% demodulation circuit for NFC tag Download PDFInfo
- Publication number
- CN106355234A CN106355234A CN201610712995.3A CN201610712995A CN106355234A CN 106355234 A CN106355234 A CN 106355234A CN 201610712995 A CN201610712995 A CN 201610712995A CN 106355234 A CN106355234 A CN 106355234A
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- pipe
- drain electrode
- substrate
- pmos pipe
- grid
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07771—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object
Abstract
The invention relates to a 100% demodulation circuit for NFC tag, comprising high pressure PMOS pipe HVPM1, HVPM2, HVPM3, high pressure NMOS pipe HVNM1, HVNM2, HVNM3, HVNM4, low pressure PMOS pipe LVPM1, LVPM2, LVPM3, LVPM4, low pressure NMOS pipe LVNM1, LVNM2, LVNM3, LVNM4, resistance R1, R2, R3 and electric capacity C1, C2. The invention has the advantages that by using the combination of nonlinear circuit and low-pass filter, the modulation signal sent from the NFC reading device is detected, by fully utilizing the difference between the threshold voltage characteristics of the high voltage devices and the low voltage devices in the circuit design, as well as with the RC filter network, the 100% demodulation function of the modulation signal can be achieved.
Description
Technical field
The present invention relates to a kind of 100% demodulator circuit being applied to nfc label.
Background technology
Nfc (near field communication, near-field communication) label chip is the ic chip of data storage, can
Read by nfc equipment, be typically used in passive communication mode, there is small volume, lightweight, low cost and long service life etc.
Advantage, be widely used with product false proof trace to the source, supply chain management, gate inhibition, each big industry such as public transit system.
Nfc label chip is mainly made up of rf analog front-end, digitial controller and three nucleus modules of memorizer.Penetrate
Frequency AFE (analog front end) is responsible for obtaining rf energy to signals such as whole label chip offer power supply, recovery data and generation clocks, is core
Piece can steady operation key, and 100% demodulator circuit be exactly in whole data recovery a part.Demodulation is the inverse mistake of modulation
Journey, is the process recovering former low-frequency modulation signal from high frequency modulated wave.Demodulator circuit is exactly to complete modulation from antenna to carry
Digital signal is demodulated in ripple signal, and for this nfc label chip major requirement to meeting 106kbit communication speed
Iso14443 typea, that is, 100% modulated signal can correctly demodulate.
The scheme main body circuit structure that existing 100% demodulator circuit adopts is as shown in Figure 1.This 100% demodulator circuit is main
Including envelope signal demodulation part, demodulated signal shaping unit and high-voltage signal to low-voltage signal conversion portion.And for bag
Network signal demodulation part circuit structure schematic diagram is as shown in Figure 1.With an2, wherein an1 represents that chip is connected the pad of exterior antenna,
Hvnz1/hvnz2 is zero threshold value high pressure nmos pipe of sampling antenna envelope, and hvpm11/hvpm21, hvnm11/hvnm21 are respectively
Produce high pressure pmos pipe and nmos pipe, the wherein resistance r of image current1/r2/r3Produce mirror image biasing with hvpm11 collective effect
Electric current.
Operation principle is as follows, when nfc label chip reads equipment near nfc, label chip internal rf front end rectified current
Road creates the supply voltage avdd for whole chip operation, and simultaneously with the generation of supply voltage avdd, chip internal gives number
Word is powered, and also normal work creates the dvdd voltage powered to low-voltage device to ldo circuit.Send 100% tune when nfc reads equipment
During signal processed, in the case of 13.56mhz carrier wave normal work, due to the drop-down less dm100 of electric current of hvnm21 nmos pipe
Signal level keeps high level state, and in modulation condition because, during 100% modulation, nfc reads equipment and do not send energy, institute
Energy cannot be coupled to on label chip antenna, dm100 end capacitance is less in the design, so dm100 terminal voltage can be by
Effect in hvnm21 pull-down current is changed into low level, thus reaching the demodulation to envelope signal.But now demodulate out
Envelope signal high level and rise and fall along due to affect the very big disturbance of presence by carrier wave, so needing shaping circuit
Shaping is carried out to this waveform, cannot believe as the input of digital circuit by the voltage domain of the demodulation waveforms work of shaping is larger
Number, need increase level shifter circuit to complete conversion from high pressure to low pressure for the demodulated signal in demodulator circuit.
Although preferably can read what equipment sent to from nfc for the scheme of this 100% demodulator circuit
Modulated signal is demodulated, but needs increase high pressure zero threshold value nmos device that envelope signal is adopted in circuit design
Sample, and in order to produce the pull-down current to dm100 end, in circuit, increased current generating circuit, and also this electric current is chip
It is constantly in the state of work it is contemplated that the requirement of the low-power consumption of chip, resistance r in circuit after upper electricity1/r2/r3The setting of resistance
Meter needs reach a megaohm magnitude.So the design of 100% demodulator circuit of the program not only increase circuit design complexity and
And the increase of area also can be brought to chip, increase the cost of chip.
Content of the invention
For overcoming the defect of prior art, the present invention provides a kind of 100% demodulator circuit being applied to nfc label.The present invention
Technical scheme be:
A kind of 100% demodulator circuit being applied to nfc label, including high pressure pmos pipe hvpm1, hvpm2, hvpm3, high pressure nmos
Pipe hvnm1, hvnm2, hvnm3, hvnm4, low pressure pmos pipe lvpm1, lvpm2, lvpm3, lvpm4, low pressure nmos pipe lvnm1,
Lvnm2, lvnm3, lvnm4, resistance r1、r2、r3And electric capacity c1, c2；
Pmos pipe hvpm1, the substrate of this pmos pipe hvpm1 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm1,
Grid and nmos pipe hvnm1, hvnm2 grid and with resistance r1One end connects, r1An end of another termination antenna component pad,
Nmos pipe hvnm1 source electrode connects the drain electrode of hvnm2, hvnm1 substrate and hvnm2 substrate and source ground；
Pmos pipe hvpm2, the substrate of this pmos pipe hvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm3,
The grid of grid and hvnm3 is commonly connected to drain electrode, the substrate of nmos pipe hvnm3 and the source ground of hvpm1 and hvnm1；
Pmos pipe lvpm1, the substrate of this pmos pipe lvpm1 and source electrode meet power supply dvdd, and drain connecting resistance r2One end, resistance r2Separately
One end and r3One end, the grid of electric capacity c1 one end, the grid of pmos pipe hvpm3 and nmos pipe hvnm4 connect, and resistance r3 is another
Drain electrode, lvnm1 substrate and the source ground of termination nmos pipe lvnm1, the other end ground connection of electric capacity c1；
Pmos pipe hvpm3, the substrate of this pmos pipe hvpm3 and source electrode meet power supply dvdd, drain electrode connect nmos pipe hvnm4 drain electrode,
The grid of one end of electric capacity c2, the grid of pmos pipe lvpm2 and nmos pipe lvnm2, the other end ground connection of electric capacity c2；
Pmos pipe lvpm2, the substrate of this pmos pipe lvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm2,
The substrate of lvnm2 and source ground；
Pmos pipe lvpm3, the substrate of this pmos pipe lvpm3 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm3
Afterwards as the outfan rx100 of demodulator circuit, grid and lvnm3 grid are commonly connected to the drain electrode of lvpm2 and the leakage of lvnm2
Pole, the substrate of lvnm3 and source ground.
The invention has the advantage that the present invention combines using nonlinear circuit and low pass filter to achieve reading to nfc
The modulated signal of equipment output carries out envelope detection, by making full use of high tension apparatus and low-voltage device threshold value in circuit design
The difference of voltage characteristic, and coordinate rc filter network can preferably achieve 100% demodulation function of modulated signal.
Power with numerical portion identical low-tension supply because the supply voltage dvdd of the present invention employs, that is, all by ldo
Circuit produces, so not only improving a lot in the complexity of circuit design and the area of reduction chip, and effectively
The loss reducing circuit energy.
Brief description
Fig. 1 is the structural representation of prior art.
Fig. 2 is the structural representation of the present invention.
Fig. 3 is when nfc reads the iso14443 typea modulated signal that device transmission transfer rate is 106kbit/s,
The simulating, verifying waveform that 100% demodulator circuit of the present invention is demodulated to the signal after antenna coupling.
Fig. 4 is the partial enlargement figure of the simulating, verifying waveform in Fig. 3.
Specific embodiment
To further describe the present invention with reference to specific embodiment, advantages of the present invention and feature will be with description and
Apparent.But these embodiments are only exemplary, any restriction is not constituted to the scope of the present invention.People in the art
Member should be understood that can be to enter to the details of technical solution of the present invention and form under without departing from the spirit and scope of the present invention
Row modification or replacement, but these modifications and replacement each fall within protection scope of the present invention.
Referring to Fig. 2, the present invention relates to a kind of 100% demodulator circuit being applied to nfc label, including high pressure pmos pipe
Hvpm1, hvpm2, hvpm3, high pressure nmos pipe hvnm1, hvnm2, hvnm3, hvnm4, low pressure pmos pipe lvpm1, lvpm2,
Lvpm3, lvpm4, low pressure nmos pipe lvnm1, lvnm2, lvnm3, lvnm4, resistance r1, r2, r3 and electric capacity c1, c2；
Pmos pipe hvpm1, the substrate of this pmos pipe hvpm1 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm1,
Grid is connected with nmos pipe hvnm1, hvnm2 grid and with resistance r1 one end, an end of r1 another termination antenna component pad,
Nmos pipe hvnm1 source electrode connects the drain electrode of hvnm2, hvnm1 substrate and hvnm2 substrate and source ground；
Pmos pipe hvpm2, the substrate of this pmos pipe hvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm3,
The grid of grid and hvnm3 is commonly connected to drain electrode, the substrate of nmos pipe hvnm3 and the source ground of hvpm1 and hvnm1；
Pmos pipe lvpm1, the substrate of this pmos pipe lvpm1 and source electrode meet power supply dvdd, and drain connecting resistance r2 one end, and resistance r2 is another
One end is connected with the grid of r3 one end, electric capacity c1 one end, the grid of pmos pipe hvpm3 and nmos pipe hvnm4, and resistance r3 is another
Drain electrode, lvnm1 substrate and the source ground of termination nmos pipe lvnm1, the other end ground connection of electric capacity c1；
Pmos pipe hvpm3, the substrate of this pmos pipe hvpm3 and source electrode meet power supply dvdd, and drain electrode connects the leakage of nmos pipe hvnm4 pipe
Pole, the grid of one end of electric capacity c2, the grid of pmos pipe lvpm2 and nmos pipe lvnm2, the other end ground connection of electric capacity c2；
Pmos pipe lvpm2, the substrate of this pmos pipe lvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm2,
The substrate of lvnm2 and source ground；
Pmos pipe lvpm3, the substrate of this pmos pipe lvpm3 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm3
Afterwards as the outfan rx100 of demodulator circuit, grid and lvnm3 grid are commonly connected to the drain electrode of lvpm2 and the leakage of lvnm2
Pole, the substrate of lvnm3 and source ground.
The operation principle of the present invention is: when nfc reads equipment and opens simultaneously near nfc label chip, nfc label antenna coupling
Close electromagnetic wave energy, produce DC voltage and to whole chip power supply, ldo module in chip simultaneously through rectification circuit module
Work creates dvdd supply voltage to numerical portion, and 100% demodulator circuit and other circuit modules are powered.In the present invention
The input of 100% demodulator circuit is connected to the pad of antenna in chip, resistance r1Purpose is to circuit inside when preventing Electro-static Driven Comb
The grid end of device causes damage.In circuit design, most crucial part is resistance r2With the low pass filter of c1 composition, this low pass
Filter bandwidth requirement is less than 13.56mhz, so when c point is 13.56mhz square wave, r2Low pass filter handle with c1 composition
13.56mhz signal
Filter.
Wherein a point is the grid of pipe hvpm1, the grid of hvnm1, the grid of nmos pipe hvnm2 and resistance r1The company of one end
Contact；B point is the grid of the grid with the junction point of drain electrode of pipe hvnm1 and pipe hvpm2 for the drain electrode of pipe hvpm1 and pipe hvnm3
The junction point of pole；C point is the drain electrode of pipe hvpm2 and the grid of the junction point of drain electrode of pipe hvnm3 and pipe lvpm1 and pipe
The junction point of the grid of lvnm1；D point is resistance r2、r3Common port and electric capacity c1 top crown and high pressure mos pipe hvpm3 grid
Pole, the junction point of hvnm4 grid；When not having modulation data to be transmitted, circuit a point is the carrier signal of 13.56mhz, and c point is
The square wave of 13.56mhz, and when this signal square wave is through the low pass filter of r2, c1, it is output as low level, so that rx100 is exported
It is high level always.
When there being modulation data to be transmitted, occur due to not having energy to transmit during modulation, so a point signal is low level,
I.e. c point is also low level when there is modulation.Because transfer rate is 106kbit/s, it is much smaller than 13.56mhz, then d point
It is high level in nfc equipment conveying modulated signal.It is output as low electricity when the effect of phase inverter final rx100 modulation occurs
Flat, the modulation data that is, 100% demodulator circuit output signal sends to nfc equipment is demodulated.
In circuit design, wherein should be noted the following aspects, high pressure nmos pipe hvnm1 and hvnm2 that a point drives
Need to be designed to down the form than pipe, purpose is when a point signal is coupled to modulated signal generation, in order to improve the driving of a point
Threshold voltage.Thus reach occurring the time of demodulation to make the raising to modulated signal response speed for the circuit by accelerating circuit.And
It is due to the cgd electric capacity coupling of high pressure mos pipe hvpm1 and hvnm1 for hvpm2 and the hvnm3 still purpose using high tension apparatus
Close reason, when 13.56mhz carrier wave reduces to minimum voltage from ceiling voltage, b point voltage meeting before not making hvpm1 conducting
Follow the change of carrier signal so that b point voltage is less than below zero level, obtain vgs or vgd voltage beyond low-voltage device
Pressure degree, so employ high tension apparatus.Phase inverter hvpm3, hvnm4 are when d exports demodulation using the purpose of high tension apparatus
When signal is low level, in order to improve the response speed of demodulated signal, d point signal can be higher than zero potential value in low level, is
Prevent nmos pipe hvnm4 conducting from adopting in the design
Low-voltage device is replaced to be designed with high tension apparatus.
This demodulator circuit supports nfc forum type2 agreement and iso14443 typea host-host protocol completely, its requirement
The speed of data communication is 106kbit/s, i.e. envelope in modulation carrier wave
The pause time be about 9.44us.
As shown in figure 3, demodulator circuit can be good at realizing to being superimposed upon carrier wave in terms of simulation result
In envelope signal be demodulated, and demodulated signal is about 210ns with respect to the delay of modulated signal, meets design and refers to
Be marked with and engineer applied demand.
Fig. 4 provides the partial enlargement figure of simulating, verifying waveform, demodulator circuit pair from figure
The modulated signal response speed of antenna coupling is very fast.
Claims (1)
1. a kind of 100% demodulator circuit being applied to nfc label it is characterised in that include high pressure pmos pipe hvpm1, hvpm2,
Hvpm3, high pressure nmos pipe hvnm1, hvnm2, hvnm3, hvnm4, low pressure pmos pipe lvpm1, lvpm2, lvpm3, lvpm4 are low
Pressure nmos pipe lvnm1, lvnm2, lvnm3, lvnm4, resistance r1、r2、r3And electric capacity c1, c2；
Pmos pipe hvpm1, the substrate of this pmos pipe hvpm1 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm1,
Grid and nmos pipe hvnm1, hvnm2 grid and with resistance r1One end connects, r1An end of another termination antenna component pad,
Nmos pipe hvnm1 source electrode connects the drain electrode of hvnm2, hvnm1 substrate and hvnm2 substrate and source ground；
Pmos pipe hvpm2, the substrate of this pmos pipe hvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe hvnm3,
The grid of grid and hvnm3 is commonly connected to drain electrode, the substrate of nmos pipe hvnm3 and the source ground of hvpm1 and hvnm1；
Pmos pipe lvpm1, the substrate of this pmos pipe lvpm1 and source electrode meet power supply dvdd, and drain connecting resistance r2One end, resistance r2Separately
One end and r3One end, the grid of electric capacity c1 one end, the grid of pmos pipe hvpm3 and nmos pipe hvnm4 connect, and resistance r3 is another
Drain electrode, lvnm1 substrate and the source ground of termination nmos pipe lvnm1, the other end ground connection of electric capacity c1；
Pmos pipe hvpm3, the substrate of this pmos pipe hvpm3 and source electrode meet power supply dvdd, drain electrode connect nmos pipe hvnm4 drain electrode,
The grid of one end of electric capacity c2, the grid of pmos pipe lvpm2 and nmos pipe lvnm2, the other end ground connection of electric capacity c2；
Pmos pipe lvpm2, the substrate of this pmos pipe lvpm2 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm2,
The substrate of lvnm2 and source ground；
Pmos pipe lvpm3, the substrate of this pmos pipe lvpm3 and source electrode meet power supply dvdd, and drain electrode connects the drain electrode of nmos pipe lvnm3
Afterwards as the outfan rx100 of demodulator circuit, grid and lvnm3 grid are commonly connected to the drain electrode of lvpm2 and the leakage of lvnm2
Pole, the substrate of lvnm3 and source ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610712995.3A CN106355234B (en) | 2016-08-24 | 2016-08-24 | Demodulator circuit suitable for NFC label |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610712995.3A CN106355234B (en) | 2016-08-24 | 2016-08-24 | Demodulator circuit suitable for NFC label |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106355234A true CN106355234A (en) | 2017-01-25 |
| CN106355234B CN106355234B (en) | 2019-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610712995.3A Active CN106355234B (en) | 2016-08-24 | 2016-08-24 | Demodulator circuit suitable for NFC label |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109993243A (en) * | 2019-03-05 | 2019-07-09 | 浙江大学 | A kind of commodity counterfeit prevention traceability system based on transparent membrane RFID chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236453A (en) * | 2008-01-30 | 2008-08-06 | 上海华虹集成电路有限责任公司 | Connection structure and communicating method between NFC control chip and SIM card chip |
| CN102456144A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Demodulator circuit of radio frequency identification (RFID) reader |
| CN104901431A (en) * | 2014-03-04 | 2015-09-09 | 美国博通公司 | Resonant tuning through rectifier time shifting |
-
2016
- 2016-08-24 CN CN201610712995.3A patent/CN106355234B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236453A (en) * | 2008-01-30 | 2008-08-06 | 上海华虹集成电路有限责任公司 | Connection structure and communicating method between NFC control chip and SIM card chip |
| CN102456144A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Demodulator circuit of radio frequency identification (RFID) reader |
| CN104901431A (en) * | 2014-03-04 | 2015-09-09 | 美国博通公司 | Resonant tuning through rectifier time shifting |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109993243A (en) * | 2019-03-05 | 2019-07-09 | 浙江大学 | A kind of commodity counterfeit prevention traceability system based on transparent membrane RFID chip |
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| Publication number | Publication date |
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| CN106355234B (en) | 2019-03-12 |
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