CN108988831A - Capacitance digital isolating chip and its modulation-demo-demodulation method - Google Patents
Capacitance digital isolating chip and its modulation-demo-demodulation method Download PDFInfo
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- CN108988831A CN108988831A CN201810638797.6A CN201810638797A CN108988831A CN 108988831 A CN108988831 A CN 108988831A CN 201810638797 A CN201810638797 A CN 201810638797A CN 108988831 A CN108988831 A CN 108988831A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- Dc Digital Transmission (AREA)
Abstract
The invention discloses a kind of capacitance digital isolating chip and its modulation-demo-demodulation methods, including modulation circuit, differential high voltage capacitor and demodulator circuit, edge modulation is incorporated into a differential path by the modulation circuit with refresh circuit, the refresh signal that output incorporates the edge signal of input signal and refresh circuit generates；The differential high voltage capacitor for realizing modulation circuit and demodulator circuit electrical isolation, and to modulated signal carry out coupled transfer；The demodulator circuit, which is received, to be exported through differential high voltage is capacity coupled by modulated signal, and after demodulation.The present invention gives a kind of reliable digital isolating chip modulation and demodulation methods, side information and refreshing information are integrated into a difference isolated transmission channel, it is opposite that fast channel is modulated at edge and refreshes the scheme that slow channel is used separately two difference isolated transmission channels, smaller chip area is occupied, the power consumption of chip is reduced.
Description
Technical field
The present invention relates to a kind of digital isolating chip and its modulation-demo-demodulation method, in particular to a kind of capacitance digital isolation
Chip and its modulation-demo-demodulation method.
Background technique
Digital isolating chip is a kind of chip that digital data transmission is carried out between two voltage domains of electrical isolation,
Isolation stress levels often can achieve 2.5kV or more, can provide electric insulation to equipment, and earth-return is isolated and isolation is made an uproar
Sound or the anti-interference ability for improving interface.Requirement with system to various aspects of performance such as High Data Rate, low delay, low-power consumption
It is promoted, is increasingly difficult to meet demand by the isolating device of representative of traditional optocoupler.Substitution of the digital isolating chip as optocoupler,
Lower delay can be realized on the basis of lower power consumption, and is easily achieved multichannel and integrates, and can effectively improve system
Performance reduces system cost and volume.The relatively common digital isolation signals transmission of realization have transformer type, condenser type and
Magnetic Sensor formula.Capacitance digital isolating chip can realize that upper difficulty is lower with CMOS technique compatible, technique.But due to CMOS
The high-voltage capacitance capacitance that technique is realized is very small, is typically only tens fF, and capacitor can only transmit high-frequency signal, generally require
Input signal, which is modulated into, efficiently to be transmitted by isolation capacitance, then the demodulation of signal is realized by demodulator circuit.A kind of side
Method is modulated using edge, and the rising edge and failing edge of signal are only detected, and detects edge signal in demodulator circuit
Signal is restored.But when not overturning for a long time in signal or being direct current signal, state output terminal does not have signal edge to brush
Newly, output level caused by interfering in order to prevent is in incorrect state, generally requires that the refreshing channel of an auxiliary is added to protect
Output level is demonstrate,proved, this means the area and power consumption for needing to increase chip.
Summary of the invention
The object of the present invention is to provide a kind of capacitance digital isolating chip and its modulation-demo-demodulation methods, by signal
Edge modulation is incorporated into a differential path with channel is refreshed, and chip area occupancy is small, chip power-consumption is low.
To achieve the above object, the technical solution adopted by the present invention is, a kind of capacitance digital isolating chip, including adjusts
Circuit, differential high voltage capacitor and demodulator circuit processed,
Edge modulation is incorporated into a differential path by the-modulation circuit with refresh circuit, and output incorporates defeated
The refresh signal that the edge signal and refresh circuit for entering signal generate；
- differential high voltage the capacitor for realizing modulation circuit and demodulator circuit electrical isolation, and to modulated letter
Number carry out coupled transfer；
- demodulator circuit the reception is capacity coupled by modulated signal through differential high voltage, and exports after demodulating.
Preferably, the modulation circuit and demodulator circuit are respectively on two independent chip dies.
Preferably, the modulation circuit includes delay circuit 1, delay circuit 2, refresh circuit and differential encoder, institute
It states delay circuit 1 to connect with differential encoder signal, outputting and inputting for delay circuit 2 is believed after XOR gate with differential encoder
Number connection, the refresh circuit connect with differential encoder signal；Differential encoder transmits modulated differential driving signal
To demodulator circuit.
Preferably, the delay of the delay circuit 1 is smaller than the delay of delay circuit 2, but it is greater than the refresh circuit
Refresh signal pulse width.
Preferably, the differential high voltage capacitor is individually made on a chips crystal grain；Or it is made in the modulation chip
On crystal grain；Or it is made on the demodulation chip crystal grain；Or by being made on modulation chip die and demodulation chip die respectively
Pass through composition in series or in parallel.
Preferably, the demodulator circuit includes that biasing resistor, hysteresis comparator and burr eliminate circuit, the biased electrical
Resistance connects non-inverting input terminal and inverting input terminal in hysteresis comparator respectively, and the output of the hysteresis comparator and burr eliminate electricity
Road connection, burr eliminate circuit and are filtered elimination burr to decoded logic level signal, and as digital isolating chip
Output.
Preferably, the demodulator circuit further includes a watchdog circuit, the watchdog circuit and burr eliminate circuit
Connection, is monitored for the output to hysteresis comparator, as general after modulation circuit power down or a period of time irregular working
Output is set as on a preset safety level.
The present invention also discloses a kind of modulation-demo-demodulation methods of capacitance digital isolating chip, comprising the following steps:
(1) in modulation circuit, refreshing shielded signal and refresh electricity that the output of delay circuit 1, delay circuit 2 generate
Input after the refresh signal integration that road generates as differential encoder, generates modulated differential driving through differential encoder and believes
Number drive differential high voltage capacitor；
(2) differential high voltage capacitor realizes the electrical isolation of modulation circuit and demodulator circuit, and carries out to modulated signal
Coupled transfer；
(3) demodulator circuit restores received pulse signal by hysteresis comparator, decodes back logic level；
(4) then decoded logic level filtering elimination refreshing bring burr is carried out by burr elimination circuit whole
It is exported after shape；Obtain output signal.
Beneficial effects of the present invention: The present invention gives a kind of reliable digital isolating chip modulation and demodulation methods, by side
It is integrated into a difference isolated transmission channel along information and refreshing information, it is opposite that fast channel is modulated at edge and refreshes slow channel point
The scheme using two difference isolated transmission channels is opened, smaller chip area is occupied, reduces the power consumption of chip.
Detailed description of the invention
It, below will be to required in embodiment or description of the prior art in order to illustrate more clearly of technical solution of the present invention
The attached drawing used is briefly described.
Fig. 1 is the functional block diagram of capacitance digital isolating chip of the present invention；
Fig. 2 is a kind of structural schematic diagram of capacitance digital isolating chip of the present invention；
Fig. 3 is the waveform diagram of modulation-demodulation circuit key node signal of the present invention；
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with embodiment pair
Technical solution in the application is clearly and completely described.
As shown in Figure 1, the invention discloses a kind of capacitance digital isolating chip, including modulation circuit, differential high voltage electricity
Appearance and demodulator circuit,
Edge modulation is incorporated into a differential path by the-modulation circuit with refresh circuit, and output incorporates defeated
The refresh signal that the edge signal and refresh circuit for entering signal generate；
- differential high voltage the capacitor for realizing modulation circuit and demodulator circuit electrical isolation, and to modulated letter
Number carry out coupled transfer；
- demodulator circuit the reception is capacity coupled by modulated signal through differential high voltage, and exports after demodulating.
In the above-mentioned technical solutions, input signal is by driving a pair of of differential high voltage capacitor, modulation after modulating circuit modulates
Signal afterwards is demodulated circuit reception demodulation after passing through differential high voltage capacitive transmission and exports.And the modulation circuit and demodulation are electric
Road is respectively on two independent chip dies.
The modulation circuit includes delay circuit 1, delay circuit 2, refresh circuit and differential encoder, the delay circuit
1 connect with differential encoder signal, and outputting and inputting for delay circuit 2 is connect after XOR gate with differential encoder signal,
The refresh circuit is connect with differential encoder signal；Modulated differential driving signal is transferred to demodulation electricity by differential encoder
Road.
The output of the delay circuit 2 and input signal are by generating refreshing shielded signal after XOR logic；The delay
The output of circuit 1, what delay circuit 2 generated refreshes the refresh signal of shielded signal and refresh circuit generation as differential encoder
Input, differential encoder generates modulated differential driving signal and is transferred to demodulator circuit, which contains
The side information and refreshing information of the output of filter circuit.
The delay of the delay circuit 1 is smaller than the delay of delay circuit 2, but is greater than the refresh signal of the refresh circuit
Pulse width.
A pair of of differential high voltage capacitor for realizing modulation circuit and demodulator circuit electrical isolation, and to modulated signal
Carry out coupled transfer.The differential high voltage capacitor is individually made on a chips crystal grain；Or it is made in the modulation chip die
On；Or it is made on the demodulation chip crystal grain；Or passed through by being made on modulation chip die and demodulation chip die respectively
Composition in series or in parallel.
In the present embodiment, structure preferably as shown in Figure 2, there are two digital channel isolation, Mei Getong in the embodiment
Road respectively includes a pair of of differential high voltage capacitor.Two integrated-circuit dies, modulation circuit reconciliation are encapsulated in the embodiment, in chip
Circuit is adjusted to be located at crystal grain 1 and crystal grain 2.Each high-voltage capacitance then two capacitor strings by being respectively on crystal grain 1 and crystal grain 2
Connection is constituted.In other embodiments, high-voltage capacitance can be only on a wherein crystal grain, or is present in an additional list
On only crystal grain.
High-voltage capacitance realizes that the capacity plate antenna that can be made up of CMOS technology different layers metal is realized, is also possible to
The interdigital capacitor that same layer metal is constituted in CMOS technology is constituted.In certain higher occasions of pressure resistance, high-voltage capacitance can also pass through
By increasing additional insulating coating, such as polyimide coating in CMOS wafer, and increase metal-plated on insulating coating
Layer realizes that the pole plate of capacitor, the pole plate can constitute high-voltage capacitance with the metal plate on wafer.
The side pole plate of differential high voltage capacitor is connected with the input terminal of demodulator circuit.Demodulator circuit input terminal passes through two respectively
A biasing resistor is connected to bias voltage Vb.The two resistance and differential high voltage capacitor constitute high-pass filter, by modulation circuit
The edge transition of output signal is differential pulse signal.Biasing circuit also acts as provide direct current biasing for subsequent comparator simultaneously
The common mode current injected due to the common-mode voltage fluctuation in isolation voltage domain by capacitor also can be absorbed in point.
The differential pulse signal of demodulator circuit input terminal passes through subsequent hysteresis comparator, can include by side information
Rising edge and failing edge Information recovering come out.It is subsequent since the signal that hysteresis comparator recovers contains refresh pulse
Burr is eliminated circuit and can be filtered out refresh pulse as output signal.In some cases, such as modulation circuit part powers off
Or when abnormal, the state of demodulator circuit output is likely to be at unknown state, and in certain embodiments, demodulator circuit will increase one
Output signal is then forced the system safety for being set to default when not receiving refresh signal for a period of time by a watchdog circuit
Level.
Fig. 3 gives the waveform diagram of modulation-demodulation circuit key node signal of the present invention.Delay circuit 1
Output signal D1 relative input signal DIN has certain delay td1.The output of delay circuit 2 and the signal BLK after input exclusive or
As shielded signal is refreshed, i.e., forbid refreshing when BLK is high.It is not overturn for a long time in input signal or demodulator circuit has just powered on
When, refresh the level state of demodulator circuit without edge signal, the output level of digital isolating chip is likely to be at incorrect
State.The output CLKRF of refresh circuit is pulse signal, and effect is mainly the offer level refresh signal of timing, is prevented defeated
It is chronically at the incorrect state of level out.The width tw of usual refresh pulse signal needs to be greater than high-voltage capacitance and biasing resistor structure
At 3 times of the filter time constant tc of composition.Td1 is typically chosen in greater than tw, delay of the delay circuit 2 with respect to D1 simultaneously
It is also selected to be greater than tw.
D1, BLK and CLKRF are obtained driving signal Tx as input by differential modulation circuit after certain combinational logic
And its reverse signal TxB, the differential driving signal fused side information and refreshing information of input signal.Differential driving signal warp
Output signal after differential high voltage capacitive transmission is Rx, RxB.The high-pass filtering constituted due to high pressure differential capacitance and biasing resistor
Effect, Rx, RxB are the sharp pulse signal for corresponding to the edge signal of differential driving signal Tx, TxB.The comparison of hysteresis comparator
Device window threshold value is vthp and vthn, the two threshold voltages be respectively smaller than the differential signal that Rx and RxB are constituted positive pulse and
Negative pulse.When compare delay it is sufficiently small when, hysteresis comparator can effectively restore the side information of input drive signal Tx
Out.Due to further comprising refresh signal in Do_pre, burr elimination circuit, which will refresh after short pulse filters away, be may act as
The output of digital isolating chip, i.e. Do.
The present invention specifically also discloses a kind of modulation-demo-demodulation method of capacitance digital isolating chip, comprising the following steps:
(1) in modulation circuit, refreshing shielded signal and refresh electricity that the output of delay circuit 1, delay circuit 2 generate
Input after the refresh signal integration that road generates as differential encoder, generates modulated differential driving through differential encoder and believes
Number drive differential high voltage capacitor；
(2) differential high voltage capacitor realizes the electrical isolation of modulation circuit and demodulator circuit, and carries out to modulated signal
Coupled transfer；
(3) demodulator circuit restores received pulse signal by hysteresis comparator, decodes back logic level；
(4) then decoded logic level filtering elimination refreshing bring burr is carried out by burr elimination circuit whole
It is exported after shape；Obtain output signal.
It is The present invention gives a kind of reliable digital isolating chip modulation and demodulation method, side information is whole with refreshing information
It closes into a difference isolated transmission channel, fast channel is modulated at edge relatively and refreshing slow channel is used separately two difference isolation
The scheme of transmission channel occupies smaller chip area, reduces the power consumption of chip.
Described embodiment is a part of the embodiment of the present invention, instead of all the embodiments.Based in the present invention
Embodiment, every other embodiment obtained by those of ordinary skill in the art without making creative efforts,
It shall fall within the protection scope of the present invention.
Claims (8)
1. a kind of capacitance digital isolating chip, including modulation circuit, differential high voltage capacitor and demodulator circuit, which is characterized in that
Edge modulation is incorporated into a differential path by the-modulation circuit with refresh circuit, and output incorporates input letter
Number edge signal and refresh circuit generate refresh signal；
- differential high voltage the capacitor for realizing modulation circuit and demodulator circuit electrical isolation, and to modulated signal into
Row coupled transfer；
- demodulator circuit the reception is capacity coupled by modulated signal through differential high voltage, and exports after demodulating.
2. capacitance digital isolating chip according to claim 1, which is characterized in that the modulation circuit and demodulator circuit
Respectively on two independent chip dies.
3. capacitance digital isolating chip according to claim 1 or 2, which is characterized in that the modulation circuit includes prolonging
When circuit 1, delay circuit 2, refresh circuit and differential encoder, the delay circuit 1 connect with differential encoder signal, is delayed
Outputting and inputting for circuit 2 is connect after XOR gate with differential encoder signal, the refresh circuit and differential encoder signal
Connection；Modulated differential driving signal is transferred to demodulator circuit by differential encoder.
4. capacitance digital isolating chip according to claim 3, which is characterized in that the delay ratio of the delay circuit 1
The delay of delay circuit 2 is small, but is greater than the refresh signal pulse width of the refresh circuit.
5. capacitance digital isolating chip according to claim 1, which is characterized in that the differential high voltage capacitor is individually done
On a chips crystal grain；Or it is made on the modulation chip die；Or it is made on the demodulation chip crystal grain；Or by
It is made on modulation chip die and demodulation chip die respectively through composition in series or in parallel.
6. capacitance digital isolating chip according to claim 1, which is characterized in that the demodulator circuit includes biased electrical
Resistance, hysteresis comparator and burr eliminate circuit, and the biasing resistor connects the non-inverting input terminal and reverse phase in hysteresis comparator respectively
Input terminal, the output of the hysteresis comparator and burr eliminate circuit connection, and burr eliminates circuit to decoded logic level
Signal is filtered elimination burr, and the output as digital isolating chip.
7. capacitance digital isolating chip according to claim 6, which is characterized in that the demodulator circuit further includes at a glance
Door dog circuit, the watchdog circuit and burr eliminate circuit connection, are monitored for the output to hysteresis comparator, work as hair
A preset safety level is set by output when raw operation irregularity.
8. a kind of modulation-demo-demodulation method of capacitance digital isolating chip, which comprises the following steps:
(1) in modulation circuit, the refreshing shielded signal and refresh circuit that the output of delay circuit 1, delay circuit 2 generate are produced
Input after raw refresh signal integration as differential encoder, generates modulated differential driving signal through differential encoder
Drive differential high voltage capacitor；
(2) differential high voltage capacitor realizes the electrical isolation of modulation circuit and demodulator circuit, and couples to modulated signal
Transmission；
(3) demodulator circuit restores received pulse signal by hysteresis comparator, decodes back logic level；
(4) after then carrying out shaping to decoded logic level filtering elimination refreshing bring burr by burr elimination circuit
Output；Obtain output signal.
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| CN201810638797.6A CN108988831A (en) | 2018-06-20 | 2018-06-20 | Capacitance digital isolating chip and its modulation-demo-demodulation method |
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| CN201810638797.6A CN108988831A (en) | 2018-06-20 | 2018-06-20 | Capacitance digital isolating chip and its modulation-demo-demodulation method |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109995372A (en) * | 2019-05-20 | 2019-07-09 | 上海客益电子有限公司 | A kind of circuit turning voltage for pwm signal |
| CN110048706A (en) * | 2019-05-20 | 2019-07-23 | 上海客益电子有限公司 | A kind of analog signal isolating conversion circuit |
| CN110048710A (en) * | 2019-05-20 | 2019-07-23 | 上海客益电子有限公司 | A kind of voltage signal isolation converting system |
| CN110266303A (en) * | 2019-07-17 | 2019-09-20 | 重庆线易电子科技有限责任公司 | Refresh circuit, method, chip and data transmission system |
| CN110581694A (en) * | 2019-09-27 | 2019-12-17 | 湖南大学 | High common-mode transient mode immunity filter applied to high-voltage isolation driving chip |
| CN111181547A (en) * | 2020-02-28 | 2020-05-19 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip and capacitive isolation circuit |
| CN111193507A (en) * | 2020-01-14 | 2020-05-22 | 苏州纳芯微电子股份有限公司 | Low-jitter digital isolator circuit and digital isolator comprising same |
| CN111490773A (en) * | 2020-05-20 | 2020-08-04 | 苏州纳芯微电子股份有限公司 | Common mode transient suppression protection circuit for digital isolator |
| WO2020176735A1 (en) | 2019-02-28 | 2020-09-03 | Texas Instruments Incorporated | Architecture for resolution of data and refresh-path conflict for low-power digital isolator |
| CN111969992A (en) * | 2020-08-03 | 2020-11-20 | 苏州纳芯微电子股份有限公司 | Coding and decoding circuit for multi-channel digital signal transmission |
| CN112003593A (en) * | 2020-08-28 | 2020-11-27 | 上海川土微电子有限公司 | Digital signal burr eliminating circuit and method |
| CN113452364A (en) * | 2021-07-22 | 2021-09-28 | 苏州纳芯微电子股份有限公司 | Digital isolator |
| CN113572469A (en) * | 2021-07-29 | 2021-10-29 | 苏州纳芯微电子股份有限公司 | Digital isolator with pseudo-differential structure |
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| WO2020176735A1 (en) | 2019-02-28 | 2020-09-03 | Texas Instruments Incorporated | Architecture for resolution of data and refresh-path conflict for low-power digital isolator |
| EP3932026A4 (en) * | 2019-02-28 | 2022-06-15 | Texas Instruments Incorporated | Architecture for resolution of data and refresh-path conflict for low-power digital isolator |
| CN110048706A (en) * | 2019-05-20 | 2019-07-23 | 上海客益电子有限公司 | A kind of analog signal isolating conversion circuit |
| CN110048710A (en) * | 2019-05-20 | 2019-07-23 | 上海客益电子有限公司 | A kind of voltage signal isolation converting system |
| CN109995372A (en) * | 2019-05-20 | 2019-07-09 | 上海客益电子有限公司 | A kind of circuit turning voltage for pwm signal |
| CN110266303A (en) * | 2019-07-17 | 2019-09-20 | 重庆线易电子科技有限责任公司 | Refresh circuit, method, chip and data transmission system |
| CN110266303B (en) * | 2019-07-17 | 2023-04-28 | 重庆线易电子科技有限责任公司 | Refreshing circuit, refreshing method, chip and data transmission system |
| CN110581694A (en) * | 2019-09-27 | 2019-12-17 | 湖南大学 | High common-mode transient mode immunity filter applied to high-voltage isolation driving chip |
| CN110581694B (en) * | 2019-09-27 | 2021-08-31 | 湖南大学 | High common-mode transient mode immunity filter applied to high-voltage isolation driving chip |
| CN111193507A (en) * | 2020-01-14 | 2020-05-22 | 苏州纳芯微电子股份有限公司 | Low-jitter digital isolator circuit and digital isolator comprising same |
| WO2021142864A1 (en) * | 2020-01-14 | 2021-07-22 | 苏州纳芯微电子股份有限公司 | Low-jitter digital isolator circuit, and digital isolator comprising same |
| US12057838B2 (en) | 2020-01-14 | 2024-08-06 | Suzhou Novosense Microelectronics Co., Ltd. | Low-jitter digital isolator circuit and digital isolator including the same |
| CN111193507B (en) * | 2020-01-14 | 2023-08-11 | 苏州纳芯微电子股份有限公司 | Low-jitter digital isolator circuit and digital isolator comprising same |
| WO2021169082A1 (en) * | 2020-02-28 | 2021-09-02 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip and capacitive isolation circuit |
| CN111181547A (en) * | 2020-02-28 | 2020-05-19 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip and capacitive isolation circuit |
| CN111490773A (en) * | 2020-05-20 | 2020-08-04 | 苏州纳芯微电子股份有限公司 | Common mode transient suppression protection circuit for digital isolator |
| CN111969992A (en) * | 2020-08-03 | 2020-11-20 | 苏州纳芯微电子股份有限公司 | Coding and decoding circuit for multi-channel digital signal transmission |
| CN112003593A (en) * | 2020-08-28 | 2020-11-27 | 上海川土微电子有限公司 | Digital signal burr eliminating circuit and method |
| CN112003593B (en) * | 2020-08-28 | 2023-11-14 | 上海川土微电子有限公司 | Burr eliminating circuit and method for digital signals |
| CN113452364A (en) * | 2021-07-22 | 2021-09-28 | 苏州纳芯微电子股份有限公司 | Digital isolator |
| CN113572469A (en) * | 2021-07-29 | 2021-10-29 | 苏州纳芯微电子股份有限公司 | Digital isolator with pseudo-differential structure |
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Application publication date: 20181211 |