CN113327989B - Thin film transistor, array substrate, display panel and display device - Google Patents
Thin film transistor, array substrate, display panel and display device Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 111
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 68
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 21
- 238000000034 method Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
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- 239000004065 semiconductor Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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- 230000000052 comparative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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Abstract
The application provides a thin film transistor, an array substrate, a display panel and a display device, wherein the thin film transistor comprises an active structure and a grid electrode which are stacked and arranged in an insulating mode through an interlayer insulating layer, the active structure comprises a source region, a drain region and a channel region, the source region and the drain region are located on two sides of the channel region, the grid electrode is a pattern structure layer comprising an opening, and the orthographic projection of the opening on the interlayer insulating layer is located in the orthographic projection of the channel region on the interlayer insulating layer. According to the embodiment of the application, the opening is formed in the grid electrode, so that the length of the inversion layer is reduced, the width-to-length ratio of the thin film transistor is increased on the premise that the line width of the source electrode or the drain electrode is not changed, and the driving capability of the thin film transistor is improved.
Description
Technical Field
The application relates to the technical field of display equipment, in particular to a thin film transistor, an array substrate, a display panel and a display device.
Background
With the development of the current generation display technology, the user's demand for display devices is gradually increasing. The conventional display devices are mainly classified into liquid crystal display devices and organic light emitting display devices, and pixel units in the two display devices are turned on by inputting driving signals into a driving circuit. The thin film transistor is used as a main composition structure of the driving circuit and plays a certain role in influencing a driving signal, so that the brightness of the pixel unit can be controlled by adjusting the structure size of the thin film transistor.
Disclosure of Invention
The embodiment of the application provides a thin film transistor, an array substrate, a display panel and a display device, which can increase the driving current in the thin film transistor and improve the driving capability.
In a first aspect, an embodiment of the present application provides a thin film transistor, including an active structure and a gate electrode, which are stacked and insulated by an interlayer insulating layer, where the active structure includes a source region, a drain region, and a channel region, the source region and the drain region are located at two sides of the channel region, the gate electrode is a pattern structure layer including an opening, and an orthographic projection of the opening on the interlayer insulating layer is located in an orthographic projection of the channel region on the interlayer insulating layer.
In a second aspect, an embodiment of the present application provides an array substrate, where the array substrate has a first region and a second region, the second region is distributed on a peripheral side of the first region, the array substrate includes a demultiplexing module disposed in the second region, the demultiplexing module includes a clock control signal line and a thin film transistor according to any of the foregoing embodiments, and a gate of the thin film transistor is electrically connected to the clock control signal line.
In a third aspect, an embodiment of the present application further provides an array substrate, where the array substrate has a first region and a second region, the second region is distributed on a peripheral side of the first region, the array substrate includes a data line, a scan line, and a first electrode that are disposed in the first region, and the thin film transistor of any of the foregoing embodiments, a first electrode of the thin film transistor is electrically connected to the data line, a second electrode of the thin film transistor is electrically connected to the first electrode, and a gate electrode of the thin film transistor is electrically connected to the scan line.
In a fourth aspect, an embodiment of the present application provides a display panel, including the array substrate of any one of the second aspects.
In a fifth aspect, an embodiment of the present application provides another display panel, including the array substrate and the driving chip of any implementation manner in the third aspect, where the driving chip is disposed in the second region and located on one side of the first region; the first electrode comprises a first sub-electrode and a second sub-electrode, and the first sub-electrode is positioned on one side of the second sub-electrode, which is far away from the driving chip.
The area of the opening in the thin film transistor connected to the first sub-electrode in the orthogonal projection of the interlayer insulating layer is S1, and the area of the opening in the thin film transistor connected to the second sub-electrode in the orthogonal projection of the interlayer insulating layer is S2, where S1> S2.
In a sixth aspect, embodiments of the present application provide a display device, including the display panel of any one of the foregoing embodiments.
The thin film transistor, the array substrate, the display panel and the display device are provided, the thin film transistor comprises a grid and an active structure, the grid falls into the position of an inversion layer in an orthographic projection area of the active structure, the opening is formed in the grid, so that the length of the inversion layer is reduced, the width-length ratio of the thin film transistor is increased on the premise that the line width of a source electrode or a drain electrode is not changed, and the driving capability of the thin film transistor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view taken along a-a' of FIG. 1;
FIG. 3 is a schematic structural diagram of a gate electrode in the TFT shown in FIG. 1;
FIG. 4 is a graph of performance of a TFT provided in an embodiment of the present application versus a TFT provided in a comparative example with respect to gate voltage and drive current;
fig. 5 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a further thin film transistor provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic view of a portion of the demultiplexer assembly of the array substrate of FIG. 8;
fig. 10 is a sectional structure diagram of a display panel according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of another array substrate provided in the embodiment of the present application;
fig. 12 is an enlarged schematic view of a region Q in the array substrate of fig. 11;
FIG. 13 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present application;
description of the labeling:
1. a thin film transistor; 11. an interlayer insulating layer; 12. an active structure; 121. a source region; 122. a drain region; 123. a channel region; 1231. a first region; 1232. a second region; 13. a gate electrode; 131. an opening; 1311. a first side; 1312. a second edge; 14. a source electrode; 15. a drain electrode; 16. a via hole; 161. a first via hole; 162. a second via hole; 17. a sub-transistor; 18. a first pole; 19. a second pole;
2. an array substrate; 21. a first region; 211. a data line; 212. scanning a line; 213. a first electrode; 2131. a first sub-electrode; 2132. a second sub-electrode; 22. a second region; 221. a demultiplexer assembly; 2211. a clock control signal line; 222. a data signal input terminal;
3. a display panel; 31. a color film substrate; 32. a driving chip;
4. a display device;
A. a first direction;
B. a second direction.
Detailed Description
Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a thin film transistor 1 according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of a cross section along a-a' of fig. 1. The embodiment of the application provides a thin film transistor 1, the thin film transistor 1 includes an active structure 12 and a gate 13 which are stacked and insulated by an interlayer insulating layer 11, the active structure 12 includes a source region 121, a drain region 122 and a channel region 123, the source region 121 and the drain region 122 are located at two sides of the channel region 123, the gate 13 is a pattern structure layer including an opening 131, and an orthographic projection of the opening 131 on the interlayer insulating layer 11 is located in an orthographic projection of the channel region 123 on the interlayer insulating layer 11.
It is understood that the thin film transistor 1 is an insulated gate field effect transistor, and mainly includes a conductive layer and a semiconductor layer, the conductive layer includes a gate layer and a source drain layer, and the semiconductor layer and the gate layer, and the gate layer and the source drain layer are respectively separated by an insulating layer. The semiconductor layer includes an active structure 12, the gate layer includes a gate electrode 13, and the gate electrode 13 is disposed corresponding to a channel region 123 in the active structure 12. The source-drain layer includes a source electrode 14 and a drain electrode 15, the source electrode 14 is electrically connected to the source region 121, and the drain electrode 15 is electrically connected to the drain region 122.
When a voltage is applied to the gate 13, a channel for carrier migration is formed in the active structure 12. Specifically, when the thin film transistor 1 is operated, the gate 13 is applied with a voltage and generates an electric field, the direction of the electric field is directed from the gate 13 to the surface of the channel region 123 of the active structure 12, and induced charges are generated at the surface. As the voltage of the gate 13 increases, the surface of the channel region 123 will change from a depletion layer to an electron accumulation layer, forming an inversion layer. When the voltage of the gate 13 reaches the threshold voltage, carriers will pass through the channel region 123 when a voltage is applied between the source region 14 and the drain region 15.
In structural terms, the thin film transistor 1 provided in the embodiment of the present application may be a back channel etching thin film transistor, or may be an etching blocking thin film transistor. In terms of materials, the thin film transistor 1 provided in the embodiment of the present application may be an N-type thin film transistor or a P-type thin film transistor. The N-type thin film transistor is characterized in that N-type ions are doped in an active structure of the thin film transistor, and the P-type thin film transistor is characterized in that P-type ions are doped in the active structure of the thin film transistor. In view of the position of the gate 13, the thin film transistor 1 provided in the embodiment of the present application may be a bottom gate thin film transistor, or a top gate thin film transistor.
In the embodiments of the present application, the thin film transistor 1 is a top gate type thin film transistor and an N-type thin film transistor, but the present invention is not limited thereto.
In the first direction a, the source 14 and the drain 15 of the thin film transistor 1 are respectively disposed on two sides of the gate 13, the gate 13 is a pattern structure layer including the opening 131, the channel region 123 includes a first region 1231 and a second region 1232, an orthographic projection of the gate 13 in the channel region 123 falls into a position where the first region 1231 is located, and an orthographic projection of the opening 131 in the channel region 123 overlaps with a position where the second region 1232 is located.
As can be seen from the foregoing, the gate 13 is applied with a voltage to form an electric field and further form an inversion layer, so that the first region 1231 is the region where the inversion layer is located. When the gate voltage reaches the threshold voltage, a voltage is applied between the source region 14 and the drain region 15 such that carriers pass through the first region 1231. In the embodiment of the present application, in order to reduce the length of the inversion layer in the first direction a, the gate 13 is provided with the opening 131, and the orthographic projection of the opening 131 on the channel region 123 overlaps with the position of the second region 1232, so that the second region 1232 is less affected by the gate 13, and the inversion layer cannot be formed, that is, in the channel region 123, the second region 1232 has a similar function as a resistor.
It can be understood that the driving current of the thin film transistor 1 can be increased by changing the width-to-length ratio of the thin film transistor 1, so as to improve the turn-off capability of the thin film transistor 1 and improve the performance of the thin film transistor 1. The drive current formula of the thin film transistor 1 is as follows:
wherein, IdsW is a line width of the source electrode 14 or the drain electrode 15; l is the distance of the first region 1231 in the first direction a; μ is electron mobility; ε is the dielectric constant of the gate insulation layer; d is the thickness of the gate insulating layer; vgIs the gate voltage; vthIs the threshold voltage.
From the above formula, when other parameters are not changed, the driving current I of the thin film transistor 1 can be increased by increasing the line width W of the source electrode 14 or the drain electrode 15dsOr the driving current I of the thin film transistor 1 is increased by decreasing the interval L of the first regions 1231 in the first direction ads. However, increasing the line width W of the source electrode 14 or the drain electrode 15 increases the overall length of the thin film transistor 1, which in turn decreases the aperture ratio of the display device.
Referring to fig. 1 and fig. 2, the distance L between the first regions 1231 in the first direction a is formed by two portions, L1 and L2, in this embodiment, on the premise of not changing the line width W, the opening 131 is disposed on the gate 13, so that the length of the gate 13 in the first direction a is reduced, the distance L between the first regions 1231 in the first direction a is reduced, and the driving current I of the thin film transistor 1 is increaseddsThe driving capability of the thin film transistor 1 is improved.
Note that the opening 131 on the gate 13 is a through hole structure, and the orthographic projection shape of the opening 131 on the interlayer insulating layer 11 may be a circle, a polygon, or other irregular shape, which is not limited in this application.
Although the resistance of the second region 1232 is increased compared to other designs, the distance L between the first regions 1231 in the first direction a is reduced, i.e., the length of the inversion layer is reduced. The inventor finds through experiments that the reduction of the distance L has a stronger influence on the driving capability of the thin film transistor 1 than the resistance value variation, and therefore, the provision of the opening 131 on the gate 13 can improve the driving capability of the thin film transistor 1 to some extent.
A thin film transistor 1 according to an embodiment of the present application includes a gate 13 and an active structure 12, where an orthographic projection area of the gate 13 on the active structure 12 is a position of the first region 1231, and in this embodiment, an opening 131 is disposed on the gate 13, so as to reduce an interval L of the first region 1231 in the first direction a, and further increase a width-to-length ratio of the thin film transistor 1 and improve a driving capability of the thin film transistor 1 on the premise of not changing a line width W of the source 14 or the drain 15.
Referring to fig. 3, an orthographic projection shape of the opening 131 on the interlayer insulating layer 11 is a rectangle, and a length of a first side 1311 of the rectangle ranges from 1 μm to 2 μm, wherein the first side 1311 is parallel to the first direction a, and the second side 1312 is perpendicular to the first side 1311 and parallel to the second direction B. The rectangular opening 131 is more advantageous for processing the gate 13 than other irregular shapes.
When the length of the first side 1311 of the rectangle is smaller than 1 μm, the pitch L changes less than when no opening is provided in the gate, and the drive current I is setdsThe lifting effect is small; when the length of the first side 1311 is greater than 2 μm, the compressive strength or tensile strength of the gate 13 may be affected due to the greater length of the opening 131 in the first direction a. Therefore, in the embodiment of the present application, the length range of the first edge 1311 is set to 1 μm to 2 μm, so that the distance L of the first region 1231 in the first direction a can be reduced as much as possible on the premise of ensuring the strength of the gate 13, thereby effectively increasing the driving current Ids。
Referring to fig. 4, fig. 4 is a graph of performance of the thin film transistor provided in the embodiment of the present application and the thin film transistor provided in the comparative example with respect to the gate voltage and the driving current, wherein the abscissa represents the driving voltage V of the gate 13gThe size of (d); the vertical axis represents the drive current IdsThe size of (d); a curve a1 represents the performance curve of the thin film transistor 1 in the conventional scheme, i.e., the performance curve in the case where the gate electrode 13 is not provided with the opening 131; a curve a2 shows the performance curve of the thin film transistor 1 in the case where the gate electrode 13 is provided with the opening 131 and the length of the first side 1311 is 2 μm. From the characteristic curves, it can be seen that in the linear region and the saturation region, i.e. VgAt > 0.4V, the voltage V is driven at the same gate 13gIn the case of two kinds of thin film crystalsDrive current I of transistor 1dsThere is a difference. The driving current I of the thin film transistor 1 in the case where the gate electrode 13 is provided with the opening 131 is compared to the conventional casedsThe larger, i.e., the stronger the driving capability of the thin film transistor 1.
Additionally, in some embodiments, the second side 1312 of the rectangle is ≧ 1 μm in length. The second side 1312 is a side of the rectangle perpendicular to the first side 1311, and since an orthogonal projection of the opening 131 on the channel region 123 overlaps with the position of the second region 1232, a length of the second side 1312 is a distance of the second region 1232 in the second direction B. When the length of the second side 1312 is less than 1 μm, the distance of the second region 1232 in the second direction B is too small, and the second region 1232 is easily affected by the gate 13 to form an inversion layer. In this case, since the inversion layers are formed in both the first region 1231 and the second region 1232, the structure of the inversion layer is the same as that of the conventional scheme, and the driving capability of the thin film transistor 1 cannot be improved. In the embodiment of the application, the length of the second edge 1312 is greater than or equal to 1 μm, so that the driving capability of the thin film transistor 1 is improved, and the processing difficulty of the gate 13 is reduced.
Fig. 5 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application, and refer to fig. 2 and fig. 5 together. Further, the interlayer insulating layer 11 includes a via hole 16 formed in the interlayer insulating layer 11, the via hole 16 includes a first via hole 161 and a second via hole 162, the source electrode 14 is electrically connected to the source region 121 through the first via hole 161, the drain electrode 15 is electrically connected to the drain region 122 through the second via hole 162, and a length of the second side 1312 is not less than a maximum distance of the first via hole 161 or the second via hole 162 in a direction parallel to the second direction B.
The first via 161 is used to connect the source 14 and the source region 121, the second via 162 is used to connect the drain 15 and the drain region 122, and the first via 161 and the second via 162 are respectively located at two sides of the gate 13 in the first direction a. In the embodiment, the length of the second side 1312 is set to be not less than the maximum distance of the first via 161 or the second via 162 along the second direction B, so that the width-to-length ratios of the tft 1 at the first via 161 and the second via 162 in the first direction a are consistent, and the driving current I is further effectively increaseddsThe transmission reliability of (2).
Fig. 6 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure, please refer to fig. 6, in some embodiments, a plurality of first vias 161 and a plurality of second vias 162 are disposed, the plurality of first vias 161 and the plurality of second vias 162 are respectively disposed in a first direction a, the plurality of first vias 161 are arranged along a second direction B, and the plurality of second vias 162 are also arranged along the second direction B. In the second direction B, a distance between any two first vias 161 or between any two second vias 162 is not greater than a length of the second side 1312.
The thin film transistor 1 in the embodiment of the present application is formed by connecting a plurality of sub-transistors 17 in parallel, each sub-transistor 17 includes a first via 161 and a corresponding second via 162, and the gates 13 of each sub-transistor 17 are adjacently arranged along the second direction B to form a strip-shaped metal pattern extending along the second direction B; the source electrodes 14 of the sub-transistors 17 are adjacently arranged along the second direction B to form a strip-shaped metal pattern extending along the second direction B; the drain electrodes 15 of each of the sub-transistors 17 are adjacently arranged along the second direction B to form a stripe-shaped metal pattern extending along the second direction B. It can be understood that when the plurality of sub-transistors 17 are connected in parallel, the distance L between the first regions 1231 in the first direction a remains unchanged, and the line width W of the source electrode 14 or the drain electrode 15 is significantly increased, so that the aspect ratio of the thin film transistor 1 is significantly increased, and the driving capability of the thin film transistor 1 is enhanced.
In addition, in the present embodiment, based on the design of the thin film transistor 1, the length of the second side 1312 is increased, so that the length of the second side 1312 is not less than the distance between any two first vias 161 and not less than the distance between any two second vias 162. In the first direction a, any two first vias 161 or any two second vias 162 are disposed corresponding to the openings 131. Therefore, the width-to-length ratio between the corresponding first via 161 and second via 162 at any position in the first direction a is consistent, and the design can ensure the driving current IdsThe transmission reliability of (2).
As shown in fig. 6, in some embodiments, an orthogonal projection of the opening 131 on the interlayer insulating layer 11 is located at the center of an orthogonal projection of the gate electrode 13 on the interlayer insulating layer 11 along the first direction a. By arranging the opening 131 in the center of the gate 13, the reliability of the gate 13 itself can be improved, the problem that the length of one side of the gate 13 in the first direction a is too short, the tensile strength or the compressive strength is insufficient can be prevented, and the processing difficulty of the gate 13 can be reduced.
Fig. 7 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure, referring to fig. 7, in some embodiments, at least two openings 131 are provided, and a plurality of openings 131 are spaced apart from each other in a second direction B in an orthogonal projection of the interlayer insulating layer 11. By arranging one opening 131 into a plurality of openings 131 arranged at intervals, the compressive strength of the grid 13 at the position where the opening 131 is arranged can be improved while the width-to-length ratio is increased, and the overall reliability of the grid 13 is improved.
On the other hand, an array substrate 2 and a display panel 3 are further provided in the embodiments of the present application, fig. 8 is a schematic structural diagram of the array substrate provided in the embodiments of the present application, fig. 9 is a schematic partial structural diagram of a demultiplexer assembly in the array substrate shown in fig. 8, and fig. 10 is a structural diagram of a cross section of the display panel provided in the embodiments of the present application.
Referring to fig. 8 and 9, the array substrate 2 has a first region 21 and a second region 22, the second region 22 is distributed around the first region 21, the array substrate 2 includes a demultiplexer element 221 disposed in the second region 22, wherein the demultiplexer element 221 includes the thin film transistor 1 and the clock control signal line 2211 of any of the foregoing embodiments, and the gate 13 of the thin film transistor 1 is electrically connected to the clock control signal line 2211.
As shown in fig. 9, the demultiplexer component 221 is used to divide a single input into multiple outputs, and the input end of the demultiplexer component is connected to the data signal input end 222, and the output end of the demultiplexer component is correspondingly connected to the plurality of data lines 211. Therefore, the multiple columns of sub-pixel units can provide data signals at different times through one demultiplexer component 221, thereby satisfying the data driving requirement of the display panel 3.
It can be understood that the conventional liquid crystal display panel and organic light emitting display panel are often insufficient to charge the data lines 211 at high frequencies, which may cause uneven brightness or uneven display standard of the pixel units. Alternatively, brightness compensation is achieved by increasing the value of the data signal input by the demultiplexer component 221 to the data line 211, so as to avoid the phenomenon of uneven brightness.
The thin film transistor 1 adopted by the demultiplexer component 221 in the embodiment of the present application is provided with the opening 131 on the gate 13, so as to reduce the length of the inversion layer formed corresponding to the gate 13, thereby improving the driving capability of the thin film transistor 1 on the premise of not changing the line width of the source 14 or the drain 15. And further, the data signal value input by the demultiplexer component 221 to the data line 211 is increased, the charging capability is improved, and the risk of insufficient charging of the data line 211 is avoided.
Referring to fig. 10, a display panel 3 provided in the present embodiment includes the array substrate 2 and the color filter substrate 31. The display panel 3 improves the driving capability of the thin film transistor 1 in the demultiplexer module 221, thereby avoiding the problem of abnormal display due to insufficient charging of the data line 211 and improving the reliability of the display panel 3.
In addition, an array substrate 2 and a display panel 3 are further provided in the embodiment of the present application, fig. 11 is a schematic structural diagram of the array substrate provided in the embodiment of the present application, fig. 12 is an enlarged structural diagram of a region Q in the array substrate shown in fig. 11, and fig. 13 is a schematic structural diagram of the display panel 3 provided in the embodiment of the present application.
Referring to fig. 11 and 12, the array substrate 2 is similar to the array substrate 2, but the difference is that the array substrate 2 includes a data line 211, a scan line 212 and a first electrode 213 disposed in the first region 21, and the thin film transistor 1 of any of the embodiments, the first electrode 18 of the thin film transistor 1 is electrically connected to the data line 211, the second electrode 19 of the thin film transistor 1 is electrically connected to the first electrode 213, and the gate 13 is electrically connected to the scan line 212.
It is understood that the first electrode 18 is the source electrode 14, the second electrode 19 is the drain electrode 15, the first electrode 213 is the pixel electrode, and during the display driving process, the scan line 212 provides the scan signal to the gate electrode 13, and the data line 211 provides the data signal to the first electrode 18. The thin film transistor 1 is switched on and off under the control of a scanning signal of the scanning line 212, thereby controlling the introduction of a data signal to the first electrode 213. It should be noted that the positions of the first electrode 18 and the second electrode 19 in the thin film transistor 1 relative to the gate 13 may be replaced according to actual situations, and the present application does not limit this.
Referring to fig. 13, an embodiment of the present application provides a display panel 3, including an array substrate 2 and a driving chip 32 in the embodiment, where the driving chip 32 is disposed in the second region 22 and located on one side of the first region 21. The first electrode 213 includes a first sub-electrode 2131 and a second sub-electrode 2132, and the first sub-electrode 2131 is located on a side of the second sub-electrode 2132 away from the driving chip 32. Wherein an orthogonal projection of the opening 131 in the thin film transistor 1 connected to the first sub-electrode 2131 on the interlayer insulating layer 11 is S1, and an orthogonal projection area of the opening 131 in the thin film transistor 1 connected to the second sub-electrode 2132 on the interlayer insulating layer 11 is S2, where S1> S2.
When the display panel 3 performs display, the driving chip 32 supplies a driving signal for driving the display to the first electrode 213 in the first region 21 through the data line 211. In a direction away from the driving chip 32, a voltage of the driving signal on the data line 211 may generate a voltage drop with an increase of a distance from the driving chip 32, and the first sub-electrode 2131 is located on a side of the second sub-electrode 2132 away from the driving chip 32, so that a signal error caused by the voltage drop exists between the driving signal received by the first sub-electrode 2131 and the driving signal received by the second sub-electrode 2132.
In this embodiment, the size of the opening 131 in the thin film transistor 1 connected to the first sub-electrode 2131 is larger than the size of the opening 131 in the thin film transistor 1 connected to the second sub-electrode 2312, so that the driving capability of the thin film transistor 1 connected to the first sub-electrode 2131 is larger than that of the thin film transistor 1 connected to the second sub-electrode 2132, thereby balancing the signal error caused by the voltage drop to a certain extent and improving the brightness uniformity in the display screen to a certain extent.
Further, in the direction pointing to the first region 21 from the driving chip 32, the opening 131 in the thin film transistor 1 to which the first electrode 213 is connected gradually increases along the direction away from the driving chip 32, so that the capability of the first electrode 213 to balance the voltage drop gradually increases, and the light emission of the display panel 3 is more uniform.
In addition, an embodiment of the present application further provides a display device 4, please refer to fig. 14, where the display device 4 includes the display panel 3 according to any of the foregoing embodiments. The embodiment of fig. 14 is only an example of a mobile phone, and the display device 4 is described, it is understood that the display device 4 provided in the embodiment of the present invention may be another display device 4 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 4 provided in the embodiment of the present invention has the beneficial effects of the display panel 3 provided in the embodiment of the present invention, and specific descriptions on the display panel 3 in the above embodiments may be specifically referred to, and this embodiment is not described herein again.
While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.
Claims (10)
1. A thin film transistor is characterized by comprising an active structure and a grid electrode which are stacked and arranged in an insulating mode through an interlayer insulating layer, wherein the active structure comprises a source region, a drain region and a channel region, the source region and the drain region are located on two sides of the channel region, the grid electrode is a pattern structure layer comprising an opening, and the orthographic projection of the opening on the interlayer insulating layer is located in the orthographic projection of the channel region on the interlayer insulating layer, so that the driving capability of the thin film transistor is improved by increasing the width-to-length ratio of the thin film transistor;
the length of a first side of the opening is 1-2 microns, the length of a second side is larger than or equal to 1 micron, the orthographic projection of the source region and the orthographic projection of the drain region are located on two sides of the orthographic projection of the channel region in the first direction, the first side is parallel to the first direction, and the second side is perpendicular to the first direction.
2. The thin film transistor according to claim 1, further comprising a source electrode and a drain electrode, wherein the interlayer insulating layer comprises via holes formed in the interlayer insulating layer, the via holes include a first via hole and a second via hole, the source electrode is electrically connected to the source region via the first via hole, the drain electrode is electrically connected to the drain region via the second via hole, and a length of the second side is not less than a maximum distance in a direction parallel to the second side of the first via hole or the second via hole, wherein the second direction is parallel to the second side.
3. The thin film transistor according to claim 2, wherein the first via hole and the second via hole are provided in plural, the plural first via holes and the plural second via holes are respectively provided in correspondence to each other in the first direction, the plural first via holes are arranged in a second direction, and a distance between any two of the first via holes or between any two of the second via holes in the second direction is not greater than a length of the second side.
4. The thin film transistor according to claim 1, wherein an orthogonal projection of the opening on the interlayer insulating layer is located at a center of an orthogonal projection of the gate electrode on the interlayer insulating layer in a first direction, wherein an orthogonal projection of the source region and an orthogonal projection of the drain region on the interlayer insulating layer are located on both sides of an orthogonal projection of the channel region in the first direction.
5. The thin film transistor according to claim 1, wherein the number of the openings is at least two, and a plurality of the openings are provided at intervals in a direction perpendicular to a first direction in an orthogonal projection of the interlayer insulating layer, and wherein an orthogonal projection of the source region and an orthogonal projection of the drain region are located on both sides of an orthogonal projection of the channel region in the first direction on the interlayer insulating layer.
6. An array substrate having a first region and a second region, the second region being distributed on a peripheral side of the first region, the array substrate comprising a demultiplexer assembly disposed in the second region, the demultiplexer assembly comprising:
a thin film transistor according to any one of claims 1 to 5;
and the grid electrode is electrically connected with the clock control signal wire.
7. An array substrate having a first region and a second region, the second region being distributed on a peripheral side of the first region, the array substrate comprising:
data lines, scan lines and first electrodes disposed in the first region, and
a thin film transistor according to any one of claims 1 to 5, wherein a source electrode of the thin film transistor is electrically connected to the data line, a drain electrode of the thin film transistor is electrically connected to the first electrode, and a gate electrode of the thin film transistor is electrically connected to the scan line.
8. A display panel comprising the array substrate according to claim 6.
9. A display panel, comprising:
an array substrate according to claim 7; and
the driving chip is arranged in the second area and is positioned on one side of the first area;
the first electrode comprises a first sub-electrode and a second sub-electrode, and the first sub-electrode is positioned on one side of the second sub-electrode, which is far away from the driving chip;
the opening in the thin film transistor connected to the first sub-electrode has an orthographic area of S1 on the interlayer insulating layer, and the opening in the thin film transistor connected to the second sub-electrode has an orthographic area of S2 on the interlayer insulating layer, wherein S1> S2.
10. A display device, characterized in that it comprises a display panel as claimed in claim 8 and/or 9.
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| CN107505793A (en) * | 2017-09-27 | 2017-12-22 | 上海天马微电子有限公司 | Array substrate and display device |
| CN107895726A (en) * | 2017-11-30 | 2018-04-10 | 武汉天马微电子有限公司 | Array substrate, manufacturing method thereof and display device |
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| JP2004296491A (en) * | 2003-03-25 | 2004-10-21 | Sanyo Electric Co Ltd | Semiconductor device |
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| US7879678B2 (en) * | 2008-02-28 | 2011-02-01 | Versatilis Llc | Methods of enhancing performance of field-effect transistors and field-effect transistors made thereby |
| KR102178766B1 (en) * | 2013-03-29 | 2020-11-13 | 엘지디스플레이 주식회사 | Thin film transistor, method for manufacturing the same and display device comprising the same |
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| CN107359126A (en) * | 2017-07-11 | 2017-11-17 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display panel |
| CN107505793A (en) * | 2017-09-27 | 2017-12-22 | 上海天马微电子有限公司 | Array substrate and display device |
| CN107895726A (en) * | 2017-11-30 | 2018-04-10 | 武汉天马微电子有限公司 | Array substrate, manufacturing method thereof and display device |
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