CN109856875B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN109856875B CN109856875B CN201910150559.5A CN201910150559A CN109856875B CN 109856875 B CN109856875 B CN 109856875B CN 201910150559 A CN201910150559 A CN 201910150559A CN 109856875 B CN109856875 B CN 109856875B
- Authority
- CN
- China
- Prior art keywords
- substrate
- semiconductor structure
- grid
- grid line
- conductive structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides an array substrate, a display panel and a display device, and belongs to the technical field of display. The array substrate of the present invention includes: the anti-static device comprises a substrate, a grid line and an anti-static assembly, wherein the grid line is arranged on the substrate, and the anti-static assembly is sleeved at a signal input end of the grid line; the antistatic assembly includes: a conductive structure, a semiconductor structure; the conductive structure and the semiconductor structure are connected with each other to form a closed ring; wherein, the orthographic projection of the semiconductor structure on the substrate is at least partially overlapped with the orthographic projection of the signal input end of the grid line on the substrate; and the semiconductor structure and the conductive structure are conducted when the voltage on the grid line is greater than a preset voltage so as to reduce the voltage on the grid line.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a display device.
Background
The Liquid Crystal Display is the most commonly used flat panel Display at present, and among them, a Thin Film Transistor Liquid Crystal Display (TFT-LCD) is the mainstream product in the Liquid Crystal Display.
In the TFT-LCD preparation process, the electrostatic problem directly influences the yield of the produced display panel. Specifically, when the display panel is conveyed by the conveying mechanism, static electricity is generated due to friction between the roller in the conveying mechanism and the display panel, and the static electricity is accumulated in each metal electrode (such as a grid metal layer) of the thin film transistor in a large quantity; it should be noted that when enough static electricity is accumulated in the gate metal layer, the static electricity may form a high voltage, so as to break down the gate insulating layer in the thin film transistor, reduce the yield of the display panel, and affect the display effect of the display panel.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides an array substrate, a display panel and a display device with high yield.
The technical scheme adopted for solving the technical problem of the invention is an array substrate, which comprises: the anti-static device comprises a substrate, a grid line and an anti-static assembly, wherein the grid line is arranged on the substrate, and the anti-static assembly is sleeved at the signal input end of the grid line;
the antistatic assembly includes: a conductive structure, a semiconductor structure; the conductive structure and the semiconductor structure are connected with each other to form a closed ring; wherein, the orthographic projection of the semiconductor structure on the substrate is at least partially overlapped with the orthographic projection of the signal input end of the grid line on the substrate; and the semiconductor structure and the conductive structure are conducted when the voltage on the grid line is greater than a preset voltage so as to reduce the voltage on the grid line.
Preferably, the array substrate further includes: a thin film transistor disposed on the substrate; wherein, the first and the second end of the pipe are connected with each other,
a grid electrode insulating layer is arranged between the grid electrode of the thin film transistor and the active layer; an interlayer insulating layer is arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode of the thin film transistor; the grid electrode insulating layer and the interlayer insulating layer are sequentially arranged on the substrate;
the grid line and the grid electrode of the thin film transistor are arranged on the same layer; the conductive structure is arranged on one side of the interlayer insulating layer far away from the substrate; the semiconductor structure is arranged on one side, close to the substrate, of the grid insulating layer;
through holes are respectively formed in two opposite sides of the grid line along the length direction of the grid line, the through holes penetrate through the interlayer insulating layer and the grid insulating layer, and the conductive structure is connected with the semiconductor structure through the through holes.
Preferably, the conductive structure and the source electrode and the drain electrode of the thin film transistor are arranged in the same layer and made of the same material.
Preferably, the semiconductor structure and the active layer of the thin film transistor are arranged in the same layer and made of the same material.
Preferably, a plurality of anti-static assemblies are sleeved on the grid line at intervals.
Preferably, the array substrate further includes: and the grid driving circuit is arranged on the substrate, is electrically connected with the signal input end of the grid line and is used for inputting voltage to the grid line.
Preferably, the semiconductor structure comprises a low temperature polysilicon layer.
Preferably, the material of the conductive structure comprises a metallic material.
The technical scheme adopted for solving the technical problem of the invention is a display panel which comprises any one of the array substrates.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the display panel.
Drawings
Fig. 1 is a schematic view of an array substrate according to embodiment 1 of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A' of an array substrate according to example 1 of the present invention;
fig. 3 is a second schematic view of an array substrate according to embodiment 1 of the invention;
wherein the reference numerals are: 1. a substrate; 2. an anti-static component; 21. a conductive structure; 22. a semiconductor structure; 3. a gate line; 4. a gate insulating layer; 5. an interlayer insulating layer; 6. and (6) a via hole.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
as shown in fig. 1 to 3, the present embodiment provides an array substrate, including: the anti-static device comprises a substrate 1, a grid line 3 arranged on the substrate 1 and an anti-static component 2 sleeved on a signal input end of the grid line 3. Wherein, prevent static subassembly 2 includes: conductive structure 21, semiconductor structure 22; the conductive structure 21 and the semiconductor structure 22 are connected to each other to form a closed loop; the orthographic projection of the semiconductor structure 22 on the substrate 1 is at least partially overlapped with the orthographic projection of the signal input end of the gate line 3 on the substrate 1, that is, as shown in fig. 2, the signal input end of the gate line 3 is arranged in the closed ring; the semiconductor structure 22 and the conductive structure 21 in the anti-static device 2 are turned on when the voltage on the gate line 3 is greater than a predetermined voltage, so as to reduce the voltage on the gate line 3.
Specifically, since the orthographic projection of the signal input end of the gate line 3 on the substrate 1 is at least partially overlapped with the orthographic projection of the semiconductor structure 22 on the substrate 1, when the voltage on the gate line 3 is greater than the preset voltage, that is, strong static electricity is formed in the gate line 3, under the action of the high voltage, the semiconductor structure 22 is excited to be a conductive semiconductor structure 22, that is, the semiconductor structure 22 in the static electricity preventing component 2 is conducted with the conductive structure 21, at this time, the semiconductor structure 22 and the conductive structure 21 can form an annular passage, and the annular passage is equivalent to a coil. Therefore, according to the electromagnetic induction principle, the changed current on the gate line 3 can generate a changed magnetic field, and the changed magnetic field can generate magnetic induction current in the coil, so as to block the change of the original current of the coil, namely block the increase of the current in the gate line 3, correspondingly, the voltage on the gate line 3 can be weakened, thereby avoiding the situation that the gate insulating layer 4 of the thin film transistor is broken down due to the high voltage on the gate line 3 in the prior art, further improving the yield of the display panel comprising the array substrate of the embodiment, and enabling the display panel to have a better display effect.
When the voltage on the gate line 3 is less than the predetermined voltage, that is, a low voltage is formed on the gate line 3, the voltage on the gate line 3 is not enough to turn on the semiconductor structure 22 and the conductive structure 21 in the anti-static component 2, and at this time, the voltage on the gate line 3 can be normally conducted to the gate electrode of the thin film transistor, so that the array substrate can work.
For the purpose of understanding the present embodiment, the structure of the static electricity prevention assembly 2 will be specifically described below.
As shown in fig. 2, the array substrate of the present embodiment further includes: a thin film transistor disposed on the substrate 1; the thin film transistor includes: a gate electrode, a gate insulating layer 4, an active layer, an interlayer insulating layer 5, a source electrode electrically connected to the source electrode contact region of the active layer, and a drain electrode electrically connected to the drain electrode contact region of the active layer, which are sequentially disposed on the substrate 1. The gate line 3 and the gate of the thin film transistor in this embodiment are arranged on the same layer; the conductive structure 21 is arranged on one side of the interlayer insulating layer 5 away from the substrate 1; the semiconductor structure 22 is arranged on one side of the gate insulating layer 4 close to the substrate 1; along the length direction of the gate line 3, via holes 6 are respectively arranged on two opposite sides of the gate line 3, the via holes 6 penetrate through the interlayer insulating layer 5 and the gate insulating layer 4, and the conductive structure 21 is connected with the semiconductor structure 22 through the via holes 6.
That is, as shown in fig. 2, along a direction away from the substrate 1, the semiconductor structure 22, the gate line 3, and the conductive structure 21 in this embodiment are sequentially disposed on the substrate 1, and the conductive structure 21 and the semiconductor structure 22 are connected through the via holes 6 on the left and right sides of the gate line 3, so that the conductive structure 21 and the semiconductor structure 22 form a closed ring, and the gate line 3 in this embodiment is limited in the closed ring. Thus, when a high voltage is formed on the gate line 3, the semiconductor structure 22 can be conducted with the conductive structure 21 to form a ring-shaped path to weaken the high voltage on the gate line 3, thereby avoiding the situation that the gate insulating layer 4 of the thin film transistor is broken due to the high voltage on the gate line 3 in the prior art, and further improving the yield of the display panel including the array substrate of the embodiment.
In order to achieve the light and thin of the array substrate of this embodiment and simplify the manufacturing process of the array substrate of this embodiment, preferably, the conductive structure 21 of this embodiment and the source and the drain of the thin film transistor are disposed in the same layer and made of the same material.
Further preferably, the semiconductor structure 22 of the present embodiment is disposed on the same layer as the active layer of the thin film transistor, and the material is the same.
In order to avoid the phenomenon that the gate insulating layer 4 is broken down by a high voltage due to an excessive voltage on the gate line 3, preferably, a plurality of anti-static components 2 are alternately sleeved on the gate line 3 of the embodiment.
Specifically, as shown in fig. 3, the plurality of anti-static components 2 are arranged on the gate line 3 in a series connection manner, and at this time, according to the voltage division principle, each anti-static component 2 on the gate line 3 can divide the voltage on the gate line 3, so as to further weaken the voltage on the gate line 3, thereby ensuring that the voltage on the gate line 3 is less than the preset voltage, that is, the voltage on the gate line 3 cannot break down the gate insulating layer 4.
Preferably, the Array substrate further includes a Gate Driver On Array (GOA) disposed On the substrate 1, and electrically connected to the signal input end of the Gate line 3, for inputting a voltage to the Gate line 3.
Preferably, in this embodiment, the semiconductor structure 22 includes a low temperature polysilicon layer. Of course, the semiconductor structure 22 in this embodiment is not limited to the low-temperature polysilicon layer, and is not limited thereto.
Preferably, in this embodiment, the material of the conductive structure 21 includes a metal material. The metal material has good conductive properties that enhance its conductivity with the semiconductor structure 22.
Of course, the material of the conductive structure 21 in the present embodiment is not limited to the above-mentioned metal material, as long as it has better conductive performance, and is not listed here.
In summary, the array substrate of the present embodiment includes the anti-static component 2 disposed at the signal input end of the gate line 3, the anti-static component 2 includes the semiconductor structure 22 and the conductive structure 21 sequentially disposed on the substrate 1 along the direction away from the substrate 1, and the conductive structure 21 and the semiconductor structure 22 are connected through the via holes 6 at the left and right sides of the gate line 3, so that the conductive structure 21 and the semiconductor structure 22 form a closed ring, and the gate line 3 in this embodiment is limited in the closed ring. Thus, when a high voltage is formed on the gate line 3, the semiconductor structure 22 can be conducted with the conductive structure 21 to form a ring-shaped path to weaken the high voltage on the gate line 3, thereby avoiding the situation that the gate insulating layer 4 of the thin film transistor is broken due to the high voltage on the gate line 3 in the prior art, and further improving the yield of the display panel including the array substrate of the embodiment.
Example 2:
the present embodiment provides a display panel including the array substrate in embodiment 1.
Since the display panel of the embodiment includes the array substrate, the display panel of the embodiment has a better display effect.
Example 3:
the present embodiment provides a display device including the display panel in embodiment 2.
Since the display device of the embodiment includes the display panel, the display device of the embodiment has a better display effect.
The display device of the present embodiment may be a liquid crystal display device or an electroluminescent display device, for example: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (7)
1. An array substrate, comprising: the anti-static device comprises a substrate, a grid line and an anti-static assembly, wherein the grid line is arranged on the substrate;
the antistatic assembly includes: a conductive structure, a semiconductor structure; the conductive structure and the semiconductor structure are connected with each other to form a closed ring; wherein the orthographic projection area of the semiconductor structure on the substrate is larger than that of the conductive structure on the substrate, and the thickness of the semiconductor structure along the direction vertical to the substrate is smaller than that of the conductive structure along the direction vertical to the substrate; the orthographic projection of the semiconductor structure on the substrate is at least partially overlapped with the orthographic projection of the signal input end of the grid line on the substrate; the semiconductor structure and the conductive structure are conducted when the voltage on the grid line is greater than a preset voltage, so that the voltage on the grid line is reduced;
the array substrate further includes: a thin film transistor disposed on the substrate; wherein the content of the first and second substances,
a grid insulating layer is arranged between the grid of the thin film transistor and the active layer; an interlayer insulating layer is arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode of the thin film transistor; the grid electrode insulating layer and the interlayer insulating layer are sequentially arranged on the substrate;
the grid line and the grid electrode of the thin film transistor are arranged on the same layer; the conductive structure is arranged on one side of the interlayer insulating layer far away from the substrate; the semiconductor structure is arranged on one side, close to the substrate, of the grid insulating layer;
through holes are respectively formed in two opposite sides of the grid line along the length direction of the grid line, the through holes penetrate through the interlayer insulating layer and the grid insulating layer, and the conductive structure is connected with the semiconductor structure through the through holes;
the conductive structure and the source electrode and the drain electrode of the thin film transistor are arranged on the same layer and are made of the same material;
the semiconductor structure and the active layer of the thin film transistor are arranged on the same layer and made of the same material.
2. The array substrate of claim 1, wherein a plurality of anti-static components are spaced apart on the gate lines.
3. The array substrate of claim 1, further comprising: and the grid driving circuit is arranged on the substrate, is electrically connected with the signal input end of the grid line and is used for inputting voltage to the grid line.
4. The array substrate of claim 1, wherein the semiconductor structure comprises a low temperature polysilicon layer.
5. The array substrate of claim 1, wherein the material of the conductive structure comprises a metal material.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A display device characterized by comprising the display panel described in claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910150559.5A CN109856875B (en) | 2019-02-28 | 2019-02-28 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910150559.5A CN109856875B (en) | 2019-02-28 | 2019-02-28 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109856875A CN109856875A (en) | 2019-06-07 |
| CN109856875B true CN109856875B (en) | 2022-06-21 |
Family
ID=66899263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910150559.5A Active CN109856875B (en) | 2019-02-28 | 2019-02-28 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109856875B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110867138A (en) * | 2019-11-28 | 2020-03-06 | 武汉天马微电子有限公司 | Display panel, manufacturing method and display device |
| CN113078172B (en) * | 2021-03-29 | 2023-05-26 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method thereof and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0556989A1 (en) * | 1992-02-21 | 1993-08-25 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
| CN1539093A (en) * | 2001-08-08 | 2004-10-20 | �ʼҷ����ֵ��ӹɷ�����˾ | Electrostatic discharge protection for pixellated electronic device |
| CN101075611A (en) * | 2006-05-18 | 2007-11-21 | 元太科技工业股份有限公司 | Active array device |
| JP2007310131A (en) * | 2006-05-18 | 2007-11-29 | Mitsubishi Electric Corp | Active matrix substrate and active matrix display device |
| CN107479283A (en) * | 2017-08-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN208422916U (en) * | 2018-08-07 | 2019-01-22 | 京东方科技集团股份有限公司 | array substrate and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008078426A1 (en) * | 2006-12-22 | 2008-07-03 | Sharp Kabushiki Kaisha | Active matrix substrate and display panel equipped with the same |
| CN113078172B (en) * | 2021-03-29 | 2023-05-26 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method thereof and display panel |
-
2019
- 2019-02-28 CN CN201910150559.5A patent/CN109856875B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0556989A1 (en) * | 1992-02-21 | 1993-08-25 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
| CN1539093A (en) * | 2001-08-08 | 2004-10-20 | �ʼҷ����ֵ��ӹɷ�����˾ | Electrostatic discharge protection for pixellated electronic device |
| CN101075611A (en) * | 2006-05-18 | 2007-11-21 | 元太科技工业股份有限公司 | Active array device |
| JP2007310131A (en) * | 2006-05-18 | 2007-11-29 | Mitsubishi Electric Corp | Active matrix substrate and active matrix display device |
| CN107479283A (en) * | 2017-08-30 | 2017-12-15 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN208422916U (en) * | 2018-08-07 | 2019-01-22 | 京东方科技集团股份有限公司 | array substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109856875A (en) | 2019-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109887985B (en) | Array substrate, display panel and display device | |
| US20200168686A1 (en) | Display panel and display device | |
| JP6483843B2 (en) | Array substrate, manufacturing method thereof, and display device | |
| US9425216B2 (en) | Thin film transistor substrate having metal oxide semiconductor and manufacturing the same | |
| US10204930B2 (en) | Ultra high density thin film transistor substrate having low line resistance structure and method for manufacturing the same | |
| TW457384B (en) | Electrode structure for a wide viewing angle liquid crystal display | |
| WO2014166153A1 (en) | Array substrate, method for manufacture thereof and display device thereof | |
| CN107577099B (en) | Array substrate, liquid crystal display panel and liquid crystal display device | |
| CN109856875B (en) | Array substrate, display panel and display device | |
| US9515191B2 (en) | Thin-film field effect transistor, driving method thereof, array substrate, display device, and electronic product | |
| US11177295B2 (en) | Array substrate, manufacturing method thereof and display device | |
| US20170033236A1 (en) | Thin-film transistor structure | |
| CN103250092B (en) | Liquid crystal indicator | |
| US11204530B2 (en) | Array substrate and display device | |
| CN105759515A (en) | Liquid crystal display device and driving method thereof | |
| US11901354B2 (en) | Array substrate, manufacturing method thereof and display device | |
| CN109188798B (en) | Display panel and display device | |
| CN106842747B (en) | Array substrate, manufacturing method thereof and display device | |
| US20080068522A1 (en) | Display device and a method of manufacturing the same | |
| WO2017206660A1 (en) | Thin film transistor, array substrate, display panel, and display device | |
| CN110010698B (en) | Thin film transistor, preparation method thereof, display substrate and display device | |
| US9818739B2 (en) | Array substrate and manufacturing method thereof, and a display device | |
| US11133334B2 (en) | Array substrate with stacked gate lines, manufacturing method thereof, and display device with stacked gate lines | |
| US20190259782A1 (en) | Display device | |
| CN111367130A (en) | Array substrate, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |