CN107479283A - A kind of array base palte, display panel and display device - Google Patents
A kind of array base palte, display panel and display device Download PDFInfo
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- CN107479283A CN107479283A CN201710764644.1A CN201710764644A CN107479283A CN 107479283 A CN107479283 A CN 107479283A CN 201710764644 A CN201710764644 A CN 201710764644A CN 107479283 A CN107479283 A CN 107479283A
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- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
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- 238000004519 manufacturing process Methods 0.000 description 4
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- 239000007769 metal material Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/22—Antistatic materials or arrangements
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Abstract
The present invention discloses a kind of array base palte, display panel and display device, and its first non-display area includes：Underlay substrate, a plurality of touch-control being arranged on underlay substrate are fanned out to cabling, the first binding pin and are connected to a plurality of touch-control connecting line that each touch-control is fanned out between cabling and the first binding pin；Touch-control is fanned out to cabling and is arranged at different film layers from touch-control connecting line and is connected one to one by via；Touch-control is fanned out to cabling and overlapping region be present in the orthographic projection of underlay substrate with the touch-control connecting line of corresponding connection；The connection corresponding with each touch-control connecting line of each touch-control electrostatic discharge protective circuit, and touch-control electrostatic discharge protective circuit partly overlaps in the orthographic projection of underlay substrate with overlapping region.Touch-control electrostatic discharge protective circuit is arranged on the overlapping region that touch-control is fanned out to cabling and touch-control connecting line; so that touch-control electrostatic discharge protective circuit does not take other wiring spaces additionally; the space taken is saved required for script touch-control electrostatic discharge protective circuit, so as to reduce the frame where non-display area to realize narrow frame.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
With the rapid development of display technology, the shape requirements of displays are gradually increasing in addition to the functions of traditional information display, for example, the current mobile phones with full-screen are favored by consumers, and it is a future development trend of the market to reduce the frame area and implement a larger screen ratio by special design. In order to meet the requirement of a user on the appearance of the display, the display screen can be subjected to special-shaped design, such as C/R cut, namely the display screen is subjected to straight chamfer or arc chamfer, the special-shaped design can enable the display screen to have better mechanism strength, can also enhance the reliability of the display screen and can obtain better appearance effect.
Generally, a switch circuit, a data signal line, a protection circuit for a touch signal line, and the like are generally disposed at an upper frame position of the irregular display screen. Due to the fact that the border area of the special-shaped display screen has the problem of pixel staggered arrangement, the circuits cannot be arranged on the border in a flush mode, 50 microns are required to be added to the left side and the right side of the upper border respectively, and therefore the space is difficult to compress to achieve a narrow border in the prior art.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for simplifying the line distribution of a non-display area and realizing narrow frame design by compressing space.
In a first aspect, an embodiment of the present invention provides an array substrate, including: the array substrate is divided into a display area and a non-display area surrounding the display area, and the non-display area comprises a first non-display area; wherein,
the first non-display area includes: the touch control device comprises a substrate base plate, a plurality of touch control fan-out wires, first binding pins and a plurality of touch control connecting wires, wherein the touch control fan-out wires, the first binding pins and the plurality of touch control connecting wires are arranged on the substrate base plate; wherein,
the touch fan-out wiring and the touch connecting line are arranged on different film layers and are connected in a one-to-one correspondence mode through via holes; an overlapping area exists between the touch fan-out wiring and the orthographic projection of the correspondingly connected touch connecting line on the substrate;
the first non-display area further includes: the touch control electrostatic protection circuit is correspondingly connected with the touch control connecting lines, and the orthographic projection of the touch control electrostatic protection circuit on the substrate is partially overlapped with the overlapping area.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, the touch electrostatic protection circuits are connected to the touch connection lines in a one-to-one correspondence manner.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, a length of the touch electrostatic protection circuit parallel to the touch connecting line is less than a length of the overlapping area parallel to the touch connecting line.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the first non-display area further includes a plurality of data signal lines;
any one data signal line comprises a data fan-out line and a data connecting line connected with the data fan-out line;
the data fan-out routing and the touch control connecting line are arranged on the same layer;
the touch fan-out wiring and the data connecting line are arranged on the same layer.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, at least one data signal line is disposed between two adjacent touch connection lines;
each touch electrostatic protection circuit is located between two adjacent data signal lines on two sides of each touch connecting line.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, orthographic projections of the touch electrostatic protection circuit and the data signal line on the substrate do not overlap each other.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, there is an overlapping area between the touch electrostatic protection circuit and the orthographic projection of the data signal line on the substrate.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the touch electrostatic protection circuit includes: at least one transistor group, each of the transistor groups including a first transistor and a second transistor of different types, wherein,
the grid electrode of the first transistor is connected with the source electrode, and the drain electrode of the first transistor is connected with the corresponding touch control connecting line;
the grid electrode of the second transistor is connected with the source electrode, and the drain electrode of the second transistor is connected with the corresponding touch control connecting line.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the first non-display area further includes: the high-level signal line and the low-level signal line are arranged on the same layer as the touch control connecting line; the orthographic projections of the high-level signal lines and the low-level signal lines on the substrate are not overlapped with the orthographic projections of the data fan-out wires and the touch connecting lines on the substrate;
the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the source electrode of the first transistor is connected with the high-level signal line, and the source electrode of the second transistor is connected with the low-level signal line.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the electrostatic protection circuit includes: at least one transistor group, each of the transistor groups including a first transistor and a second transistor of the same type; wherein,
the grid electrode of the first transistor is connected with the corresponding touch control connecting line, and the source electrode of the first transistor is connected with the grid electrode of the first transistor;
the drain electrode of the second transistor is connected with the corresponding touch control connecting line, and the source electrode of the second transistor is connected with the grid electrode of the second transistor.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the first non-display area further includes: the high-level signal line and the low-level signal line are arranged on the same layer as the touch control connecting line; the orthographic projections of the high-level signal lines and the low-level signal lines on the substrate are not overlapped with the orthographic projections of the data fan-out wires and the touch connecting lines on the substrate;
the first transistor and the second transistor are N-type transistors; the drain of the first transistor is connected with the high-level signal line, and the source of the second transistor is connected with the low-level signal line; or,
the first transistor and the second transistor are P-type transistors; the drain of the first transistor is connected to the low-level signal line, and the source of the second transistor is connected to the high-level signal line.
In a second aspect, an embodiment of the invention provides a display panel, including any one of the array substrates described above.
In a third aspect, an embodiment of the present invention provides a display device, including the display panel.
The invention has the following beneficial effects:
according to the array substrate, the display panel and the display device provided by the embodiment of the invention, the array substrate is divided into a display area and a non-display area surrounding the display area, and the non-display area comprises a first non-display area; wherein the first non-display area includes: the touch control device comprises a substrate base plate, a plurality of touch control fan-out wires, first binding pins and a plurality of touch control connecting wires, wherein the touch control fan-out wires, the first binding pins and the touch control connecting wires are arranged on the substrate base plate; the touch fan-out wiring and the touch connecting wire are arranged on different film layers and are connected in a one-to-one correspondence mode through the through holes; overlapping areas exist in orthographic projections of the touch fan-out wirings and the correspondingly connected touch connecting lines on the substrate; the first non-display area further includes: and each touch electrostatic protection circuit is correspondingly connected with each touch connecting line, and the orthographic projection and the overlapping area of the touch electrostatic protection circuits on the substrate are partially overlapped. The touch electrostatic protection circuit is arranged in an overlapping area of the touch fan-out wiring and the touch connecting line, so that the touch electrostatic protection circuit does not additionally occupy other wiring space, the space of a non-display area which is originally occupied by the touch electrostatic protection circuit is saved, the frame where the non-display area is located is reduced, and narrow frame design is realized.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first non-display area according to an embodiment of the present invention;
fig. 3 is a second schematic structural diagram of the first non-display area according to the embodiment of the invention;
fig. 4 is a schematic structural diagram of a touch electrostatic protection circuit according to an embodiment of the present invention;
fig. 5 is a second schematic structural diagram of a touch electrostatic protection circuit according to an embodiment of the present invention;
fig. 6 is an equivalent circuit diagram of the touch electrostatic protection circuit shown in fig. 5;
fig. 7a is a third schematic structural diagram of a touch electrostatic protection circuit according to an embodiment of the present invention;
FIG. 7b is an equivalent circuit diagram of the touch electrostatic protection circuit shown in FIG. 7 a;
fig. 8a is a third schematic structural diagram of a touch electrostatic protection circuit according to an embodiment of the present invention;
FIG. 8b is an equivalent circuit diagram of the touch electrostatic protection circuit shown in FIG. 8 a;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for simplifying the line distribution of a non-display area and realizing narrow frame design by compressing space.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are only for illustrating the relative positional relationship, the layer thicknesses of some parts are exaggerated in a drawing manner for easy understanding, and the layer thicknesses in the drawings do not represent the proportional relationship of the actual layer thicknesses.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. Reference throughout the specification and claims to one element being "on" side of another element includes the case where the element is adjacent to or not adjacent to the other element. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims. The thicknesses and shapes of the respective components in the drawings of the present application do not reflect the true scale of the display device, and are merely intended to schematically illustrate the present invention.
The following describes an array substrate, a display panel and a display device provided in an embodiment of the present invention with reference to the accompanying drawings. The thicknesses and shapes of the respective components in the drawings do not reflect the true scale of the display device, and are merely intended to schematically illustrate the present invention.
As shown in fig. 1, the array substrate provided by the embodiment of the invention is divided into a display area 100 and a non-display area 200 surrounding the display area 100, wherein the non-display area 200 includes a first non-display area 21.
Specifically, as shown in fig. 2, fig. 2 is a schematic structural diagram of the first non-display area 21. The first non-display area 21 includes: the touch screen comprises a substrate base plate 211, a plurality of touch fan-out wires 212, first binding pins 213 and a plurality of touch connecting wires 214, wherein the plurality of touch fan-out wires 212 and the first binding pins 213 are arranged on the substrate base plate 211; wherein: the touch fan-out traces 212 and the touch connecting lines 214 are arranged on different film layers and are connected in a one-to-one correspondence manner through the via holes 215; an overlapping area P exists between the touch fan-out traces 212 and the touch connecting lines 214 correspondingly connected to the same in the orthographic projection of the substrate.
As shown in fig. 2, the first non-display area 21 further includes: and a plurality of touch electrostatic protection circuits 216, wherein each touch electrostatic protection circuit 216 is connected to each touch connection line 214, and the orthogonal projection of the touch electrostatic protection circuit 214 on the substrate overlaps with the overlapping region P.
In an implementation, the first non-display area 21 may be a non-display area including a bonding area, the first non-display area 21 has a driving chip therein, the first bonding pins 213 may be bonding pins of the driving chip, and are used for connecting each touch signal line (including the touch fan-out trace 212 and the touch connection line 214) to the driving chip for controlling a touch signal, and another end of each touch signal line is connected to each touch electrode in the display area. Further, the extending directions of the touch fan-out traces 212 are different from each other, and therefore the touch fan-out traces 212 cannot be directly connected to the first bonding pins 213, and therefore, each touch fan-out trace 212 needs to be connected to each corresponding first bonding pin 213 through one touch connection line 214. Since the number of the touch fan-out traces is large, the length of the touch connection line 214 needs to be at least greater than a predetermined minimum value to ensure that all the touch fan-out traces 212 are connected to the first bonding pins 213 through the touch connection line 214, so that an overlapping area of the touch fan-out traces 212 and the touch connection line 214 has a certain length, and a touch electrostatic protection circuit connected to the touch connection line 214 can be disposed in a space of the overlapping area, thereby avoiding the need to additionally reserve a wiring space for the touch electrostatic protection circuit, saving a part of space where the touch electrostatic protection circuit is originally disposed, reducing a frame where the first non-display area is located, and facilitating the realization of a narrow frame design.
In the array substrate provided in the embodiment of the invention, as shown in fig. 2, the touch electrostatic protection circuit 216 partially overlaps the overlap region P, which is beneficial for connecting the touch electrostatic protection circuit to the touch connection line, and there is no need to provide more connection lines between the touch electrostatic protection circuit and the touch connection line, and in practical applications, the touch electrostatic protection circuit and the touch connection line can be directly connected to each other through the via hole.
Further, in the array substrate according to the embodiment of the present invention, as shown in fig. 2, the touch electrostatic protection circuits 216 are connected to the touch connection lines 214 in a one-to-one correspondence manner. The touch electrostatic protection circuit 216 is disposed for each touch connection line 214, so as to protect each signal line for transmitting the touch signal from electrostatic protection, and protect the touch signal lines of the array substrate from abnormality due to too large or too small transmitted electrical signals.
In specific implementation, in the array substrate provided by the embodiment of the invention, as shown in fig. 2, a length L1 of the touch esd protection circuit 216 parallel to the touch connection lines 214 is smaller than a length L2 of an overlapped area P generated by the touch fan-out traces 212 and the touch connection lines 214 parallel to the touch connection lines 214. Therefore, it can be ensured that each of the touch electrostatic protection circuits 216 is disposed in the overlapping region P without occupying other space, and each of the touch electrostatic protection circuits 216 can be protected to be effectively connected to each of the touch connection lines 214, for example, the touch electrostatic protection circuit 216 can be connected to the touch connection line 214 through a via hole.
Further, in the array substrate provided in the embodiment of the present invention, as shown in fig. 3, the first non-display area 21 further includes a plurality of data signal lines 210; any data signal line 210 includes a data fan-out trace 217 and a data connection line 218 connecting the data fan-out trace 217.
The data fan-out wiring 217 and the touch connection line 214 are arranged on the same layer; the touch fan-out traces 212 and the data connection lines 218 are disposed on the same layer.
In specific implementation, the signal lines are made of metal materials, in order to save wiring space, fan-out wiring lines and connecting lines of the signal lines can be arranged on different metal layers, and insulating layers are arranged between the metal layers. By adopting the laminated arrangement of the signal wires, the wiring space can be effectively saved. And when the signal lines at different layers are connected with each other through the via holes. For example, in the embodiment of the present invention, the touch fan-out traces 212 and the touch connection lines 214 are located at different layers, and the touch fan-out traces 212 are located at the upper layer of the touch connection lines 214; the data fan-out traces 217 and the data connection lines 218 are also located on different layers, the data fan-out traces 217 and the touch connection lines 214 are located on the same layer, and the data connection lines 218 and the touch fan-out traces 212 are located on the same layer, that is, the data connection lines 218 are located on the upper layer of the data fan-out traces 217. The data fan-out traces 217 and the data link lines 218 are also connected to each other by vias 219.
In addition, the structure that the fan-out wiring of the signal lines and the connecting lines are arranged on different layers is adopted, overlapping among some signal lines can be avoided, and therefore signal crosstalk is avoided. As shown in fig. 3, the first non-display area may include a high-level signal line for transmitting a high-level signal source signal and a low-level signal line for transmitting a low-level signal source signal, and the extending directions of the two signal lines are not consistent with the extending directions of the touch connection line 214 and the data connection line 218, so that if the signal lines are arranged in the same layer, crossing areas exist between the high-level signal line and the low-level signal line and between the touch control signal line and the data signal line, and signals cannot be effectively transmitted. In the embodiment of the present invention, the touch signal line-folding touch fan-out line 212 and the touch connection line 214 are disposed at different layers, and the data fan-out line 217 and the data connection line 218 of the pin data signal line are disposed at different layers, so that each fan-out line (or connection line) can be disconnected when encountering a high-level signal line and a low-level signal line, and the connection with the connection lines (or fan-out lines) at different layers of the high-level signal line and the low-level signal line can avoid contact with the high-level signal line and the low-level signal line.
Specifically, in the embodiment of the present invention, as shown in fig. 3, at least one data signal line 210 is disposed between two adjacent touch connection lines 214; each touch electrostatic protection circuit 216 is located between two adjacent data signal lines 210 on two sides of each touch connection line 214. In an actual manufacturing process, the spacing between the metal lines of the metal layer where the data connection line 218 is located may be about 85.5 μm, and the width of the touch electrostatic protection circuit perpendicular to the data connection line 218 may be flexibly set, and when the area of the touch electrostatic protection circuit is larger, the electrostatic protection capability is stronger; since the space at the installation position is limited, in order to set one touch electrostatic protection circuit for each touch connection line 214 and prevent the touch electrostatic protection circuits from overlapping with each other, the touch electrostatic protection circuits may be set in the following two embodiments.
In one implementation, as shown in fig. 4, the touch esd protection circuit 216 and the data signal line (specifically, the data connection line 218 in this portion) do not overlap each other in the orthographic projection of the substrate. In an actual manufacturing process, the area of the touch electrostatic protection circuit 216 may be compressed as much as possible, so that there is no overlapping area between the touch electrostatic protection circuit 216 and the data signal line, and parasitic capacitance generated in the overlapping area can be avoided.
In another implementation, as shown in fig. 5, there is an overlapping area between the touch esd protection circuit 216 and the orthographic projection of the data signal lines (specifically, the data connection lines 218) on the substrate. In an actual manufacturing process, in order to improve the anti-static capability of the touch electrostatic protection circuit 216 to the maximum extent, the area of the touch electrostatic protection circuit may be increased as large as possible. In addition, it is also ensured that each touch connection line 214 is connected to one touch esd protection circuit 216, the touch esd protection circuit 216 may have an overlapping area with both data signal lines, and to the maximum extent, the edge of the touch esd protection circuit 216 parallel to the data connection line 218 may be flush with the outer edge of the data connection line 218 (see fig. 5).
The specific structure of the touch electrostatic protection circuit is described in detail below.
In one implementation, as shown in fig. 4 and 5, the touch electrostatic protection circuit 216 includes: at least one transistor group 2161, as shown in FIG. 4, each transistor group 2161 includes a first transistor T of different type1And a second transistor T2。
Wherein the first transistor T1Gate G of1And source S1Connected, a first transistor T1Drain electrode D of1Connected 214 with the corresponding touch connection line; second transistor T2Gate G of2And source S2Connected, a second transistor T2Drain electrode D of2Connected to the corresponding touch connection line 214. In practical applications, the first transistor T is provided1And a second transistor T2The source and drain of (a) may be interchanged.
In a specific implementation, as shown in fig. 4 and 5, the first non-display area further includes: a high-level signal line VGH and a low-level signal line VGL provided on the same layer as the touch connection line 214; the orthographic projections of the high-level signal line VGH and the low-level signal line VGL on the substrate base plate are not overlapped with the orthographic projections of the data fan-out wiring 212 and the touch connection line 214 on the substrate base plate.
The high-level signal line VGH and the low-level signal line VGL are disposed on the same layer as the touch connection line 214, and also disposed on the same layer as the data fan-out line 217. As shown in fig. 4 and 5, the high-level signal line VGH and the low-level signal line VGL have different extending directions from the data fan-out line 217 and the touch connection line 214, the data fan-out line 217 and the touch connection line 214 are cut off in regions close to the high-level signal line VGH and the low-level signal line VGL, the data connection line 218 located in different layers (e.g., located in a previous metal layer) is used to connect the data fan-out line 217 through a via hole, and the touch connection line 214 is connected through a via hole by using the touch fan-out line 212, so that the data fan-out line 217 and the touch connection line 214 do not have overlapping regions with the high-level signal line VGH and the low-level signal line VGL, and abnormal signal transmission caused by mutual crossing between different signal lines is avoided.
In a specific implementation, the first transistor T1And a second transistor T2All corresponding to a diode. When the voltage of the touch connection line 214 is within a normal range, i.e., greater than the voltage of the low-level signal line VGL and less than the voltage of the high-level signal lineAt VGH voltage, the first transistor T1And a second transistor T2The electrostatic protection circuit does not work, and the voltage in the touch connection line 214 is not affected. When the voltage in the touch connection line 214 is higher than the voltage of the high level signal line VGH due to the occurrence of the static electricity of positive charges, the first transistor T1Forward conduction is performed, so that static electricity in the touch connection line 214 can be conducted away, and the voltage in the touch connection line 214 is maintained at a high potential; when the voltage in the touch connection line 214 is lower than the voltage of the low level signal line VGL due to the occurrence of the static electricity of negative charges, the second transistor T2The signal line 17 is conducted in the forward direction, so that the static electricity in the touch connection line 214 can be conducted away, and the voltage in the touch connection line 214 is maintained at a low potential, thereby performing the function of electrostatic protection.
Further, in the present embodiment, the first transistor T is provided1Can be a P-type transistor, a second transistor T2Can be an N-type transistor; wherein the first transistor T1Source electrode S of1A high level signal line VGH, a second transistor T2Source electrode S of2The low-level signal line VGL is connected.
The equivalent circuit of transistor group 2161 shown in fig. 4 and 5 is shown in fig. 6. The conditions for turning on the P-type transistor are as follows: gate voltage VgAnd source voltage Vs(or drain voltage V)d) Is less than a threshold voltage Vth. The conditions for turning on the N-type transistor are as follows: gate voltage VgAnd source voltage Vs(or drain voltage V)d) Is greater than a threshold voltage Vth. Specifically, when the voltage in the touch connection line 214 is greater than VGH, the first transistor T is turned on1Gate G of2A first transistor T connected to the high level signal line VGH1Drain electrode D of2The first transistor T is conducted with the touch connection line 2141Gate voltage V ofg(voltage of high level signal line VGH) is less than drain voltage VdThus making the first transistor T1Source electrode S of1And a drain electrode D1Conducting, the high voltage in the touch connection line 214 is conducted away, the high voltage in the touch connection line 214The voltage is maintained at VGH; when the voltage in the signal line 17 is less than VGL, due to the second transistor T2Gate G of2A second transistor T connected to the low level signal line VGL2Drain electrode D of2A second transistor T connected to the touch connection line 2142Gate voltage V ofg(voltage of low level signal line VGL) is greater than drain voltage VdThus making the second transistor T2Source electrode S of2And a drain electrode D2When the voltage is turned on, the low voltage in the touch connection line 214 is conducted away, and the voltage in the touch connection line 214 is maintained at VGL.
In another practical manner, as shown in fig. 7a and 8a, the electrostatic protection circuit 216 includes: at least one transistor group 2161, each transistor group 2161 including the same type of first transistor T1And a second transistor T2。
Wherein the first transistor T1Gate G of1Connected with the corresponding touch connection line 214, the first transistor T1Source electrode S of1And a first transistor T1Gate G of1Connecting; second transistor T2Drain electrode D of2Connected with the corresponding touch connection line 214, a second transistor T2Source electrode S of2And a second transistor T2Gate G of2And (4) connecting. In practical applications, the first transistor T is provided1And a second transistor T2The source and drain of (a) may be interchanged.
In specific implementation, as shown in fig. 7a and 8a, the first non-display area further includes: a high-level signal line VGH and a low-level signal line VGL provided on the same layer as the touch connection line 214; the orthographic projections of the high-level signal line VGH and the low-level signal line VGL on the substrate base plate are not overlapped with the orthographic projections of the data fan-out wiring 212 and the touch connection line 214 on the substrate base plate. The structure can achieve the same technical effects as the embodiments, and the functions of the structure are referred to the embodiments and are not described herein again.
In practice, the first transistor T1And a second transistor T2May be all N-type transistors, as shown in FIG. 7a, the first transistor T1Drain electrode D of1A second transistor T connected to the high-level signal line VGH2Source electrode S of2Is connected to the low-level signal line VGL.
Alternatively, the first transistor T1And a second transistor T2May be all P-type transistors, as shown in FIG. 8a, the first transistor T1Drain electrode D of1A second transistor T connected to the low-level signal line VGL2Source electrode S of2Is connected to the high-level signal line VGH.
Specifically, the equivalent circuit of the transistor group 2161 shown in fig. 7a is shown in fig. 7b, when the voltage in the touch connection line 214 is greater than VGH, the first transistor T is turned on1Gate G of1The drain D of the first transistor is connected to the touch-control connection line 2141A first transistor T connected to the high level signal line VGH1Gate voltage V ofgGreater than the drain voltage Vd(voltage of the high level signal line VGH), thereby causing the first transistor T to be turned on1Source electrode S of1And a drain electrode D1On, the high voltage in the touch connection line 214 is conducted away, and the voltage is maintained at VGH; when the voltage in the touch connection line 214 is less than VGL, the second transistor T is turned on2Gate G of2A second transistor T connected to the low level signal line VGL2Drain electrode D of2A second transistor T connected to the touch connection line 2142Gate voltage V ofg(voltage of low level signal line VGL) is greater than drain voltage VdThus making the second transistor T2Source electrode S of2And a drain electrode D2On, the low voltage in the touch connection line 214 is conducted away, and the voltage is maintained at VGL; when the voltage in the touch connection line 214 is between VGL and VGH, the first transistor T1And a second transistor T2Gate voltage V ofgAre all less than the drain voltage VdI.e. the first transistor T1And a second transistor T2Cannot be opened.
FIG. 7a shows an equivalent circuit of the transistor group 2161 when the touch-sensing connecting wires are connected as shown in FIG. 7b214 is less than VGL due to the first transistor T1Gate G of1The drain D of the first transistor is connected to the touch-control connection line 2141A first transistor T connected to the low level signal line VGL1Gate voltage V ofgLess than the drain voltage Vd(voltage of the low level signal line VGL), thereby causing the first transistor T to be turned on1Source electrode S of1And a drain electrode D1On, the low voltage in the touch connection line 214 is conducted away, and the voltage is maintained at VGL; when the voltage in the touch connection line 214 is greater than VGH, the second transistor T is turned on2Gate G of2A second transistor T connected to the high level signal line VGH2Drain electrode D of2A second transistor T connected to the touch connection line 2142Gate voltage V ofg(voltage of high level signal line VGH) is less than drain voltage VdThus making the second transistor T2Source electrode S of2And a drain electrode D2On, the high voltage in the touch connection line 214 is conducted away, and the voltage is maintained at VGH; when the voltage in the touch connection line 214 is between VGL and VGH, the first transistor T1And a second transistor T2Gate voltage V ofgAre all greater than the drain voltage VdI.e. the first transistor T1And a second transistor T2Cannot be opened.
In an actual manufacturing process, the gates of the first transistor and the second transistor in the above embodiments may be formed in the same layer, the active layer may be formed in the same layer, the source and the drain may be formed in the same layer, and the source (drain) may be shared when the source (drain) of the first transistor and the source (drain) of the second transistor are both connected to the touch connection line.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including any one of the array substrates described above. The display panel provided by the embodiment of the invention can be a liquid crystal display panel, and further comprises: the liquid crystal display panel comprises a color film substrate positioned on one side of the array substrate and a liquid crystal layer positioned between the array substrate and the color film substrate. The array substrate may adopt any one of the above structures, and is not limited herein. Since the display panel provided in this embodiment includes the array substrate described in the above embodiment, the display panel also has the advantages associated with the array substrate, and the implementation of the display panel may refer to the above embodiment of the array substrate, and repeated details are omitted.
On the other hand, an embodiment of the present invention further provides a display device, including the display panel. The display device can be a liquid crystal display, a liquid crystal television and other display devices, and can also be mobile equipment such as a mobile phone, a tablet personal computer, a notebook computer and the like. As shown in fig. 9, a top view of the display device provided in the embodiment of the present invention is a mobile phone, wherein the display screen may adopt the structure of the display panel, and the display panel may include the structure of any one of the array substrates, which is not limited herein.
According to the array substrate, the display panel and the display device provided by the embodiment of the invention, the array substrate is divided into a display area and a non-display area surrounding the display area, and the non-display area comprises a first non-display area; wherein the first non-display area includes: the touch control device comprises a substrate base plate, a plurality of touch control fan-out wires, first binding pins and a plurality of touch control connecting wires, wherein the touch control fan-out wires, the first binding pins and the touch control connecting wires are arranged on the substrate base plate; the touch fan-out wiring and the touch connecting wire are arranged on different film layers and are connected in a one-to-one correspondence mode through the through holes; overlapping areas exist in orthographic projections of the touch fan-out wirings and the correspondingly connected touch connecting lines on the substrate; the first non-display area further includes: and each touch electrostatic protection circuit is correspondingly connected with each touch connecting line, and the orthographic projection and the overlapping area of the touch electrostatic protection circuits on the substrate are partially overlapped. The touch electrostatic protection circuit is arranged in an overlapping area of the touch fan-out wiring and the touch connecting line, so that the touch electrostatic protection circuit does not additionally occupy other wiring space, the space of a non-display area which is originally occupied by the touch electrostatic protection circuit is saved, the frame where the non-display area is located is reduced, and narrow frame design is realized.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. The array substrate is characterized by being divided into a display area and a non-display area surrounding the display area, wherein the non-display area comprises a first non-display area; wherein,
the first non-display area includes: the touch control device comprises a substrate base plate, a plurality of touch control fan-out wires, first binding pins and a plurality of touch control connecting wires, wherein the touch control fan-out wires, the first binding pins and the plurality of touch control connecting wires are arranged on the substrate base plate; wherein,
the touch fan-out wiring and the touch connecting line are arranged on different film layers and are connected in a one-to-one correspondence mode through via holes; an overlapping area exists between the touch fan-out wiring and the orthographic projection of the correspondingly connected touch connecting line on the substrate;
the first non-display area further includes: the touch control electrostatic protection circuit is correspondingly connected with the touch control connecting lines, and the orthographic projection of the touch control electrostatic protection circuit on the substrate is partially overlapped with the overlapping area.
2. The array substrate of claim 1, wherein the touch electrostatic protection circuits are connected to the touch connection lines in a one-to-one correspondence.
3. The array substrate of claim 1, wherein a length of the touch electrostatic protection circuit parallel to the touch connecting line is smaller than a length of the overlapping area parallel to the touch connecting line.
4. The array substrate of claim 1, wherein the first non-display area further comprises a plurality of data signal lines;
any one data signal line comprises a data fan-out line and a data connecting line connected with the data fan-out line;
the data fan-out routing and the touch control connecting line are arranged on the same layer;
the touch fan-out wiring and the data connecting line are arranged on the same layer.
5. The array substrate of claim 4, wherein at least one data signal line is disposed between two adjacent touch connection lines;
each touch electrostatic protection circuit is located between two adjacent data signal lines on two sides of each touch connecting line.
6. The array substrate of claim 5, wherein the touch electrostatic protection circuit and the data signal line do not overlap with each other in an orthogonal projection of the substrate.
7. The array substrate of claim 5, wherein an overlapping area exists between the touch electrostatic protection circuit and the orthographic projection of the data signal line on the substrate.
8. The array substrate of any one of claims 1-7, wherein the touch electrostatic protection circuit comprises: at least one transistor group, each of the transistor groups including a first transistor and a second transistor of different types, wherein,
the grid electrode of the first transistor is connected with the source electrode, and the drain electrode of the first transistor is connected with the corresponding touch control connecting line;
the grid electrode of the second transistor is connected with the source electrode, and the drain electrode of the second transistor is connected with the corresponding touch control connecting line.
9. The array substrate of claim 8, wherein the first non-display area further comprises: the high-level signal line and the low-level signal line are arranged on the same layer as the touch control connecting line; the orthographic projections of the high-level signal lines and the low-level signal lines on the substrate are not overlapped with the orthographic projections of the data fan-out wires and the touch connecting lines on the substrate;
the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the source electrode of the first transistor is connected with the high-level signal line, and the source electrode of the second transistor is connected with the low-level signal line.
10. The array substrate of any one of claims 1-7, wherein the electrostatic protection circuit comprises: at least one transistor group, each of the transistor groups including a first transistor and a second transistor of the same type; wherein,
the grid electrode of the first transistor is connected with the corresponding touch control connecting line, and the source electrode of the first transistor is connected with the grid electrode of the first transistor;
the drain electrode of the second transistor is connected with the corresponding touch control connecting line, and the source electrode of the second transistor is connected with the grid electrode of the second transistor.
11. The array substrate of claim 10, wherein the first non-display area further comprises: the high-level signal line and the low-level signal line are arranged on the same layer as the touch control connecting line; the orthographic projections of the high-level signal lines and the low-level signal lines on the substrate are not overlapped with the orthographic projections of the data fan-out wires and the touch connecting lines on the substrate;
the first transistor and the second transistor are N-type transistors; the drain of the first transistor is connected with the high-level signal line, and the source of the second transistor is connected with the low-level signal line; or,
the first transistor and the second transistor are P-type transistors; the drain of the first transistor is connected to the low-level signal line, and the source of the second transistor is connected to the high-level signal line.
12. A display panel comprising the array substrate according to any one of claims 1 to 11.
13. A display device characterized by comprising the display panel according to claim 12.
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Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182010A (en) * | 2018-01-22 | 2018-06-19 | 京东方科技集团股份有限公司 | Touch base plate and preparation method thereof, touch control display apparatus |
| CN108628020A (en) * | 2018-05-23 | 2018-10-09 | 上海中航光电子有限公司 | A kind of array substrate and display device |
| CN108649038A (en) * | 2018-05-28 | 2018-10-12 | 武汉华星光电技术有限公司 | A kind of array substrate, display panel and display equipment |
| CN108763662A (en) * | 2018-05-10 | 2018-11-06 | 北京华大九天软件有限公司 | It is a kind of abnormity domain in the multiple-layer overlapped wiring method based on track |
| CN108877523A (en) * | 2018-06-29 | 2018-11-23 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN109377874A (en) * | 2018-12-21 | 2019-02-22 | 上海中航光电子有限公司 | Display panel and display device |
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| WO2021196010A1 (en) * | 2020-03-31 | 2021-10-07 | 京东方科技集团股份有限公司 | Touch circuit, touch panel, and display device |
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| WO2023040596A1 (en) * | 2021-09-14 | 2023-03-23 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2024197772A1 (en) * | 2023-03-31 | 2024-10-03 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| US20080218652A1 (en) * | 2006-12-29 | 2008-09-11 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device |
| CN101441372A (en) * | 2007-11-23 | 2009-05-27 | 上海广电Nec液晶显示器有限公司 | Electrostatic discharge protection device of LCD device and manufacturing method thereof |
| CN103293795A (en) * | 2012-03-05 | 2013-09-11 | 上海中航光电子有限公司 | Electrostatic protection circuit of liquid crystal display |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
| CN105607360A (en) * | 2015-12-25 | 2016-05-25 | 上海中航光电子有限公司 | Display panel and display device |
| CN106775124A (en) * | 2017-01-20 | 2017-05-31 | 上海天马微电子有限公司 | Touch display panel and display device |
| CN106842660A (en) * | 2017-04-19 | 2017-06-13 | 厦门天马微电子有限公司 | display panel, driving method and display device |
| CN106959783A (en) * | 2017-04-05 | 2017-07-18 | 上海中航光电子有限公司 | Array base palte, contact panel and contactor control device |
| CN107037646A (en) * | 2017-04-21 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of display base plate and display device |
| CN107065336A (en) * | 2017-06-13 | 2017-08-18 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
-
2017
- 2017-08-30 CN CN201710764644.1A patent/CN107479283B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| US20080218652A1 (en) * | 2006-12-29 | 2008-09-11 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device |
| CN101441372A (en) * | 2007-11-23 | 2009-05-27 | 上海广电Nec液晶显示器有限公司 | Electrostatic discharge protection device of LCD device and manufacturing method thereof |
| CN103293795A (en) * | 2012-03-05 | 2013-09-11 | 上海中航光电子有限公司 | Electrostatic protection circuit of liquid crystal display |
| CN105607360A (en) * | 2015-12-25 | 2016-05-25 | 上海中航光电子有限公司 | Display panel and display device |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
| CN106775124A (en) * | 2017-01-20 | 2017-05-31 | 上海天马微电子有限公司 | Touch display panel and display device |
| CN106959783A (en) * | 2017-04-05 | 2017-07-18 | 上海中航光电子有限公司 | Array base palte, contact panel and contactor control device |
| CN106842660A (en) * | 2017-04-19 | 2017-06-13 | 厦门天马微电子有限公司 | display panel, driving method and display device |
| CN107037646A (en) * | 2017-04-21 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of display base plate and display device |
| CN107065336A (en) * | 2017-06-13 | 2017-08-18 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
Cited By (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182010B (en) * | 2018-01-22 | 2021-11-05 | 京东方科技集团股份有限公司 | Touch substrate, preparation method thereof and touch display device |
| CN108182010A (en) * | 2018-01-22 | 2018-06-19 | 京东方科技集团股份有限公司 | Touch base plate and preparation method thereof, touch control display apparatus |
| US11276645B2 (en) | 2018-02-24 | 2022-03-15 | Huawei Technologies Co., Ltd. | Encapsulation of a substrate electrically connected to a plurality of pin arrays |
| WO2019161641A1 (en) * | 2018-02-24 | 2019-08-29 | 华为技术有限公司 | Chip and packaging method |
| US11630534B2 (en) | 2018-03-12 | 2023-04-18 | Ordos Yuansheng Optoelectronics Co., Ltd. | Wiring structure, manufacturing method thereof, and display device |
| JP2021515920A (en) * | 2018-03-12 | 2021-06-24 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Wiring structure and its manufacturing method, display device |
| EP3767440A4 (en) * | 2018-03-12 | 2021-12-22 | Boe Technology Group Co., Ltd. | Wiring structure, fabrication method therefor, and display device |
| CN108763662A (en) * | 2018-05-10 | 2018-11-06 | 北京华大九天软件有限公司 | It is a kind of abnormity domain in the multiple-layer overlapped wiring method based on track |
| WO2019218799A1 (en) * | 2018-05-14 | 2019-11-21 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| US11276713B2 (en) | 2018-05-14 | 2022-03-15 | Beijing Boe Technology Development Co., Ltd. | Array substrate, manufacturing method, display panel and display device thereof |
| CN108628020A (en) * | 2018-05-23 | 2018-10-09 | 上海中航光电子有限公司 | A kind of array substrate and display device |
| CN108628020B (en) * | 2018-05-23 | 2021-08-31 | 上海中航光电子有限公司 | Array substrate and display device |
| US10996779B2 (en) | 2018-05-25 | 2021-05-04 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, display panel, touch display device and method for fabricating the same |
| WO2019223386A1 (en) * | 2018-05-25 | 2019-11-28 | 京东方科技集团股份有限公司 | Display substrate, display panel, touch-control display device and manufacturing method therefor |
| WO2019227695A1 (en) * | 2018-05-28 | 2019-12-05 | 武汉华星光电技术有限公司 | Array substrate, display panel, and display device |
| CN108649038A (en) * | 2018-05-28 | 2018-10-12 | 武汉华星光电技术有限公司 | A kind of array substrate, display panel and display equipment |
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| JP2021526657A (en) * | 2018-06-04 | 2021-10-07 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Static electricity protection circuit, array board and display device |
| EP3806150A4 (en) * | 2018-06-04 | 2022-02-23 | Boe Technology Group Co., Ltd. | Electrostatic protection circuit, array substrate and display device |
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| US11195888B2 (en) | 2019-06-28 | 2021-12-07 | Lg Display Co., Ltd. | Display device |
| EP3757734A1 (en) * | 2019-06-28 | 2020-12-30 | LG Display Co., Ltd. | Touch sensitive display device with reduced bezel area |
| CN111025793A (en) * | 2019-12-27 | 2020-04-17 | 厦门天马微电子有限公司 | Display panel and display device |
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| US11784642B2 (en) | 2020-03-31 | 2023-10-10 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Touch circuit, touch panel and display device |
| CN112436047A (en) * | 2020-11-30 | 2021-03-02 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| CN112436047B (en) * | 2020-11-30 | 2022-08-23 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| WO2022170458A1 (en) * | 2021-02-09 | 2022-08-18 | 京东方科技集团股份有限公司 | Display panel and display device |
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