CN108877544A - A kind of display panel and electronic equipment - Google Patents
A kind of display panel and electronic equipment Download PDFInfo
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- CN108877544A CN108877544A CN201810695746.7A CN201810695746A CN108877544A CN 108877544 A CN108877544 A CN 108877544A CN 201810695746 A CN201810695746 A CN 201810695746A CN 108877544 A CN108877544 A CN 108877544A
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- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 39
- 239000002184 metal Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the present invention provides a kind of display panel and the electronic equipment comprising the display panel, including：Multi-strip scanning line, multiple data lines, multiple pixel-driving circuits, the first scanning circuit, the second scanning circuit and driving circuit.The output end of one the first output transistor of the first scanning circuit is electrically connected with first scan line, and the output end of second output transistor of the second scanning circuit is electrically connected with second scan line.First scanning circuit is greater than the second scanning circuit at a distance from driving circuit at a distance from driving circuit, and the delay time of the first scanning signal of the first scan line offer is greater than the delay time for the second scanning signal that the second scan line provides.Provided in an embodiment of the present invention kind of display panel and the electronic equipment comprising the display panel, it is far and near according to scanning circuit and driving circuit position, it is adjusted to scanning circuit and with the delay time of the scanning signal of corresponding scan line, solves the problems, such as to show unevenness in the prior art.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a display panel and an electronic device.
Background
As the application of the panel display screen becomes more and more extensive, the wide screen technology becomes an important technical item, and meanwhile, the technology of the narrow lower frame of the display panel becomes more and more important. Consumer demands for resolution and screen occupation ratio of display screens are gradually increasing, and therefore, there is a demand for further reduction in the area of non-light-transmitting regions such as wiring, pixel pitch, and the like in display devices.
In the prior art, reducing the area of non-light-transmitting areas such as leads, pixel pitches, etc. in a display device requires reducing the width of the leads and other conductive devices, resulting in increased resistance values of the leads and conductive devices and more loss of signals during transmission. The problem of uneven display of the display panel is more serious, and user experience is influenced.
Disclosure of Invention
The embodiment of the invention provides a display panel and an electronic device, which can avoid uneven display caused by loss in signal transmission and improve user experience.
An embodiment of the present invention provides a display panel, including:
the pixel driving circuit comprises a plurality of scanning lines, a plurality of data lines, a plurality of pixel driving circuits, a first scanning circuit, a second scanning circuit and a driving circuit;
the scan lines further include a first scan line and a second scan line;
the first scanning circuit further comprises first output transistors, and the output end of one first output transistor is electrically connected with one first scanning line; the second scanning circuit comprises second output transistors, and the output end of one second output transistor is electrically connected with one second scanning line;
the driving circuit provides a first voltage signal for the first scanning circuit and the second scanning circuit through a first power line;
the distance between the first scanning circuit and the driving circuit is larger than the distance between the second scanning circuit and the driving circuit, and the delay time of the first scanning signal provided by the first scanning line is larger than the delay time of the second scanning signal provided by the second scanning line.
According to the display panel provided by the embodiment of the invention, the delay time of the scanning signals of the scanning circuit and the corresponding scanning lines is adjusted according to the positions of the scanning circuit, the corresponding scanning lines and the driving circuit, so that the charging time of the pixel driving circuit can be adjusted, the uniform display of pixels in different rows is realized, and the problem of non-uniform display in the prior art is solved.
Further, the pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit, and the distance between the first pixel driving circuit and the driving circuit is greater than the distance between the second pixel driving circuit and the driving circuit; the first pixel driving circuit comprises a first switch transistor, a first driving transistor, a first light emitting transistor and a first organic light emitting diode, wherein the grid electrode of the first switch transistor is electrically connected with a first output transistor of the first scanning circuit through a first scanning line; the second pixel driving circuit includes a second switching transistor, a second driving transistor, a second light emitting transistor and a second organic light emitting diode, and a gate of the second switching transistor is electrically connected to a second output transistor of the second scanning circuit through a second scanning line.
Further, the display panel further comprises an initialization signal line, a first pole of the first switching transistor is electrically connected with the initialization signal line, and a second pole of the first switching transistor is electrically connected with the grid electrode of the first driving transistor; the second pole of the first driving transistor is electrically connected to the first pole of the first light emitting transistor, and the second pole of the first light emitting transistor is electrically connected to the first organic light emitting diode.
Further, the display panel further comprises an initialization signal line, a first pole of the second switching transistor is electrically connected with the initialization signal line, and a second pole of the second switching transistor is electrically connected with the grid electrode of the second driving transistor; the second pole of the second driving transistor is electrically connected to the first pole of the second light emitting transistor, and the second pole of the second light emitting transistor is electrically connected to the second organic light emitting diode.
In the display panel provided by the embodiment of the invention, since the delay time of the first scanning signal provided by the first scanning line is set to be longer than the delay time of the second scanning signal provided by the second scanning line, the turn-on time of the first switching transistor is longer than the turn-on time of the second switching transistor. And then the charging time of the second stage of the first switching transistor is controlled to be longer than that of the second stage of the second switching transistor, so that the potential of the second pole of the first driving transistor and the potential of the second pole of the second driving transistor are adjusted, the display chromaticity of the first organic light emitting diode and the display chromaticity of the second organic light emitting diode are adjusted, and the chromaticity uniformity of the display panel is improved.
Alternatively, the width-to-length ratio of the first output transistor may be set larger than that of the second output transistor to adjust the delay time of the scanning circuit and the scanning signal corresponding to the scanning line.
Further, the display panel includes a first region and a second region, a minimum distance between a boundary of the first region and the driving circuit is greater than a minimum distance between a boundary of the second region and the driving circuit; the first region includes a plurality of first scan circuits, each of which has an equal width-to-length ratio of the first output transistors located in the first region; the second region includes a plurality of second scan circuits, and the width-to-length ratios of the second output transistors each located in the second region are equal.
According to the display panel provided by the embodiment of the invention, the delay time of the scanning circuits of the first area and the second area and the delay time of the scanning signals of the corresponding scanning lines can be respectively adjusted through the width-length ratio of the output transistor according to the positions of the scanning circuits, the corresponding scanning lines and the driving circuits in a regionalized manner, so that the charging time of the pixel driving circuit can be adjusted, the uniform display of regionalized multi-line pixels is realized, and the process difficulty is reduced while the problem of nonuniform display in the prior art is solved.
Optionally, the display panel includes a first transfer line, an output end of the first output transistor is electrically connected to the scan line through the first transfer line, and an output end of the second output transistor is directly connected to the scan line.
In the display panel provided by the embodiment of the invention, the first transfer line is arranged between the first output transistor and the scanning line, and the transfer line is not arranged between the second output transistor and the scanning line. So as to adjust the delay time of the scanning circuit and the scanning signal of the corresponding scanning line.
Optionally, the display panel includes: the first output transistor is electrically connected with the scanning line through a first transfer line; and the second output transistor is electrically connected with the scanning line through a second patch cord, and the length of the second patch cord is smaller than that of the first patch cord.
In the display panel provided by the embodiment of the invention, the first transfer line and the second transfer line which are different in length are respectively arranged between the first output transistor and the scanning line, so that the scanning circuit and the delay time of the scanning signal corresponding to the scanning line are adjusted.
Further, the display panel includes a first region and a second region, a minimum distance between a boundary of the first region and the driving circuit is greater than a minimum distance between a boundary of the second region and the driving circuit; the first region includes a plurality of first scan circuits, and first transfer lines electrically connected to the first output transistors in each of the first regions have the same length; the second region includes a plurality of second scan circuits, and second transfer lines electrically connected to the second output transistors each located in the second region have the same length.
Further, the first output transistor includes a gate, a semiconductor structure, a first pole and a second pole; the second output transistor comprises a grid electrode, a semiconductor structure, a first pole and a second pole; the first transfer line, the second transfer line, the semiconductor structure of the first driving transistor and the semiconductor structure of the second diode transistor are positioned on the same layer and made of the same material.
According to the display panel provided by the embodiment of the invention, the delay time of the scanning circuits of the first area and the second area and the delay time of the scanning signals of the corresponding scanning lines can be respectively adjusted through the length of the short connecting line according to the positions of the scanning circuits and the corresponding scanning lines and the driving circuits in a regionalized manner, so that the charging time of the pixel driving circuits can be adjusted, the uniform display of regionalized rows of pixels is realized, and the process difficulty is reduced while the problem of nonuniform display in the prior art is solved.
The embodiment of the invention also provides electronic equipment comprising any one of the display panels provided by the embodiment of the invention. According to the electronic equipment provided by the invention, the delay time of the scanning signals of the scanning circuit and the corresponding scanning lines can be adjusted according to the positions of the scanning circuit, the corresponding scanning lines and the driving circuit, so that the charging time of the pixel driving circuit can be adjusted, the uniform display of pixels in different rows is realized, and the problem of nonuniform display in the prior art is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a top view of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing a connection relationship between the first scan circuit and the second scan circuit in FIG. 1;
FIG. 3 is a schematic waveform diagram of a first scanning signal and a second scanning signal;
fig. 4 is a schematic connection diagram of a pixel driving circuit of a display panel according to an embodiment of the invention;
fig. 5 is a schematic diagram of a level of a first driving transistor and a second driving transistor of another display panel according to an embodiment of the invention;
fig. 6 is a wiring diagram of a first driving transistor and a second driving transistor of a display panel according to an embodiment of the present invention;
FIG. 7 is a top view of another display panel according to an embodiment of the present invention;
fig. 8 is a wiring diagram of a first driving transistor and a second driving transistor of a further display panel according to an embodiment of the present invention;
fig. 9 is a wiring diagram of a first driving transistor and a second driving transistor of a further display panel according to an embodiment of the present invention;
fig. 10 is a wiring diagram of a first driving transistor and a second driving transistor of a further display panel according to an embodiment of the present invention;
fig. 11 is a wiring diagram of a first driving transistor and a second driving transistor of a further display panel according to an embodiment of the present invention;
fig. 12 is a top view of an electronic device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe the scan circuits in the embodiments of the present invention, the scan circuits should not be limited to these terms. These terms are only used to distinguish the scanning circuits from each other. For example, the first scan circuit may also be referred to as a second scan circuit, and similarly, the second scan circuit may also be referred to as a first scan circuit, without departing from the scope of embodiments of the present invention.
An embodiment of the present invention provides a display panel 100, as shown in fig. 1, the display panel 100 includes: a plurality of scanning lines G, a plurality of data lines D, a plurality of pixel units formed by insulating and crossing the scanning lines G, a plurality of pixel driving circuits P, a first scanning circuit S1, a second scanning circuit S2 and a driving circuit DC.
As shown in fig. 1 and 2, the scan lines G include a plurality of first scan lines G1 and a plurality of second scan lines G2. The first scan line G1 is spaced apart from the driving circuit DC by a distance greater than that of the second scan line G2. The first scan circuit S1 includes first output transistors T1 and a first shift unit a1, and an output terminal of one first output transistor T1 is electrically connected to one first scan line G1. The second scan circuit S2 includes second output transistors T2 and a second shift unit a2, and an output terminal of one second output transistor T2 is electrically connected to one second scan line G2.
The driving circuit DC supplies the first scan circuit S1 and the second scan circuit S2 with a first voltage signal through a first power line V1. The distance from the driving circuit DC to the first scanning circuit S1 is greater than the distance from the driving circuit DC to the second scanning circuit S1.
As shown in fig. 3, the delay time T1 of the first scan signal GOUT1 provided by the first scan line G1 is a transition time of the first scan signal GOUT2 transitioning from a steady high level to a steady low level, and the delay time T2 of the second scan signal GOUT2 provided by the second scan line G2 is a transition time of the second scan signal GOUT2 transitioning from a steady high level to a steady low level. The delay time T1 of the first scan signal GOUT1 provided by the first scan line G1 is greater than the delay time T2 of the second scan signal GOUT2 provided by the second scan line.
It should be noted that fig. 3 only illustrates an embodiment in which the signals of the first scan line G1 and the second scan line G2 are active at a low level, and in another embodiment of the present invention, the signals of the first scan line G1 and the second scan line G2 may also be active at a high level. In an active high embodiment, the transition time from a steady low level to a steady high level is the delay time.
The term "active low" means that the control circuit responds when the signal is low, for example, the gate control signal of the P-type thin film transistor is active low, and the P-type thin film transistor is turned on when the gate control signal of the P-type thin film transistor is low. Active high means that the control circuit responds when the signal is high, for example, the gate control signal of the N-type thin film transistor is active high, and the N-type thin film transistor is turned on when the gate control signal of the N-type thin film transistor is high.
According to the distance between the first scanning circuit S1 and the second scanning circuit S2 and the driving circuit DC, the delay time T1 of the first scanning signal provided by the first scanning line G1 corresponding to the first scanning circuit S1 is set to be longer than the delay time T2 of the second scanning signal provided by the second scanning line G2 corresponding to the second scanning circuit S2. And then adjust the charge time of pixel drive circuit P, realize the display homogenization of two rows of pixels with different distances from drive circuit DC, solve the problem of uneven display in the prior art.
As shown in fig. 4, the pixel driving circuit P of the display panel 100 of the embodiment of the invention includes a first pixel driving circuit P1 and a second pixel driving circuit P2, wherein a distance between the first pixel driving circuit P1 and the driving circuit DC is greater than a distance between the second pixel driving circuit P1 and the driving circuit DC;
the first pixel driving circuit P1 includes a first switching transistor T3, a first driving transistor T4, a first light emitting transistor T5 and a first organic light emitting diode, and a gate of the first switching transistor T3 is electrically connected to a first output transistor T1 of the first scan circuit S1 through a first scan line G1. The second pixel driving circuit P2 includes a second switching transistor T6, a second driving transistor T7, a second light emitting transistor T8 and a second organic light emitting diode, and a gate of the second switching transistor T6 is electrically connected to the second output transistor T2 of the second scanning circuit S2 through a second scanning line G2.
With continued reference to fig. 4, the display panel 100 further includes an initialization signal line STV, a first pole of the first switch transistor T3 is electrically connected to the initialization signal line STV, and a second pole of the first switch transistor T3 is electrically connected to the gate of the first driving transistor T1. The second pole of the first driving transistor T1 is electrically connected to the first pole of the first light emitting transistor T5, and the second pole of the first light emitting transistor T5 is electrically connected to the first organic light emitting diode. The first organic light emitting diode includes an anode, a light emitting functional layer, and a cathode, which are stacked. The light emitting function layer may further include an auxiliary light emitting layer and a light emitting material layer. The second electrode of the first light emitting transistor T5 is electrically connected to the first organic light emitting diode including the stacked anode.
With continued reference to fig. 4, the first pixel driving circuit P1 further includes a first initialization unit B1, a first signal writing unit C1, and a first threshold obtaining unit M1. The first initializing unit B1 may initialize the potential of the second pole of the first light emitting transistor T5. The first signal writing unit C1 may write a data signal to the first driving transistor T4. The first threshold obtaining unit M1 is used to control the turn-on of the gate of the first driving transistor T4 and the second pole of the first driving transistor T4.
A first pole of the second switching transistor T6 is electrically connected to the initialization signal line STV, and a second pole of the second switching transistor T6 is electrically connected to the gate of the second driving transistor T7. The second pole of the second driving transistor T7 is electrically connected to the first pole of the second light emitting transistor T8, and the second pole of the second light emitting transistor T8 is electrically connected to the second organic light emitting diode. The second organic light emitting diode includes an anode, a light emitting functional layer, and a cathode, which are stacked. The light emitting function layer may further include an auxiliary light emitting layer and a light emitting material layer. The second electrode of the second light emitting transistor T5 is electrically connected to the second organic light emitting diode including the stacked anode.
With continued reference to fig. 4, the second pixel driving circuit P2 further includes a second initialization unit B2, a second signal writing unit C2, and a second threshold obtaining unit M2. The second initializing unit B2 may initialize the potential of the second pole of the second light emitting transistor T8. The second signal writing unit C2 may write a data signal to the second driving transistor T7. The second threshold value obtaining unit M2 is used to control the turn-on of the gate of the second driving transistor T7 and the second pole of the second driving transistor T7.
In the display panel according to the embodiment of the invention, the delay time of the first scan signal provided by the first scan line G1 is set to be longer than the delay time of the second scan signal provided by the second scan line G2, so that the turn-on time of the first switch transistor T3 is longer than the turn-on time of the second switch transistor T6. Further, by controlling the charging time of the second stage of the first switching transistor T3 to be longer than the charging time of the second stage of the second switching transistor T6, the potential of the second pole of the first driving transistor T4 and the potential of the second pole of the second driving transistor T7 are adjusted, so that the display chromaticity of the first organic light emitting diode and the second organic light emitting diode is adjusted, and the chromaticity uniformity of the display panel is improved.
Embodiments of the present invention also provide a display panel that can adjust a delay time T1 of a first scan signal supplied from a first scan line G1 corresponding to a first scan circuit S1 to be longer than a delay time T2 of a second scan signal supplied from a second scan line G2 corresponding to a second scan circuit S2 by a width-to-length ratio of a first output transistor T1 and a second output transistor T2.
Fig. 5 shows a hierarchical structure diagram of the first driving transistor T1, the first capacitor C1, the second driving transistor T2, and the second capacitor C2 in the width direction. The width direction is the extending direction of the first scanning line G1 and the second scanning line G2. Fig. 6 illustrates a top view of the first and second driving transistors T1 and T2 on the display panel 100.
Referring to fig. 5 and 6, the display panel includes a substrate 200, a buffer layer 210, a semiconductor structure 220, a first insulating layer 230, a first metal layer 240, a second insulating layer 250, a second metal layer 260, a third insulating layer 270, and a third metal layer 280.
With continued reference to fig. 5 and 6, the first output transistor T1 includes a gate 301, a source drain 302, and a semiconductor structure 303. The semiconductor structure 303 further includes a channel region 3031 that overlaps the gate 301 and a region 3032 that does not overlap the gate 301. The width-to-length ratio of the first output transistor T1 is a ratio of a width W1 to a length L1 of the channel region 3031 of the first output transistor T1, the width W1 is a width of the channel region 3031 of the first output transistor T1 in the extending direction of the first scan line G1, and the length L1 is a length of the channel region 3031 of the first output transistor T1 in the extending direction of the data line D. The first capacitor C1 includes a first plate on the first metal layer 240 and a second plate on the second metal layer 260. The source and drain electrodes 302 of the first driving transistor T1 are electrically connected to the region 3032 of the semiconductor structure 220, which does not overlap with the first metal layer 240, through the via h 1. The channel region 3031 of the first output transistor T1 is shielded by the first metal layer 240 in fig. 5 because it is located on the side of the first metal layer 240 close to the substrate 200. Fig. 5 shows the width W1 and the length L1 of the overlapping region of the channel region 3031 of the first output transistor T1 and the first metal layer 240 (i.e., the gate 301 of the first drive transistor).
With continued reference to fig. 5 and 6, the second output transistor T2 includes a gate 401, a source drain 402, and a semiconductor structure 403. Semiconductor structure 403 further includes a channel region 4031 that overlaps gate 401 and a region 4032 that does not overlap gate 401. The width-to-length ratio of the second output transistor T2 is a ratio of the width W2 to the length L2 of the channel region 4031 of the second output transistor T2, the width W2 is a width of the channel region 4031 of the second output transistor T1 in the extending direction of the second scan line G2, and the length L2 is a length of the channel region 4031 of the second output transistor T2 in the extending direction of the data line D. The second capacitor C2 includes a first plate on the first metal layer 240 and a second plate on the second metal layer 260. The source drain 402 of the second driving transistor T2 is electrically connected to the region 4032 of the semiconductor structure 220 that does not overlap the first metal layer 240 through the via h 2. The channel region 4031 of the second output transistor T2 is shielded by the first metal layer 240 in fig. 5 because it is located on the side of the first metal layer 240 close to the substrate 200. Fig. 5 shows the width W2 and the length L2 of the overlapping region of the channel region 4031 of the second output transistor T2 and the first metal layer 240 (i.e., the gate 401 of the second drive transistor).
The width-to-length ratio W1/L1 of the first output transistor T1 is greater than the width-to-length ratio W2/L2 of the second output transistor T2.
In the display panel 100 according to the embodiment of the invention, by adjusting the ratio of the width W1 to the length L1 of the overlapping region of the semiconductor structure 220 in the first driving transistor T1 and the gate 301 of the first driving transistor T1 to be greater than the ratio of the width W2 to the length L2 of the overlapping region of the semiconductor structure 220 in the second driving transistor T2 and the gate 401 of the second driving transistor T2, that is, by adjusting the width-to-length ratio of the first driving transistor T1 to be greater than the width-to-length ratio of the second driving transistor T2, the delay time of the first scan signal GOUT1 of the first scan line G1 is greater than the delay time of the second scan signal GOUT2 of the second scan line G2. Therefore, the adjustment of the chromaticity of the pixel corresponding to the first scanning line G1 and the chromaticity of the pixel corresponding to the second scanning line G2 is realized, the uniformity of the display chromaticity of the display panel 100 is realized, and the problem of display unevenness caused by signal loss due to resistance in the prior art is solved.
The embodiment of the present invention further provides a display panel 100, as shown in fig. 7 and 8, the display panel includes a first region 101 and a second region 102, and a minimum distance Y1 between a boundary of the first region 101 and the driving circuit DC is greater than a minimum distance Y2 between a boundary of the second region 102 and the driving circuit DC. The minimum distance Y1 between the boundary of the first region 101 and the drive circuit DC is the vertical distance from the side of the first region 101 closest to the drive circuit DC. The minimum distance Y2 between the boundary of the second region 102 and the driving circuit DC is the vertical distance from the side of the second region 102 closest to the driving circuit DC.
As shown in fig. 7 and 8, the first region 101 includes a plurality of first scan circuits S11, S12, and the width-to-length ratios of the channel regions of the first drive transistors in the first scan circuit S11 and the second scan circuit S12 are equal, that is, the width of the semiconductor structure overlapping the first metal layer in the extending direction of the first scan line G1 and the length of the semiconductor structure overlapping the first metal layer in the extending direction of the data line. The second region 102 includes a plurality of second scan circuits S21, S22, and the width-to-length ratios of the channel regions of the second drive transistor T2 in the second scan circuit S21 and the second scan circuit S22 are equal, that is, the width of the semiconductor structure overlapping the first metal layer in the extending direction of the second scan line G2 and the length of the semiconductor structure overlapping the first metal layer in the extending direction of the data line. Further, the width-to-length ratios of the first output transistors T1 each located in the first region 101 are equal, and the width-to-length ratios of the second output transistors T2 each located in the second region 102 are equal.
It should be noted that the display panel 100 provided in the embodiment of the present invention may further include a third region 103 … … nth region. The number of the scan circuits included in each region may be the same or different, for example, the first region 101 may include 2 scan circuits, the second region 102 may include 2 scan circuits, and the third region 103 may include 3 scan circuits. The adjacent regions may be spaced by 1 or more scan circuits, or may not be provided with scan circuits.
The display panel provided by the embodiment of the invention can adjust the delay time of the scanning circuits of the first area and the second area and the delay time of the scanning signals of the corresponding scanning lines respectively through the width-length ratio of the output transistors T1 and T2 according to the DC positions of the scanning circuits and the corresponding scanning lines G1 and G2 and the driving circuits respectively in an area (for example, dividing the first area 101 and the second area 102), further can adjust the charging time of the pixel driving circuits, realizes the uniform display of multiple rows of pixels in an area, and reduces the process difficulty while solving the problem of non-uniform display in the prior art.
An embodiment of the present invention further provides a display panel 100, as shown in fig. 9, the display panel 100 includes a first transfer line X1, an output terminal of a first output transistor T1 of a first scan circuit S1 is electrically connected to the first scan line G1 through the first transfer line X1, and an output terminal of a second output transistor T2 of the first scan circuit S1 is electrically connected to the second scan line G2 directly through a via. Since the first transfer line X1 is disposed between the first output transistor T1 and the first scan line G1, no transfer line is disposed between the second output transistor T2 and the second scan line G2. Therefore, the signal output from the first output transistor T1 can be transmitted to the first scan line G1 with a delay time that is longer than the signal output from the second output transistor T1 and transmitted to the second scan line G2, i.e., the delay time of the first scan signal of the first scan line G1 is longer than the delay time of the second scan signal of the second scan line G2.
The embodiment of the present invention further provides a display panel 100, as shown in fig. 10, the display panel includes a first patch cord X1 and a second patch cord X2. An output terminal of the first output transistor T1 of the first scan circuit S1 is electrically connected to the first scan line G1 through a first transfer line X1, and an output terminal of the second output transistor T2 of the second scan circuit S2 is electrically connected to the second scan line G2 through a second transfer line X2, wherein a length of the second transfer line X2 is smaller than a length of the first transfer line X1. Since the length of the second transfer line X2 is less than the length of the first transfer line X1, the time for the signal output by the first output transistor T1 to transmit to the first scan line G1 can be delayed from the time for the signal output by the second output transistor T1 to transmit to the second scan line G2, i.e., the delay time of the first scan signal of the first scan line G1 is longer than the delay time of the second scan signal of the second scan line G2.
Further, referring to fig. 7 and 11, the display panel includes a first region 101 and a second region 102, and the minimum distance Y1 between the boundary of the first region 101 and the driving circuit DC is greater than the minimum distance Y2 between the boundary of the second region 102 and the driving circuit DC. The minimum distance Y1 between the boundary of the first region 101 and the drive circuit DC is the vertical distance from the side of the first region 101 closest to the drive circuit DC. The minimum distance Y2 between the boundary of the second region 102 and the driving circuit DC is the vertical distance from the side of the second region 102 closest to the driving circuit DC.
With continued reference to fig. 7 and 11, the first region 101 includes a plurality of first scan circuits S11, S12, and the length of the first transfer line X11 electrically connected to the first output transistor T1 of the first scan circuit S11 is equal to the length of the first transfer line X12 electrically connected to the first output transistor T1 of the first scan circuit S12. Further, the first transfer line length to which the first output transistor of each of the first scan circuits located in the first region is electrically connected may be set to be the same.
With continued reference to fig. 7 and 11, the second region 102 includes a plurality of second scan circuits S21, S22, and the length of the first transfer line X21 electrically connected to the second output transistor T2 of the second scan circuit S21 is equal to the length of the first transfer line X22 electrically connected to the second output transistor T2 of the second scan circuit S22. Further, the length of the second transfer line electrically connected to the second output transistor of each of the second scan circuits located in the second area may be set to be the same.
Referring to fig. 5 and 10, the first output transistor T1 includes a gate 301, source and drain electrodes 302 (i.e., a first electrode and a second electrode), and a semiconductor structure 303. The semiconductor structure 303 further includes a channel region 3031 that overlaps the gate 301 and a region 3032 that does not overlap the gate 301.
With continued reference to fig. 5 and 10, the second output transistor T2 includes a gate 401, source and drain electrodes 402 (i.e., a first electrode and a second electrode), and a semiconductor structure 403. Semiconductor structure 403 further includes a channel region 4031 that overlaps gate 401 and a region 4032 that does not overlap gate 401.
The first transfer line X1, the second transfer line X2, the semiconductor structure 303 of the first output transistor T1, and the semiconductor structure 404 of the second output transistor T2 are located at the same layer and made of the same material. That is, the first and second patch lines X1 and X2 are made of the material of the semiconductor structures 303 and 304 in the same process as the semiconductor structures 303 and 304. Because the resistivity of the semiconductor material is larger than that of the first metal layer, the second metal layer and the third metal layer, the delay time can be adjusted by only adjusting a smaller length of the semiconductor material, and additional space does not need to be added. Compared with the first transfer line X1 and the second transfer line X2, the process is simpler and more convenient when the metal materials of the second metal layer and the third metal layer are used for manufacturing.
In other embodiments provided by the present invention, the first transfer line X1 and the second transfer line X2 may also be made of one or more metal layers of the second metal layer and the third metal layer. The technical effects of the invention can also be realized by adjusting the lengths of the first patch cord X1 and the second patch cord X2.
The display panel 100 according to the embodiment of the invention can adjust the delay time of the scanning circuits of the first area 101 and the second area 102 and the delay time of the scanning signals of the corresponding scanning lines respectively according to the positions of the scanning circuits S1 and S1 and the DC position of the driving circuit regionally through the lengths of the transfer lines X1 and X2, so as to adjust the charging time of the pixel driving circuit, achieve uniform display of regionally multi-line pixels, and reduce the process difficulty while solving the problem of non-uniform display in the prior art.
An electronic device 500 is further provided in an embodiment of the present invention, as shown in fig. 12, the electronic device 500 includes any one of the display panels 100 provided in the embodiment of the present invention. The electronic device 500 may be an electronic device with a display function, such as a smart phone, a tablet display computer, a notebook, a display, a television, and a showcase.
It should be noted that fig. 12 is only an example of the electronic device 200, the shape of the electronic device 500 is not limited to the shape or the use state shown in fig. 12, and the electronic device 500 may be rectangular or non-rectangular. The electronic device 500 may be a foldable display device, a flexible display device, or a rigid display device. The electronic device 500 may also have at least one bezel, i.e., not a full screen display; and devices such as a camera or a receiver and the like are not arranged on the side of the display panel, so that complete full-screen display is realized.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (11)
1. A display panel, comprising:
a plurality of scan lines including a first scan line and a second scan line;
the data lines and the scanning lines are insulated and crossed to form a plurality of pixel units;
a plurality of pixel driving circuits;
a first scan circuit including first output transistors, an output terminal of one of the first output transistors being electrically connected to one of the first scan lines;
a second scanning circuit including second output transistors, an output terminal of one of the second output transistors being electrically connected to one of the second scanning lines;
a driving circuit that supplies a first voltage signal to the first scanning circuit and the second scanning circuit through a first power line; wherein,
the distance between the first scanning circuit and the driving circuit is larger than the distance between the second scanning circuit and the driving circuit, and the delay time of a first scanning signal provided by the first scanning line is larger than the delay time of a second scanning signal provided by the second scanning line.
2. The display panel of claim 1, wherein: the pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit, and the distance between the first pixel driving circuit and the driving circuit is greater than the distance between the second pixel driving circuit and the driving circuit;
the first pixel driving circuit comprises a first switch transistor, a first driving transistor, a first light emitting transistor and a first organic light emitting diode, and the grid electrode of the first switch transistor is electrically connected with the first output transistor of the first scanning circuit through the first scanning line;
the second pixel driving circuit includes a second switching transistor, a second driving transistor, a second light emitting transistor, and a second organic light emitting diode, and a gate of the second switching transistor is electrically connected to the second output transistor of the second scanning circuit through the second scanning line.
3. The display panel of claim 2, wherein: the display panel further comprises an initialization signal line, a first pole of the first switch transistor is electrically connected with the initialization signal line, and a second pole of the first switch transistor is electrically connected with the grid electrode of the first driving transistor;
the second pole of the first driving transistor is electrically connected to the first pole of the first light emitting transistor, and the second pole of the first light emitting transistor is electrically connected to the first organic light emitting diode.
4. The display panel of claim 2, wherein: the display panel further comprises an initialization signal line, a first pole of the second switching transistor is electrically connected with the initialization signal line, and a second pole of the second switching transistor is electrically connected with the grid electrode of the second driving transistor;
a second pole of the second driving transistor is electrically connected to the first pole of the second light emitting transistor, and a second pole of the second light emitting transistor is electrically connected to the second organic light emitting diode.
5. The display panel of claim 1, wherein: the width-to-length ratio of the first output transistor is greater than the width-to-length ratio of the second output transistor.
6. The display panel of claim 5, wherein: the display panel comprises a first area and a second area, wherein the minimum distance between the boundary of the first area and the driving circuit is larger than the minimum distance between the boundary of the second area and the driving circuit;
the first region includes a plurality of the first scan circuits, and the width-to-length ratios of the first output transistors each located in the first region are equal;
the second region includes a plurality of the second scanning circuits, and the width-to-length ratios of the second output transistors each located in the second region are equal.
7. The display panel of claim 1, wherein: the display panel comprises a first switching line, the output end of the first output transistor is electrically connected with the first scanning line through the first switching line, and the output end of the second output transistor is directly connected with the second scanning line.
8. The display panel according to claim 1, wherein the display panel comprises:
a first transfer line through which the first output transistor is electrically connected to the scan line;
and the second output transistor is electrically connected with the scanning line through the second patch cord, and the length of the second patch cord is smaller than that of the first patch cord.
9. The display panel according to claim 8, wherein the display panel includes a first region and a second region, a minimum distance between a boundary of the first region and the driver circuit is larger than a minimum distance between a boundary of the second region and the driver circuit;
the first region includes a plurality of the first scan circuits, and first transfer lines electrically connected to the first output transistors each located in the first region are the same in length;
the second region includes a plurality of the second scan circuits, and second transfer lines electrically connected to the second output transistors each located in the second region have the same length.
10. The display panel according to any one of claims 7 to 9, wherein the first output transistor includes a gate electrode, a semiconductor structure, a first pole, and a second pole; the second output transistor comprises a gate, a semiconductor structure, a first pole and a second pole;
the first transfer line, the second transfer line, the semiconductor structure of the first output transistor and the semiconductor structure of the second output transistor are located on the same layer and made of the same material.
11. An electronic device characterized by comprising the display panel according to any one of claims 1 to 10.
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| CN201810695746.7A CN108877544A (en) | 2018-06-29 | 2018-06-29 | A kind of display panel and electronic equipment |
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Effective date of registration: 20211108 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Applicant after: WUHAN TIANMA MICROELECTRONICS Co.,Ltd. Applicant after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Applicant before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |