CN114743504B

CN114743504B - Pixel circuit, display panel and display device

Info

Publication number: CN114743504B
Application number: CN202210539325.1A
Authority: CN
Inventors: 卢慧玲; 曹培轩; 齐栋宇; 楼均辉; 胡思明
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2022-05-18
Filing date: 2022-05-18
Publication date: 2023-12-19
Anticipated expiration: 2042-05-18
Also published as: CN114743504A

Abstract

The embodiment of the application provides a pixel circuit, display panel and display device, and pixel circuit is applied to the pixel drive of display panel, and display panel has first display area and transparent display area, and the partial pixel circuit that is arranged in first display area is connected with the light emitting component electricity in the transparent display area, and pixel circuit includes: the output end of the driving module is electrically connected with the target node; the first reset module is electrically connected with the first scanning signal line at the control end, the reference voltage signal line at the first end and the first electrode of the light-emitting element through the first wiring at the second end; the control end of the switching module is electrically connected with the light-emitting control signal wire, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is connected with the first wiring; in the light-emitting stage, the first reset module is turned off, the switching module is turned on, and the driving current is transmitted to the first pole of the light-emitting element through the switching module and the first wiring. According to the embodiment of the invention, the wiring space of the first display area can be saved.

Description

Pixel circuit, display panel and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a pixel circuit, a display panel and a display device.

Background

With the rapid development of display technology, full-screen display has become a trend of mobile display devices such as mobile phones.

The current display panel usually has a high pixel density (PPI), and most display devices are configured with front-end cameras and other modules. In order to realize full screen display and also consider a front camera, a display area with low PPI and partial transparency is usually arranged in the display panel, and this area may be called a transparent display area. In order to improve light transmittance, a transparent display region is generally provided with only light emitting elements, and pixel circuits electrically connected to the light emitting elements in the transparent display region are provided in other regions (referred to as a first display region), and the pixel circuits in the first display region are electrically connected to the light emitting elements in the transparent display region through wirings.

The inventor researches of the application find that the current wiring mode is limited, and the current first display area has the problems of insufficient wiring space and difficult wiring arrangement.

Disclosure of Invention

The embodiment of the application provides a pixel circuit, a display panel and a display device, which can save the wiring space of a first display area and facilitate the wiring arrangement of the first display area.

In a first aspect, embodiments of the present application provide a pixel circuit applied to pixel driving of a display panel, the display panel having a first display area and a transparent display area in a first direction, the transparent display area including a light emitting element, a portion of the pixel circuit located in the first display area being electrically connected to the light emitting element in the transparent display area, the portion of the pixel circuit including: the output end of the driving module is electrically connected with the target node; the control end of the first reset module is electrically connected with the first scanning signal line, the first end of the first reset module is electrically connected with the reference voltage signal line, and the second end of the first reset module is electrically connected with the first electrode of the light-emitting element through the first wiring; the control end of the switching module is electrically connected with the light-emitting control signal wire, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is electrically connected with the first electrode of the light-emitting element through the first wiring; in the light emitting stage, the first reset module is turned off in response to the off level provided by the first scanning signal line, the switching module is turned on in response to the on level provided by the light emitting control signal line, and the driving current output by the driving module is transmitted to the first electrode of the light emitting element through the turned-on switching module and the first wiring.

According to an embodiment of the first aspect of the present application, the first reset module includes a first transistor, a gate of the first transistor is electrically connected to the first scan signal line, a first pole of the first transistor is electrically connected to the reference voltage signal line, and a second pole of the first transistor is electrically connected to the first pole of the light emitting element through the first trace; the switching module comprises a second transistor, wherein the grid electrode of the second transistor is electrically connected with the light-emitting control signal line, the first electrode of the second transistor is electrically connected with the target node, and the second electrode of the second transistor is electrically connected with the first electrode of the light-emitting element through the first wiring.

In this way, in the initialization stage, the first transistor is turned on in response to the on level of the first scanning signal line, the second transistor is turned off in response to the off level of the light emission control signal line, and the reference voltage signal transmitted by the reference voltage signal line is transmitted to the first electrode of the light emitting element through the first transistor and the first trace, so that the reset of the first electrode of the light emitting element is realized; in the light emitting stage, the first transistor is turned off in response to the off level of the first scanning signal line, the second transistor is turned on in response to the on level of the light emitting control signal line, and the driving current output by the driving module is transmitted to the first electrode of the light emitting element through the turned-on second transistor and the first wiring to drive the light emitting element to emit light. In this way, the first wires can be multiplexed in a time-sharing manner by the first transistor and the second transistor cooperating with each other, that is, the wires for providing the driving current to the first electrode of the light emitting element in the light emitting stage (which may be referred to as anode wires) are multiplexed with the first wires for resetting the first electrode of the light emitting element, so that the number of anode wires in the first display area can be reduced, thereby saving the wiring space of the first display area and facilitating the wiring arrangement of the first display area.

According to any one of the foregoing embodiments of the first aspect of the present application, the second transistor includes a double-gate transistor, the double-gate transistor includes a first sub-transistor and a second sub-transistor that are disposed in series, the gate of the first sub-transistor and the gate of the second sub-transistor are electrically connected to the light emission control signal line, the first pole of the first sub-transistor is electrically connected to the target node, the second pole of the first sub-transistor is electrically connected to the first pole of the second sub-transistor, and the second pole of the second sub-transistor is electrically connected to the first pole of the light emitting element through the first trace.

In this way, since the second transistor is a double-gate transistor, the leakage current from the control terminal (i.e., the first node) of the driving module to the first electrode of the light emitting element can be reduced, and the stability and uniformity of the brightness of the light emitting element can be ensured.

According to any of the foregoing embodiments of the first aspect of the present application, the pixel circuit may further include: a first light emitting control transistor, a gate electrode of which is electrically connected with the light emitting control signal line, a first electrode of which is electrically connected with the first power voltage signal line, and a second electrode of which is electrically connected with the input end of the driving module; and the grid electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the second light-emitting control transistor is electrically connected with the output end of the driving module, and the second electrode of the second light-emitting control transistor is electrically connected with the target node.

In this way, the pixel circuit may further include a first light emitting control transistor and a second light emitting control transistor, that is, the embodiments of the present application may be applicable to various types of pixel circuits such as 7T1C, 7T2C, or 9T 1C.

According to any one of the foregoing embodiments of the first aspect of the present application, the first display area includes a main screen area and a transition area, the light transmittance of the transition area is greater than that of the main screen area, no light emitting element is disposed in at least a portion of the transition area, and the pixel circuit is located in the transition area.

In this way, the transition area is closer to the transparent display area, so that the pixel circuit is arranged in the transition area, the wiring length between the pixel circuit and the light-emitting element in the transparent display area can be shortened, the wiring space of the first display area can be further saved, and the wiring arrangement of the first display area is facilitated.

In a second aspect, embodiments of the present application provide a display panel, including a first display area and a transparent display area, the transparent display area including a light emitting element; the first display region includes the pixel circuit as provided in the first aspect, and the pixel circuit is electrically connected to the light emitting element in the transparent display region.

According to an embodiment of the second aspect of the present application, the first display area includes a main screen area and a transition area, the light transmittance of the transition area is greater than that of the main screen area, no light emitting element is provided in at least a part of the transition area, a first pixel circuit and a second pixel circuit are provided in the transition area, the first pixel circuit is a pixel circuit provided in the first aspect, and the first pixel circuit and the plurality of second pixel circuits are arranged along a first direction; the second pixel circuit includes: a driving transistor; and the grid electrode of the third light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the third light-emitting control transistor is electrically connected with the first electrode of the driving transistor, and the second electrode of the third light-emitting control transistor is electrically connected with the light-emitting element in the transparent display area through the second wiring.

In this way, since each first wire can be electrically connected with one row of pixel circuits, and one row of pixel circuits includes a plurality of pixel circuits, if anode wires of the plurality of pixel circuits all multiplex the same first wire, the light emitting elements of the transparent display area may not be driven independently; therefore, the transition region is provided with the second pixel circuits, and each second pixel circuit can be electrically connected with the light-emitting element in the transparent display region through the corresponding second wiring. In this way, one first pixel circuit and a plurality of second pixel circuits can be arranged in one row of pixel circuits, and independent driving of the light emitting elements of the transparent display area can be realized while the number of anode wires is reduced.

According to any of the foregoing embodiments of the second aspect of the present application, the transition region includes M second pixel circuits, the M second pixel circuits are in one-to-one correspondence with the M second wirings, and the second diode of the third light emission control transistor in each second pixel circuit is electrically connected to the light emitting element in the transparent display region through the corresponding second wiring.

According to any one of the foregoing embodiments in the second aspect of the present application, the display panel includes an active layer and a metal layer that are stacked; at least in the transition region, the light emission control signal line in the metal layer extends in a first direction, and a first portion of the light emission control signal line overlaps the active layer in a thickness direction of the display panel; the switching module includes a second transistor, and a first portion overlapping the active layer forms a gate of the second transistor.

Therefore, the grid electrode of the second transistor and the light-emitting control signal line can be prepared through the same process, so that the simplification of the production process is facilitated, and the production cost is reduced.

According to any of the foregoing embodiments of the second aspect of the present application, the second transistor comprises a double-gate transistor comprising a first sub-transistor and a second sub-transistor arranged in series; the first portion includes a first sub-portion and a second sub-portion arranged at intervals, the first sub-portion overlapping the active layer forms a gate of the first sub-transistor, and the second sub-portion overlapping the active layer forms a gate of the second sub-transistor.

According to any one of the foregoing embodiments in the second aspect of the present application, the display panel includes an active layer and a metal layer that are stacked; the first scanning signal line in the metal layer comprises a first body part extending along a first direction and a first extension part extending along a second direction, the first body part is electrically connected with a first pixel circuit and a plurality of second pixel circuits which are arranged along the first direction, and the first direction is intersected with the second direction; the first extension part overlaps the active layer in a thickness direction of the display panel; the first reset module includes a first transistor, and a first extension overlapping the active layer forms a gate of the first transistor.

Therefore, the grid electrode of the first transistor and the first scanning signal line can be prepared through the same process, so that the simplification of the production process is facilitated, and the production cost is reduced.

According to any of the foregoing embodiments of the second aspect of the present application, the main screen area surrounds the transition area, and the first pixel circuits are located on one side of the second pixel circuits in the same row, which is close to the main screen area, along the first direction.

In this way, since the first pixel circuit is located at the junction between the transition area and the main screen area, that is, the first pixel circuit is located at the head end of one row of pixel circuits, a plurality of other second pixel circuits in one row of pixel circuits can be closely arranged in a repeating unit, so that arrangement of transistors and wires in the transition area is facilitated.

In a third aspect, embodiments of the present application provide a display device including a display panel as provided in the second aspect.

The embodiment of the application provides a pixel circuit, a display panel and a display device, wherein the pixel circuit is applied to pixel driving of the display panel, the display panel is provided with a first display area and a transparent display area in a first direction, the transparent display area comprises a light emitting element, a part of pixel circuits in the first display area are electrically connected with the light emitting element in the transparent display area, and the part of pixel circuits comprise: the output end of the driving module is electrically connected with the target node; the control end of the first reset module is electrically connected with the first scanning signal line, the first end of the first reset module is electrically connected with the reference voltage signal line, and the second end of the first reset module is electrically connected with the first electrode of the light-emitting element through the first wiring; the control end of the switching module is electrically connected with the light-emitting control signal wire, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is electrically connected with the first electrode of the light-emitting element through the first wiring; in the light emitting stage, the first reset module is turned off in response to the off level provided by the first scanning signal line, the switching module is turned on in response to the on level provided by the light emitting control signal line, and the driving current output by the driving module is transmitted to the first electrode of the light emitting element through the turned-on switching module and the first wiring. According to the embodiment of the application, the first wires are multiplexed in a time-sharing manner, namely, the wires (which can be called anode wires) for providing driving current for the first electrode of the light-emitting element in the light-emitting stage are multiplexed to reset the first electrode of the light-emitting element, so that the number of the anode wires in the first display area can be reduced, the wiring space of the first display area is saved, and the wiring arrangement of the first display area is facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

FIG. 1 is a schematic diagram of a display panel;

fig. 2 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a display panel to which the pixel circuit according to the embodiment of the present application is applied;

fig. 4 is another schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 6;

fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of another structure of a display panel to which the pixel circuit according to the embodiment of the present application is applied;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 11 is a layout of a display panel according to an embodiment of the present disclosure;

FIG. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure;

FIG. 13 is an enlarged view of a portion of a first pixel circuit in the layout shown in FIG. 11;

FIG. 14 is another layout of a display panel provided in an embodiment of the present application;

fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The transistors in the embodiments of the present application are described by taking P-type transistors as examples, but the transistors are not limited to P-type transistors, and may be replaced by N-type transistors. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, when the control of the P-type transistor is at a very low level, the first pole and the second pole are turned on, and when the control of the P-type transistor is at a high level, the first pole and the second pole are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

In the embodiments herein, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

In the embodiment of the present application, the first node and the target node are defined only for convenience in describing the circuit structure, and the first node and the target node are not one actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

Fig. 1 is a schematic structural diagram of a display panel. As shown in fig. 1, the pixel circuit 100 in the first display area 10 is electrically connected to the anode of the light emitting element in the transparent display area 20 through the anode trace L (i.e., the trace providing the driving current to the anode of the light emitting element), so as to provide the driving current to the light emitting element and drive the light emitting element to emit light. The anode wires L may extend along the first direction X, and the plurality of anode wires L may be sequentially arranged along the second direction Y. The inventor of the present application has found that, when there are more light emitting elements in the transparent display area 20, the more anode traces L are, but because there are only a limited number of film layers (such as the first metal layer M1, the second metal layer M2 or the anode layer) that can be used as the anode traces L, and the anode traces L need to satisfy a certain interval and line width, there is a problem that the first display area has insufficient wiring space and the traces are difficult to be arranged.

The inventors of the present application further found that the anode trace L extending along the first direction X overlaps with other signal lines (e.g., power signal lines and data signal lines) extending along the second direction Y at different layers to form a coupling capacitor. In order to arrange as many anode traces L as possible, in the related art, the anode traces L are typically disposed in different film layers. Since the film layers where the anode wirings L connected to the pixel circuits 100 in different columns are located are different, there is a difference in coupling capacitance generated by the anode wirings L connected to the pixel circuits 100 in different columns. In the case of low gray scale display, the light emitting time of the light emitting elements driven by the pixel circuits 100 of different columns varies, and mura phenomenon along the second direction Y occurs. When the length of the anode wires L is longer and the interval between the anode wires L is smaller, the coupling capacitance generated by the anode wires L is further increased, so that the mura phenomenon along the second direction Y is more serious.

In view of the above-mentioned research of the inventor, the embodiment of the application provides a pixel circuit, a display panel and a display device, which at least can solve the technical problems of insufficient wiring space of a first display area and difficult wiring arrangement in the related art.

The technical conception of the embodiment of the application is as follows: the first reset module and the switching module are additionally arranged to realize time-sharing multiplexing of the first wiring, namely, the first wiring for resetting the first pole of the light-emitting element is multiplexed by the wiring (which can be called anode wiring) for providing driving current for the first pole of the light-emitting element in the light-emitting stage, so that the number of anode wirings in the first display area is reduced, the wiring space of the first display area is saved, and the wiring arrangement of the first display area is facilitated.

The pixel circuit provided in the embodiment of the present application will be described first.

Fig. 2 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. Fig. 3 is a schematic structural diagram of a display panel to which the pixel circuit according to the embodiment of the present application is applied. As shown in fig. 2 and 3, the pixel circuit 100 provided in the embodiment of the present application is applied to pixel driving of the display panel 01. The display panel 01 includes, but is not limited to, an organic light emitting diode OLED display panel. The display panel 01 has a first display area 10 and a transparent display area 20 in a first direction. The first direction here may be any direction parallel to the plane in which the display panel lies. The transparent display region 20 may include a light emitting element D1. The light emitting element D1 includes, but is not limited to, a red light emitting element, a green light emitting element, or a blue light emitting element. It should be noted that, the transparent display area 20 may be provided with only the light emitting element D1, and no pixel circuit, that is, the pixel circuit is disposed in the first display area 10, so as to ensure that the transparent display area 20 has better light transmittance. In the embodiment of the present application, the pixel circuit 100 located in the first display area 10 is electrically connected to the light emitting element D1 in the transparent display area 20 to drive the light emitting element D1 to emit light. It should be noted that, in addition to the pixel circuit 100, the first display area 10 may further include other pixel circuits for driving the light emitting elements in the first display area 10 to emit light.

As shown in fig. 2, in the embodiment of the present application, the pixel circuit 100 includes a driving module 101, a first reset module 102, and a switching module 103. The output of the drive module 101 is electrically connected to the target node Nm. The output of the drive module 101 can be understood as the output of the drive current of the drive module 101.

The control end of the first reset module 102 is electrically connected to the first scan signal line S1, the first end of the first reset module 102 is electrically connected to the reference voltage signal line Vref, and the second end of the first reset module 102 is electrically connected to the first electrode of the light emitting element D1 through the first trace L1. The first electrode of the light emitting element D1 may be an anode of the light emitting element D1. In the initialization stage, the first reset module 102 may be turned on in response to the turn-on level provided by the first scan signal line S1, and the reference voltage signal transmitted by the reference voltage signal line Vref may be transmitted to the first electrode of the light emitting element D1 through the first reset module 102 and the first trace L1 to reset the first electrode of the light emitting element D1.

The control end of the switching module 103 is electrically connected to the emission control signal line EM, the first end of the switching module 103 is electrically connected to the target node Nm, and the second end of the switching module 103 is electrically connected to the first electrode of the light emitting element D1 through the first trace L1. In the initialization phase, the switching module 103 may be turned off in response to the off level provided by the light emission control signal line EM to ensure successful reset of the first pole of the light emitting element D1.

In the light emitting stage, the first reset module 102 is turned off in response to the off level provided by the first scan signal line S1, the switching module 103 is turned on in response to the on level provided by the light emission control signal line EM, and the driving current output by the driving module 101 is transmitted to the first electrode of the light emitting element D1 through the turned-on switching module 103 and the first trace L1 to drive the light emitting element D1 to emit light.

That is, the first trace L1 may be used to transmit the reference voltage signal in the initialization stage, or transmit the driving current output by the driving module 101 in the light-emitting stage, i.e. achieve the effect of time-division multiplexing.

According to the pixel circuit, the first reset module and the switching module are additionally arranged to realize time-sharing multiplexing of the first wiring, namely, the first wiring for resetting the first electrode of the light-emitting element is multiplexed by the wiring (which can be called anode wiring) for providing driving current for the first electrode of the light-emitting element in the light-emitting stage, so that the number of anode wirings in the first display area can be reduced, the wiring space of the first display area is saved, and wiring arrangement of the first display area is facilitated.

In addition, as the wiring space of the first display region increases, the anode wirings in the first display region may be disposed in the same film layer, thereby improving mura phenomenon in the second direction Y (e.g., column inversion) of the display panel.

Fig. 4 is another schematic circuit diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 4, according to some embodiments of the present application, optionally, the first reset module 102 may include a first transistor T1, where a gate of the first transistor T1 is electrically connected to the first scan signal line S1, a first pole of the first transistor T1 is electrically connected to the reference voltage signal line Vref, and a second pole of the first transistor T1 is electrically connected to the first pole of the light emitting element D1 through the first trace L1. The switching module 103 may include a second transistor T2, a gate of the second transistor T2 is electrically connected to the emission control signal line EM, a first pole of the second transistor T2 is electrically connected to the target node Nm, and a second pole of the second transistor T2 is electrically connected to the first pole of the light emitting element D1 through the first trace L1.

In the initialization stage, the first transistor T1 may be turned on in response to the on level of the first scan signal line S1, the second transistor T2 may be turned off in response to the off level of the emission control signal line EM, and the reference voltage signal transmitted by the reference voltage signal line Vref is transmitted to the first electrode of the light emitting element D1 through the first transistor T1 and the first trace L1, thereby realizing the reset of the first electrode of the light emitting element D1. In the light emitting stage, the first transistor T1 is turned off in response to the off level of the first scan signal line S1, the second transistor T2 is turned on in response to the on level of the light emission control signal line EM, and the driving current outputted from the driving module 101 is transmitted to the first electrode of the light emitting element D1 through the turned-on second transistor T2 and the first trace L1, thereby driving the light emitting element D1 to emit light.

In this way, the first transistor T1 and the second transistor T2 cooperate with each other to realize time-sharing multiplexing of the first trace, that is, the trace (may be referred to as an anode trace) that supplies a driving current to the first electrode of the light emitting element in the light emitting stage is multiplexed with the first trace that resets the first electrode of the light emitting element, so that the number of anode traces in the first display area can be reduced, thereby saving the wiring space of the first display area and facilitating the layout of the first display area.

With continued reference to fig. 4, in accordance with some embodiments of the present application, the second transistor T2 may alternatively be a double gate transistor including a first sub-transistor T21 and a second sub-transistor T22 arranged in series. The gate of the first sub-transistor T21 and the gate of the second sub-transistor T22 are electrically connected to the emission control signal line EM, the first pole of the first sub-transistor T21 is electrically connected to the target node Nm, the second pole of the first sub-transistor T21 is electrically connected to the first pole of the second sub-transistor T22, and the second pole of the second sub-transistor T22 is electrically connected to the first pole of the light emitting element D1 through the first wiring L1.

In this way, since the second transistor T2 is a double-gate transistor, the leakage current from the control terminal (i.e., the first node N1) of the driving module 101 to the first electrode of the light emitting element D1 can be reduced, and the stability and uniformity of the brightness of the light emitting element D1 can be ensured.

Fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 5, the pixel circuit 100 may optionally further include a first light emission control transistor T3 and a second light emission control transistor T4 according to some embodiments of the present application.

The gate of the first light emitting control transistor T3 is electrically connected to the light emitting control signal line EM, the first pole of the first light emitting control transistor T3 is electrically connected to the first power voltage signal line PVDD, and the second pole of the first light emitting control transistor T3 is electrically connected to the input terminal of the driving module 101. Illustratively, the driving module 101 may include a driving transistor T0, and the input terminal of the driving module 101 may be specifically a source or a drain of the driving transistor T0.

The gate of the second light emission control transistor T4 is electrically connected to the light emission control signal line EM, the first electrode of the second light emission control transistor T4 is electrically connected to the output terminal of the driving module 101, and the second electrode of the second light emission control transistor T4 is electrically connected to the target node Nm. When the input end of the driving module 101 is the source of the driving transistor T0, the output end of the driving module 101 is the drain of the driving transistor T0. Conversely, when the input terminal of the driving module 101 is the drain of the driving transistor T0, the output terminal of the driving module 101 is the source of the driving transistor T0.

In the light emitting stage, the first light emitting control transistor T3 and the second light emitting control transistor T4 are turned on in response to the turn-on level provided by the light emitting control signal line EM, and the forward voltage signal provided by the first power voltage signal line PVDD is sequentially transmitted to the first electrode of the light emitting element D1 through the first light emitting control transistor T3, the driving transistor T0, the second light emitting control transistor T4, the second transistor T2 and the first wiring L1 to drive the light emitting element D1 to emit light.

It should be noted that the pixel circuit 100 may include other transistors in addition to the transistors listed above, and these transistors together constitute a plurality of types of pixel circuits. That is, the embodiments of the present application can be applied to various types of pixel circuits such as 7T1C, 7T2C, or 9T 1C.

For ease of understanding, the following description is provided in connection with certain specific application embodiments.

Fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 6, the pixel circuit 100 may optionally further include a data writing transistor T5, a threshold compensating transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst according to some embodiments of the present application.

The gate of the data writing transistor T5 is electrically connected to the second scanning signal line S2, the first pole of the data writing transistor T5 is electrically connected to the data signal line data, and the second pole of the data writing transistor T5 is electrically connected to the first pole of the driving transistor T0.

The gate of the threshold compensation transistor T6 is electrically connected to the second scan signal line S2, the first pole of the threshold compensation transistor T6 is electrically connected to the gate of the driving transistor T0, and the second pole of the threshold compensation transistor T6 is electrically connected to the first pole of the driving transistor T0.

The gate of the second reset transistor T7 is electrically connected to the first scan signal line S1, the first pole of the second reset transistor T7 is electrically connected to the reference voltage signal line vref, and the second pole of the second reset transistor T7 is electrically connected to the gate of the driving transistor T0.

The gate of the third reset transistor T8 is electrically connected to the first scan signal line S1, the first pole of the third reset transistor T8 is electrically connected to the second pole of the first transistor T1, and the second pole of the third reset transistor T8 is electrically connected to the first trace L1.

The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T0, and the second electrode of the storage capacitor Cst is electrically connected to the first power voltage signal line PVDD. The second electrode of the light emitting element D1 is electrically connected to the second power supply voltage signal line PVEE.

Fig. 7 is a timing diagram of the pixel circuit shown in fig. 6. As shown in fig. 7, each frame includes an initialization phase t1, a data writing phase t2, and a light emitting phase t3.

As shown in fig. 6 and 7, in the initialization stage t1, the first scan signal line S1 provides an on level, the second scan signal line S2 provides an off level, and the emission control signal line EM provides an off level. The first transistor T1 may be turned on in response to the on level of the first scan signal line S1, the third reset transistor T8 may be turned on in response to the on level of the first scan signal line S1, the second transistor T2 may be turned off in response to the off level of the light emission control signal line EM, and the reference voltage signal transmitted by the reference voltage signal line Vref may be transmitted to the first electrode of the light emitting element D1 through the first transistor T1 and the first trace L1, thereby realizing the reset of the first electrode of the light emitting element D1. The second reset transistor T7 is turned on in response to the on level transmitted by the first scan signal line S1, and the reference voltage signal of the reference voltage signal line Vref is transmitted to the first node N1 through the second reset transistor T7 to reset the first node N1.

In the data writing stage t2, the first scanning signal line S1 provides an off level, the second scanning signal line S2 provides an on level, and the emission control signal line EM provides an off level. The data writing transistor T5 and the threshold compensating transistor T6 are turned on in response to the on level transmitted by the second scan signal line S2, the data voltage signal of the data voltage signal line data is transmitted to the first pole of the driving transistor T0, the threshold compensating transistor T6 communicates the gate of the driving transistor T0 and the second pole of the driving transistor T0, and compensation of the threshold voltage of the driving transistor T0 is completed.

In the light emission period t3, the first scan signal line S1 provides an off level, the second scan signal line S2 provides an off level, and the light emission control signal line EM provides an on level. The first and second light emission control transistors T3 and T4 are turned on in response to the on level transmitted by the light emission control signal line EM, the first transistor T1 is turned off in response to the off level of the first scan signal line S1, the second transistor T2 is turned on in response to the on level of the light emission control signal line EM, the driving transistor T0 is turned on in response to the on level maintained by the storage capacitor Cst, and a forward voltage signal of the first power voltage signal line PVDD is sequentially transmitted to the first electrode of the light emitting element D1 through the first light emission control transistor T3, the driving transistor T0, the second light emission control transistor T4, the second transistor T2, and the first trace L1 to drive the light emitting element D1 to emit light.

Fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 8, unlike the embodiment shown in fig. 6, the pixel circuit 100 may not be provided with the third reset transistor T8, and other circuit structures are the same as those of the embodiment shown in fig. 6, and will not be described again.

In this way, by removing the third reset transistor T8, the wiring of the pixel circuit can be simplified, so that the wiring space of the first display area is further saved, and the wiring arrangement of the first display area is facilitated.

Fig. 9 is a schematic diagram of another structure of a display panel to which the pixel circuit according to the embodiment of the present application is applied. As shown in fig. 9, the first display area 10 may optionally include a transition area 90 and a main screen area A2, according to some embodiments of the present application. The light transmittance of the transition region 90 may be greater than that of the main screen region A2, i.e., the pixel density of the transition region 90 may be less than that of the main screen region A2. The transition area 90 and the transparent display area 20 may form a secondary screen area, and electronic devices such as a camera may be disposed below the secondary screen area, and the primary screen area A2 is also called a normal display area. At least a part of the area of the transition region 90 may be provided with no light emitting element, and the pixel circuit 100 for driving the light emitting element in the transparent display region 20 to emit light is provided, so that the pixel circuit 100 may be located in the transition region.

Based on the pixel circuit 100 provided in the foregoing embodiment, correspondingly, the present application further provides a specific implementation manner of the display panel. Please refer to the following examples.

As shown in fig. 9, the display panel 01 provided in the embodiment of the present application may include a first display area 10 and a transparent display area 20, where the transparent display area 20 includes a light emitting element. The first display area 10 may include the pixel circuit 100 provided in the above-described embodiment, and the pixel circuit 100 may be electrically connected with the light emitting element in the transparent display area 20.

According to the display panel provided by the embodiment of the application, the first reset module and the switching module are additionally arranged to realize time-sharing multiplexing of the first wiring, namely, the first wiring for resetting the first electrode of the light-emitting element is multiplexed by the wiring (which can be called anode wiring) for providing driving current for the first electrode of the light-emitting element in the light-emitting stage, so that the number of anode wirings in the first display area can be reduced, the wiring space of the first display area is saved, and the wiring arrangement of the first display area is facilitated.

Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in connection with fig. 9 and 10, the first display area 10 may optionally include a transition area 90 and a home screen area A2 according to some embodiments of the present application. The light transmittance of the transition region 90 may be greater than that of the main screen region A2, i.e., the pixel density of the transition region 90 may be less than that of the main screen region A2. The transition area 90 and the transparent display area 20 may form a secondary screen area, and electronic devices such as a camera may be disposed below the secondary screen area, and the primary screen area A2 is also called a normal display area. At least a part of the area of the transition region 90 may be provided with no light emitting element, but with pixel circuits for driving the light emitting elements in the transparent display region 20 to emit light. The transition region 90 is provided with a first pixel circuit 10a and a second pixel circuit 10b, where the first pixel circuit 10a is the pixel circuit 100 provided in the above embodiment, and the first pixel circuit 10a and the plurality of second pixel circuits 10b may be arranged along the first direction X. Wherein the first direction X may be a row direction.

The second pixel circuit 10b may include a driving transistor T0 'and a third light emission control transistor T4', the gate electrode of the third light emission control transistor T4 'is electrically connected to the light emission control signal line EM, the first electrode of the third light emission control transistor T4' is electrically connected to the first electrode of the driving transistor T0', and the second electrode of the third light emission control transistor T4' is electrically connected to the light emitting element D1 in the transparent display region 20 through the second wiring L2.

That is, the transition region 90 may be provided with not only the first pixel circuit 10a but also the second pixel circuit 10b. The anode wiring of the second pixel circuit 10b does not multiplex the first wiring L1, but is electrically connected to the corresponding light emitting element D1 in the transparent display area 20 through a separate second wiring L2, thereby realizing independent driving of the light emitting elements.

As shown in fig. 10, there may be only one first pixel circuit 10a in one row of pixel circuits (i.e., the first pixel circuit 10a and the second pixel circuit 10b arranged in the first direction X), and the remaining second pixel circuits 10b. The advantage of this is that: because each first wiring can be electrically connected with one row of pixel circuits, and one row of pixel circuits comprises a plurality of pixel circuits, if anode wirings of the pixel circuits are multiplexed with the same first wiring, the light-emitting elements of the transparent display area can not be driven independently; therefore, the transition region is provided with the second pixel circuits, and each second pixel circuit can be electrically connected with the light-emitting element in the transparent display region through the corresponding second wiring. In this way, one first pixel circuit and a plurality of second pixel circuits can be arranged in one row of pixel circuits, and independent driving of the light emitting elements of the transparent display area can be realized while the number of anode wires is reduced.

It should be noted that other transistors may be further included in the second pixel circuit 10b in the embodiment of the present application, and the second pixel circuit 10b includes various types of pixel circuits, such as but not limited to 7T1C, 7T2C, or 9T1C, and the specific circuit structure is shown in the embodiment of fig. 6 and will not be described herein.

With continued reference to fig. 10, in some specific embodiments, the transition region 90 may include M second pixel circuits 10b, where the M second pixel circuits 10b are in one-to-one correspondence with the M second traces L2. Wherein M is an integer greater than 1. The second wires L2 may extend along the first direction X, and the plurality of second wires L2 may be sequentially arranged along the second direction Y. The second pole of the third light emission control transistor T4' in each of the second pixel circuits 10b may be electrically connected to the light emitting element D1 in the transparent display area 20 through the corresponding second trace L2.

The film layer structure and layout structure of the display panel 01 provided in the embodiments of the present application are described below with reference to some embodiments.

Fig. 11 is a layout of a display panel according to an embodiment of the present application. As shown in fig. 11, the display panel 01 may optionally include an active layer P and a metal layer M that are stacked, according to some embodiments of the present application. In at least the transition region 90, the light emission control signal line EM located in the metal layer M extends in the first direction X. The first portion 110 in the light emission control signal line EM overlaps the active layer P in the thickness direction of the display panel.

As shown in connection with fig. 4 and 11, the switching module 103 includes a second transistor T2, and the first portion 110 overlapping the active layer P forms a gate electrode of the second transistor T2.

In this way, the gate electrode of the second transistor T2 and the emission control signal line EM may be manufactured by the same process, which is advantageous to simplify the manufacturing process and reduce the manufacturing cost.

As shown in connection with fig. 4 and 11, the second transistor T2 may alternatively be a double gate transistor including a first sub-transistor T21 and a second sub-transistor T22 arranged in series according to some embodiments of the present application. The first portion 110 includes a first sub-portion 110a and a second sub-portion 110b arranged at intervals, wherein the first sub-portion 110a overlapped with the active layer P forms a gate electrode of the first sub-transistor T21, and the second sub-portion 110b overlapped with the active layer P forms a gate electrode of the second sub-transistor T22.

In this way, since the second transistor T2 is a double-gate transistor, the leakage current from the control terminal (i.e., the first node) of the driving module to the first electrode of the light emitting element can be reduced, and the stability and uniformity of the brightness of the light emitting element can be ensured.

With continued reference to fig. 11, according to some embodiments of the present application, the first scan signal line S1 located in the metal layer M may optionally include a first body portion 111a extending in a first direction X and a first extension portion 111b extending in a second direction Y, the first direction X intersecting the second direction Y. For example, the first direction X is a row direction of the display panel, and the second direction Y is a column direction of the display panel. The first body 111a may be electrically connected to the first pixel circuit 10a and the plurality of second pixel circuits 10b arranged along the first direction X, so as to provide the first scan signal to the first pixel circuit 10a and the plurality of second pixel circuits 10b arranged along the first direction X.

The first extension 111b overlaps the active layer P in the thickness direction of the display panel. As shown in conjunction with fig. 4 and 11, the first reset module 102 includes a first transistor T1, and the first extension 111b overlapping the active layer P may form a gate electrode of the first transistor T1.

In this way, the gate of the first transistor T1 and the first scan signal line S1 can be manufactured by the same process, which is beneficial to simplifying the manufacturing process and reducing the manufacturing cost.

Fig. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure. As shown in fig. 12, according to some embodiments of the present application, the display panel 01 may optionally include a substrate 1, a buffer layer 02 located on a side of the substrate 1, and a driving device layer 03 disposed on a side of the buffer layer 02 remote from the substrate 1. The driving device layer 03 may include a first metal layer M1, a second metal layer M2, and a third metal layer M3 stacked in a direction away from the substrate 01. An active layer P is provided between the first metal layer M1 and the buffer layer 02. Insulating layers are provided between any adjacent metal layers and between the active layer P and the first metal layer M1. Illustratively, a gate insulating layer GI is disposed between the first metal layer M1 and the active layer P, a capacitor insulating layer IMD is disposed between the second metal layer M2 and the first metal layer M1, and an interlayer dielectric layer ILD is disposed between the third metal layer M3 and the second metal layer M2. In addition, the display panel 01 may further include a planarization layer PLN, a pixel definition layer PDL, and the light emitting element may include an anode RE, a light emitting layer OM, and a cathode SE which are stacked.

As shown in connection with fig. 6, the light emission control signal line EM, the first scan signal line S1, the second scan signal line S2, and the gate electrodes of the respective transistors may be optionally located at the first metal layer M1 according to some embodiments of the present application. The reference voltage signal line Vref, the first trace L1, the second trace L2, and the second plate of the storage capacitor Cst may be located in the second metal layer M2. The first power signal line PVDD and the data signal line data may be located at the third metal layer M3. Fig. 13 is a partial enlarged view of a first pixel circuit in the layout shown in fig. 11. As shown in fig. 13, in some specific examples, a first pole of the first transistor T1 may be electrically connected to the reference voltage signal line Vref located at the second metal layer M2 through the via h1, and a second pole of the first transistor T1 may be electrically connected to the first trace L1 located at the second metal layer M2 through the via h 2. The second pole of the second transistor T2 may be electrically connected to the first trace L1 located in the second metal layer M2 through the via h 3.

Fig. 14 is another layout of a display panel according to an embodiment of the present application. As shown in fig. 6 and 13, the third reset transistor T8 is not provided in the layout shown in fig. 14, compared with the layout shown in fig. 13. Specifically, in the layout shown in fig. 13, the first pole of the third reset transistor T8 is electrically connected to the second pole of the first transistor T1, and the second pole of the third reset transistor T8 is electrically connected to the first trace L1 through the via h and the connection line x extending in the second direction Y. In the layout shown in fig. 14, the via h and the connection line x extending in the second direction Y may be removed to disconnect the connection between the second pole of the third reset transistor T8 and the first trace L1. The other layout structure of fig. 14 is the same as the layout shown in fig. 13, and will not be described here again.

In this way, by removing the third reset transistor T8, the wiring of the pixel circuit can be simplified, the wiring space of the transition region is further saved, and the wiring arrangement of the transition region is facilitated.

As shown in connection with fig. 9 and 11, the primary screen region A2 may optionally surround the transition region 90, according to some embodiments of the present application. The first pixel circuits 10a may be located at a side of the same row of the second pixel circuits 10b near the main screen area A2 along the first direction X.

In this way, since the first pixel circuit is located at the junction between the transition area and the main screen area, that is, the first pixel circuit may be located at the head end of one row of pixel circuits, the other second pixel circuits in one row of pixel circuits may be closely arranged in a repeating unit, so as to facilitate the arrangement of transistors and wirings in the transition area.

Based on the display panel 01 provided in the above embodiment, correspondingly, the present application further provides a display device, including the display panel provided in the present application. Referring to fig. 15, fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 15 provides a display device 1000 including a display panel 01 provided in any of the above embodiments of the present application. The embodiment of fig. 15 is, for example, a mobile phone as an example, and the display device 1000 is described, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, which is not particularly limited in this application. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 01 provided in the embodiment of the present application, and the specific description of the display panel 01 in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

It should be understood that the specific structures of the pixel circuits and the layout structures of the display panels provided in the drawings in the embodiments of the present application are only examples and are not intended to limit the present application. In addition, the above embodiments provided herein may be combined with each other without contradiction.

These embodiments are not all details described in detail in accordance with the embodiments described hereinabove, nor are they intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Claims

1. A pixel circuit for pixel driving of a display panel having a first display region and a transparent display region in a first direction, the transparent display region including a light emitting element, a portion of the pixel circuit located in the first display region being electrically connected to the light emitting element in the transparent display region, the pixel circuit comprising:

The output end of the driving module is electrically connected with the target node;

the control end of the first reset module is electrically connected with a first scanning signal line, the first end of the first reset module is electrically connected with a reference voltage signal line, and the second end of the first reset module is electrically connected with the first electrode of the light-emitting element through a first wiring;

the control end of the switching module is electrically connected with the light-emitting control signal line, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is electrically connected with the first electrode of the light-emitting element through the first wiring;

in a light emitting stage, the first reset module is turned off in response to a cut-off level provided by the first scanning signal line, the switching module is turned on in response to a turn-on level provided by the light emitting control signal line, and a driving current output by the driving module is transmitted to a first pole of the light emitting element through the turned-on switching module and the first wiring;

the first display area comprises a main screen area and a transition area, the light transmittance of the transition area is larger than that of the main screen area, at least part of the transition area is not provided with a light-emitting element, a first pixel circuit and a second pixel circuit are arranged in the transition area, and the first pixel circuit comprises the pixel circuit; the first pixel circuit and the plurality of second pixel circuits are arranged along a first direction;

The second pixel circuit includes:

a driving transistor;

and the grid electrode of the third light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the third light-emitting control transistor is electrically connected with the first electrode of the driving transistor, and the second electrode of the third light-emitting control transistor is electrically connected with the light-emitting element in the transparent display area through the second wiring.

2. The pixel circuit according to claim 1, wherein the first reset module includes a first transistor having a gate electrically connected to a first scan signal line, a first electrode electrically connected to the reference voltage signal line, and a second electrode electrically connected to the first electrode of the light emitting element through the first wiring;

the switching module comprises a second transistor, wherein the grid electrode of the second transistor is electrically connected with the light-emitting control signal line, the first electrode of the second transistor is electrically connected with the target node, and the second electrode of the second transistor is electrically connected with the first electrode of the light-emitting element through the first wiring.

3. The pixel circuit according to claim 2, wherein the second transistor comprises a double-gate transistor including a first sub-transistor and a second sub-transistor arranged in series, the gate of the first sub-transistor and the gate of the second sub-transistor each being electrically connected to the light emission control signal line, the first pole of the first sub-transistor being electrically connected to the target node, the second pole of the first sub-transistor being electrically connected to the first pole of the second sub-transistor, the second pole of the second sub-transistor being electrically connected to the first pole of the light emitting element through the first trace.

4. The pixel circuit of claim 1, wherein the pixel circuit further comprises:

a first light emitting control transistor, a gate of which is electrically connected to the light emitting control signal line, a first pole of which is electrically connected to a first power supply voltage signal line, and a second pole of which is electrically connected to an input terminal of the driving module;

the grid electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the second light-emitting control transistor is electrically connected with the output end of the driving module, and the second electrode of the second light-emitting control transistor is electrically connected with the target node.

5. A display panel, wherein the display panel comprises a first display area and a transparent display area, and the transparent display area comprises a light-emitting element;

the first display region includes the pixel circuit of any one of claims 1 to 4, which is electrically connected to the light emitting element in the transparent display region.

6. The display panel according to claim 5, wherein the transition region includes M second pixel circuits, the M second pixel circuits are in one-to-one correspondence with the M second wirings, and a second pole of the third light emission control transistor in each of the second pixel circuits is electrically connected to a light emitting element in the transparent display region through the corresponding second wiring.

7. The display panel according to claim 6, wherein the display panel includes an active layer and a metal layer which are stacked;

in at least the transition region, the light emission control signal line in the metal layer extends in a first direction, and a first portion of the light emission control signal line overlaps the active layer in a thickness direction of the display panel;

the switching module includes a second transistor, and the first portion overlapping the active layer forms a gate of the second transistor.

8. The display panel of claim 7, wherein the second transistor comprises a double gate transistor comprising a first sub-transistor and a second sub-transistor arranged in series; the first part comprises a first sub-part and a second sub-part which are arranged at intervals, the first sub-part overlapped with the active layer forms a grid electrode of the first sub-transistor, and the second sub-part overlapped with the active layer forms a grid electrode of the second sub-transistor.

9. The display panel according to claim 6, wherein the display panel includes an active layer and a metal layer which are stacked;

The first scanning signal line in the metal layer comprises a first body part extending along a first direction and a first extension part extending along a second direction, the first body part is electrically connected with the first pixel circuit and a plurality of second pixel circuits which are arranged along the first direction, and the first direction is intersected with the second direction;

the first extension part overlaps the active layer in a thickness direction of the display panel;

the first reset module includes a first transistor, and the first extension overlapping the active layer forms a gate of the first transistor.

10. The display panel of claim 6, wherein the primary screen region surrounds the transition region, and the first pixel circuits are located on a side of the same row of the second pixel circuits adjacent to the primary screen region along the first direction.

11. A display device comprising the display panel according to any one of claims 5 to 10.